CAT28C257GI-15T [CATALYST]
256K-Bit CMOS PARALLEL EEPROM; 256K位CMOS并行EEPROM
| 型号： | CAT28C257GI-15T |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 256K-Bit CMOS PARALLEL EEPROM |
| 文件： | 总12页 (文件大小：523K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT28C257
256K-Bit CMOS PARALLEL EEPROM
TM
FEATURES
■ Automatic page write operation:
–1 to 128 Bytes in 5ms
–Page load timer
■ Fast read access times: 120/150 ns
■ Low power CMOS dissipation:
–Active: 25 mA max.
■ End of write detection:
–Toggle bit
–Standby: 150 µA max.
■ Simple write operation:
–DATA polling
–On-chip address and data latches
–Self-timed write cycle with auto-clear
■ Hardware and software write protection
■ 100,000 Program/erase cycles
■ 100 Year data retention
■ Fast write cycle time:
–5ms max
■ CMOS and TTL compatible I/O
■ Commercial, industrial and automotive
temperature ranges
DESCRIPTION
The CAT28C257 is a fast, low power, 5V-only CMOS
Parallel EEPROM organized as 32K x 8-bits. It requires a
simple interface for in-system programming. On-chip
addressanddatalatches,self-timedwritecyclewithauto-
clear and VCC power up/down write protection eliminate
additional timing and protection hardware. DATA Polling
and Toggle status bits signal the start and end of the self-
timed write cycle. Additionally, the CAT28C257 features
hardware and software write protection.
The CAT28C257 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP or 32-pin PLCC packages.
BLOCK DIAGRAM
32,768 x 8
EEPROM
ARRAY
ROW
DECODER
ADDR. BUFFER
A –A
7
14
& LATCHES
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
128 BYTE PAGE
REGISTER
V
CC
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
DATA POLLING
AND
TIMER
TOGGLE BIT
I/O –I/O
0
7
ADDR. BUFFER
& LATCHES
A –A
COLUMN
DECODER
0
6
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1015, Rev. D
1
CAT28C257
PIN CONFIGURATION
DIP Package (P, L)
PLCC Package (N, G)
A
A
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
14
12
2
A
A
3
A
4
3 2 1 32 31 30
7
6
5
4
3
2
1
0
0
1
2
13
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A
A
A
A
A
A
A
A
A
A
4
A
6
5
4
3
2
1
0
8
8
A
5
A
9
9
A
6
A
11
11
NC
OE
A
A
7
OE
TOP VIEW
A
8
A
10
10
11
12
13
A
9
CE
10
CE
I/O
A
10
11
12
13
14
I/O
7
NC
I/O
I/O
I/O
I/O
V
I/O
7
6
I/O
I/O
5
0
6
14 15 16 17 18 19 20
I/O
4
I/O
3
SS
PIN FUNCTIONS
Pin Name
Function
Address Inputs
Pin Name
WE
Function
Write Enable
5V Supply
Ground
A0–A14
I/O0–I/O7
CE
Data Inputs/Outputs VCC
Chip Enable
VSS
NC
OE
Output Enable
No Connect
Doc. No. 1015, Rev. D
2
CAT28C257
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature........................ -65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on Any Pin with
Respect to Ground(2) ............ -2.0V to +VCC + 2.0V
VCC with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
NEND
Parameter
Endurance
Test Method
MIL-STD-883, Test Method 1033 104 or 105
Min
Typ
Max
Units
Cycles/Byte
Years
(1)
(1)
TDR
Data Retention
MIL-STD-883, Test Method 1008
100
2000
100
(1)
VZAP
ESD Susceptibility MIL-STD-883, Test Method 3015
Latch-Up JEDEC Standard 17
Volts
(1)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
VCC = 5V 10%, unless otherwise specified.
Symbol
Parameter
VCC Current (Operating, TTL)
Test Conditions
Min
Typ
30
Max
mA
Units
ICC
CE = OE = VIL, f=6MHz
All I/O’s Open
(5)
ICCC
VCC Current (Operating, CMOS) CE = OE = VILC, f=6MHz
25
mA
All I/O’s Open
ISB
VCC Current (Standby, TTL)
CE = VIH, All I/O’s Open
1
mA
(6)
ISBC
VCC Current (Standby, CMOS)
CE = VIHC
,
150
µA
All I/O’s Open
ILI
Input Leakage Current
Output Leakage Current
VIN = GND to VCC
–10
–10
10
10
µA
µA
ILO
VOUT = GND to VCC
,
CE = VIH
(6)
VIH
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
2
VCC +0.3
0.8
V
V
V
V
V
(5)
VIL
–0.3
2.4
VOH
VOL
VWI
IOH = –400µA
IOL = 2.1mA
0.4
3.5
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V +1V.
CC
(5) V
(6) V
= –0.3V to +0.3V.
ILC
IHC
= V –0.3V to V +0.3V.
CC
CC
Doc. No. 1015, Rev. D
3
CAT28C257
MODE SELECTION
Mode
CE
L
WE
H
OE
L
I/O
DOUT
DIN
Power
ACTIVE
ACTIVE
ACTIVE
STANDBY
ACTIVE
Read
Byte Write (WE Controlled)
Byte Write (CE Controlled)
Standby, and Write Inhibit
Read and Write Inhibit
L
H
L
X
H
H
DIN
H
X
X
High-Z
High-Z
H
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
A
CC
Symbol
CI/O
Test
Conditions
VI/O = 0V
VIN = 0V
Min
Typ
Max
10
6
Units
pF
(1)
Input/Output Capacitance
Input Capacitance
(1)
CIN
pF
A.C. CHARACTERISTICS, Read Cycle
VCC=5V + 10%, Unless otherwise specified
28C257-12
Typ
28C257-15
Typ
Symbol Parameter
Min
Max
Min
Max
Units
ns
tRC
tCE
tAA
tOE
Read Cycle Time
120
150
CE Access Time
120
120
50
150
150
70
ns
Address Access Time
OE Access Time
ns
ns
(1)
tLZ
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
0
0
0
0
ns
(1)
tOLZ
ns
(1)(2)
tHZ
50
50
50
50
ns
(1)(2)
(1)
tOHZ
ns
tOH
Output Hold from Address Change
0
0
ns
Power-Up Timing
Symbol Parameter
Min
Typ
Max
Units
µs
tPUR
tPUW
Power-Up to Read
Power-Up to Write
100
10
5
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
Doc. No. 1015, Rev. D
4
CAT28C257
A.C. CHARACTERISTICS, Write Cycle
CC=5V 10%, unless otherwise specified
V
28C257-12
Typ
28C257-15
Typ
Symbol
Parameter
Min
Max
Min
Max
Units
ms
ns
tWC
tAS
tAH
tCS
tCH
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
5
5
0
50
0
0
50
0
ns
ns
CE Hold Time
0
0
ns
(3)
tCW
tOES
tOEH
CE Pulse Time
100
0
100
0
ns
OE Setup Time
ns
OE Hold Time
0
0
ns
(3)
tWP
tDS
tDH
WE Pulse Width
Data Setup Time
Data Hold Time
100
50
0
100
50
ns
ns
0
ns
(1)
tINIT
Write Inhibit Period After Power-up
Byte Load Cycle Time
5
10
5
10
ms
µs
(1)(4)
tBLC
0.1
100
0.1
100
Figure 1. A.C. Testing Input/Output Waveform(2)
V
- 0.3V
CC
2.0 V
0.8 V
INPUT PULSE LEVELS
REFERENCE POINTS
0.0 V
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
C
= 100 pF
L
C
INCLUDES JIG CAPACITANCE
L
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration t
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
BLC
however a transition from HIGH to LOW within t
max. stops the timer.
BLC
Doc. No. 1015, Rev. D
5
CAT28C257
Byte Write
DEVICE OPERATION
Awritecycleisexecutedwhenboth CEand WEarelow,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Read
Data stored in the CAT28C257 is transferred to the data
bus when WE is held high, and both OE and CE are
held low. The data bus is set to a high impedance state
when either CE or OE goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Figure 3. Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
t
WE
LZ
t
OHZ
t
t
HZ
t
OLZ
OH
HIGH-Z
DATA OUT
DATA VALID
DATA VALID
t
AA
28C256 F06
Figure 4. Byte Write Cycle [WE Controlled]
t
WC
ADDRESS
t
t
AH
AS
t
t
CH
CS
CE
OE
WE
t
t
t
OEH
OES
WP
t
BLC
HIGH-Z
DATA OUT
DATA IN
DATA VALID
DS
t
t
DH
Doc. No. 1015, Rev. D
6
CAT28C257
Page Write
to A6 (which can be loaded in any order) during the first
andsubsequentwritecycles.Eachsuccessivebyteload
cyclemustbeginwithintBLCMAX ofthe fallingedgeofthe
preceding WE pulse. There is no page write window
The page write mode of the CAT28C257 (essentially an
extended BYTE WRITE mode) allows from 1 to 128
bytesofdatatobeprogrammedwithinasingleEEPROM
write cycle. This effectively reduces the byte-write time
by a factor of 128.
limitation as long as WE is pulsed low within tBLC MAX
.
Upon completion of the page write sequence, WE must
stayhighaminimumoftBLCMAX fortheinternalautomatic
program cycle to commence. This programming cycle
consists of an erase cycle, which erases any data that
existed in each addressed cell, and a write cycle, which
writes new data back into the cell. A page write will only
write data to the locations that were addressed and will
not rewrite the entire page.
FollowinganinitialWRITEoperation(WEpulsedlow,for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a128 byte temporary buffer. The
page address where data is to be written, specified by
bits A7 to A14, is latched on the last falling edge of WE.
Each byte within the page is defined by address bits A0
Figure 5. Byte Write Cycle [CE Controlled]
t
WC
ADDRESS
t
t
t
BLC
AS
AH
t
CW
CE
OE
WE
t
OEH
t
OES
t
t
CH
CS
HIGH-Z
DATA OUT
DATA IN
DATA VALID
DS
t
t
DH
Figure 6. Page Mode Write Cycle
OE
CE
WE
t
t
BLC
WP
ADDRESS
I/O
t
WC
LAST BYTE
BYTE n+2
BYTE 0 BYTE 1
BYTE 2
BYTE n
BYTE n+1
Doc. No. 1015, Rev. D
7
CAT28C257
DATA Polling
Toggle Bit
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O7 (I/O0–I/O6
are indeterminate) until the programming cycle is
complete. Upon completion of the self-timed write cycle,
all I/O’s will output true data during a read cycle.
InadditiontotheDATAPollingfeatureoftheCAT28C257,
the device offers an additional method for determining
the completion of a write cycle. While a write cycle is in
progress, reading data from the device will result in I/O6
togglingbetweenoneandzero. However, oncethewrite
is complete, I/O6 stops toggling and valid data can be
read from the device.
Figure 7. DATA Polling
ADDRESS
CE
WE
t
OEH
t
OES
t
OE
OE
t
WC
I/O
D
= X
D
= X
D
= X
OUT
7
IN
OUT
Figure 8. Toggle Bit
WE
CE
OE
t
OEH
t
OES
t
OE
(1)
(1)
I/O
6
t
WC
Note:
(1) Beginning and ending state of I/O is indeterminate.
6
Doc. No. 1015, Rev. D
8
CAT28C257
HARDWARE DATA PROTECTION
Thefollowingisalistofhardwaredataprotectionfeatures
(4) Noise pulses of less than 20 ns on the WE or CE
that are incorporated into the CAT28C257.
inputs will not result in a write cycle.
(1) VCC sense provides for write protection when VCC
falls below 3.5V min.
SOFTWARE DATA PROTECTION
The CAT28C257 features a software controlled data
protectionschemewhich, onceenabled, requiresadata
algorithmtobeissuedtothedevicebeforeawritecanbe
performed. The device is shipped from Catalyst with the
software protection NOT ENABLED (the CAT28C257 is
in the standard operating mode).
(2) A power on delay mechanism, tINIT (see AC
characteristics), provides a 5 to 10 ms delay before
a write sequence, after VCC has reached 3.5V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
Figure 9. Write Sequence for Activating Software
Data Protection
Figure 10. Write Sequence for Deactivating
Software Data Protection
WRITE DATA:
ADDRESS:
AA
WRITE DATA:
ADDRESS:
AA
5555
5555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
ADDRESS:
55
2AAA
2AAA
WRITE DATA:
ADDRESS:
80
WRITE DATA:
ADDRESS:
A0
5555
5555
WRITE DATA:
ADDRESS:
AA
SOFTWARE DATA
PROTECTION ACTIVATED
(
(1)
5555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
XX
2AAA
TO ANY ADDRESS
WRITE LAST BYTE
TO
LAST ADDRESS
20
WRITE DATA:
ADDRESS:
5555
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
Max., after SDP activation.
BLC
Doc. No. 1015, Rev. D
9
CAT28C257
Toactivatethesoftwaredataprotection,thedevicemust
besentthreewritecommandstospecificaddresseswith
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
writetimingspecifications(Figure11).Oncethisisdone,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequenceisissuedregardlessofpoweron/offtransitions.
This gives the user added inadvertent write protection
on power-up in addition to the hardware protection
provided.
To allow the user the ability to program the device with
anEEPROMprogrammer(orfortestingpurposes)there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
t
WC
DATA
ADDRESS
AA
5555
55
2AAA
A0
5555
BYTE OR
PAGE
CE
WRITES
ENABLED
t
t
BLC
WP
WE
Figure 12. Resetting Software Data Protection Timing
t
DATA
ADDRESS
AA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
WC
SDP
RESET
CE
DEVICE
UNPROTECTED
WE
Doc. No. 1015, Rev. D
10
CAT28C257
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
28C257
N
I
-90
T
Tape & Reel
Optional
Company
ID
Product
Number
Temperature Range
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)*
Speed
Package
P: PDIP
12: 120ns
15: 150ns
N: PLCC
L: PDIP (Lead free, Halogen free)
G: PLCC (Lead free, Halogen free)
* -40°C to +125°C isavailable upon request
Notes:
(1) The device used in the above example is a CAT28C257NI-90T (100,000 Cycle Endurance, PLCC, Industrial temperature, 200 ns
Access Time, Tape & Reel).
Doc. No. 1015, Rev. D
11
REVISION HISTORY
Date
Revision Comments
3/29/2004
04/19/04
D
D
Added Green packages in all areas.
Delete data sheet designation
Update Block Diagram
Update Ordering Information
Update Revision History
Update Rev Number
Copyrights, Trademarks and Patents
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Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
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PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
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other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Publication #: 1015
Revison:
D
Fax: 408.542.1200
Issue date:
4/19/04
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