CAT28C512TI-15T [CATALYST]
512K-Bit CMOS PARALLEL EEPROM; 512K位CMOS并行EEPROM
| 型号： | CAT28C512TI-15T |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 512K-Bit CMOS PARALLEL EEPROM |
| 文件： | 总12页 (文件大小：416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT28C512/513
512K-Bit CMOS PARALLEL EEPROM
TM
FEATURES
I Fast Read Access Times: 120/150 ns
I Automatic Page Write Operation:
–1 to 128 Bytes in 5ms
I Low Power CMOS Dissipation:
–Active: 50 mA Max.
–Page Load Timer
–Standby: 200 µA Max.
I Simple Write Operation:
I End of Write Detection:
–Toggle Bit
–DATA Polling
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
I Hardware and Software Write Protection
I 100,000 Program/Erase Cycles
I 100 Year Data Retention
I Fast Write Cycle Time:
–5ms Max
I CMOS and TTL Compatible I/O
I Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28C512/513 is manufactured using Catalyst’s
advancedCMOSfloatinggatetechnology.Itisdesigned
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 32-pin DIP, PLCC and TSOP packages.
TheCAT28C512/513isafast,lowpower,5V-onlyCMOS
parallel EEPROM organized as 64K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C512/513 features hardware and software write
protection.
BLOCK DIAGRAM
65,536 x 8
EEPROM
ARRAY
ROW
DECODER
ADDR. BUFFER
& LATCHES
A –A
7
15
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
128 BYTE PAGE
REGISTER
V
CC
CE
OE
WE
CONTROL
TIMER
I/O BUFFERS
DATA POLLING
AND
TOGGLE BIT
I/O –I/O
0
7
ADDR. BUFFER
& LATCHES
A –A
COLUMN
DECODER
0
6
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1007, Rev. F
1
CAT28C512/513
PIN CONFIGURATION
DIP Package (P, L)
PLCC Package (N, G)
PLCC Package (N, G)
V
NC
NC
1
32
31
CC
WE
2
4
3 2 1 32 31 30
4
3 2 1 32 31 30
NC
A
3
30
29
28
27
26
25
24
23
22
21
20
19
18
17
15
12
A
A
A
A
A
A
A
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A
A
A
A
A
A
A
A
A
A
A
A
6
5
4
3
2
1
0
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A
A
A
7
6
5
4
3
2
1
0
14
13
8
8
A
A
4
14
9
A
A
5
7
6
5
4
3
2
1
0
0
1
2
13
11
A
A
6
8
NC
9
CAT28C513
TOP VIEW
CAT28C512
TOP VIEW
A
A
9
7
OE
A
11
A
A
8
11
10
11
12
13
A
10
11
12
13
10
OE
A
OE
9
A
CE
10
A
10
11
12
13
14
15
16
A
10
NC
I/O
I/O
CE
7
6
A
CE
I/O
I/O
I/O
0
0
7
A
14 15 16 17 18 19 20
I/O
7
14 15 16 17 18 19 20
I/O
I/O
I/O
V
I/O
6
I/O
5
I/O
4
I/O
3
SS
TSOP Package (8mmx20mm) (T, H)
A
A
A
OE
1
2
3
4
5
6
7
8
32
31
11
9
8
A
10
CE
I/O
30
29
28
27
26
25
24
23
22
21
20
19
18
A
7
13
I/O
I/O
I/O
I/O
V
A
14
6
5
4
3
NC
WE
V
CC
NC
9
CAT28C512
TOP VIEW
ss
10
11
12
13
14
15
16
I/O
NC
2
1
0
A
A
15
12
A
I/O
I/O
A
0
7
6
5
A
A
A
1
A
2
A
3
17
A
4
PIN FUNCTIONS
Pin Name
Function
Address Inputs
Pin Name
Function
Write Enable
5V Supply
Ground
A0–A15
I/O0–I/O7
CE
WE
Data Inputs/Outputs VCC
Chip Enable
VSS
NC
OE
Output Enable
No Connect
Doc. No. 1007, Rev. F
2
CAT28C512/513
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on Any Pin with
Respect to Ground(2) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min
100,000
100
Max.
Units
Cycles/Byte
Years
Test Method
(1)
NEND
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(1)
VZAP
2000
100
Volts
(1)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
VCC = 5V 10%, unless otherwise specified.
Limits
Typ
Symbol
Parameter
Min
Max.
Units
Test Conditions
ICC
VCC Current (Operating, TTL)
50
mA
CE = OE = VIL, f=6MHz
All I/O’s Open
(5)
ICCC
VCC Current (Operating, CMOS)
25
mA
CE = OE = VILC, f=6MHz
All I/O’s Open
ISB
VCC Current (Standby, TTL)
VCC Current (Standby, CMOS)
3
mA
CE = VIH, All I/O’s Open
(6)
ISBC
200
µA
CE = VIHC,
All I/O’s Open
ILI
Input Leakage Current
Output Leakage Current
-10
-10
10
10
µA
µA
VIN = GND to VCC
ILO
VOUT = GND to VCC,
CE = VIH
(6)
VIH
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
2
VCC +0.3
0.8
V
V
V
V
V
(5)
VIL
-1
VOH
VOL
VWI
2.4
IOH = –400µA
0.4
IOL = 2.1mA
3.5
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V +1V.
CC
(5) V
(6) V
= –0.3V to +0.3V.
ILC
= V –0.3V to V +0.3V.
IHC
CC
CC
Doc. No. 1007, Rev . E
3
CAT28C512/513
MODE SELECTION
Mode
CE
L
WE
OE
L
I/O
DOUT
DIN
Power
ACTIVE
ACTIVE
ACTIVE
STANDBY
ACTIVE
Read
H
Byte Write (WE Controlled)
Byte Write (CE Controlled)
Standby, and Write Inhibit
Read and Write Inhibit
L
H
L
X
H
H
DIN
H
X
X
High-Z
High-Z
H
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
CC
A
Symbol
Test
Max.
10
Units
pF
Conditions
(1)
CI/O
Input/Output Capacitance
Input Capacitance
VI/O = 0V
VIN = 0V
(1)
CIN
6
pF
A.C. CHARACTERISTICS, Read Cycle
VCC=5V + 10%, Unless otherwise specified
28C512/513-12 28C512/513-15
Min. Max. Min. Max. Units
Symbol Parameter
tRC
tCE
tAA
tOE
Read Cycle Time
120
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE Access Time
120
120
50
150
150
70
Address Access Time
OE Access Time
(1)
tLZ
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
Output Hold from Address Change
0
0
0
0
(1)
tOLZ
(1)(2)
tHZ
50
50
50
50
(1)(2)
tOHZ
(1)
tOH
0
0
Power-Up Timing
Symbol
Parameter
Min.
Max
100
10
Units
(1)
tPUR
Power-up to Read Operation
Power-up to Write Operation
µs
(2)
tPUW
5
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
Doc. No. 1007, Rev. F
4
CAT28C512/513
A.C. CHARACTERISTICS, Write Cycle
CC=5V+10%, unless otherwise specified
V
28C512/513-12 28C512/513-15
Symbol Parameter
Min. Max. Min. Max. Units
tWC
tAS
tAH
tCS
tCH
tCW
Write Cycle Time
5
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
Address Setup Time
Address Hold Time
CE Setup Time
0
50
0
0
50
0
CE Hold Time
0
0
(3)
CE Pulse Time
100
0
100
0
tOES
tOEH
OE Setup Time
OE Hold Time
0
0
(3)
tWP
tDS
WE Pulse Width
100
50
0
100
50
0
Data Setup Time
Data Hold Time
tDH
(1)
tINIT
Write Inhibit Period After Power-up
Byte Load Cycle Time
5
10
5
10
(1)(4)
tBLC
0.1
100
0.1
100
Figure 1. A.C. Testing Input/Output Waveform(2)
V
- 0.3V
CC
2.0 V
0.8 V
INPUT PULSE LEVELS
REFERENCE POINTS
0.0 V
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
C
= 100 pF
L
C
INCLUDES JIG CAPACITANCE
L
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration t
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
BLC
however a transition from HIGH to LOW within t
max. stops the timer.
BLC
Doc. No. 1007, Rev . E
5
CAT28C512/513
Byte Write
DEVICE OPERATION
Awritecycleisexecutedwhenboth CEand WE arelow,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Read
Data stored in the CAT28C512/513 is transferred to the
data bus when WE is held high, and both OE and CE
are held low. The data bus is set to a high impedance
statewheneitherCEorOEgoeshigh. This2-linecontrol
architecture can be used to eliminate bus contention in
a system environment.
Figure 3. Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
t
WE
LZ
t
OHZ
t
t
HZ
DATA VALID
t
OH
OLZ
HIGH-Z
DATA OUT
DATA VALID
t
AA
Figure 4. Byte Write Cycle [WE Controlled]
t
WC
ADDRESS
t
t
AH
AS
t
t
CH
CS
CE
OE
WE
t
t
t
OEH
OES
WP
t
BLC
HIGH-Z
DATA OUT
DATA IN
DATA VALID
DS
t
t
DH
Doc. No. 1007, Rev. F
6
CAT28C512/513
Page Write
to A6 (which can be loaded in any order) during the first
andsubsequentwritecycles.Eachsuccessivebyteload
cycle must begin within tBLC MAX of the rising edge of the
preceding WE pulse. There is no page write window
The page write mode of the CAT28C512/513 (essen-
tially an extended BYTE WRITE mode) allows from 1 to
128 bytes of data to be programmed within a single
EEPROM write cycle. This effectively reduces the byte-
write time by a factor of 128.
limitation as long as WE is pulsed low within tBLC MAX
.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLC MAX for the internal auto-
matic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
whichwritesnewdatabackintothecell. Apagewritewill
only write data to the locations that were addressed and
will not rewrite the entire page.
FollowinganinitialWRITEoperation(WEpulsedlow,for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a 128 byte temporary buffer. The
page address where data is to be written, specified by
bits A7 to A15, is latched on the last falling edge of WE.
Each byte within the page is defined by address bits A0
Figure 5. Byte Write Cycle [CE Controlled]
t
WC
ADDRESS
t
t
t
BLC
AS
AH
t
CW
CE
OE
WE
t
OEH
t
OES
t
t
CH
CS
HIGH-Z
DATA OUT
DATA IN
DATA VALID
DS
t
t
DH
Figure 6. Page Mode Write Cycle
OE
CE
WE
t
t
BLC
WP
ADDRESS
I/O
t
WC
LAST BYTE
BYTE n+2
BYTE 0 BYTE 1
BYTE 2
7
BYTE n
BYTE n+1
Doc. No. 1007, Rev . E
CAT28C512/513
DATA Polling
Toggle Bit
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O7 (I/O0–I/O6
are indeterminate) until the programming cycle is com-
plete. Upon completion of the self-timed write cycle, all
I/O’s will output true data during a read cycle.
InadditiontotheDATAPollingfeatureoftheCAT28C512/
513,thedeviceoffersanadditionalmethodfordetermin-
ing the completion of a write cycle. While a write cycle is
in progress, reading data from the device will result in I/
O6 toggling between one and zero. However, once the
write is complete, I/O6 stops toggling and valid data can
be read from the device.
Figure 7. DATA Polling
ADDRESS
CE
WE
t
OEH
t
OES
t
OE
OE
t
WC
I/O
D
= X
D
= X
D
= X
OUT
7
IN
OUT
Figure 8. Toggle Bit
WE
CE
OE
t
OEH
t
OES
t
OE
(1)
(1)
I/O
6
t
WC
Note:
(1) Beginning and ending state of I/O is indeterminate.
6
Doc. No. 1007, Rev. F
8
CAT28C512/513
HARDWARE DATA PROTECTION
The following is a list of hardware data protection fea-
tures that are incorporated into the CAT28C512/513.
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
(1) VCC sense provides for write protection when VCC
falls below 3.5V min.
SOFTWARE DATA PROTECTION
The CAT28C512/513 features a software controlled
dataprotectionschemewhich, onceenabled, requiresa
data algorithm to be issued to the device before a write
can be performed. The device is shipped from Catalyst
with the software protection NOT ENABLED (the
CAT28C512/513 is in the standard operating mode).
(2) A power on delay mechanism, tINIT (see AC charac-
teristics), provides a 5 to 10 ms delay before a write
sequence, after VCC has reached 3.5V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
Figure 9. Write Sequence for Activating Software
Data Protection
Figure 10. Write Sequence for Deactivating
Software Data Protection
WRITE DATA:
ADDRESS:
AA
WRITE DATA:
ADDRESS:
AA
5555
5555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
ADDRESS:
55
2AAA
2AAA
WRITE DATA:
ADDRESS:
80
WRITE DATA:
ADDRESS:
A0
5555
5555
WRITE DATA:
ADDRESS:
AA
(1)
SOFTWARE DATA
PROTECTION ACTIVATED
(12)
5555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
XX
2AAA
TO ANY ADDRESS
20
WRITE LAST BYTE
TO
LAST ADDRESS
WRITE DATA:
ADDRESS:
5555
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
Max., after SDP activation.
BLC
Doc. No. 1007, Rev . E
9
CAT28C512/513
Toactivatethesoftwaredataprotection,thedevicemust
besentthreewritecommandstospecificaddresseswith
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
writetimingspecifications(Figure11).Oncethisisdone,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transi-
tions. This gives the user added inadvertent write pro-
tection on power-up in addition to the hardware protec-
tion provided.
To allow the user the ability to program the device with
anEEPROMprogrammer(orfortestingpurposes)there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
t
WC
DATA
ADDRESS
AA
5555
55
2AAA
A0
5555
BYTE OR
PAGE
CE
WRITES
ENABLED
t
t
BLC
WP
WE
Figure 12. Resetting Software Data Protection Timing
t
DATA
ADDRESS
AA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
WC
SDP
RESET
CE
DEVICE
UNPROTECTED
WE
Doc. No. 1007, Rev. F
10
CAT28C512/513
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
28C512
N
I
-15
T
Tape & Reel
Temperature Range
Optional
Company
ID
Product
Number
28C512
28C513
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)*
Package
Speed
12: 120ns
15: 150ns
P: PDIP
N: PLCC
T: TSOP (8mmx20mm)
L: PDIP (Lead free, Halogen free)
G: PLCC (Lead free, Halogen free)
H: TSOP (8mmx20mm) (Lead free, Halogen free)
* -40°C to +125°C isavailable upon request
Notes:
(1) The device used in the above example is a CAT28C512NI-15T (PLCC, Industrial temperature, 150 ns Access Time, Tape & Reel).
(2) 28C513 is offered only in PLCC package.
Doc. No. 1007, Rev . E
11
REVISION HISTORY
Date
Revision Comments
Delete data sheet designation
Update Block Diagram
Update Ordering Information
Add Revision History
04/19/04
11/17/04
E
F
Update Rev Number
Delete T14 and H14 package codes
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
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Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 1007
Revison:
F
Issue date:
11/17/04
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