CAT28C64BNA-90T [CATALYST]
64K-Bit CMOS PARALLEL EEPROM; 64K位CMOS并行EEPROM
| 型号： | CAT28C64BNA-90T |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 64K-Bit CMOS PARALLEL EEPROM |
| 文件： | 总13页 (文件大小：415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT28C64B
64K-Bit CMOS PARALLEL EEPROM
TM
FEATURES
I Fast read access times:
I Commercial, industrial and automotive
– 90/120/150ns
temperature ranges
I Low power CMOS dissipation:
– Active: 25 mA max.
I Automatic page write operation:
– 1 to 32 bytes in 5ms
– Standby: 100 µA max.
– Page load timer
I Simple write operation:
I End of write detection:
– Toggle bit
– On-chip address and data latches
– Self-timed write cycle with auto-clear
– DATA polling
I Fast write cycle time:
I 100,000 program/erase cycles
I 100 year data retention
– 5ms max.
I CMOS and TTL compatible I/O
I Hardware and software write protection
DESCRIPTION
The CAT28C64B is manufactured using Catalyst’s
advancedCMOSfloatinggatetechnology.Itisdesigned
to endure 100,000 program/erase cycles and has a data
retentionof100years.ThedeviceisavailableinJEDEC-
approved 28-pin DIP, TSOP, SOIC, or, 32-pin PLCC
package .
The CAT28C64B is a fast, low power, 5V-only CMOS
Parallel EEPROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C64B features hardware and software write
protection.
BLOCK DIAGRAM
8,192 x 8
EEPROM
ARRAY
ROW
DECODER
ADDR. BUFFER
& LATCHES
A –A
5
12
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
32 BYTE PAGE
REGISTER
V
CC
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
DATA POLLING
AND
TIMER
TOGGLE BIT
I/O –I/O
0
7
ADDR. BUFFER
& LATCHES
A –A
COLUMN
DECODER
0
4
Doc. No. 1011, Rev. F
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
CAT28C64B
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W) (K, X)
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
2
12
A
2
12
A
A
3
NC
7
6
5
4
3
2
1
0
0
1
2
A
3
NC
7
6
5
4
3
2
1
0
0
1
2
4
A
A
A
8
A
4
A
A
A
8
A
5
9
A
5
9
A
6
11
A
6
11
A
7
OE
A
A
7
OE
A
A
8
10
A
8
10
A
9
CE
A
9
CE
I/O
A
10
11
12
13
14
I/O
7
A
10
11
12
13
14
7
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
6
5
4
3
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
6
5
4
3
SS
SS
TSOP Package (8mm x 13.4mm) (T13, H13)
PLCC Package (N, G)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
1
2
3
4
5
6
7
8
A
10
A
A
A
NC
CE
I/O
I/O
I/O
I/O
I/O
11
9
8
4
3 2 1 32 31 30
7
6
5
4
3
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A
A
A
A
A
A
A
A
A
A
6
5
4
3
2
1
0
8
9
WE
11
V
CC
NC
NC
OE
GND
TOP VIEW
A
A
9
I/O
I/O
1
I/O
12
7
2
10
11
12
13
14
10
11
12
13
A
10
A
A
A
A
6
5
4
3
0
CE
A
0
A
1
A
2
NC
I/O
7
I/O
I/O
0
6
14 15 16 17 18 19 20
PIN FUNCTIONS
Pin Name
Function
Address Inputs
Pin Name
WE
Function
Write Enable
5 V Supply
A0–A12
I/O0–I/O7
CE
Data Inputs/Outputs
Chip Enable
VCC
VSS
Ground
OE
Output Enable
NC
No Connect
Doc. No. 1011, Rev. F
2
CAT28C64B
*COMMENT
ABSOLUTE MAXIMUM RATINGS*
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(2) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
105
Max.
Units
Cycles/Byte
Years
Test Method
(1)
NEND
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
100
(1)
VZAP
2000
100
Volts
(1)(4)
ILTH
mA
MODE SELECTION
Mode
CE
WE
OE
L
I/O
DOUT
DIN
Power
ACTIVE
ACTIVE
ACTIVE
STANDBY
ACTIVE
Read
L
L
H
Byte Write (WE Controlled)
Byte Write (CE Controlled)
Standby, and Write Inhibit
Read and Write Inhibit
H
L
X
H
H
DIN
H
X
X
High-Z
High-Z
H
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
CC
A
Symbol
Test
Max.
10
Units
pF
Conditions
(1)
CI/O
Input/Output Capacitance
Input Capacitance
VI/O = 0V
VIN = 0V
(1)
CIN
6
pF
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V +1V.
CC
Doc. No. 1011, Rev. F
3
CAT28C64B
D.C. OPERATING CHARACTERISTICS
VCC = 5V 10%, unless otherwise specified.
Limits
Symbol
Parameter
Min. Typ.
Max.
Units
Test Conditions
CE = OE = VIL,
f = 1/tRC min, All I/O’s Open
CE = OE = VILC
ICC
VCC Current (Operating, TTL)
30
mA
(1)
ICCC
VCC Current (Operating, CMOS)
25
mA
,
f = 1/tRC min, All I/O’s Open
ISB
VCC Current (Standby, TTL)
VCC Current (Standby, CMOS)
1
mA
CE = VIH, All I/O’s Open
(2)
ISBC
100
µA
CE = VIHC,
All I/O’s Open
ILI
Input Leakage Current
Output Leakage Current
–10
–10
10
10
µA
µA
VIN = GND to VCC
ILO
VOUT = GND to VCC,
CE = VIH
(2)
VIH
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
2
VCC +0.3
0.8
V
V
V
V
V
(1)
VIL
–0.3
2.4
VOH
VOL
VWI
IOH = –400µA
0.4
IOL = 2.1mA
3.5
Note:
(1) V
(2) V
= –0.3V to +0.3V.
ILC
= V –0.3V to V +0.3V.
IHC
CC
CC
Doc. No. 1011, Rev. F
4
CAT28C64B
A.C. CHARACTERISTICS, Read Cycle
VCC = 5V 10%, unless otherwise specified.
28C64B-90
28C64B-12
28C64B-15
Symbol Parameter
Min.
Max.
Min.
Max.
Min. Max.
Units
ns
tRC
tCE
tAA
tOE
Read Cycle Time
90
120
150
150
150
70
0
CE Access Time
90
90
50
120
120
60
ns
Address Access Time
OE Access Time
ns
ns
(1)
tLZ
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
Output Hold from Address Change
0
0
0
0
ns
(1)
tOLZ
0
ns
(1)(2)
tHZ
50
50
50
50
50
50
0
ns
(1)(2)
tOHZ
ns
(1)
tOH
0
0
ns
Figure 1. A.C. Testing Input/Output Waveform(3)
V
- 0.3V
CC
2.0 V
0.8 V
INPUT PULSE LEVELS
REFERENCE POINTS
0.0 V
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
C
= 100 pF
L
C
INCLUDES JIG CAPACITANCE
L
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
(3) Input rise and fall times (10% and 90%) < 10 ns.
Doc. No. 1011, Rev. F
5
CAT28C64B
A.C. CHARACTERISTICS, Write Cycle
VCC = 5V 10%, unless otherwise specified.
28C64B-90
28C64B-12
28C64B-15
Symbol
tWC
Parameter
Min. Max. Min. Max.
Min. Max. Units
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
5
5
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
tAS
0
100
0
0
100
0
0
100
0
tAH
tCS
tCH
CE Hold Time
0
0
0
(2)
tCW
CE Pulse Time
110
0
110
0
110
0
tOES
tOEH
OE Setup Time
OE Hold Time
0
0
0
(2)
tWP
WE Pulse Width
Data Setup Time
Data Hold Time
110
60
0
110
60
0
110
60
0
tDS
tDH
(1)
tINIT
Write Inhibit Period After Power-up
Byte Load Cycle Time
5
10
5
10
5
10
(1)(3)
tBLC
.05
100
.05
100
.05
100
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration t
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
BLC
however a transition from HIGH to LOW within t
max. stops the timer.
BLC
Doc. No. 1011, Rev. F
6
CAT28C64B
Byte Write
DEVICE OPERATION
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Read
Data stored in the CAT28C64B is transferred to the data
bus when WE is held high, and both OE and CE are held
low. The data bus is set to a high impedance state when
either CE or OE goes high. This 2-line control architec-
ture can be used to eliminate bus contention in a system
environment.
Figure 3. Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
t
WE
LZ
t
OHZ
t
t
HZ
DATA VALID
t
OH
OLZ
HIGH-Z
DATA OUT
DATA VALID
t
AA
Figure 4. Byte Write Cycle [WE Controlled]
t
WC
ADDRESS
t
t
AH
AS
t
t
CH
CS
CE
OE
WE
t
t
t
OEH
OES
WP
t
BLC
HIGH-Z
DATA OUT
DATA IN
DATA VALID
DS
t
t
DH
Doc. No. 1011, Rev. F
7
CAT28C64B
Page Write
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within tBLC MAX of the rising edge of the
preceding WE pulse. There is no page write window
The page write mode of the CAT28C64B (essentially an
extended BYTE WRITE mode) allows from 1 to 32 bytes
ofdatatobeprogrammedwithinasingleEEPROMwrite
cycle. This effectively reduces the byte-write time by a
factor of 32.
limitation as long as WE is pulsed low within tBLC MAX
.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLC MAX for the internal auto-
matic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
whichwritesnewdatabackintothecell. Apagewritewill
only write data to the locations that were addressed and
will not rewrite the entire page.
FollowinganinitialWRITEoperation(WEpulsedlow,for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
anddatabytesintoa32bytetemporarybuffer. Thepage
address where data is to be written, specified by bits A5
to A12, is latched on the last falling edge of WE. Each
byte within the page is defined by address bits A0 to A4
Figure 5. Byte Write Cycle [CE Controlled]
t
WC
ADDRESS
t
t
t
BLC
AS
AH
t
CW
CE
OE
WE
t
OEH
t
OES
t
t
CH
CS
HIGH-Z
DATA OUT
DATA IN
DATA VALID
DS
t
t
DH
Figure 6. Page Mode Write Cycle
OE
CE
WE
t
t
BLC
WP
ADDRESS
I/O
t
WC
LAST BYTE
BYTE n+2
BYTE 0 BYTE 1
BYTE 2
8
BYTE n
BYTE n+1
Doc. No. 1011, Rev. F
CAT28C64B
DATA Polling
Toggle Bit
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O7 (I/O0–I/O6
are indeterminate) until the programming cycle is com-
plete. Upon completion of the self-timed write cycle, all
I/O’s will output true data during a read cycle.
In addition to the DATA Polling feature, the device offers
an additional method for determining the completion of
a write cycle. While a write cycle is in progress, reading
data from the device will result in I/O6 toggling between
one and zero. However, once the write is complete, I/O6
stops toggling and valid data can be read from the
device.
Figure 7. DATA Polling
ADDRESS
CE
WE
t
OEH
t
OES
t
OE
OE
t
WC
= X
I/O
D
= X
D
D
= X
OUT
7
IN
OUT
Figure 8. Toggle Bit
WE
CE
OE
t
OEH
t
OES
t
OE
(1)
(1)
I/O
6
t
WC
Note:
(1) Beginning and ending state of I/O is indeterminate.
6
Doc. No. 1011, Rev. F
9
CAT28C64B
HARDWARE DATA PROTECTION
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
Thefollowingisalistofhardwaredataprotectionfeatures
that are incorporated into the CAT28C64B.
SOFTWARE DATA PROTECTION
(1) VCC sense provides for write protection when VCC
falls below 3.5V min.
The CAT28C64B features a software controlled data
protectionschemewhich, onceenabled, requiresadata
algorithmtobeissuedtothedevicebeforeawritecanbe
performed. The device is shipped from Catalyst with the
softwareprotectionNOTENABLED(theCAT28C64Bis
in the standard operating mode).
(2) A power on delay mechanism, tINIT (see AC
characteristics), provides a 5 to 10 ms delay before
a write sequence, after VCC has reached 3.5V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
Figure 9. Write Sequence for Activating Software
Data Protection
Figure 10. Write Sequence for Deactivating
Software Data Protection
WRITE DATA:
ADDRESS:
AA
WRITE DATA:
ADDRESS:
AA
1555
1555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
ADDRESS:
55
0AAA
0AAA
WRITE DATA:
ADDRESS:
80
WRITE DATA:
ADDRESS:
A0
1555
1555
WRITE DATA:
ADDRESS:
AA
SOFTWARE DATA
PROTECTION ACTIVATED
(1)
1555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
XX
0AAA
TO ANY ADDRESS
WRITE LAST BYTE
TO
LAST ADDRESS
WRITE DATA:
ADDRESS:
20
1555
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
Max., after SDP activation.
BLC
Doc. No. 1011, Rev. F
10
CAT28C64B
Toactivatethesoftwaredataprotection,thedevicemust
besentthreewritecommandstospecificaddresseswith
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
writetimingspecifications(Figure11).Oncethisisdone,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequenceisissuedregardlessofpoweron/offtransitions.
This gives the user added inadvertent write protection
on power-up in addition to the hardware protection
provided.
To allow the user the ability to program the device with
anEEPROMprogrammer(orfortestingpurposes)there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
t
WC
DATA
ADDRESS
AA
1555
55
0AAA
A0
1555
BYTE OR
PAGE
CE
WRITES
ENABLED
t
t
BLC
WP
WE
Figure 12. Resetting Software Data Protection Timing
t
DATA
ADDRESS
AA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
WC
SDP
RESET
CE
DEVICE
UNPROTECTED
WE
Speed
90: 90ns
12: 120ns
15: 150ns
Doc. No. 1011, Rev. F
11
CAT28C64B
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
28C64B
N
I
-15
T
Optional Product
Company Number
ID
Temperature Range
Tape & Reel
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ to +105˚C)*
Package
Speed
P: PDIP
90: 90ns
12: 120ns
15: 150ns
J: SOIC (JEDEC)
K: SOIC (EIAJ)
N: PLCC
T13: TSOP (8mmx13.4mm)
L: PDIP (Lead free, Halogen free)
W: SOIC (JEDEC) (Lead free, Halogen free)
X: SOIC (EIAJ) (Lead free, Halogen free)
G: PLCC (Lead free, Halogen free)
H13: TSOP (8mmx13.4mm) (Lead free, Halogen free)
* -40˚C to +125˚C is available upon request
Notes:
(1) The device used in the above example is a CAT28C64BNI-15T (PLCC, Industrial temperature, 150 ns Access Time, Tape & Reel).
Doc. No. 1011, Rev. F
12
REVISION HISTORY
Date
Revision Comments
3/29/2004
B
Added Green packages in all areas.
Delete data sheet designation
Update Block Diagram
04/19/04
C
Update Ordering Information
Update Revision History
Update Rev Number
11/16/04
02/28/05
03/18/05
D
E
F
Add 90: 90ns speed to Ordering Information
Edit Ordering Information
Edit Description
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
Publication #: 1011
Revison:
F
Issue date:
03/18/05
www.catalyst-semiconductor.com
相关型号：
©2020 ICPDF网 联系我们和版权申明