CAT28C65BNA-12T 概述
64K-Bit CMOS PARALLEL EEPROM 64K位CMOS并行EEPROM EEPROM
CAT28C65BNA-12T 规格参数
是否Rohs认证: | 不符合 | 生命周期: | Transferred |
零件包装代码: | QFJ | 包装说明: | QCCJ, LDCC32,.5X.6 |
针数: | 32 | Reach Compliance Code: | unknown |
ECCN代码: | EAR99 | HTS代码: | 8542.32.00.51 |
风险等级: | 5.02 | Is Samacsys: | N |
最长访问时间: | 120 ns | 其他特性: | 100000 PROGRAM/ERASE CYCLES; DATA RETENTION = 100 YEARS |
命令用户界面: | NO | 数据轮询: | YES |
数据保留时间-最小值: | 100 | 耐久性: | 100000 Write/Erase Cycles |
JESD-30 代码: | R-PQCC-J32 | JESD-609代码: | e0 |
长度: | 13.965 mm | 内存密度: | 65536 bit |
内存集成电路类型: | EEPROM | 内存宽度: | 8 |
湿度敏感等级: | 3 | 功能数量: | 1 |
端子数量: | 32 | 字数: | 8192 words |
字数代码: | 8000 | 工作模式: | ASYNCHRONOUS |
最高工作温度: | 105 °C | 最低工作温度: | -40 °C |
组织: | 8KX8 | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | QCCJ | 封装等效代码: | LDCC32,.5X.6 |
封装形状: | RECTANGULAR | 封装形式: | CHIP CARRIER |
页面大小: | 32 words | 并行/串行: | PARALLEL |
峰值回流温度(摄氏度): | 240 | 电源: | 5 V |
编程电压: | 5 V | 认证状态: | Not Qualified |
就绪/忙碌: | YES | 座面最大高度: | 3.55 mm |
最大待机电流: | 0.0001 A | 子类别: | EEPROMs |
最大压摆率: | 0.03 mA | 最大供电电压 (Vsup): | 5.5 V |
最小供电电压 (Vsup): | 4.5 V | 标称供电电压 (Vsup): | 5 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | INDUSTRIAL | 端子面层: | Tin/Lead (Sn/Pb) |
端子形式: | J BEND | 端子节距: | 1.27 mm |
端子位置: | QUAD | 处于峰值回流温度下的最长时间: | 30 |
切换位: | YES | 宽度: | 11.425 mm |
最长写入周期时间 (tWC): | 5 ms | Base Number Matches: | 1 |
CAT28C65BNA-12T 数据手册
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CAT28C65B
64K-Bit CMOS PARALLEL EEPROM
TM
FEATURES
I Fast read access times:
I Commercial, industrial and automotive
– 90/120/150ns
temperature ranges
I Low power CMOS dissipation:
– Active: 25 mA max.
I Automatic page write operation:
– 1 to 32 bytes in 5ms
– Standby: 100 µA max.
– Page load timer
I Simple write operation:
I End of write detection:
– Toggle bit
– On-chip address and data latches
– Self-timed write cycle with auto-clear
– DATA polling
– RDY/BUSY
I Fast write cycle time:
– 5ms max
I 100,000 program/erase cycles
I 100 year data retention
I CMOS and TTL compatible I/O
I Hardware and software write protection
DESCRIPTION
The CAT28C65B is a fast, low power, 5V-only CMOS
parallel EEPROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling, a RDY/BUSY pin and Toggle status bits
signal the start and end of the self-timed write cycle.
Additionally, the CAT28C65B features hardware and
software write protection.
The CAT28C65B is manufactured using Catalyst’s
advancedCMOSfloatinggatetechnology.Itisdesigned
to endure 100,000 program/erase cycles and has a data
retentionof100years.ThedeviceisavailableinJEDEC-
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-
pin PLCC packages.
BLOCK DIAGRAM
8,192 x 8
EEPROM
ARRAY
ROW
DECODER
ADDR. BUFFER
& LATCHES
A –A
5
12
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
32 BYTE PAGE
REGISTER
V
CC
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
DATA POLLING,
TOGGLE BIT &
TIMER
RDY/BUSY LOGIC
I/O –I/O
0
7
ADDR. BUFFER
& LATCHES
A –A
COLUMN
DECODER
0
4
RDY/BUSY
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1009, Rev. E
1
CAT28C65B
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W) (K, X)
RDY/BUSY
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
RDY/BUSY
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
2
A
2
12
12
A
3
NC
A
3
NC
7
7
A
6
4
A
8
A
6
4
A
8
A
5
A
A
5
A
5
9
5
9
A
4
6
A
A
4
6
A
11
11
A
7
OE
A
7
OE
3
3
A
2
8
A
2
8
A
A
10
10
A
9
A
9
CE
CE
1
1
A
0
10
11
12
13
14
A
0
10
11
12
13
14
I/O
7
I/O
7
I/O
I/O
I/O
I/O
0
0
6
6
I/O
1
I/O
1
I/O
5
I/O
5
I/O
I/O
I/O
I/O
2
4
2
4
V
I/O
3
V
I/O
3
SS
SS
PLCC Package (N, G)
TSOP Package (8mm x 13.4mm) (T13, H13)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
10
A
A
A
NC
CE
I/O
I/O
I/O
I/O
I/O
11
9
8
7
6
5
4
3
WE
4
3 2 1 32 31 30
V
CC
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A
A
A
A
A
A
A
A
RDY/BUSY
GND
6
5
4
3
2
1
0
8
A
A
I/O
I/O
I/O
12
7
2
1
0
A
A
9
A
6
11
A
5
A
A
1
0
NC
OE
A
4
TOP VIEW
A
3
A
2
10
11
12
13
A
10
CE
NC
I/O
I/O
7
6
I/O
0
14 15 16 17 18 19 20
PIN FUNCTIONS
Pin Name
Function
Pin Name
WE
Function
Write Enable
A0–A12
I/O0–I/O7
CE
Address Inputs
Data Inputs/Outputs
Chip Enable
VCC
5 V Supply
Ground
VSS
OE
Output Enable
NC
No Connect
RDY/BSY
Ready/Busy Status
Doc. No. 1009, Rev. E
2
CAT28C65B
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on Any Pin with
Respect to Ground(2) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
105
Max.
Units
Cycles/Byte
Years
Test Method
(1)
NEND
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
100
(1)
VZAP
2000
100
Volts
(1)(4)
ILTH
mA
MODE SELECTION
Mode
CE
WE
OE
L
I/O
DOUT
DIN
Power
ACTIVE
ACTIVE
ACTIVE
STANDBY
ACTIVE
Read
L
L
H
Byte Write (WE Controlled)
Byte Write (CE Controlled)
Standby, and Write Inhibit
Read and Write Inhibit
H
L
X
H
H
DIN
H
X
X
High-Z
High-Z
H
CAPACITANCE T = 25°C, F = 1.0 MHZ, V
= 5V
A
CC
Symbol
Test
Max.
10
Units
pF
Conditions
(1)
CI/O
Input/Output Capacitance
Input Capacitance
VI/O = 0V
VIN = 0V
(1)
CIN
6
pF
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V +1V.
CC
Doc. No. 1009, Rev. E
3
CAT28C65B
D.C. OPERATING CHARACTERISTICS
VCC = 5V 10%, unless otherwise specified.
Limits
Symbol
Parameter
Min. Typ.
Max.
Units
Test Conditions
CE = OE = VIL,
f = 1/tRC min, All I/O’s Open
CE = OE = VILC
ICC
VCC Current (Operating, TTL)
30
mA
(1)
ICCC
VCC Current (Operating, CMOS)
25
mA
,
f = 1/tRC min, All I/O’s Open
ISB
VCC Current (Standby, TTL)
VCC Current (Standby, CMOS)
1
mA
CE = VIH, All I/O’s Open
(2)
ISBC
100
µA
CE = VIHC,
All I/O’s Open
ILI
Input Leakage Current
Output Leakage Current
–10
–10
10
10
µA
µA
VIN = GND to VCC
ILO
VOUT = GND to VCC
CE = VIH
,
(2)
VIH
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
2
VCC +0.3
0.8
V
V
V
V
V
(1)
VIL
–0.3
2.4
VOH
VOL
VWI
IOH = –400µA
0.4
IOL = 2.1mA
3.5
Note:
(1) V
(2) V
= –0.3V to +0.3V.
ILC
= V –0.3V to V +0.3V.
IHC
CC
CC
Doc. No. 1009, Rev. E
4
CAT28C65B
A.C. CHARACTERISTICS, Read Cycle
VCC = 5V 10%, unless otherwise specified.
28C65B-90
28C65B-12
28C65B-15
Symbol
tRC
Parameter
Read Cycle Time
Min. Max. Min. Max. Min. Max. Units
90
120
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCE
CE Access Time
90
90
50
120
120
60
150
150
70
tAA
Address Access Time
OE Access Time
tOE
(1)
tLZ
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
Output Hold from Address Change
0
0
0
0
0
0
(1)
tOLZ
(1)(2)
tHZ
50
50
50
50
50
50
(1)(2)
tOHZ
(1)
tOH
0
0
0
Figure 1. A.C. Testing Input/Output Waveform(3)
2.4 V
2.0 V
0.8 V
INPUT PULSE LEVELS
0.45 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
C
= 100 pF
L
C
INCLUDES JIG CAPACITANCE
L
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
(3) Input rise and fall times (10% and 90%) < 10 ns.
Doc. No. 1009, Rev. E
5
CAT28C65B
A.C. CHARACTERISTICS, Write Cycle
VCC = 5V 10%, unless otherwise specified.
28C65B-90
28C65B-12
28C65B-15
Symbol
tWC
Parameter
Write Cycle Time
Min. Max. Min. Max. Min. Max.
Units
ms
ns
5
5
5
tAS
Address Setup Time
Address Hold Time
CE Setup Time
0
100
0
0
100
0
0
100
0
tAH
ns
tCS
ns
tCH
CE Hold Time
0
0
0
ns
(2)
tCW
CE Pulse Time
110
0
110
0
110
0
ns
tOES
tOEH
OE Setup Time
ns
OE Hold Time
0
0
0
ns
(2)
tWP
OE Pulse Width
110
110
110
ns
tRB
tDS
tDH
WE Low to RDY/BUSY Low
Data Setup Time
120
120
120
ns
60
0
60
0
60
0
ns
Data Hold Time
ns
(1)
tINIT
Write Inhibit Period After Power-up
Byte Load Cycle Time
5
10
5
10
5
10
ms
µs
(1)(3)
tBLC
.05
100
.05
100
.05
100
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration t
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
BLC
however a transition from HIGH to LOW within t
max. stops the timer.
BLC
Doc. No. 1009, Rev. E
6
CAT28C65B
can be used to eliminate bus contention in a system
environment.
DEVICE OPERATION
Read
Byte Write
Data stored in the CAT28C65B is transferred to the data
bus when WE is held high, and both OE and CE are held
low. The data bus is set to a high impedance state when
eitherCEorOEgoeshigh.This2-linecontrolarchitecture
A write cycle is executed when both CE and WEare low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
Figure 3. Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
t
WE
LZ
t
OHZ
t
t
HZ
DATA VALID
t
OH
OLZ
HIGH-Z
DATA OUT
DATA VALID
t
AA
Figure 4. Byte Write Cycle [WE Controlled]
t
WC
ADDRESS
t
t
AH
AS
t
t
CH
CS
CE
OE
t
t
t
OEH
OES
WP
WE
t
t
BLC
RB
HIGH-Z
HIGH-Z
RDY/BUSY
HIGH-Z
DATA OUT
DATA IN
DATA VALID
DS
t
t
DH
Doc. No. 1009, Rev. E
7
CAT28C65B
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
cycle. This effectively reduces the byte-write time by a
factor of 32.
FollowinganinitialWRITEoperation(WEpulsedlow,for
t
WP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
anddatabytesintoa32bytetemporarybuffer. Thepage
address where data is to be written, specified by bits A5
to A12, is latched on the last falling edge of WE. Each
byte within the page is defined by address bits A0 to A4
Page Write
The page write mode of the CAT28C65B (essentially an
extended BYTE WRITE mode) allows from 1 to 32 bytes
ofdatatobeprogrammedwithinasingleEEPROMwrite
Figure 5. Byte Write Cycle [CE Controlled]
t
WC
ADDRESS
t
t
t
BLC
AS
AH
t
CW
CE
OE
WE
t
OEH
t
OES
t
t
CH
CS
t
RB
HIGH-Z
HIGH-Z
RDY/BUSY
DATA OUT
DATA IN
HIGH-Z
DATA VALID
DS
t
t
DH
Figure 6. Page Mode Write Cycle
OE
CE
WE
t
t
BLC
WP
ADDRESS
I/O
t
WC
LAST BYTE
BYTE n+2
BYTE 0 BYTE 1
BYTE 2
8
BYTE n
BYTE n+1
Doc. No. 1009, Rev. E
CAT28C65B
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within tBLC MAX of the rising edge of the
preceding WE pulse. There is no page write window
are indeterminate) until the programming cycle is
complete. Upon completion of the self-timed write cycle,
all I/O’s will output true data during a read cycle.
Toggle Bit
limitation as long as WE is pulsed low within tBLC MAX
.
In addition to the DATA Polling feature, the device offers
an additional method for determining the completion of
a write cycle. While a write cycle is in progress, reading
data from the device will result in I/O6 toggling between
one and zero. However, once the write is complete, I/O6
stops toggling and valid data can be read from the
device.
Upon completion of the page write sequence, WE must
stayhighaminimumoftBLCMAX fortheinternalautomatic
program cycle to commence. This programming cycle
consists of an erase cycle, which erases any data that
existed in each addressed cell, and a write cycle, which
writes new data back into the cell. A page write will only
write data to the locations that were addressed and will
not rewrite the entire page.
Ready/BUSY (RDY/BUSY)
The RDY/BUSY pin is an open drain output which
indicates device status during programming. It is pulled
low during the write cycle and released at the end of
programming. Several devices may be OR-tied to the
same RDY/BUSY line.
DATA Polling
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O7 (I/O0–I/O6
Figure 7. DATA Polling
ADDRESS
CE
WE
t
OEH
t
OES
t
OE
OE
t
WC
= X
I/O
D
= X
D
D
= X
OUT
7
IN
OUT
Figure 8. Toggle Bit
WE
CE
OE
t
OEH
t
OES
t
OE
(1)
(1)
I/O
6
t
WC
Doc. No. 1009, Rev. E
9
CAT28C65B
HARDWARE DATA PROTECTION
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
Thefollowingisalistofhardwaredataprotectionfeatures
that are incorporated into the CAT28C65B.
SOFTWARE DATA PROTECTION
(1) VCC sense provides for write protection when VCC
falls below 3.5V min.
The CAT28C65B features a software controlled data
protectionschemewhich, onceenabled, requiresadata
algorithmtobeissuedtothedevicebeforeawritecanbe
performed. The device is shipped from Catalyst with the
softwareprotectionNOTENABLED(theCAT28C65Bis
in the standard operating mode).
(2) A power on delay mechanism, tINIT (see AC
characteristics), provides a 5 to 10 ms delay before
a write sequence, after VCC has reached 3.5V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
Figure 9. Write Sequence for Activating Software
Data Protection
Figure 10. Write Sequence for Deactivating
Software Data Protection
WRITE DATA:
ADDRESS:
AA
WRITE DATA:
ADDRESS:
AA
1555
1555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
ADDRESS:
55
0AAA
0AAA
WRITE DATA:
ADDRESS:
A0
WRITE DATA:
ADDRESS:
80
1555
1555
WRITE DATA:
ADDRESS:
AA
SOFTWARE DATA
PROTECTION ACTIVATED
(1)
1555
WRITE DATA:
XX
WRITE DATA:
ADDRESS:
55
TO ANY ADDRESS
0AAA
WRITE LAST BYTE
TO
LAST ADDRESS
WRITE DATA:
ADDRESS:
20
1555
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
Max., after SDP activation.
BLC
Doc. No. 1009, Rev. E
10
CAT28C65B
Toactivatethesoftwaredataprotection,thedevicemust
besentthreewritecommandstospecificaddresseswith
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
writetimingspecifications(Figure11).Oncethisisdone,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequenceisissuedregardlessofpoweron/offtransitions.
This gives the user added inadvertent write protection
on power-up in addition to the hardware protection
provided.
To allow the user the ability to program the device with
anEEPROMprogrammer(orfortestingpurposes)there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
t
WC
DATA
ADDRESS
AA
1555
55
0AAA
A0
1555
BYTE OR
PAGE
CE
WRITES
ENABLED
t
t
BLC
WP
WE
Figure 12. Resetting Software Data Protection Timing
t
DATA
ADDRESS
AA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
WC
SDP
RESET
CE
DEVICE
UNPROTECTED
WE
Speed
90: 90ns
12: 120ns
15: 150ns
Doc. No. 1009, Rev. E
11
CAT28C65B
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
28C65B
N
I
-15
T
Optional
Company
ID
Product
Number
Temperature Range
Tape & Reel
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ to +105˚C)*
Package
Speed
P: PDIP
90: 90ns
12: 120ns
15: 150ns
J: SOIC (JEDEC)
K: SOIC (EIAJ)
N: PLCC
T13: TSOP (8mmx13.4mm)
L: PDIP (Lead free, Halogen free)
W: SOIC (JEDEC) (Lead free, Halogen free)
X: SOIC (EIAJ) (Lead free, Halogen free)
G: PLCC (Lead free, Halogen free)
H13: TSOP (Lead free, Halogen free)
* -40˚C to +125˚C is available upon request
Notes:
(1) The device used in the above example is a CAT28C65BNI-15T (PLCC, Industrial temperature, 150 ns Access Time, Tape & Reel).
Doc. No. 1009, Rev. E
12
REVISION HISTORY
Date
Revision Comments
03/29/04
04/19/04
B
C
Added Green packages in all areas.
Delete data sheet designation
Update Block Diagram
Update Ordering Information
Update Revision History
Update Rev Number
11/17/04
03/29/05
D
E
Added 90: 90ns speed to Ordering Information
Update A.C. Characteristics, Write Cycle
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Publication #: 1009
Revison:
E
Issue date:
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CAT28C65BNA-12T 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
CAT28C65BNA-15 | ONSEMI | 8KX8 EEPROM 5V, 150ns, PQCC32, PLASTIC, LCC-32 | 获取价格 | |
CAT28C65BNA-15 | CATALYST | EEPROM, 8KX8, 150ns, Parallel, CMOS, PQCC32, PLASTIC, LCC-32 | 获取价格 | |
CAT28C65BNA-15T | CATALYST | 64K-Bit CMOS PARALLEL EEPROM | 获取价格 | |
CAT28C65BNA-15T | ONSEMI | 8KX8 EEPROM 5V, 150ns, PQCC32, PLASTIC, LCC-32 | 获取价格 | |
CAT28C65BNA-20 | ETC | x8 EEPROM | 获取价格 | |
CAT28C65BNA-90T | CATALYST | 64K-Bit CMOS PARALLEL EEPROM | 获取价格 | |
CAT28C65BNA-90T | ONSEMI | IC 8K X 8 EEPROM 5V, 90 ns, PQCC32, PLASTIC, LCC-32, Programmable ROM | 获取价格 | |
CAT28C65BNI-12 | ONSEMI | 8KX8 EEPROM 5V, 120ns, PQCC32, PLASTIC, LCC-32 | 获取价格 | |
CAT28C65BNI-12T | CATALYST | 64K-Bit CMOS PARALLEL EEPROM | 获取价格 | |
CAT28C65BNI-12T | ONSEMI | 8KX8 EEPROM 5V, 120ns, PQCC32, PLASTIC, LCC-32 | 获取价格 |
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