CAT28F010TR-70T 概述
1 Megabit CMOS Flash Memory 1兆位的CMOS闪存 闪存
CAT28F010TR-70T 规格参数
是否Rohs认证: | 不符合 | 生命周期: | Transferred |
零件包装代码: | TSOP | 包装说明: | TSOP1-R, TSSOP32,.8,20 |
针数: | 32 | Reach Compliance Code: | unknown |
ECCN代码: | EAR99 | HTS代码: | 8542.32.00.51 |
风险等级: | 5.32 | Is Samacsys: | N |
最长访问时间: | 70 ns | 其他特性: | 100000 PROGRAM/ERASE CYCLES; DATA RETENTION = 10 YEARS |
命令用户界面: | YES | 数据轮询: | NO |
数据保留时间-最小值: | 10 | 耐久性: | 100000 Write/Erase Cycles |
JESD-30 代码: | R-PDSO-G32 | JESD-609代码: | e0 |
长度: | 18.4 mm | 内存密度: | 1048576 bit |
内存集成电路类型: | FLASH | 内存宽度: | 8 |
湿度敏感等级: | 2A | 功能数量: | 1 |
端子数量: | 32 | 字数: | 131072 words |
字数代码: | 128000 | 工作模式: | ASYNCHRONOUS |
最高工作温度: | 70 °C | 最低工作温度: | |
组织: | 128KX8 | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | TSOP1-R | 封装等效代码: | TSSOP32,.8,20 |
封装形状: | RECTANGULAR | 封装形式: | SMALL OUTLINE, THIN PROFILE |
并行/串行: | PARALLEL | 峰值回流温度(摄氏度): | 240 |
电源: | 5 V | 编程电压: | 12 V |
认证状态: | Not Qualified | 反向引出线: | YES |
座面最大高度: | 1.2 mm | 最大待机电流: | 0.0001 A |
子类别: | Flash Memories | 最大压摆率: | 0.03 mA |
最大供电电压 (Vsup): | 5.5 V | 最小供电电压 (Vsup): | 4.5 V |
标称供电电压 (Vsup): | 5 V | 表面贴装: | YES |
技术: | CMOS | 温度等级: | COMMERCIAL |
端子面层: | Tin/Lead (Sn/Pb) | 端子形式: | GULL WING |
端子节距: | 0.5 mm | 端子位置: | DUAL |
处于峰值回流温度下的最长时间: | 30 | 切换位: | NO |
类型: | NOR TYPE | 宽度: | 8 mm |
Base Number Matches: | 1 |
CAT28F010TR-70T 数据手册
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PDF下载CAT28F010
Licensed Intel
second source
1 Megabit CMOS Flash Memory
FEATURES
■ Commercial, Industrial and Automotive
■ Fast Read Access Time: 70/90/120 ns
Temperature Ranges
■ Low Power CMOS Dissipation:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)
■ On-Chip Address and Data Latches
■ JEDEC Standard Pinouts:
–32-pin DIP
–32-pin PLCC
–32-pin TSOP (8 x 20)
■ High Speed Programming:
–10 µs per byte
–2 Sec Typ Chip Program
■ 100,000 Program/Erase Cycles
■ 10 Year Data Retention
■ Electronic Signature
■ 0.5 Seconds Typical Chip-Erase
■ 12.0V ± 5% Programming and Erase Voltage
■ Stop Timer for Program/Erase
DESCRIPTION
using a two write cycle scheme. Address and Data are
latched to free the I/O bus and address bus during the
write operation.
TheCAT28F010isahighspeed128Kx8-bitelectrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
The CAT28F010 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
TSOP packages.
It is pin and Read timing compatible with standard
EPROM and E2PROM devices. Programming and
Erase are performed through an operation and verify
algorithm. The instructions are input via the I/O bus,
I/O –I/O
0
7
BLOCK DIAGRAM
I/O BUFFERS
ERASE VOLTAGE
SWITCH
WE
DATA
LATCH
SENSE
AMP
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
CE
OE
Y-GATING
Y-DECODER
1,048,576 BIT
MEMORY
ARRAY
A –A
16
0
X-DECODER
5108 FHD F02
VOLTAGE VERIFY
SWITCH
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25005-0A 2/98 F-1
1
CAT28F010
PIN CONFIGURATION
PIN FUNCTIONS
DIP Package (P)
Pin Name
Type
Function
V
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE
PP
A0–A16
Input
Address Inputs for
memory addressing
A
2
16
15
12
PLCC Package (N)
A
3
N/C
A
4
A
A
A
A
A
14
13
8
I/O0–I/O7
CE
I/O
Data Input/Output
Chip Enable
Output Enable
Write Enable
Voltage Supply
Ground
A
5
7
6
A
6
Input
Input
Input
4
3 2 1 32 31 30
A
7
5
9
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
0
14
13
8
A
8
OE
4
11
A
9
OE
3
A
WE
A
10
11
12
13
14
15
16
A
2
10
CE
A
9
A
1
A
11
VCC
A
I/O
I/O
I/O
I/O
I/O
0
7
6
5
4
3
10
11
12
13
A
OE
I/O
I/O
I/O
0
A
A
10
CE
VSS
1
A
2
I/O
I/O
VPP
Program/Erase
Voltage Supply
7
V
14 15 16 17 18 19 20
SS
5108 FHD F01
TSOP Package (Standard Pinout 8mm x 20mm) (T)
A
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
11
9
8
A
A
NC
I/O
I/O
I/O
I/O
I/O
13
14
7
6
5
4
3
WE
V
V
A
A
A
CC
PP
16
15
12
V
SS
I/O
I/O
I/O
2
1
0
A
A
A
A
A
A
A
A
7
6
5
4
0
1
2
3
TSOP Package (Reverse Pinout) (TR)
OE
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
A
A
A
NC
WE
V
V
A
A
A
A
A
A
A
11
9
8
13
14
A
CE
10
I/O
7
6
I/O
I/O
I/O
I/O
5
4
3
CC
9
V
SS
PP
16
15
12
7
6
5
4
10
11
12
13
14
15
16
I/O
I/O
I/O
A
A
A
2
1
0
0
1
2
3
A
5108 FHD F14
Doc. No. 25005-0A 2/98 F-1
2
CAT28F010
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................... –55°C to +95°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
Voltage on Pin A9 with
Respect to Ground(1) ................... –2.0V to +13.5V
VPP with Respect to Ground
during Program/Erase(1) .............. –2.0V to +14.0V
VCC with Respect to Ground(1) ............ –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
100K
10
Max.
Units
Cycles/Byte
Years
Test Method
(3)
NEND
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
100
Volts
(3)(4)
ILTH
mA
CAPACITANCE T = 25°C, f = 1.0 MHz
A
Limits
Max.
6
Symbol
Test
Min
Units
pF
Conditions
VIN = 0V
(3)
CIN
Input Pin Capacitance
Output Pin Capacitance
VPP Supply Capacitance
(3)
COUT
10
25
pF
VOUT = 0V
VPP = 0V
(3)
CVPP
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
Doc. No. 25005-0A 2/98 F-1
3
CAT28F010
D.C. OPERATING CHARACTERISTICS
V
= +5V ±10%, unless otherwise specified.
CC
Limits
Max.
±1
Symbol
Parameter
Min.
Unit
Test Conditions
ILI
Input Leakage Current
µA
VIN = VCC or VSS
VCC = 5.5V, OE = VIH
ILO
Output Leakage Current
±1
µA
µA
VOUT = VCC or VSS,
VCC = 5.5V, OE = VIH
ISB1
VCC Standby Current CMOS
100
CE = VCC ±0.5V,
VCC = 5.5V
ISB2
ICC1
VCC Standby Current TTL
VCC Active Read Current
1
mA
mA
CE = VIH, VCC = 5.5V
30
VCC = 5.5V, CE = VIL,
IOUT = 0mA, f = 6 MHz
(1)
ICC2
VCC Programming Current
VCC Erase Current
15
15
15
mA
mA
mA
VCC = 5.5V,
Programming in Progress
(1)
ICC3
VCC = 5.5V,
Erasure in Progress
(1)
ICC4
VCC Prog./Erase Verify Current
VCC = 5.5V, Program or
Erase Verify in Progress
IPPS
IPP1
VPP Standby Current
VPP Read Current
±10
200
30
µA
µA
VPP = VPPL
VPP = VPPH
(1)
IPP2
VPP Programming Current
mA
VPP = VPPH
,
Programming in Progress
(1)
IPP3
VPP Erase Current
30
5
mA
mA
VPP = VPPH,
Erasure in Progress
(1)
IPP4
VPP Prog./Erase Verify Current
VPP = VPPH, Program or
Erase Verify in Progress
VIL
Input Low Level TTL
–0.5
–0.5
0.8
0.8
V
V
VILC
VOL
VIH
Input Low Level CMOS
Output Low Level
0.45
V
IOL = 5.8mA, VCC = 4.5V
Input High Level TTL
Input High Level CMOS
Output High Level TTL
Output High Level CMOS
A9 Signature Voltage
A9 Signature Current
VCC Erase/Prog. Lockout Voltage
2
VCC+0.5
VCC+0.5
V
VIHC
VOH1
VOH2
VID
VCC*0.7
2.4
V
V
IOH = –2.5mA, VCC = 4.5V
IOH = –400µA, VCC = 4.5V
A9 = VID
VCC–0.4
11.4
V
13
V
(1)
IID
200
µA
V
A9 = VID
VLO
2.5
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25005-0A 2/98 F-1
4
CAT28F010
SUPPLY CHARACTERISTICS
Symbol
Limits
Parameter
Min
4.5
0
Max.
5.5
Unit
V
VCC
VCC Supply Voltage
VPPL
VPPH
VPP During Read Operations
6.5
V
VPP During Read/Erase/Program
11.4
12.6
V
A.C. CHARACTERISTICS, Read Operation
= +5V ±10%, unless otherwise specified.
V
CC
28F010-70(8) 28F010-90(7) 28F010-12(7)
Min. Max. Min. Max. Min. Max.
JEDEC Standard
Symbol Symbol Parameter
Unit
ns
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
CE Access Time
Address Access Time
OE Access Time
70
90
120
120
120
50
AVAV
ELQV
AVQV
GLQV
AXQX
RC
CE
70
70
28
90
90
35
ns
ns
ACC
OE
OH
ns
Output Hold from Address
OE/CE Change
0
0
0
ns
(1)(6)
OLZ
t
t
t
t
t
t
t
t
t
OE to Output in Low-Z
CE to Output in Low-Z
OE High to Output High-Z
CE High to Output High-Z
0
0
0
0
0
0
ns
ns
ns
ns
µs
GLQX
(1)(6)
ELZX
LZ
DF
DF
(1)(2)
(1)(2)
20
30
20
30
30
40
GHQZ
EHQZ
WHGL
(1)
-
Write Recovery Time
Before Read
6
6
6
(3)(4)(5)
Figure 2. Highspeed A.C. Testing Input/Output
Figure 1. A.C. Testing Input/Output Waveform
Waveform(3)(4)(5)
3.0 V
2.4 V
2.0 V
0.8 V
INPUT PULSE LEVELS
REFERENCE POINTS
INPUT PULSE LEVELS
1.5 V
REFERENCE POINTS
0.45 V
0.0 V
5108 FHD F03
5108 FHD F03A
Testing Load Circuit (example)
Testing Load Circuit (example)
1.3V
1.3V
1N914
1N914
3.3K
3.3K
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
OUT
OUT
C
= 100 pF
L
C
= 30 pF
L
C
INCLUDES JIG CAPACITANCE
5108 FHD F04
L
C
INCLUDES JIG CAPACITANCE
L
5108 FHD F05
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.
(5) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For load and reference points, see Fig. 1
(8) For load and reference points, see Fig. 2
Doc. No. 25005-0A 2/98 F-1
5
CAT28F010
A.C. CHARACTERISTICS, Read Operation
V
= +5V ±10%, unless otherwise specified.
CC
28F010-70
28F010-90
28F010-12
\JEDEC
Symbol
Standard
Symbol Parameter
Min. Max Min. Max. Min. Max. Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
70
0
90
0
120
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
AVAV
WC
AS
AH
DS
DH
CS
CH
WP
AVWL
WLAX
DVWH
WHDX
ELWL
40
40
10
0
40
40
10
0
40
40
10
0
CE Setup Time
CE Hold Time
0
0
0
WHEH
WLWH
WHWL
WHWH1
WHWH2
WHGL
WE Pulse Width
WE High Pulse Width
Program Pulse Width
Erase Pulse Width
40
20
10
9.5
40
20
10
9.5
40
20
10
9.5
WPH
(2)
(2)
-
-
Write Recovery Time
Before Read
-
6
6
6
µs
t
t
Read Recovery Time
Before Write
GHWL
-
-
0
0
0
µs
V
Setup Time to CE
100
100
100
ns
VPEL
PP
(1)
ERASE AND PROGRAMMING PERFORMANCE
28F010-55
28F010-70
28F010-90
28F010-12
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max Min. Typ. Max. Unit
(3)(5)
Chip Erase Time
0.5 10
12.5
0.5 10
12.5
0.5
2
10
0.5 10 Sec
12.5 Sec
(3)(4)
Chip Program Time
2
2
12.5
2
Note:
(1) Please refer to Supply characteristics for the value of VPPH and VPPL. The VPP supply can be either hardwired or switched. If VPP is
switched, VPPL can be ground, less than VCC + 2.0V or a no connect with a resistor tied to ground.
(2) Program and Erase operations are controlled by internal stop timers.
(3) ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V VPP
.
(4) Minimum byte programming time (excluding system overhead) is 16 µs (10 µs program + 6 µs write recovery), while maximum is 400 µs/
byte (16 µs x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since
most bytes program significantly faster than the worst case byte.
(5) Excludes 00H Programming prior to Erasure.
Doc. No. 25005-0A 2/98 F-1
6
CAT28F010
(1)
FUNCTION TABLE
Pins
WE
VIH
Mode
Read
CE
VIL
VIL
VIH
VIL
VIL
VIL
VIL
VIL
OE
VIL
VIH
X
VPP
VPPL
X
I/O
DOUT
High-Z
High-Z
31H
Notes
Output Disable
Standby
VIH
X
VPPL
X
Signature (MFG)
Signature (Device)
Program/Erase
Write Cycle
VIL
VIL
VIH
VIH
VIL
VIH
VIH
VIL
VIL
VIH
A0 = VIL, A9 = 12V
A0 = VIH, A9 = 12V
See Command Table
During Write Cycle
During Write Cycle
X
B4H
VPPH
VPPH
VPPH
DIN
DIN
Read Cycle
DOUT
WRITE COMMAND TABLE
Commands are written into the command register in one or two write cycles. The command register can be altered
only when V is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch
PP
addresses and data required for programming and erase operations.
Pins
First Bus Cycle
Second Bus Cycle
Mode
Set Read
Operation
Address
DIN
00H
90H
90H
20H
A0H
40H
C0H
FFH
Operation
Read
Address
DIN
DOUT
DOUT
31H
Write
Write
Write
Write
Write
Write
Write
Write
X
X
AIN
00
01
X
Read Sig. (MFG)
Read Sig. (Device)
Erase
Read
X
Read
B4H
X
Write
20H
DIN
Erase Verify
Program
AIN
X
Read
X
DOUT
Write
AIN
X
Program Verify
Reset
X
Read
DOUT
X
Write
X
FFH
Note:
(1) Logic Levels: X = Logic ‘Do not care’ (VIH, VIL, VPPL, VPPH
)
Doc. No. 25005-0A 2/98 F-1
7
CAT28F010
READ OPERATIONS
Read Mode
The conventional mode is entered as a regular READ
mode by driving the CE and OE pins low (with WE high),
andapplyingtherequiredhighvoltageonaddresspinA9
while all other address lines are held at VIL.
A Read operation is performed with both CE and OE low
and with WE high. VPP can be either high or low,
however, if VPP is high, the Set READ command has to
be sent before reading data (see Write Operations). The
data retrieved from the I/O pins reflects the contents of
thememorylocationcorrespondingtothestateofthe17
address pins. The respective timing waveforms for the
read operation are shown in Figure 3. Refer to the AC
Read characteristics for specific timing parameters.
A Read cycle from address 0000H retrieves the binary
code for the IC manufacturer on outputs I/O0 to I/O7:
CATALYST Code = 00110001 (31H)
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O7.
Signature Mode
The signature mode allows the user to identify the IC
manufacturer and the type of device while the device
residesinthetargetsystem. Thismodecanbeactivated
in either of two ways; through the conventional method
of applying a high voltage (12V) to address pin A9 or by
sending an instruction to the command register (see
Write Operations).
28F010 Code = 1011 0100 (B4H)
Standby Mode
With CE at a logic-high level, the CAT28F010 is placed
in a standby mode where most of the device circuitry is
disabled, thereby substantially reducing power con-
sumption. The outputs are placed in a high-impedance
state.
Figure 3. A.C. Timing for Read Operation
STANDBY
DEVICE AND
OUPUTS
DATA VALID
STANDBY
POWER DOWN
POWER UP
ADDRESS SELECTION
ENABLED
ADDRESS STABLE
ADDRESSES
CE (E)
t
(t
)
AVAV RC
t
t(
)
)
EHQZ DF
OE (G)
t
t
(t
WHGL
GHQZ DF
t
(t
)
WE (W)
GLQV OE
t
(t
)
ELQV CE
t
t(
)
AXQX OH
t
(t
)
GLQX OLZ
t
(t
)
ELQX LZ
HIGH-Z
HIGH-Z
OUTPUT VALID
DATA (I/O)
t
(t
)
AVQV ACC
28F010 F05
Doc. No. 25005-0A 2/98 F-1
8
CAT28F010
Signature Mode
WRITE OPERATIONS
An alternative method for reading device signature (see
Read Operations Signature Mode), is initiated by writing
the code 90H into the command register while keeping
VPP high. A read cycle from address 0000H with CE and
OE low (and WE high) will output the device signature.
The following operations are initiated by observing the
sequence specified in the Write Command Table.
Read Mode
The device can be put into a standard READ mode by
initiating a write cycle with 00H on the data bus. The
subsequent read cycles will be performed similar to a
standard EPROM or E2PROM Read.
CATALYST Code = 00110001 (31H)
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O7.
28F010 Code = 1011 0100 (B4H)
Figure 4. A.C. Timing for Erase Operation
SETUP ERASE
COMMAND
ERASE
COMMAND
ERASING
ERASE VERIFY
COMMAND
ERASE
VERIFICATION
V
POWER-DOWN/
STANDBY
V
POWER-UP
CC
CC
& STANDBY
ADDRESSES
t
t
t
t
WC
WC
WC
RC
t
AS
t
AH
CE (E)
t
t
CH
CS
t
t
CH
EHQZ
t
t
CS
CH
OE (G)
t
GHWL
t
t
t
WHGL
DF
WHWH2
t
WPH
WE (W)
t
t
t
t
WP
WP
WP
OE
t
t
t
t
DH
DH
DH
OH
t
t
t
t
DS
DS
OLZ
DS
HIGH-Z
DATA IN
= 20H
DATA IN
= 20H
DATA IN
= A0H
DATA (I/O)
VALID
DATA OUT
t
LZ
t
CE
5.0V
0V
V
CC
t
VPEL
V
V
PPH
PPL
V
PP
28F010 F11
Doc. No. 25005-0A 2/98 F-1
9
CAT28F010
(1)
Figure 5. Chip Erase Algorithm
BUS
OPERATION
START ERASURE
COMMAND
COMMENTS
RAMPS TO V
V
PP
(OR V
PPH
APPLY V
PPH
HARDWIRED)
PP
ALL BYTES SHALL BE
PROGRAMMED TO 00
BEFORE AN ERASE
OPERATION
PROGRAM ALL
BYTES TO 00H
STANDBY
INITIALIZE
ADDRESS
INITIALIZE ADDRESS
INITIALIZE
PLSCNT = 0
PLSCNT = PULSE COUNT
WRITE ERASE
SETUP COMMAND
WRITE
WRITE
ERASE
ERASE
DATA = 20H
WRITE ERASE
COMMAND
DATA = 20H
WAIT
TIME OUT 10ms
ADDRESS = BYTE TO VERIFY
WRITE ERASE
VERIFY COMMAND
ERASE
VERIFY
WRITE
DATA =
A0H
STOPS ERASE OPERATION
TIME OUT 6µs
WAIT
INCREMENT
ADDRESS
READ DATA
FROM DEVICE
READ
READ BYTE TO
VERIFY ERASURE
NO
NO
DATA =
FFH?
INC PLSCNT
1000
= ?
COMPARE OUTPUT TO FF
INCREMENT PULSE COUNT
STANDBY
YES
YES
LAST
NO
ADDRESS?
YES
DATA = 00H
RESETS THE REGISTER
FOR READ OPERATION
WRITE READ
COMMAND
WRITE
READ
V
RAMPS TO V
PPL
PP
(OR V
APPLY V
PPL
APPLY V
PPL
STANDBY
HARDWIRED)
PP
ERASURE
COMPLETED
ERASE
ERROR
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
5108 FHD F10
Doc. No. 25005-0A 2/98 F-1
10
CAT28F010
Erase Mode
Erase-Verify Mode
During the first Write cycle, the command 20H is written
into the command register. In order to commence the
eraseoperation, theidenticalcommandof20Hhastobe
written again into the register. This two-step process
ensures against accidental erasure of the memory con-
tents. The final erase cycle will be stopped at the rising
edge of WE, at which time the Erase Verify command
(A0H)issenttothecommandregister. Duringthiscycle,
the address to be verified is sent to the address bus and
latched when WE goes low. An integrated stop timer
allows for automatic timing control over this operation,
eliminating the need for a maximum erase timing speci-
fication. Refer to AC Characteristics (Program/Erase)
for specific timing parameters.
The Erase-verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.
Programming Mode
The programming operation is initiated using the pro-
gramming algorithm of Figure 7. During the first write
cycle, the command 40H is written into the command
register. During the second write cycle, the address of
thememorylocationtobeprogrammedislatchedonthe
falling edge of WE, while the data is latched on the rising
edge of WE. The program operation terminates with the
next rising edge of WE. An integrated stop timer allows
forautomatictimingcontroloverthisoperation, eliminat-
ing the need for a maximum program timing specifica-
tion. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.
Figure 6. A.C. Timing for Programming Operation
SETUP PROGRAM LATCH ADDRESS
POWER-UP
PROGRAM
VERIFY
COMMAND
PROGRAM
VERIFICATION
V
POWER-DOWN/
STANDBY
V
CC
CC
& STANDBY
COMMAND
& DATA
PROGRAMMING
ADDRESSES
t
t
t
WC
WC
RC
t
t
AS
AH
CE (E)
t
t
CH
CS
t
t
CH
EHQZ
t
t
CS
CH
OE (G)
t
GHWL
t
t
t
WHGL
DF
WHWH1
t
WPH
WE (W)
t
t
t
t
WP
WP
WP
OE
t
t
t
t
DH
DH
DH
OH
t
t
t
t
DS
DS
OLZ
DS
HIGH-Z
DATA IN
= 40H
DATA IN
= C0H
DATA (I/O)
DATA IN
VALID
DATA OUT
t
LZ
t
CE
5.0V
0V
V
CC
t
VPEL
V
V
PPH
PPL
V
PP
28F010 F08
Doc. No. 25005-0A 2/98 F-1
11
CAT28F010
(1)
Figure 7. Programming Algorithm
START
PROGRAMMING
BUS
OPERATION
COMMAND
COMMENTS
RAMPS TO V
V
APPLY V
PPH
PP
(OR V
PPH
STANDBY
HARDWIRED)
PP
INITIALIZE
ADDRESS
INITIALIZE ADDRESS
INITIALIZE PULSE COUNT
PLSCNT = PULSE COUNT
PLSCNT = 0
WRITE SETUP
PROG. COMMAND
1ST WRITE
CYCLE
WRITE
SETUP
DATA = 40H
WRITE PROG. CMD
ADDR AND DATA
2ND WRITE
CYCLE
PROGRAM VALID ADDRESS AND DATA
TIME OUT 10µs
WAIT
WRITE PROGRAM
VERIFY COMMAND
1ST WRITE
CYCLE
PROGRAM
DATA = C0H
VERIFY
TIME OUT 6µs
WAIT
READ DATA
FROM DEVICE
READ BYTE TO VERIFY
PROGRAMMING
READ
NO
INC
PLSCNT
= 25 ?
NO
VERIFY
DATA ?
COMPARE DATA OUTPUT
TO DATA EXPECTED
STANDBY
YES
YES
LAST
ADDRESS?
NO
INCREMENT
ADDRESS
YES
DATA = 00H
SETS THE REGISTER FOR
READ OPERATION
WRITE READ
COMMAND
1ST WRITE
CYCLE
READ
V
RAMPS TO V
APPLY V
PPL
APPLY V
PPL
PP
(OR V
PPL
STANDBY
HARDWIRED)
PP
PROGRAMMING
COMPLETED
PROGRAM
ERROR
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
5108 FHD F06
Doc. No. 25005-0A 2/98 F-1
12
CAT28F010
Program-Verify Mode
POWER UP/DOWN PROTECTION
A Program-verify cycle is performed to ensure that all
bits have been correctly programmed following each
byte programming operation. The specific address is
already latched from the write cycle just completed, and
stayslatcheduntiltheverifyiscompleted. TheProgram-
verify operation is initiated by writing C0H into the
command register. An internal reference generates the
necessary high voltages so that the user does not need
to modify VCC. Refer to AC Characteristics (Program/
Erase) for specific timing parameters.
The CAT28F010 offers protection against inadvertent
programming during VPP and VCC power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, VPP and VCC
may power up in any order. Additionally VPP may be
hardwired to VPPH independent of the state of VCC and
any power up/down cycling. The internal command
register of the CAT28F010 is reset to the Read Mode on
power up.
Abort/Reset
POWER SUPPLY DECOUPLING
An Abort/Reset command is available to allow the user
to safely abort an erase or program sequence. Two
consecutive program cycles with FFH on the data bus
will abort an erase or a program operation. The abort/
reset operation can interrupt at any time in a program or
erase operation and the device is reset to the Read
Mode.
To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1µF ceramic
capacitorbetweenVCC andVSS andVPP andVSS.These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.
Figure 8. Alternate A.C. Timing for Program Operation
SETUP PROGRAM LATCH ADDRESS
POWER-UP
PROGRAM
VERIFY
COMMAND
PROGRAM
VERIFICATION
V
POWER-DOWN/
STANDBY
V
CC
CC
& STANDBY
COMMAND
& DATA
PROGRAMMING
ADDRESSES
t
t
t
WC
WC
RC
t
t
ELAX
AVEL
(W)
WE
t
t
WLEL
EHWH
t
t
t
WLEL
EHWH
EHQZ
t
t
WLEL
EHWH
OE (G)
t
t
t
t
EHEH
EHGL
DF
GHEL
t
EHEL
CE
(E)
t
t
t
ELEH
ELEH
EHDX
OE
t
t
t
t
t
EHDX
EHDX
OLZ
OH
t
t
t
DVEH
DVEH
DVEH
HIGH-Z
DATA IN
= 40H
DATA IN
= C0H
DATA (I/O)
DATA IN
VALID
DATA OUT
t
LZ
t
CE
5.0V
0V
V
CC
t
VPEL
V
V
PPH
PPL
V
PP
28F010 F10
Doc. No. 25005-0A 2/98 F-1
13
CAT28F010
A.C. CHARACTERISTICS, Read Operation
V
= +5V ±10%, unless otherwise specified.
CC
28F010-70
28F010-90
28F010-12
JEDEC
Symbol
Standard
Symbol Parameter
Min. Max Min. Max Min. Max. Unit
t
t
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
70
0
90
0
120
0
ns
ns
ns
ns
ns
AVAV
WC
t
t
AS
AVEL
t
t
AH
40
40
10
40
40
10
40
40
10
ELAX
t
t
DS
DVEH
t
t
DH
EHDX
t
Write Recovery Time
Before Read
EHGL
-
0
0
0
µs
t
Read Recovery Time
Before Write
GHEL
-
0
0
0
0
0
0
µs
ns
ns
ns
ns
ns
t
t
WE Setup time Before CE
WE Hold Time After CE
Write Pulse Width
WLEL
WS
t
0
0
0
EHWH
-
t
t
t
40
20
40
20
100
40
20
100
ELEH
CP
t
Write Pulse Width High
EHEL
CPH
t
-
V
PP
Setup Time to CE Low 100
VPEL
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
28F010
N
-90
I
T
Product
Number
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
Tape & Reel
T: 500/Reel
A = Automotive (-40˚C to +105˚C)*
Optional
Company ID
Package
Speed
N: PLCC
70: 70ns
90: 90ns
P: PDIP
T: TSOP (8mmx20mm)
TR: TSOP (Reverse Pinout)
12: 120ns
28F010 F12
* -40˚ to +125˚ is available upon request.
Note:
(1) The device used in the above example is a CAT28F010NI-90T(PLCC, Industrial Temperature, 90 ns access time, Tape & Reel).
Doc. No. 25005-0A 2/98 F-1
14
CAT28F010TR-70T 相关器件
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CAT28F010TR-90 | ONSEMI | 128KX8 FLASH 12V PROM, 90ns, PDSO32, 8 X 20 MM, REVERSE, TSOP-32 | 获取价格 | |
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CAT28F010TR-90T | ONSEMI | IC 128K X 8 FLASH 12V PROM, 90 ns, PDSO32, 8 X 20 MM, REVERSE, TSOP-32, Programmable ROM | 获取价格 | |
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CAT28F010TR-90TE7 | ONSEMI | IC 128K X 8 FLASH 12V PROM, 90 ns, PDSO32, 8 X 20 MM, REVERSE, TSOP-32, Programmable ROM | 获取价格 | |
CAT28F010TR1412 | CATALYST | Memory IC | 获取价格 | |
CAT28F010TR14I12 | CATALYST | Memory IC | 获取价格 | |
CAT28F010TRA-12 | ONSEMI | 128KX8 FLASH 12V PROM, 120ns, PDSO32, 8 X 20 MM, REVERSE, TSOP-32 | 获取价格 | |
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