CAT28F102NI-12T [CATALYST]
Flash, 64KX16, 120ns, PQCC44, PLASTIC, LCC-44;
| 型号： | CAT28F102NI-12T |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | Flash, 64KX16, 120ns, PQCC44, PLASTIC, LCC-44 内存集成电路 |
| 文件： | 总15页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Main Menu
CAT28F102
Licensed Intel
second source
1 Megabit CMOS Flash Memory
FEATURES
■ 64K x 16 Word Organization
■ Fast Read Access Time: 100/120 ns
■ Stop Timer for Program/Erase
■ Low Power CMOS Dissipation:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)
■ On-Chip Address and Data Latches
■ JEDEC Standard Pinouts:
–40-pin DIP
■ High Speed Programming:
–10 µs per byte
–44-pin PLCC
–40-pin TSOP
–1 Sec Typ Chip Program
■ 100,000 Program/Erase Cycles
■ 10 Year Data Retention
■ Electronic Signature
■ 0.5 Seconds Typical Chip-Erase
■ 12.0V ± 5% Programming and Erase Voltage
■ Commercial,Industrial and Automotive
Temperature Ranges
DESCRIPTION
write cycle scheme. Address and Data are latched to
free the I/O bus and address bus during the write
operation.
TheCAT28F102isahighspeed64Kx16-bitelectrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
The CAT28F102 is manufactured using Catalyst’s
advancedCMOSfloatinggatetechnology.Itisdesigned
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 40-pin DIP, 44-pin PLCC, or 40-pin TSOP
packages.
It is pin and Read timing compatible with standard
EPROMandE2PROMdevices.ProgrammingandErase
areperformedthroughanoperationandverifyalgorithm.
The instructions are input via the I/O bus, using a two
I/O –I/O
BLOCK DIAGRAM
0
15
I/O BUFFERS
ERASE VOLTAGE
SWITCH
WE
DATA
LATCH
SENSE
AMP
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
CE
OE
Y-GATING
Y-DECODER
1,048,576-BIT
MEMORY
ARRAY
A –A
15
0
X-DECODER
VOLTAGE VERIFY
SWITCH
Doc. No. 1014, Rev. A
© 2001 by Catalyst Semiconductor, Inc.
1
Characteristics subject to change without notice
Main Menu
CAT28F102
PIN CONFIGURATION
PIN FUNCTIONS
Pin Name
Type
Function
A0–A15
Input
Address Inputs for
memory addressing
I/O0–I/O15
CE
I/O
Data Input/Output
Chip Enable
Output Enable
Write Enable
Voltage Supply
Ground
PLCC Package (N)
Input
Input
Input
OE
WE
6
5 4 3 2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
A
A
A
A
A
V
I/O
12
7
13
12
11
10
9
VCC
I/O
8
11
10
I/O
9
VSS
I/O
10
11
12
13
14
15
16
17
9
8
VPP
Program/Erase
Voltage Supply
I/O
V
SS
SS
NC
NC
NC
No Connect
A
8
A
7
A
6
A
5
I/O
7
I/O
I/O
I/O
6
5
4
18 19 20 21 22 23 24 25 26 27 28
TSOP Package (T14)
A
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
A
A
A
A
A
A
9
SS
8
7
6
5
4
3
2
A
10
A
11
12
13
14
15
A
A
A
A
NC
A
WE
9
A
A
1
V
V
10
11
12
13
14
15
16
17
18
19
20
0
CC
PP
CE
OE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O
15
14
13
12
I/O
I/O
I/O
DIP Package (P)
I/O
I/O
11
10
V
1
40
39
38
37
36
35
34
33
32
31
V
PP
CE
CC
I/O
9
2
WE
NC
I/O
8
V
SS
I/O
3
15
14
13
12
4
A
I/O
I/O
I/O
15
5
A
14
6
A
Reverse TSOP Package (T14R)
13
7
A
I/O
12
11
10
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
9
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OE
0
1
2
3
4
5
6
8
A
I/O
11
I/O
0
I/O
I/O
I/O
I/O
1
2
3
4
9
A
I/O
10
9
8
10
11
12
13
14
15
16
17
18
A
9
I/O
V
V
30
29
I/O
I/O
I/O
SS
SS
5
6
7
A
A
7
8
A
8
I/O
7
6
5
4
3
2
1
0
10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
28
27
26
25
24
23
22
21
A
7
A
6
GND
GND
A
11
12
13
14
15
16
17
18
19
20
I/O
8
9
A
A
10
I/O
I/O
I/O
I/O
I/O
I/O
9
11
A
5
A
4
A
3
A
2
10
11
12
13
14
A
A
A
12
13
14
15
A
NC
WE
I/O
V
PP
CE
15
19
20
A
1
A
0
V
CC
OE
Doc. No. 1014, Rev. A
2
Main Menu
CAT28F102
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +105°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ........... –0.6V to +VCC + 2.0V
Voltage on Pin A9 with
Respect to Ground(1) ................... –2.0V to +13.5V
VPP with Respect to Ground
during Program/Erase(1) .............. –0.6V to +14.0V
V
CC with Respect to Ground(1) ............ –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
100K
10
Max.
Units
Cycles/Byte
Years
Test Method
(3)
NEND
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
100
Volts
(3)(4)
ILTH
mA
CAPACITANCE T = 25°C, f = 1.0 MHz
A
Limits
Max.
6
Symbol
Test
Min
Units
pF
Conditions
VIN = 0V
(3)
CIN
Input Pin Capacitance
Output Pin Capacitance
VPP Supply Capacitance
(3)
COUT
10
25
pF
VOUT = 0V
VPP = 0V
(3)
CVPP
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
Doc. No. 1014, Rev. A
3
Main Menu
CAT28F102
D.C. OPERATING CHARACTERISTICS
V
CC
= +5V ±10%, unless otherwise specified
Limits
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
ILI
Input Leakage Current
±1
µA
VIN = VCC or VSS
VCC = 5.5V, OE = VIH
ILO
Output Leakage Current
±1
µA
µA
VOUT = VCC or VSS,
VCC = 5.5V, OE = VIH
ISB1
VCC Standby Current CMOS
100
CE = VCC ±0.5V,
VCC = 5.5V
ISB2
ICC1
VCC Standby Current TTL
VCC Active Read Current
1
mA
mA
CE = VIH, VCC = 5.5V
50
VCC = 5.5V, CE = VIL,
IOUT = 0mA, f = 6 MHz
(1)
ICC2
VCC Programming Current
VCC Erase Current
30
30
30
mA
mA
mA
VCC = 5.5V,
Programming in Progress
(1)
ICC3
VCC = 5.5V,
Erasure in Progress
(1)
ICC4
VCC Prog./Erase Verify Current
VCC = 5.5V, Program or
Erase Verify in Progress
IPPS
IPP1
VPP Standby Current
VPP Read Current
±10
100
50
µA
µA
VPP = VPPL
VPP = VPPH
(1)
IPP2
VPP Programming Current
mA
VPP = VPPH
,
Programming in Progress
(1)
IPP3
VPP Erase Current
30
5
mA
mA
VPP = VPPH,
Erasure in Progress
(1)
IPP4
VPP Prog./Erase Verify Current
VPP = VPPH, Program or
Erase Verify in Progress
VIL
Input Low Level TTL
–0.5
–0.5
0.8
0.8
V
V
VILC
VOL
VIH
Input Low Level CMOS
Output Low Level
0.45
V
IOL = 5.8mA, VCC = 4.5V
Input High Level TTL
Input High Level CMOS
Output High Level TTL
Output High Level CMOS
A9 Signature Voltage
A9 Signature Current
VCC Erase/Prog. Lockout Voltage
2
VCC+0.5
VCC+0.5
V
VIHC
VOH1
VOH2
VID
VCC*0.7
2.4
V
V
IOH = –2.5mA, VCC = 4.5V
IOH = –400µA, VCC = 4.5V
A9 = VID
VCC-0.4
11.4
V
13.0
200
V
(1)
IID
µA
V
A9 = VID
VLO
2.5
Supply Characteristics
V
V
V
V
Supply Voltage
4.5
0
5.5
6.5
V
V
V
CC
CC
V
During Read Operations
During Read/Erase/Program
PPL
PPH
PP
V
11.4
12.6
PP
Doc. No. 1014, Rev. A
4
Main Menu
A.C. CHARACTERISTICS, Read Operation
CAT28F102
VCC = +5V ±10%, unless otherwise specified
(7)
JEDEC
Symbol
Standard
Symbol
28F102- 10
Min.
28F102- 12
Parameter
Max.
Min.
Max.
Unit
ns
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
CE Access Time
Address Access Time
OE Access Time
100
120
AVAV
ELQV
AVQV
GLQV
AXQX
RC
CE
100
120
120
50
ns
100
45
ns
ACC
OE
OH
ns
Output Hold from Address
0
0
ns
OE/CE Chan
(1)(6)
OLZ
t
t
t
t
t
t
t
t
OE to Output in Low-Z
CE to Output in Low-Z
OE High to Output High-Z
CE High to Output High-Z
0
0
0
0
ns
ns
ns
ns
µs
GLQX
ELQX
GHQZ
EHQZ
(1)(6)
LZ
(1)(2)
-
25
35
30
40
DF
(1)(2)
Write Recovery Time Before
Read
6
WHGL
(3)(4)(5)
Figure 1. A.C. Testing Input/Output Waveform
2.4 V
2.0 V
INPUT PULSE LEVELS
0.45 V
REFERENCE POINTS
0.8 V
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
C
= 100 pF
L
C
INCLUDES JIG CAPACITANCE
L
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V. For high speed input pulse levels 0.0V and 3.0V.
(5) Input and Output Timing Reference = 0.8V and 2.0V. For high speed input and output timing reference=1.5V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For Load and Reference Points see Figures 1 and 2
Doc. No. 1014, Rev. A
5
Main Menu
CAT28F102
A.C. CHARACTERISTICS, Program/Erase Operation
= +5V ±10%, unless otherwise specified.
V
CC
JEDEC
Symbol
tAVAV
Standard
Symbol
tWC
28F102-10
28F102-12
Parameter
Min. Max. Min. Max. Unit
Write Cycle Time
100
0
120
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
µs
tAVWL
tWLAX
tDVWH
tWHDX
tELWL
tWHEH
tWLWH
tWHWL
tAS
tAH
tDS
tDH
tCS
tCH
tWP
tWPH
-
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
40
40
10
0
40
40
10
0
CE Setup Time
CE Hold Time
0
0
WE Pulse Width
WE High Pulse Width
Program Pulse Width
Erase Pulse Width
40
20
10
9.5
6
40
20
10
9.5
6
(2)
tWHWH1
tWHWH2
tWHGL
(2)
-
-
Write Recovery Time
Before Read
tGHWL
tVPEL
-
-
Read Recovery Time
Before Write
0
0
µs
VPP Setup Time to CE
100
100
ns
(1)
Erase and Programming Performance
28F102-10
28F102-10
Parameter
Min. Typ. Max. Min. Typ. Max. Unit
(3)(5)
Chip Erase Time
0.5
1
10
0.5
1
10
sec
sec
(3)(4)
Chip Program Time
6.5
6.5
Note:
(1) Please refer to Supply characteristics for the value of V
and V
. The V supply can be either hardwired or switched. If V is
PPL PP PP
PPH
switched, V
can be ground, less than V + 2.0V or a no connect with a resistor tied to ground.
PPL
CC
(2) Program and Erase operations are controlled by internal stop timers.
(3) ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V V
.
PP
(4) Minimum byte programming time (excluding system overhead) is 16 µs (10 µs program + 6 µs write recovery), while maximum is 400 µs/
byte (16 µs x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since
most bytes program significantly faster than the worst case byte.
(5) Excludes 00H Programming prior to Erasure.
Doc. No. 1014, Rev. A
6
Main Menu
CAT28F102
(1)
FUNCTION TABLE
Pins
WE
VIH
Mode
Read
CE
VIL
VIL
VIH
VIL
VIL
VIL
VIL
VIL
VIL
VIH
OE
VIL
VIH
X
VPP
VPPL
X
I/O
Notes
DOUT
High-Z
High-Z
0031H
0051H
DIN
Output Disable
Standby
VIH
X
VPPL
VPPL
X
Signature (MFG)
Signature (Device)
Program/Erase
Write Cycle
VIL
VIL
VIH
VIH
VIL
VIH
X
VIH
VIH
VIL
VIL
VIH
VIH
X
A0 = VIL, A9 = 12V
A0 = VIH, A9 = 12V
See Command Table
During Write Cycle
During Write Cycle
During Write Cycle
During Write Cycle
VPPH
VPPH
VPPH
VPPH
VPPH
DIN
Read Cycle
DOUT
High-Z
High-Z
Output Disable
Standby
WRITE COMMAND TABLE
Commands are written into the command register in one or two write cycles. The command register can be altered
only when V is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch
PP
addresses and data required for programming and erase operations.
Pins
First Bus Cycle
Second Bus Cycle
Mode
Set Read
Operation
Address
DIN
Operation
Read
Address
DIN
DOUT
DOUT
Write
Write
Write
Write
Write
Write
Write
Write
X
X
XX00H
XX90H
XX90H
XX20H
XXA0H
XX40H
XXC0H
XXFFH
AIN
0000
0001
X
Read Sig. (MFG)
Read Sig. (Device)
Erase
Read
0031H
0051H
X
Read
X
Write
XX20H
DIN
Erase Verify
Program
AIN
X
Read
X
DOUT
Write
AIN
X
Program Verify
Reset
X
Read
DOUT
X
Write
X
XXFFH
Note:
(1) Logic Levels: X = Logic ‘Do not care’ (V , V , V
, V )
PPH
IH
IL
PPL
Doc. No. 1014, Rev. A
7
Main Menu
CAT28F102
READ OPERATIONS
Read Mode
The conventional mode is entered as a regular READ
mode by driving the CE and OE pins low (with WE high),
andapplyingtherequiredhighvoltageonaddresspinA9
while all other address lines are held at VIL.
A Read operation is performed with both CE and OE low
and with WE high. VPP can be either high or low,
however, if VPP is high, the Set READ command has to
be sent before reading data (see Write Operations). The
data retrieved from the I/O pins reflects the contents of
thememorylocationcorrespondingtothestateofthe16
address pins. The respective timing waveforms for the
read operation are shown in Figure 5. Refer to the AC
Read characteristics for specific timing parameters.
A Read cycle from address 0000H retrieves the binary
code for the IC manufacturer on outputs I/O0 to I/O15:
CATALYST Code = 0000 0000 0011 0001 (0031H)
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O15.
Signature Mode
The signature mode allows the user to identify the IC
manufacturer and the type of device while the device
residesinthetargetsystem. Thismodecanbeactivated
in either of two ways; through the conventional method
of applying a high voltage (12V) to address pin A9 or by
sending an instruction to the command register (see
Write Operations).
28F102 Code = 0000 0000 0101 0001 (0051H)
Standby Mode
With CE at a logic-high level, the CAT28F102 is placed
in a standby mode where most of the device circuitry is
disabled, thereby substantially reducing power
consumption.Theoutputsareplacedinahigh-impedance
state.
Figure 5. A.C. Timing for Read Operation
STANDBY
DEVICE AND
OUPUTS
DATA VALID
STANDBY
POWER DOWN
POWER UP
ADDRESS SELECTION
ENABLED
ADDRESS STABLE
ADDRESSES
CE (E)
t
(t
)
AVAV RC
t
(t
EHQZ DF
)
)
OE (G)
t
t
(t
WHGL
GHQZ DF
t
(t
)
WE (W)
GLQV OE
t
(t
ELQV CE
)
t
(t
)
AXQX OH
t
(t
)
GLQX OLZ
t
(t
)
ELQX LZ
HIGH-Z
HIGH-Z
OUTPUT VALID
DATA (I/O)
t
(t
)
AVQV ACC
Doc. No. 1014, Rev. A
8
Main Menu
CAT28F102
WRITE OPERATIONS
Erase-Verify Mode
The Erase-verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.
The following operations are initiated by observing the
sequence specified in the Write Command Table.
Read Mode
Erase Mode
The device can be put into a standard READ mode by
initiating a write cycle with XX00H on the data bus. The
subsequent read cycles will be performed similar to a
standard EPROM or E2PROM Read.
During the first Write cycle, the command XX20H is
writtenintothecommandregister.Inordertocommence
the erase operation, the identical command of XX20H
has to be written again into the register. This two-step
process ensures against accidental erasure of the
memory contents. The final erase cycle will be stopped
at the rising edge of WE, at which time the Erase Verify
command (XXA0H) is sent to the command register.
During this cycle, the address to be verified is sent to the
address bus and latched when WE goes low. An
integrated stop timer allows for automatic timing control
over this operation, eliminating the need for a maximum
erase timing specification. Refer to AC Characteristics
(Program/Erase) for specific timing parameters.
Signature Mode
An alternative method for reading device signature (see
Read Operations Signature Mode), is initiated by writing
thecodeXX90Hintothecommandregisterwhilekeeping
VPP high. A read cycle from address 0000H with CE and
OE low (and WE high) will output the device signature.
CATALYST Code = 0000 0000 0011 0001 (0031H)
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O7.
28F102 Code = 0000 0000 0101 0001 (0051H)
Figure 6. A.C. Timing for Erase Operation
SETUP ERASE
COMMAND
ERASE
COMMAND
ERASING
ERASE VERIFY
COMMAND
ERASE
VERIFICATION
V
POWER-DOWN/
STANDBY
V
POWER-UP
CC
CC
& STANDBY
ADDRESSES
t
t
t
t
WC
WC
WC
RC
t
t
AS
AH
CE (E)
t
t
CH
CS
t
t
CH
EHQZ
t
t
CS
CH
OE (G)
t
GHWL
t
t
t
WHGL
DF
WHWH2
t
WPH
WE (W)
t
t
t
t
OE
WP
WP
WP
t
t
t
t
t
DH
t
DH
DH
OH
t
t
OLZ
DS
DS
DS
HIGH-Z
DATA IN
= XX20H
DATA IN
= XX20H
DATA IN
= XXA0H
DATA (I/O)
VALID
DATA OUT
t
t
LZ
CE
5.0V
0V
V
CC
t
VPEL
V
V
PPH
PPL
V
PP
28F102 F06
Doc. No. 1014, Rev. A
9
Main Menu
CAT28F102
(1)
Figure 7. Chip Erase Algorithm
BUS
OPERATION
START ERASURE
COMMAND
COMMENTS
RAMPS TO V
V
PP
(OR V
PPH
APPLY V
PPH
HARDWIRED)
PP
ALL BYTES SHALL BE
PROGRAMMED TO 00
BEFORE AN ERASE
OPERATION
PROGRAM ALL
BYTES TO 0000H
STANDBY
INITIALIZE
ADDRESS
INITIALIZE ADDRESS
INITIALIZE
PLSCNT = 0
PLSCNT = PULSE COUNT
DATA = XX20H
WRITE ERASE
SETUP COMMAND
WRITE
WRITE
ERASE
ERASE
WRITE ERASE
COMMAND
DATA = XX20H
WAIT
TIME OUT 10ms
ADDRESS = BYTE TO VERIFY
DATA = XXA0H
STOPS ERASE OPERATION
WRITE ERASE
VERIFY COMMAND
ERASE
VERIFY
WRITE
TIME OUT 6µs
WAIT
INCREMENT
ADDRESS
READ DATA
FROM DEVICE
READ
READ BYTE TO
VERIFY ERASURE
NO
NO
DATA =
FFH?
INC PLSCNT
= 1000 ?
COMPARE OUTPUT TO FF
INCREMENT PULSE COUNT
STANDBY
YES
YES
LAST
NO
ADDRESS?
YES
DATA = 0000H
RESETS THE REGISTER
FOR READ OPERATION
WRITE READ
COMMAND
WRITE
READ
V
RAMPS TO V
PP
(OR V
PPL
APPLY V
PPL
APPLY V
PPL
STANDBY
HARDWIRED)
PP
ERASURE
COMPLETED
ERASE
ERROR
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
Doc. No. 1014, Rev. A
10
Main Menu
CAT28F102
Programming Mode
Program-Verify Mode
The programming operation is initiated using the
programming algorithm of Figure 9. During the first write
cycle, the command XX40H is written into the command
register. During the second write cycle, the address of
thememorylocationtobeprogrammedislatchedonthe
falling edge of WE, while the data is latched on the rising
edge of WE. The program operation terminates with the
next rising edge of WE. An integrated stop timer allows
for automatic timing control over this operation,
eliminating the need for a maximum program timing
specification. Refer to AC Characteristics (Program/
Erase) for specific timing parameters.
A Program-verify cycle is performed to ensure that all
bits have been correctly programmed following each
byte programming operation. The specific address is
already latched from the write cycle just completed, and
stayslatcheduntiltheverifyiscompleted. TheProgram-
verify operation is initiated by writing XXC0H into the
command register. An internal reference generates the
necessary high voltages so that the user does not need
to modify VCC. Refer to AC Characteristics (Program/
Erase) for specific timing parameters.
Figure 8. A.C. Timing for Programming Operation
SETUP PROGRAM LATCH ADDRESS
POWER-UP
PROGRAM
VERIFY
COMMAND
PROGRAM
VERIFICATION
V
POWER-DOWN/
STANDBY
V
CC
CC
& STANDBY
COMMAND
& DATA
PROGRAMMING
ADDRESSES
t
t
t
WC
WC
RC
t
t
AH
AS
CE (E)
t
t
CH
CS
t
t
CH
EHQZ
t
t
CS
CH
OE (G)
t
GHWL
t
t
t
WHGL
DF
WHWH1
t
WPH
WE (W)
t
t
t
t
OE
WP
WP
WP
t
t
t
t
DH
DH
DH
OH
t
t
t
OLZ
t
DS
DS
DS
HIGH-Z
DATA IN
= XX 40H
DATA IN
= XX C0H
DATA (I/O)
DATA IN
VALID
DATA OUT
t
LZ
t
CE
5.0V
0V
V
CC
t
VPEL
V
V
PPH
PPL
V
PP
Doc. No. 1014, Rev. A
11
Main Menu
CAT28F102
(1)
Figure 9. Programming Algorithm
START
PROGRAMMING
BUS
OPERATION
COMMAND
COMMENTS
RAMPS TO V
V
APPLY V
PPH
PP
(OR V
PPH
STANDBY
HARDWIRED)
PP
INITIALIZE
ADDRESS
INITIALIZE ADDRESS
INITIALIZE PULSE COUNT
PLSCNT = PULSE COUNT
PLSCNT = 0
WRITE SETUP
PROG. COMMAND
1ST WRITE
CYCLE
WRITE
SETUP
DATA = XX40H
WRITE PROG. CMD
ADDR AND DATA
2ND WRITE
CYCLE
PROGRAM VALID ADDRESS AND DATA
TIME OUT 10µs
WAIT
WRITE PROGRAM
VERIFY COMMAND
1ST WRITE
CYCLE
PROGRAM
DATA = XXC0H
VERIFY
TIME OUT 6µs
WAIT
READ DATA
FROM DEVICE
READ BYTE TO VERIFY
PROGRAMMING
READ
NO
INC
PLSCNT
= 25 ?
NO
VERIFY
DATA ?
COMPARE DATA OUTPUT
TO DATA EXPECTED
STANDBY
YES
YES
LAST
ADDRESS?
NO
INCREMENT
ADDRESS
YES
DATA = XX00H
SETS THE REGISTER FOR
READ OPERATION
WRITE READ
COMMAND
1ST WRITE
CYCLE
READ
V
RAMPS TO V
APPLY V
PPL
APPLY V
PPL
PP
(OR V
PPL
STANDBY
HARDWIRED)
PP
PROGRAMMING
COMPLETED
PROGRAM
ERROR
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
Doc. No. 1014, Rev. A
12
Main Menu
CAT28F102
Abort/Reset
POWER UP/DOWN PROTECTION
An Abort/Reset command is available to allow the user
to safely abort an erase or program sequence. Two
consecutive program cycles with XXFFH on the data
bus will abort an erase or a program operation. The
abort/reset operation can interrupt at any time in a
programoreraseoperationandthedeviceisresettothe
Read Mode.
The CAT28F102 offers protection against inadvertent
programming during VPP and VCC power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, VPP and VCC
may power up in any order. Additionally VPP may be
hardwired to VPPH independent of the state of VCC and
any power up/down cycling. The internal command
register of the CAT28F102 is reset to the Read Mode on
power up.
DATA PROTECTION
1. Power Supply Voltage
POWER SUPPLY DECOUPLING
When the power supply voltage (VCC) is less than 2.5V,
the device ignores WE signal.
To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1µF ceramic
capacitorbetweenVCC andVSS andVPP andVSS.These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.
2. Write Inhibit
When CE and OE are terminated to the low level, write
mode is not set.
Figure 10. Alternate A.C. Timing for Program Operation
SETUP PROGRAM LATCH ADDRESS
POWER-UP
PROGRAM
VERIFY
COMMAND
PROGRAM
VERIFICATION
V
POWER-DOWN/
STANDBY
V
CC
CC
& STANDBY
COMMAND
& DATA
PROGRAMMING
ADDRESSES
WE (E)
t
t
t
WC
WC
RC
t
t
AVEL
ELAX
t
t
WLEL
EHWH
t
t
t
WLEL
EHWH
EHQZ
t
t
WLEL
EHWH
OE (G)
CE (W)
t
t
t
t
EHEH
EHGL
DF
GHEL
t
EHEL
t
t
t
ELEH
ELEH
EHDX
OE
t
t
t
t
t
EHDX
EHDX
OLZ
OH
t
t
t
DVEH
DVEH
DVEH
HIGH-Z
DATA IN
= XX40H
DATA IN
= XXC0H
DATA (I/O)
DATA IN
VALID
DATA OUT
t
LZ
t
CE
5.0V
0V
V
CC
t
VPEL
V
V
PPH
PPL
V
PP
Doc. No. 1014, Rev. A
13
Main Menu
CAT28F102
ALTERNATE CE-CONTROLLED WRITES
VCC = +5V ±10%, unless otherwise specified.
JEDEC Standard
28F102-10
28F102-12
Min. Max.
Symbol Symbol
Parameter
Min.
100
0
Max.
Unit
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
tAVAV
tAVEL
tELAX
tDVEH
tEHDX
tEHGL
tGHEL
tWLEL
tEHWH
tELEH
tEHEL
tVPEL
Write Cycle Time
120
0
WC
tAS
tAH
tDS
Address Setup Time
Address Hold Time
40
40
10
6
40
40
10
6
Data Setup Time
Data Hold Time
tDH
-
Write Recovery Time Before Read
Read Recovery Time Before Write
WE Setup Time Before CE
WE Hold Time After CE
Write Pulse Width
-
0
0
tWS
tWH
tCP
tCPH
-
0
0
0
0
40
20
100
40
20
100
Write Pulse Width High
VPP Setup Time to CE Low
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
28F102
N
-10
I
T
Product
Number
Temperature Range
Tape & Reel
T: 500/Reel
Blank = Commercial (0˚ - 70˚C)
I = Industrial (-40˚ - 85˚C)
A = Automotive (-40˚ - 105˚C)*
Optional
Company ID
Package
Speed
10: 100ns
12: 120ns
N: PLCC
P: PDIP
T14: TSOP
T14R: TSOP (Reverse Pinout)
o
o
*-40 to + 125 C is available upon request
Note:
(1) The device used in the above example is a CAT28F102NI-10T (PLCC, Industrial Temperature, 100 ns access time, Tape & Reel).
Doc. No. 1014, Rev. A
14
Main Menu
Copyrights, Trademarks and Patents
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issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
Publication #: 1014
Revison:
Issue date:
Type:
A
08/01/01
Final
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