CAT28LV65JI-15T [CATALYST]
64K-Bit CMOS PARALLEL EEPROM; 64K位CMOS并行EEPROM
| 型号： | CAT28LV65JI-15T |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 64K-Bit CMOS PARALLEL EEPROM |
| 文件： | 总12页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT28LV65
64K-Bit CMOS PARALLEL EEPROM
TM
FEATURES
■ CMOS and TTL compatible I/O
■ 3.0V to 3.6V supply
■ Automatic page write operation:
– 1 to 32 bytes in 5ms
■ Read access times:
– 150/200/250ns
– Page load timer
■ Low power CMOS dissipation:
– Active: 8 mA max.
■ End of write detection:
– Toggle bit
– Standby: 100 µA max.
– DATA polling
– RDY/BUSY
■ Simple write operation:
– On-chip address and data latches
– Self-timed write cycle with auto-clear
■ Hardware and software write protection
■ 100,000 program/erase cycles
■ 100 year data retention
■ Fast write cycle time:
– 5ms max.
■ Commercial, industrial and automotive
temperature ranges
DESCRIPTION
The CAT28LV65 is manufactured using Catalyst’s
advancedCMOSfloatinggatetechnology.Itisdesigned
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-
pin PLCC packages.
The CAT28LV65 is a low voltage, low power, CMOS
parallel EEPROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling, RDY/BUSY and Toggle status bit signal
thestartandendoftheself-timedwritecycle.Additionally,
the CAT28LV65 features hardware and software write
protection.
BLOCK DIAGRAM
8,192 x 8
E2PROM
ARRAY
ROW
DECODER
ADDR. BUFFER
A –A
5
12
& LATCHES
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
32 BYTE PAGE
REGISTER
V
CC
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
DATA POLLING,
RDY/BUSY &
TOGGLE BIT
TIMER
I/O –I/O
0
7
ADDR. BUFFER
& LATCHES
A –A
COLUMN
DECODER
0
4
RDY/BUSY
© 2005 by Catalyst Semiconductor, Inc.
Doc. No. 1024, Rev. D
Characteristics subject to change without notice
1
CAT28LV65
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W) (K, X)
RDY/BUSY
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
RDY/BUSY
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
2
A
2
12
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
3
NC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
3
NC
4
A
8
A
9
4
A
8
A
9
5
5
6
A
6
A
11
11
7
OE
7
OE
8
A
8
A
10
10
9
CE
9
CE
10
11
12
13
14
I/O
7
I/O
6
I/O
5
I/O
4
10
11
12
13
14
I/O
7
I/O
6
I/O
5
I/O
4
I/O
0
I/O
1
I/O
2
I/O
0
I/O
1
I/O
2
V
I/O
3
V
I/O
3
SS
SS
PLCC Package (N, G)
TSOP Top View (8mm x 13.4mm) (T13, H13)
A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
OE
10
A
CE
I/0
I/0
I/0
I/0
I/0
11
A
A
NC
9
8
7
6
5
4
3
4
3 2 1 32 31 30
WE
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A
A
A
A
A
A
A
A
A
A
6
5
4
3
2
1
0
8
9
V
cc
GND
I/O
RDY/BUSY
A
9
11
12
2
10
11
12
13
14
A
7
I/O
1
NC
OE
A
I/O
0
6
TOP VIEW
A
5
A
0
10
11
12
13
A
10
CE
A
4
A
1
A
3
A
2
NC
I/O
I/O
7
6
I/O
0
14 15 16 17 18 19 20
PIN FUNCTIONS
Pin Name
Function
Address Inputs
Pin Name
WE
Function
Write Enable
A0–A12
I/O0–I/O7
CE
Data Inputs/Outputs
Chip Enable
VCC
3.0 to 3.6 V Supply
Ground
VSS
OE
Output Enable
NC
No Connect
RDY/BSY
Ready/Busy Status
Doc. No. 1024, Rev. D
2
CAT28LV65
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on Any Pin with
Respect to Ground(2) ........... –2.0V to +VCC + 2.0V
V
CC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
105
Max.
Units
Cycles/Byte
Years
Test Method
(1)
NEND
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
100
(1)
VZAP
2000
100
Volts
(1)(4)
ILTH
mA
MODE SELECTION
Mode
CE
WE
OE
L
I/O
DOUT
DIN
Power
ACTIVE
ACTIVE
ACTIVE
STANDBY
ACTIVE
Read
L
L
H
Byte Write (WE Controlled)
Byte Write (CE Controlled)
Standby, and Write Inhibit
Read and Write Inhibit
H
L
X
H
H
DIN
H
X
X
High-Z
High-Z
H
CAPACITANCE T = 25°C, f = 1.0 MHz
A
Symbol
Test
Max.
10
Units
pF
Conditions
(1)
CI/O
Input/Output Capacitance
Input Capacitance
VI/O = 0V
VIN = 0V
(1)
CIN
6
pF
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V +1V.
CC
Doc. No. 1024, Rev. D
3
CAT28LV65
D.C. OPERATING CHARACTERISTICS
V
cc
= 3.0V to 3.6V, unless otherwise specified.
Limits
Symbol
Parameter
Min. Typ.
Max.
Units
Test Conditions
CE = OE = VIL,
f = 1/tRC min, All I/O’s Open
CE = VIHC
ICC
VCC Current (Operating, TTL)
8
mA
(3)
ISBC
VCC Current (Standby, CMOS)
100
µA
,
All I/O’s Open
ILI
Input Leakage Current
Output Leakage Current
–1
–5
1
5
µA
µA
VIN = GND to VCC
ILO
VOUT = GND to VCC
,
CE = VIH
(3)
VIH
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
2
–0.3
2
VCC +0.3
0.6
V
V
V
V
V
VIL
VOH
VOL
VWI
IOH = –100µA
0.3
IOL = 1.0mA
2
A.C. CHARACTERISTICS, Read Cycle
= 3.0V to 3.6V, unless otherwise specified.
V
cc
28LV65-15
28LV65-20
Min. Max.
28LV65-25
Symbol
tRC
Parameter
Min.
Max.
Min.
Max.
Units
ns
Read Cycle Time
150
200
250
tCE
CE Access Time
150
150
70
200
200
80
250
250
100
ns
tAA
Address Access Time
OEAccess Time
ns
tOE
ns
(1)
tLZ
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
0
0
0
0
0
ns
(1)
tOLZ
0
ns
(1)(2)
tHZ
50
50
50
50
55
55
ns
(1)(2)
tOHZ
ns
Output Hold from
Address Change
(1)
tOH
0
0
0
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
(3) V = V –0.3V to V +0.3V.
IHC
CC
CC
Doc. No. 1024, Rev. D
4
CAT28LV65
(4)
Figure 1. A.C. Testing Input/Output Waveform
V
- 0.3 V
CC
2.0 V
0.6 V
INPUT PULSE LEVELS
REFERENCE POINTS
0.0 V
Figure 2. A.C. Testing Load Circuit (example)
Vcc
1.8 K
DEVICE
UNDER
TEST
OUTPUT
1. 3K
C
= 100 pF
L
C INCLUDES JIG CAPACITANCE
L
A.C. CHARACTERISTICS, Write Cycle
= 3.0V to 3.6V, unless otherwise specified.
V
cc
28LV65-15
Min Max
28LV65-20
Min Max
28LV65-25
Symbol
tWC
Parameter
Min
Max
Units
ms
ns
Write Cycle Time
Address Setup Time0
Address Hold Time
CE Setup Time
CE Hold Time
5
5
5
tAS
0
100
0
0
100
0
0
100
0
tAH
ns
tCS
ns
tCH
0
0
0
ns
(2)
tCW
CE Pulse Time
OE Setup Time
OE Hold Time
110
0
150
10
10
150
100
0
150
10
10
150
100
0
ns
tOES
tOEH
ns
0
ns
(2)
tWP
WE Pulse Width
Data Setup Time
Data Hold Time
110
60
0
ns
tDS
tDH
ns
ns
(1)
tINIT
Write Inhibit Period
After Power-up
5
10
5
10
5
10
ms
µs
ns
(1)(3)
tBLC
Byte Load Cycle Time
0.05
100
220
0.1
100
220
0.1
100
220
tRB
WE Low to RDY/Busy Low
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration t
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
BLC
however a transition from HIGH to LOW within t
max. stops the timer.
BLC
(4) Input rise and fall times (10% and 90%) < 10 ns.
Doc. No. 1024, Rev. D
5
CAT28LV65
Byte Write
DEVICE OPERATION
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Read
Data stored in the CAT28LV65 is transferred to the data
bus when WE is held high, and both OE and CE are held
low. The data bus is set to a high impedance state when
either CE or OE goes high. This 2-line control architec-
ture can be used to eliminate bus contention in a system
environment.
Figure 3. Read Cycle
t
RC
ADDRESS
t
CE
CE
t
OE
OE
V
IH
t
WE
LZ
t
OHZ
t
t
HZ
DATA VALID
t
OH
OLZ
HIGH-Z
DATA OUT
DATA VALID
t
AA
Figure 4. Byte Write Cycle [WE Controlled]
t
WC
ADDRESS
t
t
AH
AS
t
t
CH
CS
CE
OE
t
t
t
OEH
OES
WP
WE
t
t
BLC
RB
HIGH-Z
HIGH-Z
RDY/BUSY
HIGH-Z
DATA OUT
DATA IN
DATA VALID
DS
t
t
DH
Doc. No. 1024, Rev. D
6
CAT28LV65
Page Write
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within tBLC MAX of the rising edge of the
preceding WE pulse. There is no page write window
The page write mode of the CAT28LV65 (essentially an
extended BYTE WRITE mode) allows from 1 to 32 bytes
ofdatatobeprogrammedwithinasingleEEPROMwrite
cycle. This effectively reduces the byte-write time by a
factor of 32.
limitation as long as WE is pulsed low within tBLC MAX
.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLC MAX for the internal auto-
matic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
whichwritesnewdatabackintothecell. Apagewritewill
only write data to the locations that were addressed and
will not rewrite the entire page.
FollowinganinitialWRITEoperation(WEpulsedlow,for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
anddatabytesintoa32bytetemporarybuffer. Thepage
address where data is to be written, specified by bits A5
to A12, is latched on the last falling edge of WE. Each
byte within the page is defined by address bits A0 to A4
Figure 5. Byte Write Cycle [CE Controlled]
t
WC
ADDRESS
t
t
t
BLC
AS
AH
t
CW
CE
OE
WE
t
OEH
t
OES
t
t
CH
CS
t
RB
HIGH-Z
HIGH-Z
RDY/BUSY
DATA OUT
DATA IN
HIGH-Z
DATA VALID
DS
t
t
DH
Figure 6. Page Mode Write Cycle
OE
CE
WE
t
t
BLC
WP
ADDRESS
I/O
t
WC
LAST BYTE
BYTE n+2
BYTE 0 BYTE 1
BYTE 2
7
BYTE n
BYTE n+1
Doc. No. 1024, Rev. D
CAT28LV65
DATA Polling
data from the device will result in I/O6 toggling between
one and zero. However, once the write is complete, I/O6
stops toggling and valid data can be read from the
device.
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O7 (I/O0–I/O6
are indeterminate) until the programming cycle is com-
plete. Upon completion of the self-timed write cycle, all
I/O’s will output true data during a read cycle.
Ready/BUSY (RDY/BUSY)
The RDY/BUSY pin is an open drain output which
indicates device status during programming. It is pulled
low during the write cycle and released at the end of
programming. Several devices may be OR-tied to the
same RDY/BUSY line.
Toggle Bit
In addition to the DATA Polling feature, the device offers
an additional method for determining the completion of
a write cycle. While a write cycle is in progress, reading
Figure 7. DATA Polling
ADDRESS
CE
WE
t
OEH
t
OES
t
OE
OE
t
WC
= X
I/O
D
IN
= X
D
D
= X
OUT
7
OUT
28LV65 F11
Figure 8. Toggle Bit
WE
CE
OE
t
OEH
t
OES
t
OE
(1)
(1)
I/O
6
t
WC
Note:
(1) Beginning and ending state of I/O is indeterminate.
6
Doc. No. 1024, Rev. D
8
CAT28LV65
HARDWARE DATA PROTECTION
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
The following is a list of hardware data protection fea-
tures that are incorporated into the CAT28LV65.
SOFTWARE DATA PROTECTION
(1) VCC sense provides for write protection when VCC
falls below 2.0V min.
The CAT28LV65 features a software controlled data
protectionschemewhich, onceenabled, requiresadata
algorithmtobeissuedtothedevicebeforeawritecanbe
performed. The device is shipped from Catalyst with the
software protection NOT ENABLED (the CAT28LV65 is
in the standard operating mode).
(2) A power on delay mechanism, tINIT (see AC charac-
teristics), provides a 5 to 10 ms delay before a write
sequence, after VCC has reached 2.40V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
Figure 9. Write Sequence for Activating Software
Data Protection
Figure 10. Write Sequence for Deactivating
Software Data Protection
WRITE DATA:
ADDRESS:
AA
WRITE DATA:
ADDRESS:
AA
1555
1555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
ADDRESS:
55
0AAA
0AAA
WRITE DATA:
ADDRESS:
80
WRITE DATA:
ADDRESS:
A0
1555
1555
WRITE DATA:
ADDRESS:
AA
(1)
SOFTWARE DATA
PROTECTION ACTIVATED
1555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
XX
0AAA
TO ANY ADDRESS
WRITE DATA:
ADDRESS:
20
WRITE LAST BYTE
TO
LAST ADDRESS
1555
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
Max., after SDP activation.
BLC
Doc. No. 1024, Rev. D
9
CAT28LV65
Toactivatethesoftwaredataprotection,thedevicemust
besentthreewritecommandstospecificaddresseswith
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
writetimingspecifications(Figure11).Oncethisisdone,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transi-
tions. This gives the user added inadvertent write pro-
tection on power-up in addition to the hardware protec-
tion provided.
To allow the user the ability to program the device with
anEEPROMprogrammer(orfortestingpurposes)there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
t
WC
DATA
ADDRESS
AA
1555
55
0AAA
A0
1555
BYTE OR
PAGE
CE
WRITES
ENABLED
t
t
BLC
WP
WE
Figure 12. Resetting Software Data Protection Timing
t
DATA
ADDRESS
AA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
WC
SDP
RESET
CE
DEVICE
UNPROTECTED
WE
Doc. No. 1024, Rev. D
10
CAT28LV65
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
28LV65
N
-25
T
I
Optional
Company
ID
Tape & Reel
Product
Number
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ to +105˚C)*
Package
P: PDIP
Speed
15: 150ns
20: 200ns
25: 250ns
J: SOIC (JEDEC)
K: SOIC (EIAJ)
N: PLCC
T13: TSOP (8mmx13.4mm)
L: PDIP (Lead free, Halogen free)
W: SOIC (JEDEC) (Lead free, Halogen free)
X: SOIC (EIAJ) (Lead free, Halogen free)
G: PLCC (Lead free, Halogen free)
H13: TSOP (8mmx13.4mm) (Lead free, Halogen free)
* -40˚C to +125˚C is available upon request
Notes:
(1) The device used in the above example is a CAT28LV65NI-25T (PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel).
Doc. No. 1024, Rev. D
11
REVISION HISTORY
Date
Revision Comments
03/29/04
04/20/04
B
C
Added Green packages in all areas
Delete data sheet designation
Update Ordering Information
Update Revision History
Update Rev Number
03/29/05
D
Update A.C Characteristics, Write Cycle
Copyrights, Trademarks and Patents
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2
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issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
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Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Publication #: 1024
Revison:
D
Issue date:
03/29/05
Fax: 408.542.1200
www.catalyst-semiconductor.com
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