CAT34AC02WE-TE13 [CATALYST]
2K-Bit SMBus EEPROM for ACR Card Configuration; 2K位的SMBus EEPROM，用于ACR卡配置
| 型号： | CAT34AC02WE-TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 2K-Bit SMBus EEPROM for ACR Card Configuration |
| 文件： | 总10页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
E
CAT34AC02
2K-Bit SMBus EEPROM for ACR Card Configuration
TM
FEATURES
■ 400 kHz (5V) and 100 kHz (1.8V) SMBus
■ Self-timed write cycle with auto-clear
■ 1,000,000 program/erase cycles
■ 100 year data retention
compatible
■ 1.8 to 6.0 volt operation
■ Low power CMOS technology
– zero standby current
■ 8-pin DIP, 8-pin SOIC and 8-pin TSSOP packages
■ 256 x 8 memory organization
■ 16-byte page write buffer
■ Hardware write protect
■ Industrial, automotive and extended
temperature ranges
DESCRIPTION
16-byte page write buffer. The device operates via the
SMBus serial interface for ACR card configuration and
is available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP
packages.
The CAT34AC02 is a 2K-bit Serial CMOS EEPROM
internallyorganizedas256wordsof8bitseach.Catalyst’s
advanced CMOS technology substantially reduces de-
vice power requirements. The CAT34AC02 features a
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package (P, L)
SOIC Package (J, W)
EXTERNAL LOAD
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A
A
A
V
A
A
A
SENSE AMPS
SHIFT REGISTERS
0
1
2
CC
0
1
2
V
CC
WP
D
OUT
WP
ACK
SCL
SDA
SCL
SDA
V
V
CC
V
V
SS
SS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SS
TSSOP Package (U, Y)
MSOP Package (R, Z)
START/STOP
SDA
WP
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A
A
A
LOGIC
0
1
2
V
CC
WP
SCL
SDA
E2PROM
V
XDEC
SS
CONTROL
LOGIC
PIN FUNCTIONS
Pin Name
Function
DATA IN STORAGE
A0, A1, A2
SDA
Device Address Inputs
Serial Data/Address
Serial Clock
HIGH VOLTAGE/
TIMING CONTROL
SCL
SCL
WP
Write Protect
STATE COUNTERS
VCC
+1.8V to +6.0V Power Supply
Ground
SLAVE
ADDRESS
COMPARATORS
A
A1
A2
0
VSS
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1025, Rev. E
1
CAT34AC02
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias
–55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Storage Temperature....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Typ
Max
Units
Cycles/Byte
Years
(3)
NEND
Endurance
MIL-STD-883, Test Method 1033 1,000,000
(3)
TDR
Data Retention
MIL-STD-883, Test Method 1008
100
2000
100
(3)
VZAP
ESD Susceptibility MIL-STD-883, Test Method 3015
Latch-up JEDEC Standard 17
Volts
(3)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Symbol
ICC
Parameter
Test Conditions
fSCL = 100 kHz
Min
Typ
Max
Units
mA
mA
µA
Power Supply Current (Read)
Power Supply Current (Write)
Standby Current (VCC = 5.0V)
Input Leakage Current
1
3
ICC
fSCL = 100 kHz
(5)
ISB
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
0
ILI
ILO
10
10
µA
Output Leakage Current
Input Low Voltage
µA
VIL
–1
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
VIH
Input High Voltage
VCC x 0.7
VOL1
VOL2
Output Low Voltage (VCC = 3.0V)
Output Low Voltage (VCC = 1.8V)
IOL = 3 mA
IOL = 1.5 mA
0.5
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
CC
A
Symbol Parameter
Test Conditions
VI/O = 0V
Min
Typ
Max
8
Units
pF
(3)
CI/O
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
(3)
CIN
VIN = 0V
6
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) Standby Current (I ) = 0µA (<900nA).
SB
Doc. No. 1025, Rev. E
2
CAT34AC02
A.C. CHARACTERISTICS
V
= +1.8V to +6.0V, unless otherwise specified.
CC
Read & Write Cycle Limits
1.8V-6.0V, 2.5V - 6.0V
4.5V - 5.5V
Symbol
Parameter
Units
Min
Max
Min
Max
FSCL
TI(1)
Clock Frequency
100
400
100
kHz
ns
Noise Suppression Time Constant at
SCL, SDA Inputs
100
3.5
SCL Low to SDA Data Out
and ACK Out
tAA
1
µs
µs
Time the Bus Must be Free Before a
New Transmission Can Start
(1)
tBUF
4.7
1.2
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4
4.7
4
0.6
1.2
0.6
µs
µs
µs
tHIGH
Clock High Period
Start Condition Setup Time (for a
Repeated Start Condition)
tSU:STA
4.7
0.6
µs
tHD:DAT
tSU:DAT
Data In Hold Time
0
0
ns
ns
µs
ns
µs
ns
Data In Setup Time
50
50
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
0.3
(1)
tF
300
300
tSU:STO
tDH
4
0.6
100
100
(1)(2)
Power-Up Timing
Symbol
tPUR
Parameter
Min
Min
Typ
Max
1
Units
ms
Power-up to Read Operation
Power-up to Write Operation
tPUW
1
ms
Write Cycle Limits
Symbol
Parameter
Write Cycle Time
Typ
Max
Units
tWR
4
5
ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Doc No. 1025, Rev. E
3
CAT34AC02
alldatatransfersintooroutofthedevice. Thisisaninput
pin.
FUNCTIONAL DESCRIPTION
TheCAT34AC02supportstheSMBusdatatransmission
protocol. This serial protocol defines any device that
sends data to the bus to be a transmitter and any device
receivingdatatobeareceiver.Datatransferiscontrolled
by the Master device which generates the serial clock
andallSTARTandSTOPconditionsforbusaccess.The
CAT34AC02 operates as a Slave device. Both the
Master and Slave devices can operate as either
transmitter or receiver, but the Master device controls
which mode is activated. A maximum of 8 devices may
be connected to the bus as determined by the device
address inputs A0, A1, and A2.
SDA: Serial Data/Address
The CAT34AC02 bidirectional serial data/address pin is
usedtotransferdataintoandoutofthedevice. TheSDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
A0, A1, A2: Device Address Inputs
Theseinputssetdeviceaddresswhencascadingmultiple
devices. A maximum of eight devices can be cascaded
when using the device.
WP: Write Protect
This input, when tied to GND, allows write operations to
theentirememory. ForCAT34AC02whenthispinistied
to VCC, the entire array of memory is write protected.
When left floating, memory is unprotected.
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT34AC02 serial clock input pin is used to clock
Figure 1. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
DH
AA
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Doc. No. 1025, Rev. E
4
CAT34AC02
eight CAT34AC02 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
SERIAL BUS PROTOCOL
ThefollowingdefinesthefeaturesoftheACRSerial bus
protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
After the Master sends a START condition and the slave
address byte, the CAT34AC02 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT34AC02 then performs a Read or a Write operation
depending on the state of the R/W bit.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
Acknowledge
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT34AC02 monitor the
SDA and SCL lines and will not respond until this
condition is met.
Afterasuccessfuldatatransfer, eachreceivingdeviceis
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
STOP Condition
The CAT34AC02 responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
DEVICE ADDRESSING
WhentheCAT34AC02beginsaREADmode,ittransmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT34AC02 will continue to transmit
data. IfnoacknowledgeissentbytheMaster, thedevice
terminates data transmission and waits for a STOP
condition.
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1011 for the CAT34AC02 (see Fig. 5). The next three
significant bits (A2, A1, A0) are the device address bits
and define which device the Master is accessing. Up to
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
1
A2
A1
A0 R/W
DEVICE ADDRESS
Doc No. 1025, Rev. E
5
CAT34AC02
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT34AC02. After receiving another
acknowledgefromtheSlave,theMasterdevicetransmits
the data byte to be written into the addressed memory
location. The CAT34AC02 acknowledges once more
and the Master generates the STOP condition, at which
time the device begins its internal programming to
nonvolatile memory. While this internal cycle is in
progress, thedevicewillnotrespondtoanyrequestfrom
the Master device.
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT34AC02 in a single write cycle.
Acknowledge Polling
Thedisablingoftheinputscanbeusedtotakeadvantage
of the typical write cycle time. Once the stop condition
isissuedtoindicatetheendofthehost’swriteoperation,
the CAT34AC02 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT34AC02 is still busy with
the write operation, no ACK will be returned. If the
CAT34AC02hascompletedthewriteoperation,anACK
will be returned and the host can then proceed with the
next read or write operation.
Page Write
The CAT34AC02 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted the CAT34AC02 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain
unchanged.
WRITE PROTECTION
The write protection feature of CAT34AC02 allows the
user to protect against inadvertent programming of the
memory array. If the WP pin is tied to Vcc, the entire
memoryarrayisprotectedandbecomesreadonly. Ifthe
WP pin is left floating or tied to Vss, the device can be
written into.
If the Master transmits more than 16 bytes prior to
sendingtheSTOPcondition,theaddresscounter‘wraps
around’, and previously transmitted data will be
overwritten.
Figure 6. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
SLAVE
ADDRESS
BYTE
ADDRESS
MASTER
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 7. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+P
SDA LINE
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
6
Doc. No. 1025, Rev. E
CAT34AC02
READ OPERATIONS
The READ operation for the CAT34AC02 is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
and the slave address, this time with the R/W bit set to
one. The CAT34AC02 then responds with its
acknowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
Immediate Address Read
Sequential Read
TheCAT34AC02’saddresscountercontainstheaddress
of the last byte accessed, incremented by one. In other
words,ifthelastREADorWRITEaccesswastoaddress
N, the READ immediately following would access data
from address N+1. If N = 255 for the CAT34AC02, then
the counter will ‘wrap around’ to address 0 and continue
to clock out data. After the CAT34AC02 receives its
slave address information (with the R/W bit set to one),
it issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT34AC02 sends the initial 8-bit
data requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT34AC02 will continue to output a byte for
each acknowledge sent by the Master. The operation
willterminateoperationwhentheMasterfailstorespond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from the CAT34AC02 is
outputtedsequentiallywithdatafromaddressNfollowed
bydatafromaddressN+1.TheREADoperationaddress
counter increments all of the CAT34AC02 address bits
so that the entire memory array can be read during one
operation. If more than the 256 bytes are read out, the
counterwill“wraparound”andcontinuetoclockoutdata
bytes.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT34AC02 acknowledge the word
address,theMasterdeviceresendstheSTARTcondition
Figure 8. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Doc No. 1025, Rev. E
7
CAT34AC02
Figure 9. Memory Array
FFH
Hardware Write Protectable
(by connecting WP pin toVcc)
00H
Figure 10. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
*
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
5020 FHD F11
Figure 11. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
5020 FHD F12
Doc. No. 1025, Rev. E
8
CAT34AC02
ORDERING INFORMATION
Prefix
Device #
34AC02
Suffix
TE13
-1.8
CAT
J
I
Optional
Company ID
Temperature Range
Tape & Reel
TE13: 2000/Reel
Product
Number
I = Industrial (-40ßC to 85ßC)
A = Automotive (-40ßC to 105ßC)
E = Extended (-40ßC to 125ßC)
Package
Operating Voltage
Blank: 2.5V - 6.0V
1.8: 1.8V - 6.0V
P: PDIP
J: SOIC (JEDEC)
U: TSSOP
R: MSOP
L: PDIP (Lead free, Halogen free)
W: SOIC (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
Z: MSOP (Lead free, Halogen free)
Notes:
(1) The device used in the above example is a 34AC02JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)
Doc No. 1025, Rev. E
9
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
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PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Publication #: 1025
Revison:
Issue date:
Type:
E
5/9/03
Preliminary
Fax: 408.542.1200
www.catalyst-semiconductor.com
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