CAT34FC02SP2A-REV-E [CATALYST]
EEPROM, 256X8, Serial, CMOS, TDFN-8;
| 型号： | CAT34FC02SP2A-REV-E |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 256X8, Serial, CMOS, TDFN-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总10页 (文件大小：414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT34FC02
2-kb I2C Serial EEPROM, Serial Presence Detect
TM
FEATURES
I 400 kHz (2.5 V) and 100 kHz (1.7 V) I2C bus
I Permanent software write protection for lower
compatible
128 bytes
I 1.7 to 5.5 volt operation
I Low power CMOS technology
I 16-byte page write buffer
I 1,000,000 program/erase cycles
I 100 year data retention
I 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and TDFN
packages
I Commercial, industrial and automotive
temperature ranges
- “Green” package option available
I 256 x 8 memory organization
I Hardware write protect
I Self-timed write cycle with auto-clear
DESCRIPTION
a 16-byte page write buffer. The device operates via the
I2C bus serial interface and is available in 8-pin DIP,
8-pin SOIC, 8-pin TSSOP and TDFN packages.
The CAT34FC02 is a 2-kb Serial CMOS EEPROM
internallyorganizedas256wordsof8bitseach.Catalyst’s
advanced CMOS technology substantially reduces
device power requirements. The CAT34FC02 features
PIN CONFIGURATION
BLOCK DIAGRAM
V
CC
DIP Package (P, L)
SOIC Package (J, W)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A
A
A
V
A
A
A
0
1
2
CC
0
1
2
V
CC
WP
WP
SCL
SCL
SDA
SCL
SDA
V
V
SS
SS
A2, A1, A0
WP
CAT34FC02
SDA
TDFN Package (SP2, VP2)
A
V
1
2
3
4
8
7
6
5
1
2
3
CC
A
A
WP
V
SS
SCL
SDA
V
SS
PIN FUNCTIONS
TSSOP Package (U, Y)
Pin Name
Function
1
2
3
4
8
7
6
5
A
0
V
CC
WP
A0, A1, A2
SDA
Device Address Inputs
Serial Data/Address
Serial Clock
A
A
1
2
SCL
SDA
V
SS
SCL
WP
Write Protect
VCC
1.7 V to 5.5 V Power Supply
Ground
VSS
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1045, Rev. H
1
CAT34FC02
Lead Soldering Temperature (10 seconds) ...... 300°C
Output Short Circuit Current(2) ....................... 100 mA
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
–55°C to +125°C
Storage Temperature....................... –65°C to +150°C
*COMMENT
Voltage on Any Pin with
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outsideofthoselistedintheoperationalsectionsofthisspecificationisnot
implied. Exposure to any absolute maximum rating for extended periods
Respect to Ground(1) ............–2.0 V to VCC + 2.0 V
VCC with Respect to Ground ............. –2.0 V to +7.0 V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
may affect device performance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Reference Test Method
Min
Typ
Max
Units
Cycles/Byte
Years
(3)
NEND
MIL-STD-883, Test Method 1033 1,000,000
(3)
TDR
Data Retention
MIL-STD-883, Test Method 1008
100
4000
100
(3)
VZAP
ESD Susceptibility MIL-STD-883, Test Method 3015
Latch-up JEDEC Standard 17
Volts
(3)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
V
= 1.7 V to 5.5 V, unless otherwise specified.
CC
Symbol
ICC
Parameter
Test Conditions
fSCL = 100 kHz
Min
Typ
Max
Units
mA
mA
µA
Power Supply Current (Read)
Power Supply Current (Write)
Standby Current (VCC = 5.0 V)
Input Leakage Current
1
3
1
1
1
ICC
fSCL = 100 kHz
(5)
ISB
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
ILI
ILO
µA
Output Leakage Current
Input Low Voltage
µA
VIL
–1
VCC x 0.3
VCC + 1.0
V
V
V
V
VIH
Input High Voltage
VCC x 0.7
VOL1
VOL2
Output Low Voltage (VCC = 3.0 V)
Output Low Voltage (VCC = 1.7 V)
IOL = 3 mA
0.4
0.5
IOL = 1.5 mA
CAPACITANCE T = 25°C, f = 400 kHz, V
= 5 V
CC
A
Symbol
Test
Conditions
VI/O = 0 V
VIN = 0 V
Min
Typ
Max
8
Units
pF
(3)
CI/O
Input/Output Capacitance (SDA)
Input Capacitance (other pins)
(3)
CIN
6
pF
Note:
(1) The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1.0 V to V + 1.0 V.
CC
(5) Maximum standby current (I ) = 10µA for the Extended Automotive temperature range.
SB
Doc. No. 1045, Rev. H
2
CAT34FC02
A.C. CHARACTERISTICS
V
= 1.7 V to 5.5 V, unless otherwise specified.
CC
Read & Write Cycle Limits
Symbol
Parameter
1.7 V - 5.5 V
2.5 V - 5.5 V
Min
Max
100
100
Min
Max
Units
kHz
ns
FSCL
TI(1)
Clock Frequency
400
100
Noise Suppression Time
Constant at SCL, SDA Inputs
tAA
SCL Low to SDA Data Out
and ACK Out
3.5
0.9
µs
µs
(1)
tBUF
Time the Bus Must be Free Before
a New Transmission Can Start
4.7
1.3
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4
0.6
1.3
0.6
0.6
µs
µs
µs
µs
4.7
4
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
tHD:DAT
tSU:DAT
Data In Hold Time
0
0
ns
ns
µs
ns
µs
ns
Data In Setup Time
250
100
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
0.3
(1)
tF
300
300
tSU:STO
tDH
4
0.6
100
100
(1)(2)
Power-Up Timing
Symbol
Parameter
Min
Min
Typ
Max
1
Units
ms
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1
ms
Write Cycle Limits
Symbol
Parameter
Typ
Max
Units
tWR
Write Cycle Time
5
ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Doc No. 1045, Rev. H
3
CAT34FC02
data transfers into or out of the device. This is an input
pin.
FUNCTIONAL DESCRIPTION
TheCAT34FC02supportstheI2CBusdatatransmission
protocol.ThisInter-IntegratedCircuitBusprotocoldefines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditionsforbusaccess. TheCAT34FC02operatesas
a Slave device. Both the Master and Slave devices can
operate as either transmitter or receiver, but the Master
device controls which mode is activated. A maximum of
8devicesmaybeconnectedtothebusasdeterminedby
the device address inputs A0, A1, and A2.
SDA: Serial Data/Address
The CAT34FC02 bidirectional serial data/address pin is
usedtotransferdataintoandoutofthedevice. TheSDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
A0, A1, A2: Device Address Inputs
Theseinputssetdeviceaddresswhencascadingmultiple
devices. A maximum of eight devices can be cascaded
when using the device.
WP: Write Protect
This input, when tied to GND, allows write operations to
theentirememory. ForCAT34FC02whenthispinistied
to VCC, the entire array of memory is write protected.
When left floating, memory is unprotected.
PIN DESCRIPTIONS
SCL: Serial Clock
TheCAT34FC02serialclockinputpinisusedtoclockall
t
t
t
Figure 1. Bus Timing
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
t
DH
AA
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Doc. No. 1045, Rev. H
4
CAT34FC02
I2C BUS PROTOCOL
and define which device the Master is accessing. Up to
eight CAT34FC02 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
The following defines the features of the I2C bus proto-
col:
(1) Data transfer may be initiated only when the bus is
not busy.
After the Master sends a START condition and the slave
address byte, the CAT34FC02 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT34FC02 then performs a Read or a Write operation
depending on the state of the R/W bit.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT34FC02 monitor the
SDA and SCL lines and will not respond until this
condition is met.
Acknowledge
Afterasuccessfuldatatransfer, eachreceivingdeviceis
requiredtogenerateanacknowledge.TheAcknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
STOP Condition
The CAT34FC02 responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
DEVICE ADDRESSING
When the CAT34FC02 begins a READ mode, it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT34FC02 will continue to transmit
data. IfnoacknowledgeissentbytheMaster, thedevice
terminates data transmission and waits for a STOP
condition.
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed
(except when accessing the Write Protect Register) as
1010 for the CAT34FC02 (see Fig. 5). The next three
significant bits (A2, A1, A0) are the device address bits
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
1
0
0
A2
A1
A0 R/W
Normal Read and Write
DEVICE ADDRESS
Programming the Write
Protect Register
0
1
A2
A1
A0 R/W
Doc No. 1045, Rev. H
5
CAT34FC02
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT34FC02 in a single write cycle.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT34FC02. After receiving another
acknowledgefromtheSlave,theMasterdevicetransmits
the data byte to be written into the addressed memory
location. The CAT34FC02 acknowledges once more
and the Master generates the STOP condition, at which
time the device begins its internal programming to
nonvolatile memory. While this internal cycle is in
progress, thedevicewillnotrespondtoanyrequestfrom
the Master device.
Acknowledge Polling
Thedisablingoftheinputscanbeusedtotakeadvantage
of the typical write cycle time. Once the stop condition
isissuedtoindicatetheendofthehost’swriteoperation,
the CAT34FC02 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT34FC02 is still busy with
the write operation, no ACK will be returned. If the
CAT34FC02hascompletedthewriteoperation, anACK
will be returned and the host can then proceed with the
next read or write operation.
Page Write
WRITE PROTECTION
The CAT34FC02 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted the CAT34FC02 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain
unchanged.
The CAT34FC02 is designed with a hardware protect
pin that enables the user to protect the entire memory.
The CAT34FC02 also has a software write protection
feature. By programming the software write protection
register, the first 128 bytes are write protected. The
software and hardware protection features of the
CAT34FC02aredesignedintotheparttoprovideadded
flexibility to the design engineers.
If the Master transmits more than 16 bytes prior to
sendingtheSTOPcondition,theaddresscounter‘wraps
around’, and previously transmitted data will be
overwritten.
Hardware
The write protection feature of CAT34FC02 allows the
user to protect against inadvertent programming of the
memory array. If the WP pin is tied to Vcc, the entire
Figure 6. Byte Write Timing
S
T
S
A
R
T
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 7. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
Doc. No. 1045, Rev. H
6
CAT34FC02
memory array is protected and becomes read only. The
entire memory becomes write protected regardless of
whether the write protect register has been written or
not.WhenWPpinistiedtoVcc,theusercannotprogram
the write protect register. If the WP pin is left floating or
tiedtoVss, thedevicecanbewritteninto(exceptthefirst
128 bytes if the write protect register is programmed).
requested. The master device does not send an
acknowledge but will generate a STOP condition.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT34FC02 acknowledge the word
address,theMasterdeviceresendstheSTARTcondition
and the slave address, this time with the R/W bit set to
one. The CAT34FC02 then responds with its
acknowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
Software
ThesoftwareprotectionontheCAT34FC02protectsthe
first128bytesofthememoryarraypermanently.Software
write protect is implemented by programming the write
protect register. A user can write only once to the write
protect register and once written it is irreversible (even
if you reset the CAT34FC02).
Sequential Read
Read Operations
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT34FC02 sends the initial 8-bit
data requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT34FC02 will continue to output a byte for
each acknowledge sent by the Master. The operation
willterminateoperationwhentheMasterfailstorespond
with an acknowledge, thus sending the STOP condition.
The READ operation for the CAT34FC02 is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Immediate Address Read
TheCAT34FC02’saddresscountercontainstheaddress
of the last byte accessed, incremented by one. In other
words,ifthelastREADorWRITEaccesswastoaddress
N, the READ immediately following would access data
from address N + 1. If N = 255 for 34FC02, then the
counter will ‘wrap around’ to address 0 and continue to
clock out data. After the CAT34FC02 receives its slave
address information (with the R/W bit set to one), it
issues an acknowledge, then transmits the 8-bit byte
The data being transmitted from the CAT34FC02 is
outputtedsequentiallywithdatafromaddressNfollowed
by data from address N + 1. The READ operation
address counter increments all of the CAT34FC02
addressbitssothattheentirememoryarraycanberead
duringoneoperation.Ifmorethanthe256bytesareread
out, the counter will “wrap around” and continue to clock
out data bytes.
Figure 8. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
DATA
O
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Doc No. 1045, Rev. H
7
CAT34FC02
Figure 9. Memory Array
FFH
Hardware Write Protectable
(by connecting WP pin to
Vcc)
7FH
00H
Software Write Protectable
(by programming the write
protect register)
Figure 10. Software Write Protect Register (Write)
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
BYTE
ADDRESS
*
ADDRESS
DATA
SDA LINE
S
X X X X X X X X X X X X X X X X
P
A
C
K
A
C
K
A
C
K
X = Don't Care
Figure 11. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 12. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc. No. 1045, Rev. H
8
CAT34FC02
ORDERING INFORMATION
Prefix
Device #
34FC02
Suffix
CAT
J
I
TE13
REV C
Optional
Company ID
Temperature Range
I = Industri
Tape & Reel
Product
Number
A = Automotive (-40°C to +105°C)
E = Extended (-40°C to +125°C)
Die Revision
34FC02: C, E
Package
P: PDIP
J: SOIC (JEDEC)
U: TSSOP
SP2: TDFN
L: PDIP (Lead free, Halogen free)
W: SOIC (JEDEC), (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
VP2: TDFN (Lead free, Halogen free)
Notes:
(1) The device used in the above example is a 34FC02JI-TE13 (SOIC, Industrial Temperature, 1.7 Volt to 5.5 Volt Operating Voltage, Tape & Reel)
Doc No. 1045, Rev. H
9
REVISION HISTORY
Date
Revision Comments
09/22/03
C
D
E
Eliminated commercial temperature range
Updated marking
12/19/03
01/20/04
Changed “ Blank” to “ I” for Industrial temperature range in Ordering
Information
Upated TDFN package drawing
Created new block diagram
Updated package information to reflect new TDFN
06/07/04
F
Update D.C. Operating Characteristics
Update Write Cycle Limits
Update Ordering Information
Update Revision History
Update Rev Number
07/27/04
11/30/04
G
H
Update notes on page 2
Added Die Revision E to Ordering Information
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Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Publication #: 1045
Revison:
H
Issue date:
11/30/04
Fax: 408.542.1200
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