CAT34RC02SP2I-TE13REV-E [CATALYST]
EEPROM, 256X8, Serial, CMOS, TDFN-8;
| 型号： | CAT34RC02SP2I-TE13REV-E |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 256X8, Serial, CMOS, TDFN-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 内存集成电路 |
| 文件： | 总14页 (文件大小：666K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT34RC02
2-kb I2C Serial EEPROM, Serial Presence Detect
FEATURES
I 400 kHz I2C bus compatible*
I 1.7 to 5.5 volt operation
I 16-byte page write buffer
I Schmitt trigger on SCL and SDA inputs
I Low power CMOS technology
I 1,000,000 program/erase cycles
I 100 year data retention
I Hardware write protection for entire memory
I Permanent and reversible software write
I 8-pin TSSOP and TDFN packages
I Industrial temperature range
protection for lower 128 bytes
DESCRIPTION
a 16-byte page write buffer. The device operates via the
I2C bus serial interface and is available in 8-pin TSSOP
and TDFN packages.
The CAT34RC02 is a 2-kb Serial CMOS EEPROM
internallyorganizedas256wordsof8bitseach.Catalyst’s
advanced CMOS technology substantially reduces
device power requirements. The CAT34RC02 features
PIN CONFIGURATION
FUNCTIONAL SYMBOL
TDFN Package (SP2, VP2)
V
CC
A
A
A
V
1
2
3
4
8
7
6
5
0
1
2
CC
WP
SCL
SDA
SCL
V
SS
A , A , A
CAT34RC02
SDA
2
1
0
TSSOP Package (U, Y, GY)
1
2
3
4
8
7
6
5
A
A
A
WP
0
V
CC
WP
1
2
SCL
SDA
V
SS
V
SS
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
SDA
SCL
Device Address Inputs
Serial Data/Address
Serial Clock
WP
Write Protect
VCC
1.7 V to 5.5 V Power Supply
Ground
VSS
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1052, Rev. O
1
CAT34RC02
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outsideofthoselistedintheoperationalsectionsofthisspecificationisnot
implied. Exposure to any absolute maximum rating for extended periods
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature........................ -65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ............ -2.0 V to VCC + 2.0 V
may affect device performance and reliability.
Voltage on A0 .................................................. -2.0 V to +12.0 V
VCC with Respect to VSS.............................. -2.0 V to +7.0 V
(2)
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min
1,000,000
100
Units
(*)
NEND
Program/ Erase Cycles
(*)
TDR
Data Retention
ESD Susceptibility
Latch-up
Years
Volts
mA
(*)
VZAP
4000
(3)
ILTH
100
(*) Page Mode, VCC = 5 V, 25°C
D.C. OPERATING CHARACTERISTICS
V
= 1.7 V to 5.5 V, unless otherwise specified.
CC
Symbol
ICC
Parameter
Test Conditions
Min
Typ
Max
Units
mA
mA
µA
µA
µA
V
Power Supply Current (Read)
Power Supply Current (Write)
Standby Current (VCC = 5.0 V)
Input Leakage Current
fSCL = 100 kHz
fSCL = 100 kHz
1
ICC
3
(4)
ISB
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
1
ILI
ILO
1
1
Output Leakage Current
Input Low Voltage
VIL
–1
VCC x 0.3
VCC + 1.0
0.4
VIH
Input High Voltage
VCC x 0.7
V
VOL1
VOL2
VHV
Output Low Voltage (VCC = 3.0 V)
Output Low Voltage (VCC = 1.7 V)
IOL = 3 mA
IOL = 1.5 mA
V
0.5
V
RSWP Set/Clear Overdrive
A0 High Voltage
VHV - VCC > 4.8 V
7
10
V
CAPACITANCE T = 25°C, f = 400 kHz, V
= 5 V
CC
A
Symbol
Test
Conditions
VI/O = 0 V
VIN = 0 V
Min
Typ
Max
8
Units
pF
(2)
CI/O
Input/Output Capacitance (SDA)
Input Capacitance (other pins)
WP Input Impedance
(2)
CIN
6
pF
ZWPL
ZWPH
VIN < 0.5 V
VIN > VCC x 0.7
5
70
kΩ
WP Input Impedance
500
kΩ
Note:
(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin
CC
may undershoot to no less than -2.0 V or overshoot to no more than VCC + 2.0 V, for periods of less than 20 ns. The maximum DC
voltage on address pin A is +12.0 V.
0
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(3) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1.0 V to V + 1.0 V.
CC
(4) Standby Current, I = 10 µA max at extended temperature range.
SB
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1052, Rev. O
2
CAT34RC02
A.C. CHARACTERISTICS
V
= 1.7 V to 5.5 V, unless otherwise specified.
CC
Read & Write Cycle Limits
Symbol
Parameter
1.7 V - 5.5 V
2.5 V - 5.5 V
Min
Max
100
100
Min
Max
Units
kHz
ns
FSCL
TI(1)
Clock Frequency
400
100
Noise Suppression Time
Constant at SCL, SDA Inputs
tAA
SCL Low to SDA Data Out
and ACK Out
3.5
0.9
µs
µs
(1)
tBUF
Time the Bus Must be Free Before
a New Transmission Can Start
4.7
1.3
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4
0.6
1.3
0.6
0.6
µs
µs
µs
µs
4.7
4
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
tHD:DAT
tSU:DAT
Data In Hold Time
0
0
ns
ns
µs
ns
µs
ns
Data In Setup Time
250
100
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
0.3
(1)
tF
300
300
tSU:STO
tDH
4
0.6
100
100
(1)(2)
Power-Up Timing
Symbol
Parameter
Min
Min
Typ
Max
1
Units
ms
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1
ms
Write Cycle Limits
Symbol
Parameter
Typ
Max
Units
tWR
Write Cycle Time
5
ms
The write cycle time is the time elapsed between the
STOP command (following the write instruction) and the
completion of the internal write cycle. During the internal
write cycle, SDA is released by the Slave and the device
does not acknowledge external commands.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1052, Rev. O
3
CAT34RC02
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The CAT34RC02 supports the I2C (2-wire) Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver.DatatransferiscontrolledbytheMasterdevice
which generates the serial clock and all START and
STOP conditions for bus access. The CAT34RC02
operates as a Slave device. Both the Master and Slave
devicescanoperateaseithertransmitterorreceiver,but
the Master alone assigns those roles. A maximum of 8
devices may be connected to the bus as determined by
the device address inputs A0, A1, and A2.
SCL: Serial Clock
The serial clock input pin is used to clock all data
transfers into or out of the device.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer data into and out of the device. This pin is an
open drain output in transmit mode.
A0, A1, A2: Device Address Inputs
These inputs set the device address. When left floating,
the address pins are internally pulled to ground.
WP: Write Protect
This input, when grounded or left floating, allows write
operations to the entire memory. When this pin is tied to
VCC, the entire memory is write protected.
Figure 1. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
DH
AA
SDA OUT
Figure 2. Write Cycle Timing
SCL
th
SDA
8
Bit
ACK
Byte n
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1052, Rev. O
4
CAT34RC02
I2C BUS PROTOCOL
Device Addressing
The I2C bus consists of two ‘wires’, SCL and SDA. The
two ‘wires’ are connected to the supply (VCC) via pull-up
resistors. Master and Slave devices connect to the bus
via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
TheMasterinitiatesadatatransferbycreatingaSTART
condition on the bus. The Master then broadcasts an 8-
bit serial Slave address. The four most significant bits of
the Slave address (the ‘preamble’) are fixed to 1010
(Ah), for normal read/write operations and 0110 (6h) for
Software Write Protect (SWP) operations (Fig. 5). The
nextthreebits,A2,A1 andA0,selectoneofeightpossible
Slave devices. The last bit, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed.
(1) Data transfer may be initiated only when the bus is
not busy (see A.C. Characteristics).
(2) During a data transfer, the data line must remain
stable whenever the SCL line is high. An SDA
transition while SCL is high will be interpreted as a
START or STOP condition.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9th clock cycle. The Slave will aslo
acknowledge the 8-bit byte address and every data byte
presented in WRITE mode. In READ mode the Slave
shifts out eight bits of data, and then ‘releases’ the SDA
linedurngthe9th clockcycle.IftheMasteracknowledges
in the 9th clock cycle (by pulling down the SDA line), then
the Slave continues transmitting. When data transfer is
complete, the Master responds with a NoACK (it does
not acknowledge the last data byte) and the Slave stops
transmitting and waits for a STOP condition.
START Condition
TheSTARTConditionprecedesallcommands.Itconsists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START condition acts as a ‘wake-up’ call for the
Slave devices. A Slave will not respond to commands
unless the MASTER generates a START condition.
STOP Condition
TheSTOPconditioncompletesallcommands.Itconsists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP condition starts the internal write cycle, when
following a WRITE command and sends the Slave into
standby mode, when following a READ command.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
0
1
1
0
0
A
A
A
0
R/W
R/W
Normal Read and Write
2
1
DEVICE ADDRESS
Programming the Write
Protect Register
1
A
A
A
0
2
1
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1052, Rev. O
5
CAT34RC02
acknowledge the Slave address, as long as internal
write is in progress.
WRITE OPERATIONS
Byte Write
WRITE PROTECTION
InByteWritemodetheMastercreatesaSTARTcondition,
and then broadcasts the Slave address, byte address
and data to be written. The Slave acknowledges the
three bytes by pulling down the SDA line during the 9th
clock cycle following each byte. The Master creates a
STOP condition after the last ACK from the Slave, which
then starts the internal write operation (Fig. 6). During
internalwrite,theSlavewillignoreanyread/writerequest
from the Master.
Hardware Write Protection
With the WP pin held HIGH, the entire memory, as well
astheSWPflagsareprotectedagainstWRITEoperations
(Fig. 9). If the WP pin is left floating or is grounded. then
it has no impact on the operation of the CAT34RC02.
Software Write Protection
Page Write
The lower half of memory (first 128 bytes) can be
protected against WRITE operations by setting one of
two Software Write Protection (SWP) flags/switches.
The PSWP (Permanent Software Write Protection) flag
can be set but not cleared by the user. The RSWP
(Reversible Software Write Protection) flag can be set
and cleared by the user. Whereas the PSWP flag can be
set ‘in-system’, the RSWP flag is meant to be used
during testing. RSWP commands require the presence
of a very high voltage (higher than VCC) on address pin
A0 and fixed logic levels for the other two address pins.
The CAT34RC02 contains 256 bytes of data, arranged
in16pagesof16byteseach.Thepageisselectedbythe
four most significant bits of the address byte presented
tothedeviceaftertheSlaveaddress, whilethefourleast
significant bits point to the byte within the page. By
‘loading’ more than one data byte into the device, up to
an entire page can be written in one write cycle (Fig. 7).
The internal byte address counter will increment after
each data byte. If the Master transmits more than 16
data bytes, then earlier bytes will be overwritten by later
bytes in a ‘wrap-around’ fashion within the selected
page. The internal write cycle is started following the
STOP condition created by the Master.
The CAT34RC02 is shipped ‘unprotected’. The state of
the SWP flags can be read by issuing an ‘Immediate
Address Read’ command, with the Slave address
‘preamble’ set to 0110 (6h) instead of the ‘normal’ 1010
(Ah).ASWPREADwillreturnthecomplementedversions
of the two flags in the last two slots of the resulting data
byte; the other six more significant bits in the data byte
have no meaning to the user (Fig. 11).
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT34RC02 is busy writing or is ready to accept
commands. Polling is implemented by sending a
‘Selective Read’ command (described under READ
OPERATIONS) to the device. The CAT34RC02 will not
Figure 6. Byte Write Timing
S
T
S
A
R
T
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 7. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1052, Rev. O
6
CAT34RC02
The PSWP flag can be set (forever) by issuing a ‘Byte
Write’command,withtheSlaveaddresspreamblesetto
‘6h’, followedbya‘don’tcare’address, followedby‘don’t
care’ data and a STOP condition. The CAT34RC02 will
acknowledge the Slave address, dummy byte address
and dummy data (Fig. 10). The PSWP flag will be
permanently set (after the internal write cycle is
completed).
command attempts to ‘reaffirm’ one of the two switches,
thentheCAT34RC02willnotacknowledgethecommand
itself. In addition, the CAT34RC02 will not acknowledge
a ‘reaffirming’ SWP command, even if the WP pin is
LOW.
Power-On Reset (POR)
The CAT34RC02 incorporates Power-On Reset (POR)
circuitrywhichprotectsthedeviceagainstmalfunctioning
while VCC is lower than the recommended operating
voltage.
The SWP commands are shown in Table 1.
Table 1. SWP Commands
The device will power up into a read-only state and will
power-down into a reset state when VCC crosses the
POR level of ~1.3V.
Slave Address
PIN
Preamble
Device Address
R/W
READ OPERATIONS
Command
A2
A2
0
A1
A0
A0
B7
0
B6
1
B5
1
B4
0
B3
A2
0
B2
A1
0
B1
A0
1
B0
SWP
READ
Immediate Address Read
A1
0
1
0
0
0
In standby mode, the CAT34RC02 internal address
counterpointstothedatabyteimmediatelyfollowingthe
last byte accessed by a previous operation. If the
‘previous’ byte was the last byte in memory, then the
address counter will point to the first memory byte, etc.
If the CAT34RC02 decodes a Slave address with a ‘1’ in
the R/W bit position (Fig. 8), it will issue an ACK in the 9th
clock cycle, and will then transmit the data byte being
pointed at by the address counter. The Master can then
stop further transmission by issuing a NoACK, followed
by a STOP condition.
RSWP SET
VHV
VHV
A0
0
1
1
0
RSWP
CLEAR
0
1
0
1
1
0
0
1
1
PSWP SET
A2
A1
0
1
1
0
A2
A1
A0
TheCAT34RC02willnotacknowledgeRSWPorPSWP
commands, once the PSWP flag is set. If the PSWP flag
is not set, but the WP pin is HIGH, then the CAT34RC02
willreacttoRSWPorPSWPcommandsasfollows:ifthe
commandattemptsto‘flip’oneofthetwoSWPswitches,
then the CAT34RC02 will respond the same way the
regular memory would, i.e. the command and address
(in this case dummy) are acknowledged, but the data (in
this case dummy) will not be acknowledged; if the
Selective Read
The READ operation can also be started at an address
differentfromtheonestoredintheaddresscounter. The
Figure 8. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
th
8
Bit
DATA OUT
NO ACK
STOP
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1052, Rev. O
7
CAT34RC02
address counter can be ‘initialized’ by performing a
‘dummy’ WRITE operation (Fig. 12). The START
condition is followed by the Slave address (with the R/W
bit set to ‘0’) and the desired byte address. Instead of
following up with data, the Master then issues a 2nd
START, followed by the ‘Immediate Address Read’
sequence, as described earlier.
Sequential Read
If the Master acknowledges the 1st data byte transmitted
by the CAT34RC02, then the device will continue
transmitting as long as each data byte is acknowledged
by the Master (Fig. 13). If the end of memory is reached
during sequential READ, the address counter will ‘wrap-
around’ to the beginning of memory, etc. Sequential
READ works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting
byte address.
Figure 9. Memory Array
FFH
Hardware Write Protectable
(by connecting WP pin to
Vcc)
7FH
Software Write Protectable
(by setting the write
protect flags)
00H
Figure 10. Software Write Protect (Write)
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
X X X X X X X X X X X X X X X X
P
A
C
K
A
C
K
A
C
K
X = Don't Care
* For PSWP A0 is at normal CMOS levels and for RSWP, A0 is at VHV which must be held high beyond the end
of the STOP condition (approximately 1µs of “overlap” is sufficient).
© 2005 by Catalyst Semiconductor, Inc.
Doc. No. 1052, Rev. O
8
Characteristics subject to change without notice
CAT34RC02
Figure 11. Software Write Protect (Read)
RSWP
S
T
A
R
T
S
T
O
P
PSWP
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
0 0 0 0 0 0
DATA
N
A
C
K
O
A
C
K
Figure 12. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 13. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1052, Rev. O
9
CAT34RC02
8-PAD TDFN 2X3 PACKAGE (VP2, SP2)
A
E
PIN 1 INDEX AREA
D
A1
D2
A2
A3
K
SYMBOL
MIN
0.70
0.00
0.45
NOM
0.75
MAX
0.80
0.05
0.65
A
A1
A2
A3
b
0.02
E2
0.55
0.20 REF
0.25
0.18
1.90
1.27
2.90
1.23
0.30
2.10
1.75
3.10
1.90
PIN 1 ID
D
2.00
D2
E
3.00
0.50 TYP
0.40
E2
e
L
K
0.20
0.30
b
L
0.50
e
3 x e
NOTE:
1. ALL DIMENSIONS IN MM. ANGLES IN DEGREES.
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMNALS. COPLANARITY SHALL NOT EXCEED 0.08 MM.
3. WARPAGE SHALL NOT EXCEED 0.10 MM.
4. PACKAGE LENGTH / PACKAGE WIDTH ARE NOT CONSIDERED AS SPECIAL CHARACTERISTIC.
TDFN2X3_(02).eps
© 2005 by Catalyst Semiconductor, Inc.
Doc. No. 1052, Rev. O
10
Characteristics subject to change without notice
CAT34RC02
8-LEAD TSSOP (U, Y, GY)
+
3.0 0.1
-A-
5
8
7.72 TYP
4.16 TYP
6.4
+
4.4 0.1
-B-
(1.78 TYP)
3.2
0.42 TYP
0.65 TYP
LAND PATTERN RECOMMENDATION
0.2 C B A
ALL LEAD TIPS
1
4
PIN #1 IDENT.
SEE DETAIL A
1.1 MAX TYP
0.1
C
ALL LEAD TIPS
0.09 - 0.20 TYP
(0.9)
-C-
+
0.10 0.05 TYP
0.65 TYP
GAGE PLANE
0.25
0.19 - 0.30 TYP
0.3 M
A B S C S
0o- 8o
0.6+0.1
SEATING PLANE
DETAIL A
Notes:
1. Lead coplanarity is 0.004" (0.102mm) maximum.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1052, Rev. O
11
CAT34RC02
ORDERING INFORMATION
Prefix
Device #
34RC02
Suffix
TE13
REV-E
CAT
J
I
Company ID
Temperature Range
I = Industrial (-40°C to +85°C)
Product
Number
Die Revision
34RC02: E
Tape & Reel
Package
U: TSSOP
Y: TSSOP (Lead-free, Halogen-free)
SP2: TDFN
VP2: TDFN (Lead-free, Halogen-free)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
Notes:
(1) The device used in the above example is a CAT34RC02UI-TE13 REV E (TSSOP, Industrial Temperature, 1.7 Volt to 5.5 Volt
Operating Voltage, Tape & Reel)
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1052, Rev. O
12
CAT34RC02
REVISION HISTORY
Date
Revision Comments
09/22/03
A
B
Initial Issue
12/09/03
Removed Automotive temperature range
Changed Industrial Temp to “ I” from “ Blank” in ordering information
01/12/04
C
Updated Features
Replaced Block Diagram with Functional Symbol
Updated Notes for Reliability Characteristics, D.C. Operating
Characteristics and Capacitance
Updated TDFN package
Updated packaging information to reflect new TDFN package
02/20/04
03/22/04
D
E
Re-labeled TDFN package to A0, A1, A2 instead of A1, A2, A3
Updated Absolute Max. Ratings
Updated DC Operating Characteristics
Updated Table 1 (SWP Commands)
Updated Fig 11
Added mechanical package drawings
Corrected TDFN drawing
03/31/04
05/16/04
F
Corrected table 1 SWP Commands
G
Update D.C. Operating Characteristics
Update Write Cycle Limits
Update Revision History
Update Rev Number
06/03/04
H
Update Die Revision in Ordering Information
Eliminate data sheet designation
Updated DC Operating Characteristics
06/07/04
9/27/04
I
Updated Write Cycle Limits
J
Added Power-On Reset (POR) description
Added VHV and deleted ∆VHV in DC Operating Characteristics
10/18/04
1/11/05
K
L
Updated DC Operating Characteristics & notes (removed Note 5)
Deleted DIP and SOIC packages in all areas
Deleted Extended temperature range in all areas
2/17/05
07/19/05
08/05/05
M
N
O
Update Reliability Characteristics table and notes
Update Ordering Information
Update 8-Pad TDFN 2X3 Package (VP2, SP2)
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1052, Rev. O
13
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