CAT5132RI-10 [CATALYST]
Digital Potentiometer, 1 Func, 10000ohm, 2-wire Serial Control Interface, 128 Positions, PDSO10, MSOP-10;
| 型号： | CAT5132RI-10 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | Digital Potentiometer, 1 Func, 10000ohm, 2-wire Serial Control Interface, 128 Positions, PDSO10, MSOP-10 光电二极管 |
| 文件： | 总13页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT5132
15 Volt Digitally Programmable Potentiometer (DPP™)
with 128 Taps and 2-wire Interface
FEATURES
DESCRIPTION
■ Single linear Digitally Programmable Potentiometer The CAT5132 is a high voltage Digitally Programmable
Potentiometer (DPP) integrated with EEPROM memory
and control logic to operate in a similar manner as a
mechanicalpotentiometer. TheDPPconsistsofaseries
■ 128 Resistor taps
■ End-to-end resistance of 10kΩ, 50kΩ & 100kΩ
of resistive elements connected between two externally
accessible end points. The tap points between each
resistive element are connected to the wiper output with
CMOSswitches.Aseparate7-bitcontrolregister(WCR)
independently controls the wiper tap switches for the
DPP. Associated with the control register is a 7-bit
nonvolatile memory data register (DR) used for storing
wiper settings. Writing to the wiper control register or the
nonvolatile data register is via a 2-wire serial bus (I2C-
like).
■ Potentiometer control and memory access via
2-wire interface (I2C-like)
■ Nonvolatile memory storage for wiper settings
■ Automatic recall of saved wiper setting at power up
■ Special increment/decrement instruction mode for
automatic trimming adjustments
■ VCC operation from 2.7 V to 5.5 V
■ V+ (Analog Voltage Supply) operation from +8 V to
+15V
On power-up, WCR is set to mid scale (1000000) and
after the Power Supply becomes stable, the contents of
thedataregister(DR)aretransferredtothewipercontrol
register (WCR) and the wiper is positioned to that
location.
■ Standby current less than 15 µA
■ 100 year nonvolatile memory data retention
■ 10-pin MSOP package
■ Operating temperature of -40˚C to + 85˚C
The CAT5132 comes with 2 voltage supply inputs: VCC
,
the digital supply voltage input and V+, an analog supply
voltage input. These inputs allow the V+ to be as much
as 10 volts higher than the VCC and allow the DPP
terminal values to be as much as 15 volts above ground.
APPLICATIONS
■ LCD screen adjustment
■ Volume control
The CAT5132 can be used as a potentiometer or as a
two-terminal variable resistor. It is intended for circuit
level adjustments. It is supplied standard in the -40°C to
+85°Cindustrialoperatingtemperaturerangeandoffered
in the 10-pin MSOP package.
■ Mechanical potentiometer replacement
■ Gain adjustment
■ Line impedance matching
■ VCOM setting adjustments
BLOCK DIAGRAM
V
V+
CC
SDA
127
R
H
SCL
A0
CONTROL LOGIC AND
ADDRESS DECODE
A1
128 TAP POSITION
DECODE CONTROL
7-BIT
7-BIT WIPER
NONVOLATILE
MEMORY
REGISTER
(DR)
CONTROL
REGISTER
(WCR)
0
R
R
L
W
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25092, Rev. 01
1
CAT5132
PIN CONFIGURATION
PIN DESCRIPTION
Pin
Number
Name
Description
SDA
GND
1
2
3
4
5
10
9
SCL
V+
1
SDA
Serial Data Input/Output - Bidirectional Serial Data pin
used to transfer data into and out of the CAT5132. This
is an Open-Drain I/O and can be wire OR'd with other
Open-Drain (or Open Collector) I/Os.
V
8
R
L
CC
A1
7
R
W
A0
6
R
H
2
3
4
GND
VCC
A1
Ground
Digital Supply Voltage (2.7V to 5.5V)
MSOP 10-Pin Package
Address Select Input to select slave address for
2-wire bus.
5
A0
Address Select Input to select slave address for
2-wire bus.
6
7
8
9
RH
RW
RL
High Reference Terminal for the potentiometer
Wiper Terminal for the potentiometer
Low Reference Terminal for the potentiometer
V+
Analog Supply Voltage for the potentiometer (+8.0V to
15.0V)
10
SCL
Serial Bus Clock input for the 2-wire Serial Bus. This
clock is used to clock all data transfers into and out of
the CAT5132
ORDERING INFORMATION
Prefix
Device #
Suffix
5132
R
CAT
TE13
I
-10
Temperature Range
Company ID
Product
Number
Tape & Reel
2500 units/Reel
I = Industrial (-40°C to 85°C)
Resistance
Package
R: MSOP
Z: MSOP (Green with Sn Lead Finish)
-10: 10k ohms
-50: 50k ohms
-100: 100k ohms
ZG: MSOP (Green with NiPd Au Lead Finsh)
Notes:
1. The device used in the above example is a CAT5132R-10TE13 (MSOP, 10k ohms, Tape & Reel).
2. The Industrial Temperature range of -40˚C to +85˚C is standard on the above product.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25092, Rev. 01
2
CAT5132
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Temperature Under Bias....................-55˚C to +125˚C
Storage Temperature........................ -65˚C to +150˚C
VCC = +2.7V to +5.5V
V+ = 8.0V to +15V
Operating Temperature Range: -40˚C to +85˚C
Voltage on any SDA, SCL, A0 & A1 pins with respect
to Ground (1)(2) .............................. -2.0V to VCC + 2.0V
COMMENT
Voltage on RH, RL & RW Pins with respect
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanentdamagetothedevice.Thesearestressratingsonly,andfunctional
operation of the device at these or any other conditions outside of those listed
in the operational sections of this specification is not implied. Exposure to any
absolutemaximumratingforextendedperiodsmayaffectdeviceperformance
and reliability.
to Ground .................................... -2.0V to “V+” + 1.0V
VCC with respect to Ground ................... -2.0V to 7.0V
V+ with respect to Ground ................... -2.0V to 16.0V
Wiper Current (10 sec) ...................................... +6mA
Lead Soldering temperature (10 sec) ..............+300˚C
POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Limits
Typ
100
50
Symbol
Parameter
Test Conditions
Units
Min
Max
RPOT
RPOT
RPOT
RTOL
Potentiometer Resistance (100kΩ)
Potentiometer Resistance (50kΩ)
Potentiometer Resistance (10kΩ)
Potentiometer Resistance Tolerance
Power Rating
kΩ
kΩ
10
kΩ
+20
50
%
25• C
mW
mA
IW
Wiper Current
+3
Ω
IW = +1mA @ V+ = 12V
IW = +1mA @ V+ = 8V
70
150
200
V+
RW
Wiper Resistance
Ω
110
VTERM
RES
ALIN
Voltage on RW, RH or RL
Resolution
Absolute Linearity (2)
GND = 0V; V+ = 8V to 15V
GND
V
0.78
%
(5)
RW(n)(actual) - RW(n)(expected)
+1
LSB (4)
LSB (4)
ppm/• C
ppm/• C
pF
RLIN
Relative Linearity (3)
RW(n+1) - [RW(n)+LSB](5)
+0.5
(1)
TCRPOT
TCRatio
Temperature Coefficient of RPOT
Ratiometric Temperature Coefficient
+300
(1)
(1)
30
CH/CL/CW Potentiometer Capacitances
fc Frequency Response
10/10/25
0.4
RPOT = 50kΩ
MHz
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
3. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.
4. LSB = (R
R
)/127; where R
and R are the highest and lowest measured values on the wiper terminal.
HM - LM
HM
LM
5. n = 1, 2, ..., 127
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 25092, Rev. 01
3
CAT5132
D.C. ELECTRICAL CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Min
Max
Units
F
= 400kHz, SDA Open,
Power Supply Current
(Volatile Write/Read)
VSCCCL = 5.5V, Input = GND
ICC1
1
mA
FSCL = 400kHz, SDA Open,
VCC = 5.5V, Input = GND
Power Supply Current
(Nonvolatile WRITE)
ICC2
3.0
mA
ISB(VCC) Standby Current (VCC = 5V)
VIN = GND or VCC , SDA = VCC
VCC = 5V, V+ = 15V
VIN = GND to VCC
5
10
µA
µA
µA
µA
V
ISB(V+)
ILI
V+ Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
10
ILO
VOUT = GND to VCC
10
VIL
-1
VCC x 0.3
VCC + 1.0
0.4
VIH
VOL1
Input High Voltage
VCC x 0.7
V
Output Low Voltage (VCC = 3.0) IOL = 3mA
V
CAPACITANCE
TA = 25˚C, f = 1.0MHz, VCC = 5.0V
Symbol
CI/O
Parameter
Test Conditions
VI/O = 0V (1)
Min
Max
8
Units
pF
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, SCL)
CIN
VIN = 0V (1)
6
pF
A.C. CHARACTERISTICS
VCC = 2.7 - 5.5V
Symbol
Parameter (see Fig. 1)
Min
Max
400
50
Units
kHz
ns
FSCL
Clock Frequency
(1)
TI
Noise Suppression Time Constant at SCL & SDA Inputs
SLC Low to SDA Data Out and ACK Out
tAA
1
µs
(1)
tBUF
Time the bus must be free before a new transmission can start
1.2
0.6
1.2
0.6
0.6
0
µs
tHD:STA Start Condition Hold Time
µs
tLOW
tHIGH
Clock Low Period
µs
Clock High Period
µs
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
µs
tHD:DAT Data in Hold Time
ns
(1)
tR
tF
SDA and SCL Rise Time
SDA and SCL Fall Time
0.3
µs
(1)
300
ns
tSU:STO Stop Conditions Setup Time
tDH Data Out Hold Time
0.6
µs
100
ns
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25092, Rev. 01
4
CAT5132
POWER UP TIMING(1)(2)
Symbol
tPUR
Parameter
Min
Max
1
Units
ms
Power-up to Read Operation
Power-up to Write Operation
tPUW
1
ms
XDCP TIMING
Symbol
Parameter
Min
Max
Units
µs
tWRPO
tWRL
Wiper Response Time After Power Supply Stable
Wiper Response Time After Instruction Issued
5
5
10
10
µs
WRITE CYCLE LIMITS
Symbol
Parameter
Write Cycle Time (see Fig. 2)
Min
Max
Units
tWR
5
ms
Thewritecycleisthetimefromavalidstopconditionofawritesequencetotheendoftheinternalprogram/erasecycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not
respond to its slave address.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Reference Test Method
Min
Max
Units
(1)
NEND
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
100,000
100
Cycles/Byte
Years
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(1)
VZAP
2000
100
Volts
(1)
ILTH
mA
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. and t are the delays required from the time VCC is stable until the specified operation can be initiated.
t
PUR
PUW
TYPICAL PERFORMANCE CHARACTERISTICS
Resistance between RW and RL
Icc2 (NV write) vs Temperature
12.000
400
350
300
250
200
150
100
50
Vcc=2.7V; V+=8v
Vcc=5.5V; V+=15V
10.000
8.000
6.000
4.000
2.000
0.000
Vcc = 2.7V
Vcc = 5.5V
0
-50 -30 -10 10 30 50 70 90 110 130
0
16
32
48
64
80
96
112
128
Temperature (°C)
Tap position
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 25092, Rev. 01
5
CAT5132
TYPICAL PERFORMANCE CHARACTERISTICS (CONT)
Absolute Linearity Error per Tap Position
Relative Linearity Error
1.000
0.500
Tamb = 25 C
Vcc=2.7V; V+=8v
0.800
Vcc=2.7V; V+=8V
Vcc=5.5V; V+=15V
Rtotal = 10K
Tamb = 25 C
Rtotal = 10K
0.400
0.300
0.200
0.100
0.000
-0.100
-0.200
-0.300
-0.400
-0.500
Vcc=5.5V; V+=15V
0.600
0.400
0.200
0.000
-0.200
-0.400
-0.600
-0.800
-1.000
0
16
32
48
64
80
96
112
128
0
16
32
48
64
80
96
112
128
Tap position
Tap position
t
t
t
R
F
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
t
DH
AA
SDA OUT
Figure 1. Bus Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 2. Write Cycle Timing
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25092, Rev. 01
6
CAT5132
Acknowledge
SERIAL BUS PROTOCOL
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data (see Fig. 4).
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock is high will be
interpreted as a START or STOP condition.
The CAT5132 responds with an acknowledge after
receiving a START condition and its slave address. If
thedevicehasbeenselectedalongwithawriteoperation,
it responds with an acknowledge after receiving each
8-bit byte.
The device controlling the transfer is a master, typically
aprocessororcontroller,andthedevicebeingcontrolled
istheslave.Themasterwillalwaysinitiatedatatransfers
and provide the clock for both transmit and receive
operations. Therefore, the CAT5132 will be considered
a slave device in all applications.
WhentheCAT5132isinaREADmodeittransmits8bits
of data, releases the SDA line, and monitors the line for
an acknowledge. Once it receives this acknowledge,
the CAT5132 will continue to transmit data. If no
acknowledgeissentbytheMaster,thedeviceterminates
data transmission and waits for a STOP condition.
START Condition
Acknowledge Polling
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT5132 monitors the
SDA and SCL lines and will not respond until this
condition is met (see Fig. 3).
Thedisablingoftheinputscanbeusedtotakeadvantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
the CAT5132 initiates the internal write cycle. ACK
pollingcanbeinitiatedimmediately.Thisinvolvesissuing
the start condition followed by the slave address. If the
CAT5132 is still busy with the write operation, no ACK
willbereturned. IftheCAT5132hascompletedthewrite
operation,anACKwillbereturnedandthehostcanthen
proceed with the next instruction operation.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition (see Fig. 3).
SDA
SCL
START CONDITION
STOP CONDITION
Figure 3. Start/Stop Condition
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 4. Acknowledge Condition
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 25092, Rev. 01
7
CAT5132
The next two bits, A1 and A0, are the internal slave
address and must match the physical device address
which is defined by the state of the A1 and A0 input pins
to successfully address the CAT5132. Only the device
with slave address matching the input byte will be
accessed by the master. This allows up to 4 devices to
reside on the same bus. The A1 and A0 inputs can be
actively driven by CMOS input signals or tied to VCC or
Ground.
DEVICE DESCRIPTION
Access Control Register
The volatile register WCR and the non-volatile register
DR of CAT5132 are accessed only by addressing the
volatile Access Register AR first, using the 3 byte I2C
interface for all read and write operations (see Table 1).
The first byte is the slave address/instruction byte (see
details below). The second byte contains the address
(02h) of the AR register. The data in the third byte
controls which register WCR (80h) or DR (00h) is being
addressed (see Figure 5).
The last bit is the READ/WRITE bit and determines the
function to be performed. If it is a “1” a read command is
initiated and if it is a “0” a write is initiated. For the AR
register only write is allowed.
Slave Address Instruction Byte Description
The first byte sent to the CAT5132 from the master
processor is called the Slave/DPP Address Byte. The
most significant five bits of the slave address are a
device type identifier. These bits for the CAT5132 are
fixed at 01010 (refer to Table 2).
After the Master sends a START condition and the slave
address byte, the CAT5132 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address.
Table 1. Access Control Register
1st byte
2nd byte
AR address - 02h
3rd byte
WCR(80h) / DR(00h) selection
ST
ST
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
A
A
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
A
A
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A
A
SP
SP
0
Table 2. Byte 1 Slave Address and Instruction Byte
Device Type Identifier
Slave Address
Read/Write
ID4
0
ID3
1
ID2
0
ID1
1
ID0
0
A1
X
A0
X
R/W
X
(MSB)
(LSB)
SLAVE
ADDRESS
AR REGISTER
ADDRESS
WCR/DR
SELECTION
S
T
A
R
T
& INSTRUCTION
S
T
O
P
BUS ACTIVITY:
MASTER
FIXED
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
VARIABLE
Figure 5. Access Register Addressing Using 3 Bytes
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25092, Rev. 01
8
CAT5132
Wiper Control Register (WCR) Description
The CAT5132 contains a 7-bit Wiper Control Register
which is decoded to select one of the 128 switches along
its resistor array. The WCR is a volatile register and is
written with the contents of the nonvolatile Data Register
(DR) on power-up. The Wiper Control Register loses its
contents when the CAT5132 is powered-down. The
contents of the WCR may be read or changed directly by
thehostusingaREAD/WRITEcommandafteraddressing
the WCR (see Table 1 to access WCR). Since the
CAT5132 will only make use of the 7 LSB bits (The first
data bit, or MSB, is ignored) on write instructions and will
always come back as a “0” on read commands.
A write operation (see Table 3) requires a Start condition, followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the three bytes the CAT5132 responds with an acknowledge.
At this time the data is written only to volatile registers, then the device enters its standby state.
Table 3. WCR Write Operation
1st byte
2nd byte
3rd byte
AR address - 02h
WCR(80h) selection
ST
0
1
0
1
0
0
0
0
A
A
0
0
0
0
0
0
0
0
1
0
0
0
A
A
1
0
0
0
0
0
0
0
A
A
SP
SP
slave address byte
WCR address - 00h
data byte
ST
0
1
0
1
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
An increment operation (see Table 4) requires a Start condition, followed by a valid increment address byte (01011),
a valid address byte 00h. After each of the two bytes, the CAT5132 responds with an acknowledge. At this time if the
data is high then the wiper is incremented or if the data is low the wiper is decremented at each clock. Once the stop
is issued then the device enters its standby state with the WCR data as being the last inc/dec position. Also, the wiper
position does not roll over but is limited to min and max positions.
Table 4. WCR Increment/Decrement Operation
1st byte
2nd byte
3rd byte
AR address - 02h
WCR(80h) selection
ST
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
1
0
0
0
0
0
0
0
A
SP
SP
slave address byte
WCR address - 00h
increment (1) / decrement (0) bits
ST
0
1
0
1
1
0
0
0
A
0
0
0
0
0
0
0
0
A
1
1
1
1
0
0
0
0
Areadoperation(seeTable5)requiresaStartcondition,followedbyavalidslaveaddressbyteforwrite,avalidaddress
byte 00h, a second START and a second slave address byte for read. After each of the three bytes, the CAT5132
responds with an acknowledge and then the device transmits the data byte. The master terminates the read operation
by issuing a STOP condition following the last bit of Data byte.
Table 5. WCR Read Operation
1st byte
2nd byte
3rd byte
AR address - 02h
WCR(80h) selection
ST
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
1
0
0
0
0
0
0
0
A
SP
slave address byte
WCR address - 00h
ST
ST
0
0
1
1
0
1
0
0
0
0
0
1
A
A
0
0
0
0
0
0
0
0
0
slave address byte
data byte
0
1
0
0
X
X
X
X
X
X
X
SP
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 25092, Rev. 01
9
CAT5132
Data Register (DR)
being performed. During the internal non-volatile write
cycle, the device ignores transitions at the SDA and SCL
pins, and the SDA output is at a high impedance state.
The WCR is also written during a write to DR. After a DR
WRITE is complete the DR and WCR will contain the
same wiper position.
The Data Register (DR) is a nonvolatile register and its
contents are automatically written to the Wiper Control
Register (WCR) on power-up. It can be read at any time
without effecting the value of the WCR. The DR, like the
WCR, only stores the 7 LSB bits and will report the MSB
bit as a “0”. Writing to the DR is performed in the same
fashionastheWCRexceptthatatimedelayofupto5ms
is experienced while the nonvolatile store operation is
To write or read to the DR, first the access to DR is selected, see table 1 then the data is written or read using the
following sequences.
A write operation (see Table 6) requires a Start condition, followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the three bytes the CAT5132 responds with an acknowledge.
At this time the data is written both to volatile and non-volatile registers, then the device enters its standby state.
Table 6. DR Write Operation
1st byte
2nd byte
3rd byte
AR address - 02h
DR(00h) selection
ST
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
0
0
0
0
0
0
0
0
A
SP
slave address byte
DR address - 00h
data byte
ST
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
0
0
A
X
X
X
X
X
X
X
X
A
SP
A read operation (see Table 7) requires a Start condition, followed by a valid slave address byte, a valid address byte
00h, a second Start and a second slave address byte for read. After each of the three bytes the CAT5132 responds
with an acknowledge and then the device transmits the data byte. The master terminates the read operation by issuing
a STOP condition following the last bit of Data byte.
Table 7. DR Read Operation
1st byte
2nd byte
3rd byte
AR address - 02h
DR(00h) selection
ST
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
0
0
0
0
0
0
0
0
A
SP
slave address byte
DR address - 00h
ST
ST
0
0
1
1
0
1
0
0
0
0
0
1
A
A
0
0
0
0
0
0
0
0
0
slave address byte
data byte
0
1
0
0
X
X
X
X
X
X
X
SP
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25092, Rev. 01
10
CAT5132
POTENTIOMETER OPERATION
Power-On
The CAT5132 is a 128-position, digital controlled
potentiometer. At power-up the device turns on at the
mid-point wiper location (64) until the wiper register can
beloadedwiththenonvolatilememorylocationpreviously
stored in the device. After the nonvolatile memory data
is loaded into the wiper register the wiper location will
change to the previously stored wiper position.
This offset will appear in each of the CAT5132 end-to-
end resistance values in the same way as the 10kΩ
example. However resistance between each wiper
position for the 50kΩ version will be ~395Ω and for the
100kΩ version will be ~790Ω.
Table 8. Potentiometer Resistance and Wiper
Resistance Offset Effects
The end-to-end nominal resistance of the potentiometer
has 128 contact points linearly distributed across the
total resistor. Each of these contact points is addressed
by the 7 bit wiper register which is decoded to select one
of these 128 contact points.
Typical R to RL Resistance for
Position
00
W10kΩ DPP
70Ω or
0Ω + 70Ω
79Ω + 70Ω
01
149Ω or
5,047Ω or
10,070Ω or
Each contact point generates a linear resistive value
between the 0 position and the 127 position. These
values can be determined by dividing the end-to-end
value of the potentiometer by 127. In the case of the
10kΩ potentiometer~79Ω is the resistance between
each wiper position. However in addition to the ~79Ω for
each resistive segment of the potentiometer, a wiper
resistanceoffsetmustbeconsidered. Table8showsthe
effect of this value and how it would appear on the wiper
terminal.
63
4,977Ω + 70Ω
10,000Ω + 70Ω
127
Typical R to RH Resistance for
Position
00
W10kΩ DPP
10,070Ω or
5,047Ω or
149Ω or
10,000Ω + 70Ω
4,977Ω + 70Ω
79Ω + 70Ω
64
126
127
70Ω or
0Ω + 70Ω
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 25092, Rev. 01
11
CAT5132
PACKAGE OUTLINES
10-LEAD MSOP
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25092, Rev. 01
12
REVISION HISTORY
Date
Rev.
Reason
09/12/2005
01/18/2006
00
01
Initial Issue
Update Ordering Information
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
2
DPP ™
AE ™
MiniPot™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Publication #: 25092
Phone: 408.542.1000
Revison:
01
Fax: 408.542.1200
Issue date:
01/18/06
www.catalyst-semiconductor.com
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