CAT521WI-TE10 [CATALYST]
Configured Digitally Programmable Potentiometer; 配置数字可编程电位计
| 型号： | CAT521WI-TE10 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | Configured Digitally Programmable Potentiometer |
| 文件： | 总10页 (文件大小：73K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT521
Configured Digitally Programmable Potentiometer (DPP™):
Programmable Voltage Applications
TM
FEATURES
APPLICATIONS
■ 8-bit DPP configured as a programmable
■ Automated product calibration
voltage source in DAC-like applications
■ Remote control adjustment of equipment
■ Buffered wiper output
■ Offset, gain and zero adjustments in
■ Non-volatile NVRAM memory wiper storage
■ Output voltage range includes both supply rails
■ 1 LSB accuracy, high resolution
self-calibrating and adaptive control systems
■ Tamper-proof calibrations
■ DAC (with memory) substitute
■ Serial Microwire-like interface
■ Single supply operation: 2.7V - 5.5V
■ Setting read-back without effecting outputs
DESCRIPTION
The CAT521 is a 8-bit digitally-programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for
self-calibrating systems and for applications where
equipment which requires periodic adjustment is either
difficult to access or in a hazardous environment.
settings and stored settings can be read back without
disturbing the DPP’s output.
TheCAT521iscontrolledwithasimple3-wire,Microwire-
like serial interface. A Chip Select pin allows several
devices to share a common serial interface.
Communication back to the host controller is via a single
serial data line thanks to the CAT521 Tri-Stated Data
Output pin. A RDY/BSY output working in concert with
aninternallowvoltagedetectorsignalsproperoperation
of the non-volatile NVRAM memory Erase/Write cycle.
The programmable DPP has an output voltage range
which includes both supply rails. The wiper is buffered
by a rail to rail op amp. The wiper setting, stored in
non-volatile NVRAM memory, is not lost when the
device is powered down and is automatically reinstated
when power is returned. The wiper can be dithered to
test new output values without effecting the stored
The CAT521 is available in 0°C to 70°C commercial and
-40°C to 85°C industrial operating temperature ranges.
Both 14-pin plastic DIP and surface mount packages
are available.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
V
V
DD
REFH
14
RDY/BSY
3
1
DIP Package (P, L)
SOIC Package (J, W)
7
PROGRAM
CONTROL
PROG
1
2
3
4
5
14
13
12
11
10
9
14
13
12
11
10
9
V
V
1
2
3
4
5
V
V
REFH
DD
REFH
DD
5
2
CLK
RDY/BSY
CS
NC
V
CLK
RDY/BSY
CS
NC
V
DI
WIPER
CONTROL
REGISTER
AND
CAT521
CAT521
SERIAL
CONTROL
CLK
OUT
OUT
NVRAM
NC
NC
V
NC
NC
V
4
12
+
CS
V
OU
DI
DI
DO
DO
6
7
6
7
REFL
REFL
SERIAL
DATA
OUTPUT
REGISTER
6
8
PROG
GND
8
PROG
GND
DO
8
9
CAT521
V
GND
REFL
Doc. No. 2003, Rev. F
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
CAT521
ABSOLUTE MAXIMUM RATINGS
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix) ...... 0°C to +70°C
Industrial (‘I’ suffix)........................ -40°C to +85°C
Junction Temperature ..................................... +150°C
Storage Temperature ........................ -65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
Supply Voltage*
VDD to GND ...................................... -0.5V to +7V
Inputs
CLK to GND............................ -0.5V to VDD +0.5V
CS to GND.............................. -0.5V to VDD +0.5V
DI to GND ............................... -0.5V to VDD +0.5V
RDY/BSY to GND ................... -0.5V to VDD +0.5V
PROG to GND ........................ -0.5V to VDD +0.5V
VREFH to GND ........................ -0.5V to VDD +0.5V
VREFL to GND ......................... -0.5V to VDD +0.5V
Outputs
*StressesabovethoselistedunderAbsoluteMaximumRatings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied.Deviceperformanceandreliabilitymaybeimpairedby
exposure to absolute rating conditions for extended periods of
time.
D0 to GND............................... -0.5V to VDD +0.5V
VOUT 1– 4 to GND................... -0.5V to VDD +0.5V
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min
Max
Units
Test Method
(1)
VZAP
ESD Susceptibility
Latch-Up
2000
100
Volts
mA
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(1)(2)
ILTH
NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
POWER SUPPLY
Symbol Parameter
IDD1 Supply Current (Read)
IDD2
Conditions
Min
Typ
Max
Units
Normal Operating
Programming, VDD = 5V
VDD = 3V
—
—
400
1600
1000
—
600
2500
1600
5.5
µA
µA
µA
V
Supply Current (Write)
—
VDD
Operating Voltage Range
2.7
LOGIC INPUTS
Symbol Parameter
Conditions
Min
Typ
Max Units
IIH
Input Leakage Current
VIN = VDD
VIN = 0V
—
—
2
—
—
—
—
10
-10
VDD
0.8
µA
µA
V
IIL
Input Leakage Current
High Level Input Voltage
Low Level Input Voltage
VIH
VIL
0
V
LOGIC OUTPUTS
Symbol Parameter
Conditions
Min
VDD -0.3
—
Typ
—
Max
—
Units
VOH
VIL
High Level Output Voltage IOH = -40µA
V
V
V
Low Level Output Voltage IOL = 1 mA, VDD = +5V
IOL = 0.4 mA, VDD = +3V
—
0.4
0.4
—
—
Doc. No. 2003, Rev. F
2
CAT521
POTENTIOMETER CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
24
Max
Units
kΩ
RPOT
Potentiometer Resistance
See Note 3
RPOT to RPOT Match
Pot Resistance Tolerance
Voltage on VREFH pin
Voltage on VREFL pin
Resolution
—
+0.5
+1
+20
%
%
2.7
0V
VDD
V
VDD - 2.7
V
0.4
0.5
%
INL
Integral Linearity Error
Differential Linearity Error
Buffer Output Resistance
Buffer Output Current
TC of Pot Resistance
Potentiometer Capacitances
1
0.5
10
3
LSB
LSB
Ω
DNL
0.25
ROUT
IOUT
mA
ppm/˚C
pF
TCRPOT
CH/CL
300
8/8
AC ELECTRICAL CHARACTERISTICS:
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol Parameter
Digital
Conditions
Min
Typ
Max
Units
tCSMIN
tCSS
tCSH
tDIS
Minimum CS Low Time
150
100
0
—
—
—
—
—
—
—
400
400
4
—
—
—
—
—
150
150
—
—
5
ns
ns
CS Setup Time
CS Hold Time
ns
DI Setup Time
50
ns
CL=100pF,
tDIH
DI Hold Time
50
ns
see note 1
tDO1
tDO0
tHZ
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Output Delay to Low-Z
Erase/Write Cycle Time
PROG Setup Time
Minimum Pulse Width
Minimum CLK High Time
Minimum CLK Low Time
Clock Frequency
—
ns
—
ns
—
ns
tLZ
—
ns
tBUSY
tPS
—
ms
ns
150
700
500
300
DC
—
—
—
—
—
—
—
—
—
1
tPROG
ns
tCLK
tCLK
fC
H
L
ns
ns
MHz
Analog
tDS
DPP Settling Time to 1 LSB
CLOAD = 10 pF, VDD = +5V
CLOAD = 10 pF, VDD = +3V
—
—
3
6
10
10
µs
µs
NOTES:
1. All timing measurements are defined at the point of signal crossing V / 2.
DD
2. These parameters are periodically sampled and are not 100% tested.
3. The 24kΩ +20% resistors are configured as 4 resistors in parallel which would provide a measured value between V
resistors are not measurable but guaranteed by design and verification of the 6kΩ +20% value.
and V
of 6kΩ +20%. The individual 24kΩ
REFL
REFH
Doc. No. 2003, Rev. F
3
CAT521
A. C. TIMING DIAGRAM
t
1
2
3
4
5
o
t
H
CLK
CLK
t
t
L
t
CSH
CSS
CLK
CS
t
CSMIN
t
DIS
DI
t
DIH
t
DO0
t
LZ
DO
t
HZ
t
DO1
PROG
t
PS
t
PROG
RDY/BSY
t
BUSY
t
1
2
3
4
5
o
Doc. No. 2003, Rev. F
4
CAT521
PIN DESCRIPTION
DPP addressing is as follows:
Pin
Name
Function
DPP OUTPUT
A0
A1
1
2
3
4
5
6
7
VDD
Power supply positive
Clock input pin
V
OUT
1
0
CLK
RDY/BSY
CS
Ready/Busy output
Chip select
DI
Serial data input pin
Serial data output pin
DO
PROG
EEPROM Programming Enable
Input
8
GND
VREFL
NC
Power supply ground
Minimum DAC output voltage
No Connect
9
10
11
12
13
14
NC
No Connect
VOUT
NC
DPP output
No Connect
VREFH
Maximum DPP 1 output voltage
DEVICE OPERATION
CHIP SELECT
The CAT521 is a single 8-bit configured digitally
programmable potentiometer (DPP™) whose output
can be programmed to any one of 256 individual voltage
steps. Once programmed, the output setting is retained
in non-volatile memory and will not be lost when power
is removed from the chip. Upon power up the DPP
returnstothesettingstoredinnon-volatilememory. The
DPPcanbewrittentoandreadfromwithouteffectingthe
output voltage during the read or write cycle. The output
can also be adjusted without altering the stored output
setting, which is useful for testing new output settings
before storing them in memory.
Chip Select (CS) enables and disables the CAT521’s
readandwriteoperations. WhenCSishighdatamaybe
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DPP control register will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DPP outputs to the settings stored in non-
volatile memory and switches DO to its high impedance
Tri-State mode.
Because CS functions like a reset the CS pin has been
desensitized with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
DIGITAL INTERFACE
CLOCK
The CAT521 employs a 3 wire, Microwire-like serial
control interface consisting of Clock (CLK), Chip Select
(CS) and Data In (DI) inputs. For all operations, address
and data are shifted in LSB first. In addition, all digital
data must be preceded by a logic “1” as a start bit. The
DPP address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
The CAT521 clock controls both data flow in and out of
the device and non-volatile memory cell programming.
Serial data is shifted into the DI pin and out of the DO pin
on the clock’s rising edge. While it is not necessary for
theclocktoberunningbetweendatatransfers, theclock
mustbeoperatinginordertowritetonon-volatilememory,
even though the data being saved may already be
resident in the DPP wiper control register.
No clock is necessary upon system power-up. The
CAT521 internal power-on reset circuitry loads data
from non-volatile memory to the DPP without using the
external clock.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
Doc. No. 2003, Rev. F
5
CAT521
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking data
into the control register. Standard CMOS and TTL logic
families work well in this regard and it is recommended
thatanymechanicalswitchesusedforbreadboardingor
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
single serial data line and simplifies interfacing multiple
521s to a microprocessor.
WRITING TO MEMORY
Programming the CAT521’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followedbyatwobitDPPaddressandeightdatabitsare
clockedintotheDPPwipercontrolregisterviatheDIpin.
Data enters on the clock’s rising edge. The DPP output
changes to its new setting on the clock cycle following
D7, the last data bit.
V
REF
VREF, the voltage applied between pins VREFH &VREFL
,
sets the DPP’s Zero to Full Scale output range where
VREFL = Zero and VREFH = Full Scale. VREF can span the
full power supply range or just a fraction of it. In typical
applications VREFH &VREFL are connected across the
power supply rails. When using less than the full supply
voltage be mindfull of the limits placed on VREFH and
VREFL as specified in the References section of DC
Electrical Characteristics.
Programming is accomplished by bringing PROG high
sometimeafterthestartbitandatleast150nspriortothe
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DPP wiper
control register will be ready to receive the next set of
address and data bits. The clock must be kept running
throughout the programming cycle. Internal control
circuitry takes care of generating and ramping up the
programmingvoltagefordatatransfertothenon-volatile
memory cells. The CAT521 non-volatile memory cells
will endure over 1,000,000 write cycles and will retain
dataforaminimumof100yearswithoutbeingrefreshed.
READY/BUSY
When saving data to non-volatile memory, the Ready/
Busy ouput (RDY/BSY) signals the start and duration of
the non-volatile erase/write cycle. Upon receiving a
command to store data (PROG goes high) RDY/BSY
goes low and remains low until the programming cycle
is complete. During this time the CAT521 will ignore any
data appearing at DI and no data will be output on DO.
READING DATA
Each time data is transferred into the DPP wiper control
register currently held data is shifted out via the D0 pin,
thusineverydatatransactionareadcycleoccurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DPP’s output. This feature allows µPs to
poll DPPs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in non-volatile memory so that it can be
restored at the end of the read cycle. In Figure 2 CS
returns low before the 13th clock cycle completes. In
doing so the non-volatile memory's setting is reloaded
into the DPP wiper control register. Since this value is
RDY/BSYisinternallyANDedwithalowvoltagedetector
circuitmonitoringVDD.IfVDDisbelowtheminimumvalue
required for non-volatile programming, RDY/BSY will
remain high following the program command indicating
afailuretorecordthedesireddatainnon-volatilememory.
DATA OUTPUT
Data is output serially by the CAT521, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
itshighimpedanceTri-StatemodewhenCSreturnslow.
Tri-Stating the DO pin allows several 521s to share a
Figure 1. Writing to Memory
Figure 2. Reading from Memory
t
o
1
2
3
4
5
6
7
8
9
10 11 12
t
1
2
3
4
5
6
7
8
9
10 11 12
N
N+1 N+2
o
CS
DI
CS
DI
NEW DPP DATA
1
A0 A1
1
A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA
CURRENT DPP DATA
DO
D0 D1 D2 D3 D4 D5 D6 D7
DO
PROG
D0 D1 D2 D3 D4 D5 D6 D7
PROG
RDY/BSY
RDY/BSY
CURRENT
DPP VALUE
DPP
OUTPUT
DPP
OUTPUT
CURRENT
DPP VALUE
NEW
DPP VALUE
NEW
DPP VALUE
NON-VOLATILE
NON-VOLATILE
VOLATILE
NON-VOLATILE
Doc. No. 2003, Rev. F
6
CAT521
Figure 3. Temporary Change in Output
the same as that which had been there previously no
change in the DPP’s output is noticed. Had the value
heldinthecontrolregisterbeendifferentfromthatstored
innon-volatilememory thenachangewouldoccuratthe
read cycle’s conclusion.
t
1
2
3
4
5
6
7
8
9
10 11 12
N
N+1 N+2
o
CS
DI
NEW DPP DATA
1
A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
TEMPORARILY CHANGE OUTPUT
CURRENT DPP DATA
The CAT521 allows temporary changes in the DPP’s
outputtobemadewithoutdisturbingthesettingsretained
in non-volatile memory. This feature is particularly
useful when testing for a new output setting and allows
for user adjustment of preset or default values without
losing the original factory settings.
D0 D1 D2 D3 D4 D5 D6 D7
DO
PROG
RDY/BSY
DPP
OUTPUT
CURRENT
DPP VALUE
NEW
DPP VALUE
CURRENT
DPP VALUE
Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP settings may be
changed as many times as required. The temporary
settingremainsineffectlongasCSremainshigh. When
CS returns low the DPP will return to the output value
stored in non-volatile memory.
NON-VOLATILE
VOLATILE
NON-VOLATILE
When it is desired to save a new setting acquired using
this feature, the new value must be reloaded into the
DPP wiper control register prior to programming. This is
becausetheCAT521’sinternalcontrolcircuitrydiscards
from the programming register the new data two clock
cycles after receiving it if no PROG signal is received.
APPLICATION CIRCUITS
DPP INPUT
DPP OUTPUT
CODE
ANALOG
OUTPUT
+5V
V
R
R
F
V
V
= ——— (V - V
) + V
ZERO
i
i
DPP
FS
ZERO
255
= 0.99 V
= 0.01 V
FS
V
= 5V
F
+15V
REF
R = R
V
V
V
MSB LSB
1111 1111
REFH
DD
I
ZERO
V
–
OUT
255
—— (.98 V
255
) + .01 V
= .990 V
V
= +4.90V
REF
REF
REF
CONTROL
& DATA
OUT
+
CAT521
OP 07
128
-15V
1000 0000
0111 1111
0000 0001
—— (.98 V
255
) + .01 V
) + .01 V
+ .01 V
= .502 V
= .498 V
= .014 V
V
= +0.02V
= -0.02V
= -4.86V
REF
REF
REF
REF
REF
GND
OUT
V
REFL
127
—— (.98 V
V
REF
REF
REF
255
OUT
OUT
V
(R +R )-V R
I F
DPP
F
I
F
V
=
1
OUT
—— (.98 V
V
REF
R
255
I
For R =R
I
0
0000 0000 —— (.98 V
) + .01 V
= .010 V
REF
V
= -4.90V
V
= 2V -V
REF
REF
OUT
OUT
DPP I
255
Bipolar DPP Output
+5V
R
I
R
F
+15V
V
V
DD
REFH
V
–
OUT
CONTROL
& DATA
+
CAT521
OP 07
DPP
-15V
GND
V
REFL
R
F
V
= (1 + –––) V
OUT
R
I
Amplified DPP Output
Doc. No. 2003, Rev. F
7
CAT521
APPLICATION CIRCUITS (Cont.)
28 - 32V
V+
I > 2 mA
15K
10 µF
V
= 5.000V
REF
1N5231B
V
V
REFH
DD
5.1V
V
V
REFH
DD
CONTROL
& DATA
LT 1029
10K
CAT521
CONTROL
& DATA
+
MPT3055EL
CAT521
GND
V
REFL
–
LM 324
4.02 K
GND
V
REFL
OUTPUT
10 µF
35V
0 - 25V
@ 1A
1.00K
Digitally Trimmed Voltage Reference
Digitally Controlled Voltage Reference
Doc. No. 2003, Rev. F
8
CAT521
ORDERING INFORMATION
Prefix
Device #
Suffix
-TE13
CAT
521
J
I
Package
Optional
Company ID
Product
Number
Tape & Reel
TE13:
2000/Reel
P: PDIP
J: SOIC
L: PDIP (Lead free, Halogen free)
W: SOIC (Lead free, Halogen free)
Temperature Range
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
Notes:
(1) The device used in the above example is a CAT521JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Doc. No. 2003, Rev. F
9
REVISION HISTORY
Date
Rev.
Reason
3/16/2004
7/12/2004
E
F
Updated Potentiometer Characteristics
Updated Functional Diagram
Updated Potentiometre Characteristics
Added Note 3 under Potentiometer/AC Characteristics tables
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
2
DPP ™
AE ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 2003
Revison:
Issue date:
Type:
F
7/12/04
Final
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CATALYST
CAT5221JI-00
IC DUAL 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO20, 0.300 INCH, SOIC-20, Digital Potentiometer
ONSEMI
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