CAT523PTE13_技术文档

Advance Information

CAT523

Configured Digitally Programmable Potentiometer (DPP): Programmable Voltage Applications

APPLICATIONS

FEATURES

■ Two 8-bit DPPS Configured as Programmable

■ Automated product calibration.

■ Remote control adjustment of equipment

Voltages in DAC-like Applications

■ Buffered Wiper Outputs

■ Offset, gain and zero adjustments in Self-

■ Nonvolatile Wiper Storage

Calibrating and Adaptive Control systems.

■ Output voltage range includes both supply rails

■ 2 independently addressable output wipers

■ 1 LSB Accuracy, High Resolution

■ Serial µP interface

■ Tamper-proof calibrations.

■ DAC (with memory) substitute

■ Single supply operation: 2.7V-5.5V

■ Setting read-back without effecting outputs

DESCRIPTION

The CAT523 is a dual, 8-bit digitally-programmable

potentiometerconfiguredforprogrammablevoltageand

DAC-like applications. Intended for final calibration of

productssuchascamcorders,faxmachinesandcellular

telephones on automated high volume production lines,

it is also well suited for systems capable of self

calibration, and applications where equipment which is

either difficult to access or in a hazardous environment,

requires periodic adjustment.

effecting the stored settings and stored settings can be

read back without disturbing the DAC’s output.

Control of the CAT523 is accomplished with a simple 3

wire serial interface. A Chip Select pin allows several

CAT523's to share a common serial interface and

communication back to the host controller is via a single

serial data line thanks to the CAT523’s Tri-Stated Data

Output pin. A RDY/BSY output working in concert with

aninternallowvoltagedetectorsignalsproperoperation

of non-volatile Erase/Write cycle.

The 2 independently programmable DPPs have a

common output voltage range which includes both

supply rails. The wipers are buffered by rail to rail OP

AMPS. Wiper settings, stored in non-volatile memory,

are not lost when the device is powered down and are

automatically reinstated when power is returned. Each

wiper can be dithered to test new output values without

The CAT523 is available in the 0 to 70° C Commercial

and –40° C to + 85° C Industrial operating temperature

ranges and offered in 14-pin plastic DIP and SOIC

mount packages.

PIN CONFIGURATION

FUNCTIONAL DIAGRAM

RDY/BSY

V

H

DD

REF

SOIC Package (J)

DIP Package (P)

14

3

1

H

1

H

1

V

DD

V

1

2

3

4

5

6

14

13

12

11

10

9

1

2

3

4

5

6

14

13

12

11

10

9

DD

REF

7

PROGRAM

CONTROL

PROG

CLK

RDY/BSY

CS

CLK

OUT

2

V

RDY/BSY

CS

OUT

CAT

523

CAT

523

NC

5

2

DI

NC

V

NC

V

DATA

REGISTER

AND

13

12

+

V

1

2

L

OUT

DO

7KΩ

DO

REF

SERIAL

CONTROL

CLK

NONVOLATILE

MEMORY

PROG

GND

PROG

GND

8

7

8

7

4

CS

V

7KΩ

OU

SERIAL

DATA

OUTPUT

6

DO

REGISTER

CAT523

8

9

L

GND

V

REF

Doc. No. 25076-00 2/98 M-1

1

Characteristics subject to change without notice

CAT523

Advance Information

ABSOLUTE MAXIMUM RATINGS*

Junction Temperature ..................................... +150°C

Storage Temperature ....................... –65°C to +150°C

Lead Soldering (10 sec max) .......................... +300°C

Supply Voltage

V_DDto GND ......................................–0.5V to +7V

Inputs

CLK to GND............................–0.5V to V_DD+0.5V

CS to GND..............................–0.5V to V_DD+0.5V

DI to GND ...............................–0.5V to V_DD+0.5V

PROG to GND ........................–0.5V to V_DD+0.5V

V_REFH to GND ........................–0.5V to V_DD+0.5V

V_REFL to GND .........................–0.5V to V_DD+0.5V

Outputs

*StressesabovethoselistedunderAbsoluteMaximumRatings

may cause permanent damage to the device. Absolute

Maximum Ratings are limited values applied individually while

other parameters are within specified operating conditions,

and functional operation at any of these conditions is NOT

implied.Deviceperformanceandreliabilitymaybeimpairedby

exposure to absolute rating conditions for extended periods of

time.

D₀to GND...............................–0.5V to V_DD+0.5V

V_OUT1– 4 to GND...................–0.5V to V_DD+0.5V

Operating Ambient Temperature

Commercial (‘C’ suffix) .................... 0°C to +70°C

Industrial (‘I’ suffix)...................... – 40°C to +85°C

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Min

Max

Units

Test Method

(1)

V_ZAP

ESD Susceptibility

Latch-Up

2000

100

Volts

mA

MIL-STD-883, Test Method 3015

JEDEC Standard 17

(1)(2)

I_LTH

NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.

2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V_CC+ 1V.

DC ELECTRICAL CHARACTERISTICS:

V_DD= +2.7 to +5.5V, V_REFH = V_DD, V_REFL = 0V, unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Resolution

8

—

Bits

Accuracy

INL

Integral Linearity Error

I_LOAD= 10 µA, T_R= C

—

± 1

LSB

T_R= I

I_LOAD= 40 µA,

T_R= C

T_R= I

± 2

DNL

Differential Linearity Error

I_LOAD= 10 µA, T_R= C

T_R= I

± 0.5

± 1.5

I_LOAD= 40 µA,

T_R= C

T_R= I

Logic Inputs

I_IH

Input Leakage Current

High Level Input Voltage

Low Level Input Voltage

V_IN= V_DD

V_IN= 0V

—

2

—

10

–10

V_DD

0.8

µA

V

I_IL

V_IH

V_IL

0

V

References

V_RH

V_RL

Z_IN

V_REFH Input Voltage Range

V_REFL Input Voltage Range

V_REFH–V_REFL Resistance

2.7

GND

—

7k

V_DD

V_DD-2.7

—

V

Ω

Logic Outputs

V_OH

V_OL

High Level Output Voltage

Low Level Output Voltage

I_OH= – 40 µA

V_DD–0.3

—

V

I_OL= 1 mA, V_DD= +5V

I_OL= 0.4 mA, V_DD= +3V

—

0.4

2

CAT523

Units

Advance Information

DC ELECTRICAL CHARACTERISTICS (Cont.):

V_DD= +2.7V to +5.5V , V_REFH = +V_DD, V_REFL = 0V, unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Analog Output

FSO

ZSO

I_L

Full-Scale Output Voltage

V_R= V_REFH–V_REF

L

0.99 V_R

—

0.995 V_R

—

0.01 V_R

1

V

Zero-Scale Output Voltage

DAC Output Load Current

DAC Output Impedance

V_R= V_REFH–V_REF

0.005 V_R

V

—

µA

R_OUT

V_DD= +5V

—

100k

150k

1

Ω

V_DD= +3V

—

Ω

PSSR

Power Supply Rejection

I_LOAD= 250 nA

—

LSB / V

Temperature

TC_O

V_OUTTemperature Coefficient

V_REFH = +5V, V_REFL = 0V

V_DD= +5V, I_LOAD= 250nA

—

200

—

µV/ °C

TC_REF

Temperature Coefficient of

V_REFResistance

V_REFH to V_REF

L

700

ppm / °C

Power Supply

I_DD1

I_DD2

Supply Current (Read)

Supply Current (Write)

Normal Operating

V_DD=5V

V_DD=3V

—

400

1600

1000

600

2500

1600

µA

V_DD

Operating Voltage Range

2.7

—

5.5

V

AC ELECTRICAL CHARACTERISTICS:

V_DD= +2.7V to +5.5V, V_REFH = +V_DD, V_REFL = 0V, unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Digital

t_CSMIN

t_CSS

t_CSH

t_DIS

Minimum CS Low Time

CS Setup Time

150

100

0

—

400

4

—

150

—

5

ns

ms

ns

MHz

CS Hold Time

DI Setup Time

C_L= 100 pF,

50

see note 1

t_DIH

DI Hold Time

50

t_DO1

t_DO0

t_HZ

Output Delay to 1

—

Output Delay to 0

—

Output Delay to High-Z

Erase/Write Cycle Time

Output Delay to Low-Z

Erase/Write Pulse Width

PROG Setup Time

Minimum CLK High Time

Minimum CLK Low Time

Clock Frequency

—

t_Busy

t_LZ

t_PROG

t_PS

—

400

—

1

700

150

500

300

DC

t_CLK

f_C

H

L

Analog

t_DS

DAC Settling Time to 1/2 LSB

C_LOAD= 10 pF, V_DD= +5V

C_LOAD= 10 pF, V_DD= +3V

—

3

6

10

µs

Pin Capacitance

C_IN

Input Capacitance

Output Capacitance

V_IN= 0V, f = 1 MHz⁽²⁾

V_OUT= 0V, f = 1 MHz⁽²⁾

—

8

6

—

pF

C_OUT

NOTES: 1. All timing measurements are defined at the point of signal crossing V_DD/ 2.

2. These parameters are periodically sampled and are not 100% tested.

3

CAT523

Advance Information

A. C. TIMING DIAGRAM

t

1

2

3

4

5

o

t

H

CLK

t

L

t

CSH

CSS

CLK

CS

t

CSMIN

t

DIS

DI

t

DIH

t

DO0

t

LZ

DO

t

HZ

t

DO1

PROG

t

PS

t

PROG

RDY/BSY

t

BUSY

t

1

2

3

4

5

o

4

CAT523

Advance Information

PIN DESCRIPTION

DAC addressing is as follows:

Name

Function

DAC OUTPUT

A0

0

A1

0

1

2

3

4

5

6

7

V_DD

CLK

Power supply positive.

Clock input pin.Clock input pin.

Ready/Busy Output

Chip Select

V

1

OUT

2

1

0

RDY/BSY

CS

DI

Serial data input pin.

Serial data output pin.

DO

PROG

EEPROM Programming Enable

Input

8

GND

Power supply ground.

Minimum DAC output voltage.

No Connect.

9

V_REF

NC

L

10

11

12

13

14

NC

No Connect.

V_OUT

2

1

DAC output channel 2.

DAC output channel 1.

Maximum DAC output voltage.

V_REF

H

DEVICE OPERATION

read to or from the chip, and the Data Output (DO) pin is

active. Data loaded into the DAC control registers will

remain in effect until CS goes low. Bringing CS to a logic

low returns all DAC outputs to the settings stored in

EEPROM memory and switches DO to its high imped-

ance Tri-State mode.

The CAT523 is a quad 8-bit Digital to Analog Converter

(DAC) whose outputs can be programmed to any one of

256 individual voltage steps. Once programmed, these

output settings are retained in non-volatile EEPROM

memoryandwillnotbelostwhenpowerisremovedfrom

the chip. Upon power up the DACs return to the settings

stored in EEPROM memory. Each DAC can be written

to and read from independently without effecting the

output voltage during the read or write cycle. Each

output can also be temporarily adjusted without chang-

ing the stored output setting, which is useful for testing

new output settings before storing them in memory.

Because CS functions like a reset the CS pin has been

equipped with a 30 ns to 90 ns filter circuit to prevent

noise spikes from causing unwanted resets and the loss

of volatile data.

CLOCK

The CAT523’s clock controls both data flow in and out of

the IC and EEPROM memory cell programming. Serial

data is shifted into the DI pin and out of the DO pin on the

clock’srisingedge. Whileitisnotnecessaryfortheclock

to be running between data transfers, the clock must be

operating in order to write to EEPROM memory, even

though the data being saved may already be resident in

the DAC control register.

DIGITAL INTERFACE

The CAT523 employs a standard 3 wire serial control

interface consisting of Clock (CLK), Chip Select (CS)

and Data In (DI) inputs. For all operations, address and

data are shifted in LSB first. In addition, all digital data

must be preceded by a logic “1” as a start bit. The DAC

address and data are clocked into the DI pin on the

clock’s rising edge. When sending multiple blocks of

information a minimum of two clock cycles is required

between the last block sent and the next start bit.

No clock is necessary upon system power-up. The

CAT523’s internal power-on reset circuitry loads data

from EEPROM to the DACs without using the external

clock.

Multiple devices may share a common input data line by

selectively activating the CS control of the desired IC.

Data Outputs (DO) can also share a common line

because the DO pin is Tri-Stated and returns to a high

impedance when not in use.

As data transfers are edge triggered clean clock transi-

tionsarenecessarytoavoidfalselyclockingdataintothe

control registers. Standard CMOS and TTL logic fami-

lies work well in this regard and it is recommended that

any mechanical switches used for breadboarding or

device evaluation purposes be debounced by a flip-flop

or other suitable debouncing circuit.

CHIP SELECT

Chip Select (CS) enables and disables the CAT523’s

readandwriteoperations. WhenCSishighdatamaybe

5

CAT523

Advance Information

V

complished through the control signals: Chip Select

(CS) and Program (PROG). With CS high, a start bit

followedbyatwobitDACaddressandeightdatabitsare

clockedintotheDACcontrolregisterviatheDIpin. Data

enters on the clock’s rising edge. The DAC output

changes to its new setting on the clock cycle following

D7, the last data bit.

REF

V_REF,thevoltageappliedbetweenpinsV_REFHandV_REFL,

sets the DAC’s Zero to Full Scale output range where

V_REFL=ZeroandV_REFH=FullScale. V_REFcanspanthe

full power supply range or just a fraction of it. In typical

applications V_REFHandV_REFL are connected across the

power supply rails. When using less than the full supply

voltageV_REFHisrestrictedtovoltagesbetweenV_DDand

V_DD/2 and V_REFL to voltages between GND and V_DD/2.

Programming is achieved by bringing PROG high for a

minimum of 3 ms. PROG must be brought high some-

time after the start bit and at least 150 ns prior to the

rising edge of the clock cycle immediately following the

D7 bit. Two clock cycles after the D7 bit the DAC control

register will be ready to receive the next set of address

and data bits. The clock must be kept running through-

out the programming cycle. Internal control circuitry

takes care of ramping the programming voltage for data

transfertotheEEPROMcells. TheCAT523’sEEPROM

memory cells will endure over 100,000 write cycles and

will retain data for a minimum of 100 years without being

refreshed.

READY/BUSY

Whensavingdatatonon-volatileEEPROMmemory,the

Ready/Busy ouput (RDY/BSY) signals the start and

durationoftheEEPROMerase/writecycle.Uponreceiv-

ing a command to store data (PROG goes high) RDY/

BSY goes low and remains low until the programming

cycle is complete. During this time the CAT523 will

ignore any data appearing at DI and no data will be

output on DO.

RDY/BSY is internally ANDed with a low voltage detec-

tor circuit monitoring V_DD.If V_DDis below the minimum

value required for EEPROM programming, RDY/BSY

willremainhighfollowingtheprogramcommandindicat-

ing a failure to record the desired data in non-volatile

memory.

READING DATA

Each time data is transferred into a DAC control register

currently held data is shifted out via the D0 pin, thus in

every data transaction a read cycle occurs. Note,

however, that the reading process is destructive. Data

must be removed from the register in order to be read.

Figure 2 depicts a Read Only cycle in which no change

occurs in the DAC’s output. This feature allows µPs to

poll DACs for their current setting without disturbing the

output voltage but it assumes that the setting being read

isalsostoredinEEPROMsothatitcanberestoredatthe

end of the read cycle. In Figure 2 CS returns low before

the13^thclockcyclecompletes. IndoingsotheEEPROM’s

setting is reloaded into the DAC control register. Since

DATA OUTPUT

Data is output serially by the CAT523, LSB first, via the

Data Out (DO) pin following the reception of a start bit

and two address bits by the Data Input (DI). DO

becomes active whenever CS goes high and resumes

itshighimpedanceTri-StatemodewhenCSreturnslow.

Tri-Stating the DO pin allows several 523s to share a

single serial data line and simplifies interfacing multiple

523s to a microprocessor.

WRITING TO MEMORY

Programming the CAT523’s EEPROM memory is ac-

Figure 1. Writing to Memory

Figure 2. Reading from Memory

t

1

2

3

4

5

6

7

8

9

10 11 12

N

N+1 N+2

o

t

1

2

3

4

5

6

7

8

9

10 11 12

o

CS

DI

CS

DI

NEW DAC DATA

1

A0 A1 D0 D1 D2 D3 D4 D5 D6 D7

CURRENT DAC DATA

1

A0 A1

DO

PROG

CURRENT DAC DATA

D0 D1 D2 D3 D4 D5 D6 D7

DO

D0 D1 D2 D3 D4 D5 D6 D7

PROG

RDY/BSY

CURRENT

DAC VALUE

DAC

OUTPUT

DAC

OUTPUT

CURRENT

DAC VALUE

NEW

DAC VALUE

NEW

DAC VALUE

NON-VOLATILE

VOLATILE

NON-VOLATILE

6

CAT523

Advance Information

this value is the same as that which had been there

previously no change in the DAC’s output is noticed.

Had the value held in the control register been different

from that stored in EEPROM then a change would occur

at the read cycle’s conclusion.

this feature, the new value must be reloaded into the

DAC control register prior to programming. This is be-

cause the CAT523’s internal control circuitry discards

the new data from the programming register two clock

cycles after receiving it (after reception is complete) if no

PROG signal is received.

TEMPORARILY CHANGE OUTPUT

Figure 3. Temporary Change in Output

TheCAT523 allowstemporarychangesinDAC’soutput

to be made without disturbing the settings retained in

EEPROM memory. This feature is particularly useful

when testing for a new output setting and allows for user

adjustment of preset or default values without losing the

original factory settings.

t

1

2

3

4

5

6

7

8

9

10 11 12

N

N+1 N+2

o

CS

DI

NEW DAC DATA

1

A0 A1 D0 D1 D2 D3 D4 D5 D6 D7

CURRENT DAC DATA

Figure 3 shows the control and data signals needed to

effect a temporary output change. DAC settings may be

changed as many times as required and can be made to

any of the four DACs in any order or sequence. The

temporarysetting(s)remainineffectlongasCSremains

high. WhenCSreturnslowallfourDACswillreturntothe

output values stored in EEPROM memory.

D0 D1 D2 D3 D4 D5 D6 D7

DO

PROG

CURRENT

DAC VALUE

NEW

DAC VALUE

CURRENT

DAC VALUE

NON-VOLATILE

VOLATILE

NON-VOLATILE

DAC

OUTPUT

When it is desired to save a new setting acquired using

APPLICATION CIRCUITS

DAC INPUT

DAC OUTPUT

ANALOG

OUTPUT

+5V

CODE

= ——— (V - V

FS

V

) + V

DAC

ZERO

255

V

R

i

F

= 0.99 V

FS

REF

= 0.01 V

V

= 5V

F

REF

R = R

V

MSB LSB

1111 1111

+15V

I

ZERO

REF

V

H

L

DD

REF

V

255

–

OUT

—— (.98 V

) + .01 V

= .990 V

V

= +4.90V

REF

OUT

CONTROL

& DATA

+

OPT 504

CAT523

OP 07

128

1000 0000

0111 1111

0000 0001

—— (.98 V

255

) + .01 V

= .502 V

= .498 V

= .014 V

V

= +0.02V

= -0.02V

= -4.86V

REF

OUT

-15V

GND

V

REF

127

—— (.98 V

255

V

R

F

V

=

(

R ) -V

R +

F i

i

OUT

DAC

1

—— (.98 V

255

R

i

For R =R

0

i

F

0000 0000 —— (.98 V

) + .01 V

= .010 V

V

= -4.90V

REF

OUT

255

V

= 2V -V

OUT

DAC i

Bipolar DAC Output

+5V

R

i

R

F

+15V

V

H

L

DD

REF

–

V

OUT

CONTROL

& DATA

CAT523

OPT 504

+

OP 07

-15V

GND

V

REF

R

F

V

= (1 + –––) V

OUT

DAC

R

I

Amplified DAC Output

7

CAT523

Advance Information

APPLICATION CIRCUITS (Cont.)

+5V

V

+V

REF

V

REF

R

= —————

C

256 1 µA

*

V

H

DD

REF

+5V

V

REF

Fine adjust gives ± 1 LSB change in V

OFFSET

V

REF

2

when V

= ———

127R

OFFSET

C

V

H

V

DD

REF

FINE ADJUST

DAC

+

)

OFFSET

1 µA

(+V

) - (V

REF

127R

R

= ———————————

C

FINE ADJUST

DAC

+

(-V

) + (V

)

REF

OFFSET

R

= ———————————

o

1 µA

R

C

COARSE ADJUST

DAC

+V

R

C

V

OFFSET

COARSE ADJUST

DAC

+

GND

V

L

REF

+V

-V

R

o

V

–

OFFSET

+

-V

REF

GND

V

L

REF

–

Coarse-Fine Offset Control by Averaging DAC Outputs

for Single Power Supply Systems

Coarse-Fine Offset Control by Averaging DAC Outputs

for Dual Power Supply Systems

28 - 32V

V+

I > 2 mA

15K

10 µF

1N5231B

5.1V

V

= 5.000V

REF

V

H

L

DD

REF

V

H

DD

REF

10K

CONTROL

& DATA

CONTROL

& DATA

LT 1029

+

MPT3055EL

CAT523

OPT 504

CAT523

OPT 504

–

LM 324

4.02 K

GND

V

REF

L

GND

V

REF

OUTPUT

10 µF

35V

0 - 25V

@ 1A

1.00K

Digitally Trimmed Voltage Reference

Digitally Controlled Voltage Reference

8

CAT523

Advance Information

APPLICATION CIRCUITS (Cont.)

+5V

2.2K

V

REF

4.7 µA

DD

LM385-2.5

+15V

I

= 2 - 255 mA

1 mA steps

SINK

DAC

+

2N7000

+5V

–

10K

39Ω1W

39Ω 1W

CONTROL

& DATA

OPT 504

CAT523

DAC

+

5 µA steps

2N7000

3.9K

–

GND

V

L

5 meg

10K

5 meg

REF

10K

–

TIP 30

+

-15V

Current Sink with 4 Decades of Resolution

+15V

51K

+

TIP 29

–

10K

+5V

V

H

DD

REF

5 meg

39Ω 1W

DAC

–

CONTROL

& DATA

OPT 504

CAT523

BS170P

3.9K

1 mA steps

+

5 meg

DAC

–

GND

V

L

REF

BS170P

5 µA steps

+

LM385-2.5

-15V

I

= 2 - 255 mA

SOURCE

Current Source with 4 Decades of Resolution

9

CAT523

Advance Information

ORDERING INFORMATION

Prefix

Device #

Suffix

-TE13

CAT

523

J

I

Optional

Company ID

Product

Number

Package

P: PDIP

J: SOIC

Tape & Reel

TE13: 2000/Reel

Temperature Range

Blank = Commercial (0˚C to +70˚C)

I = Industrial (-40˚C to +85˚C)

Notes:

(1) The device used in the above example is a CAT523JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)

10


型号：	CAT523PTE13
厂家：	CATALYST SEMICONDUCTOR
描述：	Configured Digitally Programmable Potentiometer (DPP): Programmable Voltage Applications 配置的数字可编程电位计（ DPP ）：可编程电压应用
文件：	总10页 (文件大小：72K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CAT523PTE13 [CATALYST]

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CAT524

CAT524

CAT5241