CAT5241J-10TE13 [CATALYST]
10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO20, 0.300 INCH, SOIC-20;
| 型号： | CAT5241J-10TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO20, 0.300 INCH, SOIC-20 光电二极管 转换器 电阻器 |
| 文件： | 总14页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
E
CAT5241
Quad Digitally Programmable Potentiometers (DPP™)
with 64 Taps and 2-wire Interface
TM
FEATURES
■ Automatic recall of saved wiper settings at
■ Four linear-taper digitally programmable
power up
potentiometers
■ 2.5 to 6.0 volt operation
■ 64 resistor taps per potentiometer
■ Standby current less than 1µA
■ 1,000,000 nonvolatile WRITE cycles
■ 100 year nonvolatile memory data retention
■ 20-lead SOIC packages
■ End to end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ
■ Potentiometer control and memory access via
2-wire interface (I2C like)
■ Low wiper resistance, typically 80Ω
■ Nonvolatile memory storage for up to four wiper
■ Commercial and industrial temperature ranges
settings for each potentiometer
DESCRIPTION
registers is via a 2-wire serial bus (I2C-like). On power-
up, the contents of the first data register (DR0) for each
ofthefourpotentiometersisautomaticallyloadedintoits
respective wiper control register (WCR).
The CAT5241 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
aseriesof63resistiveelementsconnectedbetweentwo
externallyaccessibleendpoints.Thetappointsbetween
eachresistiveelementareconnectedtothewiperoutputs
with CMOS switches. A separate 6-bit control register
(WCR)independentlycontrolsthewipertapswitchesfor
each DPP. Associated with each wiper control register
are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
The CAT5241 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.Itisavailableinthe0°Cto70°Ccommercial
and -40°C to 85°C industrial operating temperature
ranges and offered in a 20-lead SOIC package.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
SOIC Package (J, W)
R
R
H3
R
R
H2
H1
H0
20
19
18
17
16
15
14
13
12
11
V
CC
R
1
2
3
4
5
6
7
8
9
10
W0
R
R
R
A
R
W3
L3
L0
R
R
R
R
W0
W1
W2
W3
H0
WIPER
CONTROL
REGISTERS
SCL
SDA
2-WIRE BUS
INTERFACE
A
0
H3
A
2
CAT
5241
1
A
R
3
WP
W1
SCL
R
L1
RH
A0
A1
A2
A3
R
NONVOLATILE
DATA
REGISTERS
1
W2
CONTROL
LOGIC
R
L2
SDA
GND
R
R
H2
R
R
L3
R
R
L2
L1
L0
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Document No. 2011, Rev. F
1
CAT5241
Prelimiary Information
PIN DESCRIPTION
PIN DESCRIPTIONS
Pin
SCL:
Serial Clock
(SOIC)
Name
RW0
RL0
Function
The CAT5241 serial clock input pin is used to clock
all data transfers into or out of the device.
1
Wiper Terminal for Potentiometer 0
Low Reference Terminal for Potentiometer 0
High Reference Terminal for Potentiometer 0
Device Address, LSB
SDA:
Serial Data
2
The CAT5241 bidirectional serial data pin is used
to transfer data into and out of the device. The
SDA pin is an open drain output and can be wire-
Ored with the other open drain or open collector
outputs.
3
RH0
A0
4
5
A2
Device Address
6
RW1
RL1
Wiper Terminal for Potentiometer 1
Low Reference Terminal for Potentiometer 1
High Reference Terminal for Potentiometer 1
Serial Data Input/Output
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when ad-
dressing multiple devices. When these pins are left
floating the default values are zero. A total of
sixteen devices can be addressed on a single bus.
A match in the slave
7
8
RH1
SDA
GND
RH2
RL2
9
10
11
12
13
14
15
16
17
18
19
20
Ground
address must be made with the address input in
order to initiate communication with the CAT5241.
High Reference Terminal for Potentiometer 2
Low Reference Terminal for Potentiometer 2
Wiper Terminal for Potentiometer 2
Bus Serial Clock
RH, RL: Resistor End Points
The four sets of RH and RL pins are equivalent to
the terminal connections on a mechanical potenti-
ometer.
RW2
SCL
A3
Device Address
RW:
Wiper
A1
Device Address
The four RW pins are equivalent to the wiper
terminal of a mechanical potentiometer.
RH3
RL3
High Reference Terminal for Potentiometer 3
Low Reference Terminal for Potentiometer 3
Wiper Terminal for Potentiometer 3
Supply Voltage
RW3
VCC
DEVICE OPERATION
The CAT5241 is four resistor arrays integrated with 2-
wireserialinterfacelogic,four6-bitwipercontrolregisters
and sixteen 6-bit, non-volatile memory data registers.
Each resistor array contains 63 separate resistive
elements connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (RH and RL). RH and RL are
symmetricalandmaybeinterchanged.Thetappositions
between and at the ends of the series resistors are
connected to the output wiper terminals (RW) by a
CMOS transistor switch. Only one tap point for each
potentiometerisconnectedtoitswiperterminalatatime
and is determined by the value of the wiper control
register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via
the 2-wire bus. Additional instructions allows data to be
transferred between the wiper control registers and
each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate
in an "increment/decrement" mode.
Document No. 2011, Rev. F
2
Preliminary Information
CAT5241
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions outside of those listed in the operational sections
of this specification is not implied. Exposure to any absolute
maximum rating for extended periods may affect device perfor-
mance and reliability.
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature........................ -65°C to +150°C
Voltage on any Pin with
Respect toVSS(1) .................... -2.0V to +VCC +2.0V
VCC with Respect to Ground ................ -2.0V to +7.0V
Recommended Operating Conditions:
Package Power Dissipation
V
= +2.5V to +6.0V
CC
Capability (TA = 25°C) ................................... 1.0W
Temperature
Commercial
Industrial
Min
0°C
-40°C
Max
70°C
85°C
Lead Soldering Temperature (10 secs) ............ 300°C
Wiper Current.................................................. +12mA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
RPOT
Parameter
Test Conditions
Min
Typ
100
50
Max
Units
kΩ
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance (-10)
Potentiometer Resistance (-2.5)
RPOT
kΩ
RPOT
10
kΩ
RPOT
2.5
kΩ
Potentiometer Resistance
Tolerance
+20
%
RPOT Matching
Power Rating
1
%
mW
mA
25°C, each pot
50
IW
RW
Wiper Current
+6
Wiper Resistance
Wiper Resistance
Voltage on any RH or RL Pin
Noise
IW = +3mA @ VCC =3V
IW = +3mA @ VCC = 5V
VSS = 0V
300
150
VCC
Ω
RW
80
Ω
VTERM
VN
GND
V
TBD
1.6
nV/ Hz
%
Resolution
Absolute Linearity (3)
Relative Linearity (4)
Rw(n)(actual)-R(n)(expected)
+1
LSB (5)
LSB (5)
ppm/°C
(6)
(6)
Rw(n+1)-[Rw(n)+LSB
]
+0.2
Temperature Coefficient of
RPOT
+300
TCRPOT
TCRATIO
CH/CL/CW
RISO
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Isolation Resistance
20
ppm/°C
pF
10/10/25
TBD
Ω
fc
Frequency Response
RPOT = 50kΩ
0.4
MHz
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(3) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(4) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(5) MI = R
/ 63 or (R - R ) / 63, single pot
TOT
H L
(6) n = 0, 1, 2, ..., 63
Document No. 2011, Rev. F
3
CAT5241
Prelimiary Information
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
ICC
Parameter
Test Conditions
fSCL = 400kHz
Min
Typ
Max
Units
mA
µA
µA
µA
V
Power Supply Current
Standby Current (VCC = 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
1
ISB
VIN = GND or VCC; SDA Open
VIN = GND to VCC
1
10
ILI
ILO
VOUT = GND to VCC
10
VIL
-1
VCC x 0.3
VCC + 1.0
0.4
VIH
Input High Voltage
VCC x 0.7
V
VOL1
Output Low Voltage (VCC = 3.0V)
IOL = 3 mA
V
CAPACITANCE
T = 25°C, f = 1.0 MHz, V
= 5V
A
CC
Symbol Test
Conditions
Min
Typ
Max
8
Units
pF
(1)
CI/O
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL)
VI/O = 0V
(1)
CIN
VIN = 0V
6
pF
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Min
Typ
Max
400
50
Units
kHz
ns
fSCL
TI(1)
tAA
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
0.9
µs
(1)
tBUF
Time the Bus Must be Free Before a New
Transmission Can Start
1.2
µs
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
0.6
1.2
0.6
0.6
0
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
tHIGH
Clock High Period
tSU:STA
tHD:DAT
tSU:DAT
Start Condition SetupTime (For a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
100
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.3
(1)
tF
300
tSU:STO
tDH
0.6
50
(1)
POWER UP TIMING
Over recommended operating conditions unless otherwise stated.
Symbol
tPUR
Parameter
Min
Typ
Max
Units
ms
Power-up to Read Operation
Power-up to Write Operation
1
1
tPUW
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Document No. 2011, Rev. F
4
Preliminary Information
CAT5241
WRITE CYCLE LIMITS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Min
Typ
Max
Units
tWR
Write Cycle Time
5
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle,
the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
Typ
Max
Units
Cycles/Byte
Years
(1)
NEND
Endurance
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(1)
VZAP
2000
Volts
(1)(2)
ILTH
100
mA
Figure 1. Bus Timing
t
t
t
R
F
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
t
BUF
t
t
DH
AA
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Document No. 2011, Rev. F
5
CAT5241
Prelimiary Information
SERIAL BUS PROTOCOL
theparticularslavedeviceitisrequesting. Thefourmost
significant bits of the 8-bit slave address are fixed as
0101 for the CAT5241 (see Figure 5). The next four
significant bits (A3, A2, A1, A0) are the device address
bitsanddefinewhichdevicetheMasterisaccessing. Up
to sixteen devices may be individually addressed by the
system. Typically, +5V and ground are hard-wired to
these pins to establish the device's address.
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high will
be interpreted as a START or STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT5241 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address.
The device controlling the transfer is a master,
typically a processor or controller, and the device
being controlled is the slave. The master will always
initiate data transfers and provide the clock for both
transmit and receive operations. Therefore, the
CAT5241 will be considered a slave device in all
applications.
Acknowledge
Afterasuccessfuldatatransfer, eachreceivingdeviceis
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT5241 monitors the
SDA and SCL lines and will not respond until this
condition is met.
The CAT5241 responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
8-bit byte.
STOP Condition
WhentheCAT5241isinaREADmodeittransmits8bits
of data, releases the SDA line, and monitors the line for
anacknowledge. Onceitreceivesthisacknowledge, the
CAT5241 will continue to transmit data. If no
acknowledgeissentbytheMaster,thedeviceterminates
data transmission and waits for a STOP condition.
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
STARTcondition. TheMasterthensendstheaddressof
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
5020 FHD F06
Document No. 2011, Rev. F
6
Preliminary Information
WRITE OPERATIONS
CAT5241
Acknowledge Polling
Thedisablingoftheinputscanbeusedtotakeadvantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
the CAT5241 initiates the internal write cycle. ACK
pollingcanbeinitiatedimmediately.Thisinvolvesissuing
the start condition followed by the slave address. If the
CAT5241 is still busy with the write operation, no ACK
will be returned. If the CAT5241 has completed the write
operation, anACKwillbereturnedandthehostcanthen
proceed with the next instruction operation.
In the Write mode, the Master device sends the START
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte that defines the
requested operation of CAT5241. The instruction byte
consist of a four-bit opcode followed by two register
selection bits and two pot selection bits. After receiving
another acknowledge from the Slave, the Master device
transmitsthedatatobewrittenintotheselectedregister.
TheCAT5241acknowledgesoncemoreandtheMaster
generates the STOP condition, at which time if a non-
volatiledataregisterisbeingselected,thedevicebegins
an internal programming cycle to non-volatile memory.
Whilethisinternalcycleisinprogress, thedevicewillnot
respond to any request from the Master device.
Figure 5. Slave Address Bits
0
1
0
1
A3
A2
A1
A0
CAT5241
*
A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
Figure 6. Write Timing
S
SLAVE/DPP
ADDRESS
INSTRUCTION
BYTE
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
Pot/WCR Data Register
DR WCRDATA
Fixed
Variable
op code
Address
Address
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
5020 FHD F08
Document No. 2011, Rev. F
7
CAT5241
Prelimiary Information
INSTRUCTION BYTE
INSTRUCTION AND REGISTER
DESCRIPTION
ThenextbytesenttotheCAT5241containstheinstruction
andregisterpointerinformation.Thefourmostsignificant
bits used provide the instruction opcode I [3:0]. The P1
and P0 bits point to one of four Wiper Control Registers.
The least two significant bits, R1 and R0, point to one of
thefourdataregistersofeachassociatedpotentiometer.
The format is shown in Table 2.
Instructions
SLAVE ADDRESS BYTE
The first byte sent to the CAT5241 from the master/
processor is called the Slave/DPP Address Byte. The
most significant four bits of the slave address are a
device type identifier. These bits for the CAT5241 are
fixed at 0101[B] (refer to Table 1).
Data Register Selection
Data Register Selected
R1
0
R0
0
Thenextfourbits, A3-A0, aretheinternalslaveaddress
and must match the physical device address which is
defined by the state of the A3 - A0 input pins for the
CAT5241 to successfully continue the command
sequence.Onlythedevicewhichslaveaddressmatches
theincomingdeviceaddresssentbythemasterexecutes
the instruction. The A3 - A0 inputs can be actively driven
DR0
DR1
DR2
DR3
0
1
1
0
1
1
by CMOS input signals or tied to VCC or VSS
.
Table 1. Identification Byte Format
Device Type
Identifier
Slave Address
ID3
0
ID2
1
ID1
0
ID0
1
A3
A2
A1
A0
(MSB)
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
Data Register
Selection
WCR/Pot Selection
I3
I2
I1
I0
P1
P0
R1
R0
(LSB)
(MSB)
Document No. 2011, Rev. F
8
Preliminary Information
CAT5241
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data Registers
is a non-volatile operation and will take a maximum of
5ms.
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
TheCAT5241containsfour6-bitWiperControlRegisters,
one for each potentiometer. The Wiper Control Register
output is decoded to select one of 64 switches along its
resistor array. The contents of the WCR can be altered
in four ways: it may be written by the host via Write Wiper
Control Register instruction; it may be written by
transferring the contents of one of four associated Data
RegistersviatheXFRDataRegisterinstruction,itcanbe
modified one step at a time by the Increment/decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the content of its data register
zero (DR0) upon power-up.
If the application does not require storage of multiple
settingsforthepotentiometer,theDataRegisterscanbe
used as standard memory locations for system
parameters or user preference data.
INSTRUCTIONS
Four of the nine instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register - read the current
wiperpositionoftheselectedpotentiometerintheWCR
— Write Wiper Control Register - change current
The Wiper Control Register is a volatile register that
loses its contents when the CAT5241 is powered-down.
Although the register is automatically loaded with the
value in DR0 upon power-up, this may be different from
the value present at power-down.
wiperpositionintheWCRoftheselectedpotentiometer
— Read Data Register - read the contents of the
selected Data Register
— Write Data Register - write a new value to the
Data Registers (DR)
selected Data Register
Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
Table 3. Instruction Set
Instruction Set
WCR1/ WCR0/
Instruction
I3
I2
I1
I0
R1
R0
Operation
P1
P0
Read Wiper Control
Register
1
0
0
1
0
0
Read the contents of the Wiper Control
Register pointed to by P1-P0
1/0
1/0
Write Wiper Control Register
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
0
Write new value to the Wiper Control
Register pointed to by P1-P0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
Read Data Register
1/0
1/0
1/0
1/0
1/0
1/0
Read the contents of the Data Register
pointed to by P1-P0 and R1-R0
Write Data Register
Write new value to the Data Register
pointed to by P1-P0 and R1-R0
XFR Data Register to Wiper
Control Register
Transfer the contents of the Data Register
pointed to by P1-P0 and R1-R0 to its
associated Wiper Control Register
XFR Wiper Control Register
to Data Register
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
0
1/0
1/0
1/0
0
1/0
1/0
1/0
0
Transfer the contents of the Wiper Control
Register pointed to by P1-P0 to the Data
Register pointed to by R1-R0
1/0
0
1/0
0
Global XFR Data Registers
to Wiper Control Registers
Transfer the contents of the Data Registers
pointed to by R1-R0 of all four pots to their
respective Wiper Control Regsister
Global XFR Wiper Control
Registers to Data Register
Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1-R0 of all four pots
0
0
Increment/Decrement Wiper
Control Register
Enable Increment/decrement of the Control
Latch pointed to by P1-P0
1/0
1/0
Note: 1/0 = data is one or zero
Document No. 2011, Rev. F
9
CAT5241
Prelimiary Information
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be delayed
bytWRL.AtransferfromtheWCR(currentwiperposition),
to a Data Register is a write to non-volatile memory and
takes a minimum of tWR to complete. The transfer can
occur between one of the four potentiometers and one
of its associated registers; or the transfer can occur
betweenallpotentiometersandoneassociatedregister.
— Global XFR Data Register to Wiper
Control Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
— Global XFR Wiper Counter Register to
Data Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
CAT5241; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 5
and 9). The Increment/Decrement command is different
from the other commands. Once the command is issued
and the CAT5241 has responded with an acknowledge,
the master can clock the selected wiper up and/or down
in one segment steps; thereby providing a fine tuning
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
capability to the host. For each SCL clock pulse (tHIGH
)
while SDA is HIGH, the selected wiper will move one
resistor segment towards the RH terminal. Similarly, for
each SCL clock pulse while SDA is LOW, the selected
wiper will move one resistor segment towards the RL
terminal.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated
Data Register.
See Instructions format for more detail.
Figure 7. Two-Byte Instruction Sequence
SDA
0
1
0
1
ID3 ID2 ID1 ID0
S
A2 A1 A0
S
T
A
R
T
A3
A I3 I2 I1
P0
I0
P1
R1 R0
A
C
K
C
T
K
O
P
Internal
Address
Instruction
Opcode
Register
Address
Pot/WCR
Address
Device ID
Figure 8. Three-Byte Instruction Sequence
SDA
0
1
0
1
S
T
A
R
T
I3
ID3 ID2
ID0
A
C
K
I2
I1
I0
R1 R0
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
P1 P0
ID1
A3 A2 A1 A0
Internal
Address
Device ID
WCR[7:0]
or
Data Register D[7:0]
Instruction
Opcode
Data
Register
Address
Pot/WCR
Address
Figure 9. Increment/Decrement Instruction Sequence
0
1
0
1
SDA
ID3 ID2 ID1 ID0
Device ID
I1
A3 A2 A1 A0
I3
I2
I0
R1 R0
P1 P0
S
T
A
R
T
A
C
K
A
C
K
I
I
D
E
C
1
S
I
D
E
C
n
N
C
1
N
C
2
T
O
P
N
C
n
Internal
Address
Instruction
Opcode
Data
Register
Address
Pot/WCR
Address
Document No. 2011, Rev. F
10
Preliminary Information
CAT5241
Figure 10. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
t
WRID
SCL
SDA
Voltage Out
R
W
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
S
T
A
R
T
A
C
K
S
T
O
P
A
C
K
A
C
K
DEVICE ADDRESSES
0 1 0 1 A3 A2 A1 A0
INSTRUCTION
DATA
1 0 0 1 P1 P0 0 0
7 6
7 6
7 6
5
5
5
4 3 2 1 0
Write Wiper Control Register (WCR)
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
A
C
K
DEVICE ADDRESSES
0 1 0 1 A3 A2 A1 A0
INSTRUCTION
DATA
1 0 1 0 P1 P0 0 0
4 3 2 1 0
Read Data Register (DR)
S
T
A
R
T
A
C
K
S
T
O
P
A
C
K
A
C
K
DEVICE ADDRESSES
INSTRUCTION
DATA
0 1 0 1 A3 A2 A1 A0
1 0 1 1 P1 P0 R1 R0
4 3 2 1 0
Write Data Register (DR)
A
C
K
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
DEVICE ADDRESSES
INSTRUCTION
DATA
0 1 0 1 A3 A2 A1 A0
1 1 0 0 P1 P0 R1 R0
7 6
5
4 3 2 1 0
Document No. 2011, Rev. F
11
CAT5241
Prelimiary Information
INSTRUCTION FORMAT (continued)
Global Transfer Data Register (DR) to Wiper Control Register (WCR)
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
DEVICE ADDRESS
INSTRUCTION
0 1 0 1 A3 A2 A1 A0
0 0 0 1 0 0 R1R0
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
DEVICE ADDRESS
INSTRUCTION
0 1 0 1 A3 A2 A1 A0
1 0 0 0 0 0 R1R0
Transfer Wiper Control Register (WCR) to Data Register (DR)
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
DEVICE ADDRESS
INSTRUCTION
0 1 0 1 A3 A2 A1 A0
1 1 1 0 P1 P0 R1R0
Transfer Data Register (DR) to Wiper Control Register (WCR)
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
DEVICE ADDRESS
INSTRUCTION
0 1 0 1 A3 A2 A1 A0
1 1 1 0 P1 P0 R1R0
Increment (I)/Decrement (D) Wiper Control Register (WCR)
S
T
A
R
T
A
C
K
S
T
O
P
A
C
K
A
C
K
DEVICE ADDRESS
INSTRUCTION
DATA
0 1 0 1 A3 A2 A1 A0
0 0 1 0 P1 P0 0 0
I/D I/D
I/D I/D
• • •
Notes:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
Document No. 2011, Rev. F
12
Preliminary Information
ORDERING INFORMATION
CAT5241
5241
-10
W: SOIC (Lead free, Halogen free)
-25: 2.5kohm
-10: 10kohm
-50: 50kohm
-00: 100kohm
Notes:
(1) The device used in the above example is a CAT5241JI-10-TE13 (SOIC, Industrial Temperature, 10kohm, Tape & Reel)
PACKAGING INFORMATION
20-LEAD 300 MIL WIDE SOIC (J)
0.2914 (7.40) 0.394 (10.00)
0.2992 (7.60) 0.419 (10.65)
0.5985 (15.20)
0.6141 (15.60)
0.0926 (2.35)
0.1043 (2.65)
0.050 (1.27) BSC
0.0040 (0.10)
0.0118 (0.30)
0.013 (0.33)
0.020 (0.51)
0.010 (0.25)
X 45
0.029 (0.75)
0.0091 (0.23)
0.0125 (0.32)
0 —8
0.016 (0.40)
0.050 (1.27)
Document No. 2011, Rev. F
13
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
DPPs ™ AE2 ™
I2C is a trademark of Philips Corporation
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issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
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PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Publication #: 2011
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
Revison:
Issue date:
Type:
F
6/27/03
Preliminary
www.catalyst-semiconductor.com
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