CAT5259UI-00 [CATALYST]
Digital Potentiometer, 4 Func, 100000ohm, 2-wire Serial Control Interface, 256 Positions, PDSO24, TSSOP-24;
| 型号： | CAT5259UI-00 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | Digital Potentiometer, 4 Func, 100000ohm, 2-wire Serial Control Interface, 256 Positions, PDSO24, TSSOP-24 光电二极管 转换器 电阻器 |
| 文件： | 总16页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT5259
Quad Digitally Programmable Potentiometers (DPP™)
with 256 Taps and 2-wire Interface
TM
FEATURES
■ Four linear taper digitally programmable
■ Automatic recall of saved wiper settings at
potentiometers
power up
■ 256 resistor taps per potentiometer
■ End to end resistance 50kΩ or 100kΩ
■ 2.5 to 6.0 volt operation
■ Standby current less than 1 µA
■ 1,000,000 nonvolatile WRITE cycles
■ 100 year nonvolatile memory data retention
■ 24-lead SOIC and 24-lead TSSOP packages
■ Industrial temperature range
■ Potentiometer control and memory access via
2-wire interface (I2C like)
■ Low wiper resistance, typically 100Ω
■ Nonvolatile memory storage for up to four
wiper settings for each potentiometer
DESCRIPTION
The CAT5259 is four digitally programmable
potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of resistive elements connected between two
externallyaccessibleendpoints.Thetappointsbetween
eachresistiveelementareconnectedtothewiperoutputs
with CMOS switches. A separate 8-bit control register
(WCR)independentlycontrolsthewipertapswitchesfor
each DPP. Associated with each wiper control register
are four 8-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
registers is via a 2-wire serial bus. On power-up, the
contents of the first data register (DR0) for each of the
four potentiometers is automatically loaded into its
respective wiper control registers.
The CAT5259 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.Itisavailableinthe0˚Cto70˚Ccommercial
and -40˚C to 85˚C industrial operating temperature
ranges and offered in a 24-lead SOIC and TSSOP
package.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
SOIC/TSSOP Package (J, W/U, Y)
R
R
H3
R
H1
R
H2
H0
24
23
22
21
20
19
18
17
16
15
14
13
1
NC
A0
A3
2
SCL
RL2
RH2
R
R
R
W0
W1
W2
W3
3
R
WIPER
CONTROL
REGISTERS
SCL
SDA
W3
H3
L3
2-WIRE BUS
INTERFACE
4
R
R
5
R
W2
WP
6
NC
NC
CAT
5259
7
V
GND
CC
A0
A1
A2
A3
NONVOLATILE
DATA
REGISTERS
8
CONTROL
LOGIC
R
R
W1
L0
9
R
R
R
R
H0
H1
10
11
12
R
L1
W0
A2
A1
R
R
L3
R
R
L2
L1
L0
WP
SDA
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Document No. 2000, Rev. F
1
CAT5259
PIN DESCRIPTION
PIN DESCRIPTIONS
Pin
(SOIC/
TSSOP)
SCL: Serial Clock
The CAT5259 serial clock input pin is used to
clock all data transfers into or out of the device.
Name
NC
Function
1
No Connect
SDA: Serial Data
2
A0
Device Address, LSB
The CAT5259 bidirectional serial data pin is
used to transfer data into and out of the device.
The SDA pin is an open drain output and can be
wire-Ored with the other open drain or open
collector I/Os.
3
RW3
RH3
RL3
NC
Wiper Terminal for Potentiometer 3
High Reference Terminal for Potentiometer 3
Low Reference Terminal for Potentiometer 3
No Connect
4
5
6
A0, A1, A2, A3:Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A
match in the slave address must be made with
the address input in order to initiate communica-
tion with the CAT5259.
7
VCC
RL0
RH0
RW0
A2
Supply Voltage
8
Low Reference Terminal for Potentiometer 0
High Reference Terminal for Potentiometer 0
Wiper Terminal for Potentiometer 0
Device Address
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
RH, RL: Resistor End Points
Write Protection
WP
The four sets of RH and RL pins are equivalent
to the terminal connections on a mechanical
potentiometer.
SDA
A1
Serial Data Input/Output
Device Address
RW:
Wiper
RL1
RH1
RW1
GND
NC
Low Reference Terminal for Potentiometer 1
High Reference Terminal for Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
The four RW pins are equivalent to the wiper
terminal of a mechanical potentiometer.
WP:
Write Protect Input
The WP pin when tied low prevents non-volatile
writes to the device (change of wiper control
register is allowed) and when tied high or left
floating normal read/write operations are
allowed. See Write Protection on page 6 for
more details.
No Connect
RW2
RH2
RL2
SCL
A3
Wiper Terminal for Potentiometer 2
High Reference Terminal for Potentiometer 2
Low Reference Terminal for Potentiometer 2
Bus Serial Clock
Device Address
DEVICE OPERATION
The CAT5259 is four resistor arrays integrated with a 2-wire serial interface logic, four 8-bit wiper control registers and
sixteen 8-bit, non-volatile memory data registers. Each resistor array contains 255 separate resistive elements
connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL). The tap positions between and at the ends of the series resistors are connected to the
output wiper terminals (RW) by a CMOS transistor switch. Only one tap point for each potentiometer is connected to
its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written
to the wiper control registers or the non-volatile memory data registers via the 2-wire bus. Additional instructions allow
data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate in an "increment/decrement" mode.
Document No. 2000, Rev. F
2
CAT5259
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any
other conditions outside of those listed in the operational sections
of this specification is not implied. Exposure to any absolute
maximum rating for extended periods may affect device perfor-
mance and reliability.
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Voltage on any Pin with
Respect toVSS(1)(2) ................ –2.0V to +VCC +2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Recommended Operating Conditions:
Package Power Dissipation
V
CC
= +2.5V to +6.0V
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Wiper Current.................................................... +6mA
Note:
Temperature
Min
Max
Industrial
-40°C
85°C
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
Min.
Typ.
100
50
Max.
Units
kΩ
Test Conditions
RPOT Potentiometer Resistance (100KΩ)
RPOT
Potentiometer Resistance (50KΩ)
kΩ
Potentiometer Resistance
Tolerance
+20
%
RPOT Matching
Power Rating
1
%
mW
mA
Ω
50
25°C, each pot
IW
RW
Wiper Current
+3
Wiper Resistance
Wiper Resistance
Voltage on any RH or RL Pin
Noise
200
100
300
150
VCC
IW = +3mA @ VCC = 3V
IW = +3mA @ VCC = 5V
VSS = 0V
RW
Ω
VTERM
VN
VSS
V
nV/√Hz
%
(1)
Resolution
0.4
(5)
Absolute Linearity (2)
Relative Linearity (3)
+1
LSB (4) Rw(n)(actual)-R(n)(expected)
(5)
+0.2
LSB (4)
ppm/˚C
ppm/˚C
pF
Rw(n+1)-[Rw(n)+LSB]
TCRPOT Temperature Coefficient of RPOT
+300
(1)
(1)
(1)
TCRATIO
CH/CL/CW
fc
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
20
10/10/25
0.4
MHz
RPOT = 50KΩ(1)
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(4) LSB = R
/ 255 or (R - R ) / 255, single pot
TOT
H L
(5) n = 0, 1, 2, ..., 255
Document No. 2000, Rev. F
3
CAT5259
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +6.0V, unless otherwise specified.
Symbol
Parameter
Min
Max
Units
Test Conditions
ICC1
Power Supply Current
1
mA
fSCL = 400 KHz, SDA = Open
VCC = 6 V, Inputs = GND
ICC2
Power Supply Current
Non-volatile WRITE
5
mA
fSCK = 400 KHz, SDA Open
VCC = 6 V, Input = GND
ISB
ILI
Standby Current (VCC = 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
5
10
µA
µA
µA
V
VIN = GND or VCC, SDA = Open
VIN = GND to VCC
ILO
VIL
VIH
10
VOUT = GND to VCC
-1
VCC x 0.3
Input High Voltage
VCC x 0.7 VCC + 1.0
0.4
V
VOL1 Output Low Voltage (VCC = 3.0V)
V
IOL = 3 mA
CAPACITANCE
T = 25˚C, f = 1.0 MHz, V
= 5V
A
CC
Symbol
Test
Max. Units
Conditions
VI/O = 0V
VIN = 0V
(1)
CI/O
Input/Output Capacitance (SDA)
8
6
pF
pF
(1)
CIN
Input Capacitance (A0, A1, A2, A3, SCL, WP)
A.C. CHARACTERISTICS
2.5V-6.0V
Symbol
fSCL
Parameter
Min.
Max.
400
200
1
Units
kHz
ns
Clock Frequency
TI(1)
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
tAA
µs
(1)
tBUF
Time the bus must be free before a new transmission can start
Start Condition Hold Time
1.2
0.6
1.2
0.6
0.6
0
µs
tHD:STA
tLOW
µs
Clock Low Period
µs
tHIGH
Clock High Period
µs
tSU:STA
tHD:DAT
tSU:DAT
Start Condition SetupTime (for a Repeated Start Condition)
Data in Hold Time
µs
ns
Data in Setup Time
50
ns
(1)
tR
SDA and SCL Rise Time
0.3
µs
(1)
tF
SDA and SCL Fall Time
300
ns
tSU:STO
Stop Condition Setup Time
Data Out Hold Time
0.6
µs
tDH
100
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Document No. 2000, Rev. F
4
CAT5259
(1)(2)
POWER UP TIMING
Symbol
Parameter
Max
1
Units
ms
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are delays required from the time VCC is stable until the specified operation can be initiated.
PUR
PUW
XDCP TIMING
Symbol
tWRPO
tWRL
Parameter
Min
5
Max Units
Wiper Response Time After Power Supply Stable
Wiper Response Time After Instruction Issued
10
10
µs
µs
5
WRITE CYCLE LIMITS
Symbol
Parameter
Max
Units
tWR
Write Cycle Time
5
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min
1,000,000
100
Max
Units
Cycles/Byte
Years
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(1)
NEND
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(1)
VZAP
2000
Volts
(1)
ILTH
100
mA
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Figure 1. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
SU:STA
HD:DAT
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
AA
DH
SDA OUT
Document No. 2000, Rev. F
5
CAT5259
SERIAL BUS PROTOCOL
The CAT5259 responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
8-bit byte.
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high will
be interpreted as a START or STOP condition.
WhentheCAT5259isinaREADmodeittransmits8bits
of data, releases the SDA line, and monitors the line for
anacknowledge. Onceitreceivesthisacknowledge, the
CAT5259 will continue to transmit data. If no
acknowledgeissentbytheMaster,thedeviceterminates
data transmission and waits for a STOP condition.
The device controlling the transfer is a master,
typically a processor or controller, and the device
being controlled is the slave. The master will always
initiate data transfers and provide the clock for both
transmit and receive operations. Therefore, the
CAT5259 will be considered a slave device in all
applications.
WRITE OPERATIONS
In the Write mode, the Master device sends the START
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte that defines the
requested operation of CAT5259. The instruction byte
consist of a four-bit opcode followed by two register
selection bits and two pot selection bits. After receiving
another acknowledge from the Slave, the Master device
transmitsthedatatobewrittenintotheselectedregister.
TheCAT5259acknowledgesoncemoreandtheMaster
generates the STOP condition, at which time if a non-
volatiledataregisterisbeingselected,thedevicebegins
an internal programming cycle to non-volatile memory.
Whilethisinternalcycleisinprogress, thedevicewillnot
respond to any request from the Master device.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT5259 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
Acknowledge Polling
Thedisablingoftheinputscanbeusedtotakeadvantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
the CAT5259 initiates the internal write cycle. ACK
pollingcanbeinitiatedimmediately.Thisinvolvesissuing
the start condition followed by the slave address. If the
CAT5259 is still busy with the write operation, no ACK
will be returned. If the CAT5259 has completed the write
operation, anACKwillbereturnedandthehostcanthen
proceed with the next instruction operation.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
STARTcondition. TheMasterthensendstheaddressof
theparticularslavedeviceitisrequesting. Thefourmost
significant bits of the 8-bit slave address are fixed as
0101 for the CAT5259 (see Figure 5). The next four
significant bits (A3, A2, A1, A0) are the device address
bitsanddefinewhichdevicetheMasterisaccessing. Up
to sixteen devices may be individually addressed by the
system. Typically, +5V and ground are hard-wired to
these pins to establish the device's address.
WRITE PROTECTION
After the Master sends a START condition and the slave
address byte, the CAT5259 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address.
The Write Protection feature allows the user to protect
against inadvertent programming of the non-volatile
data registers. If the WP pin is tied to LOW, the data
registersareprotectedandbecomereadonly. Similarly,
the WP pin is going low after start will interrupt non-
volatile write to data registers, while WP pin going low
afteraninternalwritecyclehasstartedwillhavenoeffect
on any write operation. The CAT5259 will accept both
slave addresses and instructions, but the data registers
are protected from programming by the device’s failure
to send an acknowledge after data is received.
Acknowledge
Afterasuccessfuldatatransfer, eachreceivingdeviceis
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
Document No. 2000, Rev. F
6
CAT5259
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Condition
SDA
SCL
START CONDITION
STOP CONDITION
Figure 4. Acknowledge Condition
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
0
1
0
1
A3
A2
A1
A0
CAT5259
*
A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
Document No. 2000, Rev. F
7
CAT5259
INSTRUCTION BYTE
INSTRUCTION AND REGISTER
DESCRIPTION
ThenextbytesenttotheCAT5259containstheinstruction
andregisterpointerinformation.Thefourmostsignificant
bits used provide the instruction opcode I3 - I0. The R1
and R0 bits point to one of the four data registers of each
associated potentiometer. The least two significant bits
point to one of four Wiper Control Registers. The format
is shown in Table 2.
SLAVE ADDRESS BYTE
The first byte sent to the CAT5259 from the master/
processor is called the Slave/DPP Address Byte. The
most significant four bits of the slave address are a
device type identifier. These bits for the CAT5259 are
fixed at 0101[B] (refer to Table 1).
Thenextfourbits, A3-A0, aretheinternalslaveaddress
and must match the physical device address which is
defined by the state of the A3 - A0 input pins for the
CAT5259 to successfully continue the command
sequence.Onlythedevicewhichslaveaddressmatches
theincomingdeviceaddresssentbythemasterexecutes
the instruction. The A3 - A0 inputs can be actively driven
Data Register Selection
Data Register Selected
R1
0
R0
0
DR0
DR1
DR2
DR3
0
1
1
0
by CMOS input signals or tied to VCC or VSS
.
1
1
Figure 6. Write Timing
S
SLAVE/DPP
ADDRESS
INSTRUCTION
BYTE
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
Register
Pot1 WCR
Address
DR1 WCRDATA
Fixed
Variable
op code
Address
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
5020 FHD F08
Table 1. Identification Byte Format
Device Type
Identifier
Slave Address
ID3
0
ID2
1
ID1
0
ID0
A3
A2
A1
A0
1
(MSB)
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
Data Register
Selection
WCR/Pot Selection
I3
I2
I1
I0
R1
R0
P1
P0
(MSB)
(LSB)
Document No. 2000, Rev. F
8
CAT5259
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data Registers
is a non-volatile operation and will take a maximum of
10ms.
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
TheCAT5259containsfour8-bitWiperControlRegisters,
one for each potentiometer. The Wiper Control Register
output is decoded to select one of 256 switches along its
resistor array. The contents of the WCR can be altered
in four ways: it may be written by the host via Write Wiper
Control Register instruction; it may be written by
transferring the contents of one of four associated Data
RegistersviatheXFRDataRegisterinstruction,itcanbe
modified one step at a time by the Increment/decrement
instruction (see Instruction section for more details).
Finally, it is loaded with the content of its data register
zero (DR0) upon power-up.
If the application does not require storage of multiple
settingsforthepotentiometer,theDataRegisterscanbe
used as standard memory locations for system
parameters or user preference data.
INSTRUCTIONS
Four of the nine instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register - read the current
wiperpositionoftheselectedpotentiometerintheWCR
— Write Wiper Control Register - change current
The Wiper Control Register is a volatile register that
loses its contents when the CAT5259 is powered-down.
Although the register is automatically loaded with the
value in DR0 upon power-up, this may be different from
the value present at power-down.
wiperpositionintheWCRoftheselectedpotentiometer
— Read Data Register - read the contents of the
selected Data Register
— Write Data Register - write a new value to the
Data Registers (DR)
selected Data Register
Each potentiometer has four 8-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
Table 3. Instruction Set
Instruction Set
WCR1/ WCR0/
Instruction
I3
I2
I1
I0
R1
R0
Operation
P1
P0
Read Wiper Control
Register
1
0
0
1
0
0
1/0
1/0
Read the contents of the Wiper Control
Register pointed to by P1-P0
Write Wiper Control Register
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
Write new value to the Wiper Control
Register pointed to by P1-P0
Read Data Register
1/0 1/0
1/0 1/0
1/0 1/0
Read the contents of the Data Register
pointed to by P1-P0 and R1-R0
Write Data Register
Write new value to the Data Register
pointed to by P1-P0 and R1-R0
XFR Data Register to Wiper
Control Register
Transfer the contents of the Data Register
pointed to by P1-P0 and R1-R0 to its
associated Wiper Control Register
XFR Wiper Control Register
to Data Register
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
0
1/0 1/0
1/0 1/0
1/0 1/0
1/0
0
1/0
0
Transfer the contents of the Wiper Control
Register pointed to by P1-P0 to the Data
Register pointed to by R1-R0
Gang XFR Data Registers
to Wiper Control Registers
Transfer the contents of the Data Registers
pointed to by R1-R0 of all four pots to their
respective Wiper Control Registers
Gang XFR Wiper Control
Registers to Data Register
0
0
Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1-R0 of all four pots
Increment/Decrement Wiper
Control Register
0
0
1/0
1/0
Enable Increment/decrement of the Control
Latch pointed to by P1-P0
Note: 1/0 = data is one or zero
Document No. 2000, Rev. F
9
CAT5259
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be delayed
bytWR. AtransferfromtheWCR(currentwiperposition),
to a Data Register is a write to non-volatile memory and
takes a minimum of tWR to complete. The transfer can
occur between one of the four potentiometers and one
of its associated registers; or the transfer can occur
betweenallpotentiometersandoneassociatedregister.
— Gang XFR Data Register to Wiper
Control Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
— Gang XFR Wiper Counter Register to
Data Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
CAT5259; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 9
and 10). The Increment/Decrement command is differ-
ent from the other commands. Once the command is
issued and the CAT5259 has responded with an ac-
knowledge, the master can clock the selected wiper up
and/or down in one segment steps; thereby providing a
fine tuning capability to the host. For each SCL clock
pulse (tHIGH) while SDA is HIGH, the selected wiper will
move one resistor segment towards the RH terminal.
Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the RL terminal.
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated
Data Register.
See Instructions format for more detail.
Figure 7. Two-Byte Instruction Sequence
SDA
0
1
0
1
ID3 ID2 ID1 ID0
S
A2 A1 A0
S
T
A
R
T
A3
A I3 I2 I1
I0
R1 R0 P1 P0
A
C
K
C
K
T
O
P
Internal
Address
Instruction
Opcode
Register
Address
Pot/WCR
Address
Device ID
Figure 8. Three-Byte Instruction Sequence
SDA
0
1
0
1
S
T
A
R
T
I3
ID3 ID2
ID0
A
C
K
I2
I1
P1 P0
I0 R1 R0
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
ID1
A3 A2 A1 A0
Internal
Address
Device ID
WCR[7:0]
or
Data Register D[7:0]
Instruction
Opcode
Data
Register Address
Pot/WCR
Address
Figure 9. Increment/Decrement Instruction Sequence
0
1
0
1
SDA
ID3 ID2 ID1 ID0
Device ID
I1
A3 A2 A1 A0
I3
I2
I0
R1 R0 P1 P0
S
T
A
R
T
A
C
K
A
C
K
I
I
D
E
C
1
S
T
O
P
I
D
E
C
n
N
C
1
N
C
2
N
C
n
Internal
Address
Instruction
Opcode
Pot/WCR
Address
Data
Register
Address
Document No. 2000, Rev. F
10
CAT5259
Figure 10. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
t
WRL
SCL
SDA
Voltage Out
R
W
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
S
T
A
R
T
A
C
K
S
T
O
P
A
C
K
A
C
K
DEVICE ADDRESSES
0 1 0 1 A A A A
INSTRUCTION
1 0 0 1 0 0 P P
1 0
DATA
7 6
5
4 3 2 1 0
3
2 1 0
Write Wiper Control Register (WCR)
S
T
A
R
T
A
C
K
S
T
O
P
A
C
K
A
C
K
DEVICE ADDRESS
INSTRUCTION
1 0 1 0 0 0 P P
1 0
DATA
0 1 0 1 A A A A
7 6
5
4 3 2 1 0
3
2 1 0
Read Data Register (DR)
S
T
A
R
T
A
C
K
S
T
O
P
A
C
K
A
C
K
DEVICE ADDRESS
INSTRUCTION
1 0 1 1 R R P P
1 0 1 0
DATA
0 1 0 1 A A A A
7 6
5
4 3 2 1 0
3
2 1 0
Write Data Register (DR)
S
T
A
R
T
A
C
K
S
T
O
P
A
C
K
A
C
K
DEVICE ADDRESS
INSTRUCTION
1 1 0 0 R R P P
1 0 1 0
DATA
0 1 0 1 A A A A
7 6
5
4 3 2 1 0
3
2 1 0
Document No. 2000, Rev. F
11
CAT5259
INSTRUCTION FORMAT (continued)
Gang Transfer Data Register (DR) to Wiper Control Register (WCR)
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
DEVICE ADDRESS
INSTRUCTION
0 0 0 1 R R 0 0
1 0
0 1 0 1 A A A A
3
2 1 0
Gang Transfer Wiper Control Register (WCR) to Data Register (DR)
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
DEVICE ADDRESS
INSTRUCTION
1 0 0 0 R R 0 0
1 0
0 1 0 1 A A A A
3
2 1 0
Transfer Wiper Control Register (WCR) to Data Register (DR)
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
DEVICE ADDRESS
INSTRUCTION
1 1 1 0 R R P P
1 0 1 0
0 1 0 1 A A A A
3
2 1 0
Transfer Data Register (DR) to Wiper Control Register (WCR)
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
DEVICE ADDRESS
INSTRUCTION
1 1 0 1 R R P P
1 0 1 0
0 1 0 1 A A A A
3
2 1 0
Increment (I)/Decrement (D) Wiper Control Register (WCR)
S
T
A
R
T
A
C
K
S
T
O
P
A
C
K
A
C
K
DEVICE ADDRESS
INSTRUCTION
0 0 1 0 0 0 P P
1 0
DATA
0 1 0 1 A A A A
I
/
I
/
I
/
I
/
• • •
3
2 1 0
D D
D D
Notes:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
Document No. 2000, Rev. F
12
CAT5259
ORDERING INFORMATION
U: TSSOP
Y: TSSOP (Lead free, Halogen free)
Notes:
(1) The device used in the above example is a CAT5259JI00-TE13 (SOIC, Industrial Temperature, 100K Ohm, Tape & Reel)
Document No. 2000, Rev. F
13
CAT5259
PACKAGING INFORMATION
24-LEAD 300 MIL WIDE SOIC (J, W)
0.2914 (7.40) 0.394 (10.00)
0.2992 (7.60) 0.419 (10.65)
0.5985 (15.20)
0.6141 (15.60)
0.0926 (2.35)
0.1043 (2.65)
0.050 (1.27) BSC
0.0040 (0.10)
0.0118 (0.30)
0.013 (0.33)
0.020 (0.51)
0.010 (0.25)
X 45
0.029 (0.75)
0.0091 (0.23)
0.0125 (0.32)
0 —8
0.016 (0.40)
0.050 (1.27)
Note: Package information shown in Inches (mm).
Document No. 2000, Rev. F
14
CAT5259
PACKAGING INFORMATION
24-LEAD TSSOP (U, Y)
7.8 + 0.1
-A-
7.72 TYP
6.4
4.16 TYP
4.4 + 0.1
-B-
(1.78 TYP)
3.2
0.42 TYP
0.65 TYP
0.2 C B A
ALL LEAD TIPS
LAND PATTERN RECOMMENDATION
PIN #1 INDENT.
1.1 MAX TYP
0.1 C
ALL LEAD TIPS
(0.9)
-C-
0.10 + 0.05 TYP
0.65 TYP
0.19 - 0.30 TYP
0.3 M A B S C S
SEE DETAIL A
GAGE PLANE
0.25
0.09 - 0.20 TYP
0o- 8o
0.6+0.1
SEATING PLANE
DETAIL A
Note: Package information shown in mm.
Document No. 2000, Rev. F
15
REVISION HISTORY
Date
Rev.
Reason
11/12/2003
C
Eliminated BGA package in all areas
Eliminated Commercial temperature range
Added "Green" package marking
3/18/04
D
E
Added TSSOP package in all areas
5/7/2004
Updated Functional Diagram
Updated Pin Descriptions
Updated notes in Absolute Max Ratings
Updated Potentiometer Characteristics table
Updated DC Characteristics table
Added XDCP table
Updated Write Protection text
Changed Figure 3 drawing to Start/Stop Condition from
Start/Stop Timing
Changed Figure 4 title from Acknowledge Timing to Acknowledge Condition
Corrected Instruction Format for Gang Transfer Data Register (DR)
to Wiper Control Register (WCR)
9/21/2004
F
Updated DC Operating Characteristics table
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2
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issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Publication #: 2000
Fax: 408.542.1200
Revison:
F
www.catalyst-semiconductor.com
Issue date:
9/21/04
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