CAT93C46R [CATALYST]
1-Kb Microwire Serial EEPROM; 1 kb的Microwire串行EEPROM
| 型号： | CAT93C46R |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 1-Kb Microwire Serial EEPROM |
| 文件： | 总13页 (文件大小：486K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT93C46R
1-Kb Microwire Serial EEPROM
FEATURES
DESCRIPTION
I High speed operation: 4MHz @ 5V, 2MHz @ 1.8V
I 1.8V to 5.5V supply voltage range
I Selectable x8 or x16 memory organization
I Sequential read
The CAT93C46R is a 1-Kb CMOS Serial EEPROM
device which is organized as either 64 registers of
16 bits or 128 registers of 8 bits, as determined by the
state of the ORG pin. The CAT93C46R features
sequential read and self-timed internal write with auto-
clear. On-chip Power-On Reset circuitry protects the
internal logic against powering up in the wrong state.
I Software write protection
I Power-up inadvertent write protection
I Low power CMOS technology
I 1,000,000 program/erase cycles
I 100 year data retention
In contrast to the CAT93C46, the CAT93C46R features
an internal instruction clock counter which provides
improved noise immunity for Write/Erase commands.
I Industrial temperature range
I RoHS-compliant 8-pin PDIP, SOIC, TSSOP and
8-pad TDFN packages
PIN CONFIGURATION
FUNCTIONAL SYMBOL
PDIP (L)
SOIC (V, X)
TSSOP (Y)
VCC
SOIC (W)
TDFN (VP2)
ORG
CS
1
8
V
NC
1
8
ORG
CC
CS
SK
DI
DO
CAT93C46R
GND
SK
DI
2
3
4
7
6
5
NC
V
2
3
4
7
6
5
GND
DO
DI
CC
CS
ORG
GND
DO
SK
PIN FUNCTIONS
Pin Name
Function
Chip Select
Clock Input
Serial Data Input
CS
SK
For Ordering Information details, see page 12.
DI
DO
VCC
GND
ORG
NC
Serial Data Output
Power Supply
Ground
Memory Organization
No Connection
Note: When the ORG pin is connected to V , the x16 organization
CC
is selected. When it is connected to ground, the x8 pin is selected.
If the ORG pin is left unconnected, then an internal pull-up device
will select the x16 organization.
* The Green & Gold seal identifies RoHS-compliant packaging, using NiPdAu
pre-plated lead frames.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1107, Rev. F
1
CAT93C46R
ABSOLUTE MAXIMUM RATINGS (1)
Storage Temperature
-65°C to +150°C
Voltage on Any Pin with Respect to Ground (2)
-0.5 V to +6.5 V
RELIABILITY CHARACTERISTICS (3)
Symbol
Parameter
Min
Units
(4)
NEND
Endurance
1,000,000
Program/ Erase Cycles
TDR
Data Retention
100
Years
D.C. OPERATING CHARACTERISTICS
= +1.8V to +5.5V, unless otherwise specified.
V
CC
Symbol
Parameter
Test Conditions
Min
Max
Units
ICC1
Power Supply Current
(Write)
fSK = 1MHz
VCC = 5.0V
1
mA
ICC2
ISB1
ISB2
Power Supply Current
(Read)
fSK = 1MHz
VCC = 5.0V
500
10
µA
µA
µA
Power Supply Current
(Standby) (x8 Mode)
CS = 0V
ORG = GND
Power Supply Current
(Standby) (x16Mode)
CS = 0V
ORG = Float or VCC
10
ILI
Input Leakage Current
VIN = 0V to VCC
2
2
µA
µA
ILO
Output Leakage Current
(Including ORG pin)
VOUT = 0V to VCC
CS = 0V
,
VIL1
VIH1
VIL2
VIH2
VOL1
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
4.5V ≤ VCC < 5.5V
4.5V ≤ VCC < 5.5V
1.8V ≤ VCC < 4.5V
1.8V ≤ VCC < 4.5V
-0.1
0.8
VCC + 1
VCC x 0.2
VCC+1
0.4
V
V
V
V
V
2
0
VCC x 0.7
4.5V ≤ VCC < 5.5V
IOL = 2.1mA
VOH1
VOL2
VOH2
Output High Voltage
Output Low Voltage
Output High Voltage
4.5V ≤ VCC < 5.5V
IOH = -400µA
2.4
V
V
V
1.8V ≤ VCC < 4.5V
0.2
IOL = 1mA
1.8V ≤ VCC < 4.5V
IOH = -100µA
VCC - 0.2
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than V +0.5V. During transitions, the voltage on any pin may
CC
undershoot to no less than -1.5V or overshoot to no more than V +1.5V, for periods of less than 20 ns.
CC
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Block Mode, V = 5V, T = 25°C.
CC
A
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1107, Rev. F
2
CAT93C46R
PIN CAPACITANCE
Symbol
Test
Conditions
VOUT = 0V
VIN = 0V
Max
5
Units
pF
(1)
COUT
Output Capacitance (DO)
(1)
CIN
Input Capacitance (CS, SK, DI, ORG)
5
pF
A.C. CHARACTERISTICS(2)
VCC = 1.8V- 5.5V
VCC = 4.5V- 5.5V
Symbol Parameter
Min
50
Max
Min
Max
Units
ns
tCSS
tCSH
tDIS
CS Setup Time
50
0
CS Hold Time
0
ns
DI Setup Time
100
100
50
50
ns
tDIH
tPD1
tPD0
DI Hold Time
ns
Output Delay to 1
0.25
0.25
100
5
0.1
0.1
100
5
µs
Output Delay to 0
µs
(1)
tHZ
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
ns
tEW
ms
µs
tCSMIN
tSKHI
tSKLOW
tSV
0.25
0.25
0.25
0.1
0.1
0.1
µs
µs
0.25
2
0.1
4
µs
SKMAX
DC
DC
MHz
POWER-UP TIMING (1)(3)
Symbol
tPUR
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
Units
ms
1
1
tPUW
ms
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
≤ 50ns
0.4V to 2.4V
0.8V, 2.0V
0.2VCC to 0.7VCC
0.5VCC
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 4.5V
1.8V ≤ VCC ≤ 4.5V
Current Source IOLmax/IOHmax; CL = 100pF
NOTE:
(1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(2) Test conditions according to “A.C. Test Conditions” table.
(3)
t
and t are the delays required from the time V is stable until the specified operation can be initiated.
PUW CC
PUR
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1107, Rev. F
3
CAT93C46R
INSTRUCTION SET
Address
Data
Instruction Start Bit Opcode
x8
x16
x8
x16
Comments
READ
ERASE
WRITE
EWEN
EWDS
ERAL
1
1
1
1
1
1
1
10
11
01
00
00
00
00
A6-A0
A6-A0
A5-A0
A5-A0
A5-A0
11XXXX
00XXXX
10XXXX
01XXXX
Read Address AN– A0
Clear Address AN– A0
A6-A0
D7-D0
D15-D0 Write Address AN– A0
Write Enable
11XXXXX
00XXXXX
10XXXXX
01XXXXX
Write Disable
Clear All Addresses
WRAL
D7-D0
D15-D0 Write All Addresses
DEVICE OPERATION
The CAT93C46R is a 1024-bit nonvolatile memory
intended for use with industry standard microproces-
sors. The CAT93C46R can be organized as either
registers of 16 bits or 8 bits. When organized as X16,
seven 9-bit instructions control the reading, writing and
erase operations of the device. When organized as X8,
seven 10-bit instructions control the reading, writing and
erase operations of the device. The CAT93C46R oper-
ates on a single power supply and will generate on chip
the high voltage required during any write operation.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C46R
will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting out
the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable
after the specified time delay (tPD0 or tPD1).
Sequential Read
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
After the 1st data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle,
the CAT93C46R will automatically increment to the next
address and shift out the next data word. As long as CS
is continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address
automatically until it reaches the end of the address
space, then loops back to address 0. In the sequential
Read mode, only the initial data word is preceeded by a
dummy zero bit; all subsequent data words will follow
without a dummy zero bit.
The ready/busy status can be determined after the start
ofawriteoperationbyselectingthedevice(CShigh)and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DIpin. TheDOpinwillenterthehighimpedancestateon
the rising edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applica-
tions where the DI pin and the DO pin are to be tied
together to form a common DI/O pin. The Ready/Busy
flag can be disabled only in Ready state; no change is
allowed in Busy state.
Erase/Write Enable and Disable
The CAT93C46R powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once the write instruction is
enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C46R write
and erase instructions, and will prevent any accidental
writing or clearing of the device. Data can be read
normally from the device regardless of the write enable/
disable status.
The format for all instructions sent to the device is a
logical"1"startbit, a2-bit(or4-bit)opcode, 6-bitaddress
(an additional bit when organized X8) and for write
operations a 16-bit data field (8-bit for X8 organization).
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1107, Rev. F
4
CAT93C46R
Figure 1. Sychronous Data Timing
t
t
t
SKLOW
SKHI
CSH
SK
t
t
t
DIS
DIH
VALID
VALID
DI
t
CSS
CS
t
t
t
CSMIN
DIS
PD0, PD1
DO
DATA VALID
Figure 2. Read Instruction Timing
SK
t
CSMIN
CS
STANDBY
A
A
A
0
N
N—1
DI
1
1
0
t
HZ
t
HIGH-Z
HIGH-Z
PD0
DO
0
D
D
D
D
0
N
N—1
1
Figure 2b. Sequential Read Instruction Timing
SK
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CS
DI
Don't Care
A
A
A
0
N
N–1
1
1
0
HIGH-Z
DO
Dummy 0
D
D
Address + 1 Address + 2 Address + n
15 . . .
0
or
D
D
D
D
D
15 . . .
0
15 . . .
0
15 . . .
D
D
0
or
or
or
7 . . .
D
D
D
D
D
7 . . .
7 . . .
0
7 . . .
0
Figure 3. EWEN/EWDS Instruction Timing
SK
STANDBY
CS
DI
1
0
0
*
* ENABLE=11
DISABLE=00
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1107, Rev. F
5
CAT93C46R
Write
Erase All
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN (see Design Note for details). The
falling edge of CS will start the self clocking clear and
data store cycle of the memory location specified in the
instruction. The clocking of the SK pin is not necessary
after the device has entered the self clocking mode.
The ready/busy status of the CAT93C46R can be
determined by selecting the device and polling the DO
pin. Since this device features Auto-Clear before write,
it is NOT necessary to erase a memory location before
it is written into.
UponreceivinganERALcommand,theCS(ChipSelect)
pin must be deselected for a minimum of tCSMIN. The
falling edge of CS will start the self clocking clear cycle
of all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory bits return to a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
hasenteredtheselfclockingmode. (Note1.) Theready/
busy status of the CAT93C46R can be determined by
selecting the device and polling the DO pin. It is not
necessary for all memory locations to be cleared before
the WRAL command is executed.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of tCSMIN after the proper number of clock pulses (see
Design Note). The falling edge of CS will start the self
clocking clear cycle of the selected memory location.
The clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The ready/
busy status of the CAT93C46R can be determined by
selecting the device and polling the DO pin. Once
cleared, the content of a cleared location returns to a
logical “1” state.
Design Note
With CAT93C46R, after the last data bit has been
sampled, Chip Select (CS) must be brought Low before
the next rising edge of the clock(SK) in order to start the
slef-timed high voltage cycle. This is important because
if the CS is brought low before or after this specific frame
window, the addressed location will not be programmed
or erased.
Figure 4. Write Instruction Timing
SK
t
CS MIN
STANDBY
STATUS
VERIFY
CS
A
A
A
0
D
D
0
N
N-1
N
DI
1
0
1
t
t
SV
HZ
BUSY
HIGH-Z
DO
READY
HIGH-Z
t
EW
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1107, Rev. F
6
CAT93C46R
Figure 5. Erase Instruction Timing
SK
CS
STANDBY
STATUS VERIFY
CS MIN
t
A
N
A
0
A
N-1
DI
1
1
1
t
t
HZ
SV
HIGH-Z
DO
BUSY
READY
HIGH-Z
t
EW
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
t
CS MIN
DI
1
0
0
1
0
t
t
SV
HZ
HIGH-Z
HIGH-Z
DO
BUSY
READY
t
EW
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY
CS MIN
STANDBY
t
D
D
DI
1
0
0
0
1
N
0
t
t
SV
HZ
DO
BUSY
READY
HIGH-Z
t
EW
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1107, Rev. F
7
CAT93C46R
8-LEAD 300 MIL WIDE PLASTIC DIP (L)
E1
E
D
A2
A
L
A1
e
eB
b2
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
4.57
0.38
3.05
0.36
1.14
9.02
7.62
6.09
3.81
0.56
1.77
10.16
8.25
7.11
0.46
b2
D
E
7.87
6.35
E1
e
2.54 BSC
eB
L
7.87
9.65
0.115
0.130
0.150
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC Standard MS001.
3. Dimensioning and tolerancing per ANSI Y14.5M-1982
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1107, Rev. F
8
CAT93C46R
8-LEAD 150 MIL WIDE SOIC (V, W)
E1
E
h x 45
D
C
A
θ1
e
A1
L
b
SYMBOL
MIN
NOM
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
A1
A
0.10
1.35
0.33
0.19
4.80
5.80
3.80
b
C
D
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.50
1.27
8°
L
θ1
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC specification MS-012.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1107, Rev. F
9
CAT93C46R
8-LEAD TSSOP (Y)
D
5
8
SEE DETAIL A
c
E
E1
E/2
GAGE PLANE
0.25
1
4
PIN #1 IDENT.
θ1
L
A2
SEATING PLANE
SEE DETAIL A
A
e
A1
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
c
D
3.00
6.4
E
E1
e
4.40
0.65 BSC
0.60
L
0.50
0.00
0.75
8.00
θ1
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC Standard MO-153
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1107, Rev. F
10
CAT93C46R
8-PAD TDFN 2X3 PACKAGE (VP2)
A
E
PIN 1 INDEX AREA
D
A1
D2
A2
A3
SYMBOL
MIN
0.70
0.00
0.45
NOM
0.75
MAX
0.80
0.05
0.65
A
A1
A2
A3
b
0.02
E2
0.55
0.20 REF
0.25
0.20
1.90
1.30
2.90
1.20
0.30
2.10
1.50
3.10
1.40
PIN 1 ID
D
2.00
D2
E
1.40
3.00
E2
e
1.30
L
0.50 TYP
0.30
L
0.20
0.40
b
e
3 x e
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC specification MS-229.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1107, Rev. F
11
CAT93C46R
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
93C46R
V
I
– G
T3
Optional
Company ID
Product Number
Temperature Range
I = Industrial (-40°C - 85°C)
Tape & Reel
T: Tape & Reel
2: 2000/Reel(4)
3: 3000/Reel
93C46R
Package
L = PDIP
V = SOIC, JEDEC
W = SOIC, JEDEC
X = SOIC, EIAJ(4)
Y = TSSOP
Lead Finish
G: NiPdAu
VP2 = TDFN (2X3mm)
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT93C46RVI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel).
(4) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C46RXI-T2.
(5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
© 2006 by Catalyst Semiconductor, Inc.
Doc. No. 1107, Rev. F
12
Characteristics subject to change without notice
REVISION HISTORY
Date
Revision Comments
12/01/05
12/07/05
12/14/05
A
B
C
Initial Issue
Update D.C. Operating Characteristics
Update Pin Functions
Update Ordering Information
03/06/06
D
Update Features
Update Pin Configuration
Update A.C. Characteristics
Update Device Operation
Update Package Dimensions
Update Package Marking
Update Tape and Reel
05/16/06
09/11/06
E
F
Update Pin Configuration
Update D.C. Operating Characteristics
Update A.C. Characteristics
Update Device Operation
Update Package Marking
Update Tape and Reel
Update Features
Update Description
Update Pin Functions
Update Functional Symbol
Update Absolute Maximum Ratings
Update Reliability Characteristics
Upadte D.C. Operating Characteristics
Update Pin Capacitance
Update A.C. Characteristics
Update Timing Diagrams
Update Package Dimensions
Remove Package Marking
Update Ordering Information
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Publication #: 1107
Revison:
F
Issue date:
09/11/06
相关型号：
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