CAT93C46WI-1.8G [CATALYST]
EEPROM, 64X16, Serial, CMOS, PDSO8;
| 型号： | CAT93C46WI-1.8G |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 64X16, Serial, CMOS, PDSO8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总16页 (文件大小：511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT93C46
1K-Bit Microwire Serial EEPROM
FEATURES
DESCRIPTION
I High speed operation: 1MHz
The CAT93C46 is a 1K-bit Serial EEPROM memory
device which is configured as either registers of 16 bits
(ORG pin at VCC) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the
DI (or DO) pin. The CAT93C46 is manufactured using
Catalyst’s advanced CMOS EEPROM floating gate
technology. Thedeviceisdesignedtoendure1,000,000
program/erase cycles and has a data retention of 100
years. The device is available in 8-pin DIP, 8-pin SOIC,
8-pin TSSOP and 8-pad TDFN packages.
I Low power CMOS technology
I 1.8 to 5.5 volt operation
I Selectable x8 or x16 memory organization
I Self-timed write cycle with auto-clear
I Hardware and software write protection
I Power-up inadvertant write protection
I 1,000,000 Program/erase cycles
I 100 year data retention
I Industrial temperature ranges
I RoHS compliant “
” & “
”
8-pin PDIP, SOIC, TSSOP and TDFN packages
PIN CONFIGURATION
FUNCTIONAL SYMBOL
VCC
SOIC Package (W)
DIP Package (L)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
DI
V
ORG
GND
DO
NC
CC
ORG
CS
DI
NC
V
CC
CS
ORG
GND
DO
DO
SK
DI
SK
NC
SOIC Package (V)
SOIC Package (X)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
DI
V
CS
SK
DI
V
CC
NC
ORG
GND
CC
GND
NC
ORG
GND
PIN FUNCTIONS
DO
DO
Pin Name
Function
Chip Select
Clock Input
CS
TSSOP Package (Y)
SK
1
2
3
4
8
7
6
5
CS
SK
DI
V
CC
DI
Serial Data Input
Serial Data Output
+1.8 to 6.0V Power Supply
Ground
NC
DO
VCC
GND
ORG
NC
ORG
GND
DO
TDFN Package (ZD4)
Memory Organization
No Connection
V
CC
NC
1
2
3
4
8
7
6
5
CS
SK
DI
Note: When the ORG pin is connected to VCC, the x16 organiza-
tion is selected. When it is connected to ground, the x8 pin is
selected. If the ORG pin is left unconnected, then an internal pullup
device will select the x16 organization.
ORG
GND
DO
Bottom View
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1106, Rev. B
1
CAT93C46
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature
-65°C to +150°C
Voltage on Any Pin with Respect to Ground (1)
-0.5 V to +6.5 V
*
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RELIABILITY CHARACTERISTICS(2)
Symbol
Parameter
Min
Units
NEND(*)
Endurance
1,000,000
Program/ Erase Cycles
TDR
Data Retention
100
Years
D.C. OPERATING CHARACTERISTICS
= +1.8V to +5.5V, unless otherwise specified.
V
CC
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
ICC1
Power Supply Current
(Write)
fSK = 1MHz
VCC = 5.0V
3
mA
ICC2
ISB1
ISB2
Power Supply Current
(Read)
fSK = 1MHz
VCC = 5.0V
500
10
µA
µA
µA
Power Supply Current
(Standby) (x8 Mode)
CS = 0V
ORG=GND
Power Supply Current
(Standby) (x16Mode)
CS=0V
ORG=Float or VCC
0
10
ILI
Input Leakage Current
VIN = 0V to VCC
2
2
µA
µA
ILO
Output Leakage Current
(Including ORG pin)
VOUT = 0V to VCC
,
CS = 0V
VIL1
VIH1
VIL2
VIH2
VOL1
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
4.5V ≤ VCC < 5.5V
4.5V ≤ VCC < 5.5V
1.8V ≤ VCC < 4.5V
1.8V ≤ VCC < 4.5V
-0.1
0.8
VCC + 1
VCC x 0.2
VCC+1
0.4
V
V
V
V
V
2
0
VCC x 0.7
4.5V ≤ VCC < 5.5V
IOL = 2.1mA
VOH1
VOL2
Output High Voltage
Output Low Voltage
4.5V ≤ VCC < 5.5V
IOH = -400µA
2.4
V
V
1.8V ≤ VCC < 4.5V
0.2
IOL = 1mA
VOH2
Output High Voltage
1.8V ≤ VCC < 4.5V
IOH = -100µA
VCC - 0.2
V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1106, Rev. B
2
CAT93C46
PIN CAPACITANCE
Symbol
Test
Conditions
VOUT=0V
VIN=0V
Min
Typ
Max
5
Units
pF
(1)
COUT
Output Capacitance (DO)
(1)
CIN
Input Capacitance (CS, SK, DI, ORG)
5
pF
INSTRUCTION SET
Address
Data
Instruction Start Bit Opcode
x8
x16
x8
x16
Comments
READ
ERASE
WRITE
EWEN
EWDS
ERAL
1
1
1
1
1
1
1
10
11
01
00
00
00
00
A6-A0
A6-A0
A5-A0
A5-A0
A5-A0
Read Address AN– A0
Clear Address AN– A0
A6-A0
D7-D0
D15-D0 Write Address AN– A0
Write Enable
11XXXXX
00XXXXX
10XXXXX
01XXXXX
11XXXX
00XXXX
10XXXX
01XXXX
Write Disable
Clear All Addresses
WRAL
D7-D0
D15-D0 Write All Addresses
A.C. CHARACTERISTICS
Limits
VCC
=
VCC
=
VCC
=
1.8V-5.5V
2.5V-5.5V
4.5V-5.5V
Test
Symbol Parameter
Conditions
Min Max Min
Max Min
Max
Units
ns
tCSS
tCSH
tDIS
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
200
0
100
0
50
0
ns
400
400
200
200
100
100
ns
tDIH
tPD1
tPD0
ns
Output Delay to 1
Output Delay to 0
1
1
0.5
0.5
200
10
0.25
0.25
100
10
µs
CL = 100pF
(3)
µs
(1)
tHZ
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
400
10
ns
tEW
ms
µs
tCSMIN
tSKHI
tSKLOW
tSV
1
1
1
0.5
0.5
0.5
0.25
0.25
0.25
µs
µs
1
0.5
0.25
µs
SKMAX
DC
250
DC
500
DC
1000
kHz
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1106, Rev. B
3
CAT93C46
(1)(2)
POWER-UP TIMING
Symbol
tPUR
Parameter
Max
1
Units
ms
Power-up to Read Operation
Power-up to Write Operation
tPUW
1
ms
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
NOTE:
≤ 50ns
0.4V to 2.4V
0.8V, 2.0V
0.2VCC to 0.7VCC
0.5VCC
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 4.5V
1.8V ≤ VCC ≤ 4.5V
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) and t are the delays required from the time V is stable until the specified operation can be initiated.
t
PUR
PUW
CC
(3) The input levels and timing reference points are shown in “AC Test Conditions” table.
DEVICE OPERATION
The CAT93C46 is a 1024-bit nonvolatile memory in-
tended for use with industry standard microprocessors.
The CAT93C46 can be organized as either registers of
16 bits or 8 bits. When organized as X16, seven 9-bit
instructionscontrolthereading,writinganderaseopera-
tions of the device. When organized as X8, seven 10-bit
instructions control the reading, writing and erase
operations of the device. The CAT93C46 operates on
a single power supply and will generate on chip, the high
voltage required during any write operation.
The format for all instructions sent to the device is a
logical"1"startbit, a2-bit(or4-bit)opcode, 6-bitaddress
(an additional bit when organized X8) and for write
operationsa16-bitdatafield(8-bitforX8organizations).
Read
Upon receiving a READ command and an address
(clockedintotheDIpin),theDOpinoftheCAT93C46will
come out of the high impedance state and, after sending
an initial dummy zero bit, will begin shifting out the data
addressed(MSBfirst). Theoutputdatabitswilltoggleon
the rising edge of the SK clock and are stable after the
specified time delay (tPD0 or tPD1).
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46 can be determined by selecting the device
and polling the DO pin. Since this device features Auto-
Clear before write, it is NOT necessary to erase a
memory location before it is written into.
The ready/busy status can be determined after the start
ofawriteoperationbyselectingthedevice(CShigh)and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DIpin. TheDOpinwillenterthehighimpedancestateon
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applica-
tions where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1106, Rev. B
4
CAT93C46
Figure 1. Sychronous Data Timing
t
t
t
SKLOW
SKHI
CSH
SK
t
t
t
DIS
DIH
VALID
VALID
DI
t
CSS
CS
t
t
t
DIS
PD0, PD1
CSMIN
DO
DATA VALID
Figure 2. Read Instruction Timing
SK
t
CSMIN
CS
STANDBY
A
N
A
A
0
N—1
DI
1
1
0
t
HZ
t
HIGH-Z
HIGH-Z
PD0
DO
0
D
D
D
D
0
N
N—1
1
Figure 3. Write Instruction Timing
SK
t
CSMIN
STANDBY
STATUS
VERIFY
CS
A
A
A
0
D
D
N
N-1
N
0
DI
1
0
1
t
t
SV
HZ
BUSY
HIGH-Z
DO
READY
HIGH-Z
t
EW
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1106, Rev. B
5
CAT93C46
Erase
Erase All
UponreceivinganERALcommand,theCS(ChipSelect)
pin must be deselected for a minimum of tCSMIN. The
falling edge of CS will start the self clocking clear cycle
of all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory bits return to a logical “1” state.
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
oftCSMIN.ThefallingedgeofCSwillstarttheselfclocking
clearcycleoftheselectedmemorylocation.Theclocking
of the SK pin is not necessary after the device has
enteredtheselfclockingmode.Theready/busystatusof
the CAT93C46 can be determined by selecting the
deviceandpollingtheDOpin. Oncecleared, thecontent
of a cleared location returns to a logical “1” state.
Write All
Erase/Write Enable and Disable
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C46 can be determined by selecting
the device and polling the DO pin. It is not necessary for
all memory locations to be cleared before the WRAL
command is executed.
TheCAT93C46powersupinthewritedisablestate. Any
writing after power-up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable)instruction.Oncethewriteinstructionisenabled,
itwillremainenableduntilpowertothedeviceisremoved,
or the EWDS instruction is sent. The EWDS instruction
can be used to disable all CAT93C46 write and clear
instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from
the device regardless of the write enable/disable status.
Figure 4. Erase Instruction Timing
SK
STANDBY
STATUS VERIFY
CS
t
CS
A
A
0
A
N
N-1
DI
1
1
1
t
t
SV
HZ
HIGH-Z
DO
BUSY
EW
READY
HIGH-Z
t
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1106, Rev. B
6
CAT93C46
Figure 5. EWEN/EWDS Instruction Timing
SK
CS
STANDBY
DI
1
0
0
*
* ENABLE=11
DISABLE=00
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
t
CS
DI
1
0
0
1
0
t
t
SV
HZ
HIGH-Z
HIGH-Z
DO
BUSY
READY
t
EW
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
t
CSMIN
D
D
DI
1
0
0
0
1
N
0
t
t
SV
HZ
DO
BUSY
READY
HIGH-Z
t
EW
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1106, Rev. B
7
CAT93C46
8-LEAD 300 MIL WIDE PLASTIC DIP (L)
E1
E
D
A2
A
L
A1
e
eB
b2
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
0.120
0.015
0.115
0.014
0.045
0.355
0.300
0.300
0.240
0.210
0.130
0.018
0.060
0.365
0.195
0.022
0.070
0.400
0.325
0.325
0.280
b2
D
D2
E
0.310
0.250
E1
e
0.100 BSC
eB
L
0.430
0.150
0.115
0.130
24C02_8-LEAD_DIP_(300P).eps
Notes:
1. Complies with JEDEC Standard MS001.
2. All dimensions are in inches.
3. Dimensioning and tolerancing per ANSI Y14.5M-1982
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1106, Rev. B
8
CAT93C46
8-LEAD 150 MIL WIDE SOIC (V, W)
E1
E
D
C
A
θ1
e
A1
L
b
SYMBOL
MIN
NOM
MAX
A1
A2
b
0.0040
0.0532
0.013
0.0098
0.0688
0.020
C
0.0075
0.1890
02284
0.149
0.0098
0.1968
0.2440
0.1574
D
E
E1
e
0.050 BSC
f
0.0099
0.0196
24C02_8-LEAD_SOIC.eps
θ1
0°
8°
Notes:
1. Complies with JEDEC specification MS-012 dimensions.
2. All linear dimensions in millimeters.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1106, Rev. B
9
CAT93C46
8-LEAD TSSOP (Y)
D
5
8
SEE DETAIL A
c
E
E1
E/2
GAGE PLANE
0.25
1
4
PIN #1 IDENT.
θ1
L
A2
SEATING PLANE
SEE DETAIL A
A
e
A1
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
c
D
3.00
6.4
E
E1
e
4.40
0.65 BSC
0.60
L
0.50
0.00
0.75
8.00
θ1
Notes:
1. All dimensions in millimeters.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1106, Rev. B
10
CAT93C46
8-PAD TDFN 3X3 PACKAGE (ZD4)
A
E
PIN 1 INDEX AREA
D
A1
D2
A2
A3
E2
SYMBOL
MIN
0.70
0.00
0.45
NOM
0.75
MAX
0.80
0.05
0.65
PIN 1 ID
A
A1
A2
A3
b
0.02
0.55
0.20 REF
0.30
L
0.25
2.90
2.20
2.90
1.40
0.35
3.10
2.40
3.10
1.60
D
3.00
b
D2
E
2.30
e
3.00
E2
e
1.50
3 x e
0.65 TYP
0.30
L
0.20
0.40
NOTE:
1. ALL DIMENSIONS IN MM. ANGLES IN DEGREES.
2. COPLANARITY SHALL NOT EXCEED 0.08 mm.
3. WARPAGE SHALL NOT EXCEED 0.10 mm.
4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC.
5. REFER JEDEC MO-229 / WEEC
TDFN3X3 (01).eps
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1106, Rev. B
11
CAT93C46
ORDERING INFORMATION
Prefix
Device #
Suffix
GT3
V
-1.8
CAT
93C46
I
Optional
Company ID
Product
Number
Temperature Range
I = Industrial (-40°C - 85°C)
Package
L = PDIP (Lead free, Halogen free)
V = SOIC, JEDEC (Lead free, Halogen free)
Operating Voltage
Blank (V = 2.5 to 6.0V)
cc
1.8 (V = 1.8 to 6.0V)
cc
W = SOIC, JEDEC (Lead free, Halogen free)
X = SOIC, EIAJ (Lead free, Halogen free)
Y = TSSOP (Lead free, Halogen free)
Lead Finish/Tape & Reel
G: NiPdAu Lead Plating
T: Tape & Reel
ZD4 =TDFN (3X3mm, Lead-free, Halogen-free)
3: 3000/Reel
Notes:
(1) The device used in the above example is a CAT93C46VI-1.8GT3 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating
Voltage, Tape & Reel)
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1106, Rev. B
12
CAT93C46
PACKAGE MARKING
8-Lead PDIP
8-Lead SOIC
XX
XX
93C46LI
93C46VI
YYWWN
YYWWN
CSI = Catalyst Semiconductor, Inc.
93C46L = Device Code
I = Temperature Range
YY = Production Year
WW = Production Week
N = Product Revision
XX = Voltage Range
CSI = Catalyst Semiconductor, Inc.
93C46V = Device Code
I = Temperature Range
YY = Production Year
WW = Production Week
N = Product Revision
XX = Voltage Range
1.8V - 5.5V = 18
2.5V - 5.5V = Blank
1.8V - 5.5V = 18
2.5V - 5.5V = Blank
8-Lead TSSOP
8-Lead TDFN
C C F F
N N N N
Y M O O
YMNV
93C46I
Y = Production Year
M = Production Month
N = Die Revision
C C F F = Device Code
N N N N = Traceability Code
Y = Production Year
93C46 = Device Code
I = Industrial Temperature Range
V = Voltage Range
M = Production Month
O O = Origin Country
1.8V - 5.5V = 8
2.5V - 5.5V = Blank
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1106, Rev. B
13
CAT93C46
TAPE AND REEL
Direction of Feed
Device Orientation
SPROKET HOLE
TOP COVER
TAPE THICKNESS (t1)
0.10mm (0.004) MAX THICK
DEVICE ORIENTATION
EMBOSSED
CARRIER
PIN 1
PIN 1
PIN 1
EMBOSSMENT
TDFN
SOIC
TSSOP
Reel Dimensions(1)
T
40mm (1.575) MIN.
ACCESS HOLE
AT SLOT LOCATION
B*
A
D*
C
N
FULL RADIUS*
TAPE SLOT IN CORE
FOR TAPE START.
2.5mm (0.098) MIN WIDTH
10mm (0.394) MIN DEPTH
* DRIVE SPOKES OPTIONAL, IF USED
ASTERISKED DIMENSIONS APPLY.
G (MEASURED AT HUB)
Embossed Carrier Dimensions
A
TAPE
SIZE
MAX
QTY/REEL
B MIN
C
D* MIN N MIN
G
T MAX
8.4 (0.328)
9.9 (0.389)
_14.4_
0.566
8MM
330
(13.00)
1.5
(0.059)
12.80 (0.504)
13.20 (0.5200) (0.795) (1.969)
20.2
50
3000
12.4 (0.488) _18.4_
14.4 (0.558) (0.724)
12MM
Component/Tape Size Cross-Reference
Component
8L SOIC
Package Type
Tape Size (W)
12mm
Part Pitch (P)
8mm
J, S, W, V
SP2, VP2
8L TDFN 2x3xmm
8mm
4mm
Notes:
(1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1106, Rev. B
14
CAT93C46
Embossed Carrier Dimensions (12 Pape Only)
10 PITCHES
CUMULATIVE TOLERANCE
ON TAPE 0.2mm( 0.008)
K
D
P
0
T
P
2
TOP
COVER
TAPE
E
(2)
A
0
F
W
(2)
B
B
0
K
1
0
P
CENTER LINES
OF CAVITY
D
1
FOR COMPONENTS
2.0mm X 1.2mm
AND LARGER
EMBOSSMENT
FOR MACHINE REFERENCE ONLY
INCLUDING DRAFT AND RADII
USER DIRECTION OF FEED
CONCENTRIC ABOUT B
0
Embossed Tape—Constant Dimensions(1)
Tape Sizes
D
E
P0
T Max.
D1 Min.
A0 B0 K0(2)
1.5 (0.059)
1.6 (0.063)
1.65 (0.065)
1.85 (0.073)
3.9 (0.153)
4.1 (0.161)
400
(0.016)
1.5
(0.059)
12mm
Embossed Tape—Variable Dimensions(1)
Tape Sizes
B1 Max.
F
K Max.
P2
R Min.
W
P
8.2
5.45 (0.0215)
4.5
(0.177)
1.95 (0.077)
2.05 (0.081)
30
(1.181)
11.7 (0.460) 7.9 (0.275)
12.3 (0.484) 8.1 (0.355)
12mm
(0.0323) 5.55 (0.0219)
Note:
(1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses.
(2) A B K are determined by component size. The clearance between the component and the cavity must be within 0.05 (0.002) min. to
0
0
0
0.65 (0.026) max. for 12mm tape, 0.05 (0.002) min. to 0.90 (0.035) max. for 16mm tape, and 0.05 (0.002) min. to 1.00 (0.039) max. for
24mm tape and larger. The component cannot rotate more than 20° within the determined cavity, see Component Rotation.
© 2005 by Catalyst Semiconductor, Inc.
Doc No. 1106, Rev. B
15
Characteristics subject to change without notice
REVISION HISTORY
Date
Revision Comments
12/01/05
12/08/05
A
B
Initial Issue
Update D.C Operating Characteristics
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Publication #: 1106
Revison:
B
Issue date:
12/08/05
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