首页 |元器件品牌

CAT93C57SI-1.8REV-E [CATALYST]

EEPROM, 128KX16, Serial, CMOS, PDSO8, SOIC-8;
CAT93C57SI-1.8REV-E
型号： CAT93C57SI-1.8REV-E
厂家： CATALYST SEMICONDUCTOR    CATALYST SEMICONDUCTOR
描述：

EEPROM, 128KX16, Serial, CMOS, PDSO8, SOIC-8

可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路
文件： 总9页 (文件大小：408K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
E
CAT93C56/57 (Die Rev. E)  
2K-Bit Microwire Serial EEPROM  
TM  
FEATURES  
ꢀ High speed operation: 1MHz  
ꢀ Power-up inadvertant write protection  
ꢀ 1,000,000 Program/erase cycles  
ꢀ 100 year data retention  
ꢀ Low power CMOS technology  
ꢀ 1.8 to 6.0 volt operation  
ꢀ Selectable x8 or x16 memory organization  
ꢀ Self-timed write cycle with auto-clear  
ꢀ Hardware and software write protection  
ꢀ Commercial, industrial and automotive  
temperature ranges  
ꢀ Sequential read  
ꢀ “Green” package option available  
DESCRIPTION  
using Catalyst’s advanced CMOS EEPROM floating  
gate technology. The devices are designed to endure  
1,000,000 program/erase cycles and has a data reten-  
tion of 100 years. The devices are available in 8-pin DIP,  
SOIC, TSSOP and 8-pad TDFN packages.  
The CAT93C56/57 are 2K-bit Serial EEPROM memory  
devices which are configured as either registers of 16  
bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each  
register can be written (or read) serially by using the  
DI (or DO) pin. The CAT93C56/57 are manufactured  
PIN CONFIGURATION  
FUNCTIONAL SYMBOL  
VCC  
SOIC Package (J,W)  
DIP Package (P, L)  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
ORG  
GND  
DO  
NC  
CC  
ORG  
CS  
DI  
NC  
V
CC  
CS  
ORG  
GND  
DO  
DO  
SK  
DI  
SK  
NC  
SOIC Package (S,V)  
SOIC Package (K,X)  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
CS  
SK  
DI  
V
CC  
NC  
ORG  
GND  
CC  
GND  
NC  
ORG  
GND  
PIN FUNCTIONS  
DO  
DO  
Pin Name  
Function  
Chip Select  
Clock Input  
CS  
TSSOP Package (U,Y)  
SK  
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
CC  
DI  
Serial Data Input  
Serial Data Output  
+1.8 to 6.0V Power Supply  
Ground  
NC  
DO  
VCC  
GND  
ORG  
NC  
ORG  
GND  
DO  
TDFN Package (RD4, ZD4)  
Memory Organization  
No Connection  
V
CC  
NC  
1
2
3
4
8
7
6
5
CS  
SK  
DI  
Note: When the ORG pin is connected to VCC, the x16 organiza-  
tion is selected. When it is connected to ground, the x8 pin is  
selected. If the ORG pin is left unconnected, then an internal pullup  
device will select the x16 organization.  
ORG  
GND  
DO  
Bottom View  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice.  
Doc. No. 1088, Rev. N  
CAT93C56/57  
ABSOLUTE MAXIMUM RATINGS*  
*COMMENT  
Temperature Under Bias .................. -55°C to +125°C  
Storage Temperature........................ -65°C to +150°C  
Stresses above those listed under “Absolute Maximum  
Ratings” may cause permanent damage to the device.  
These are stress ratings only, and functional operation of  
the device at these or any other conditions outside of those  
listed in the operational sections of this specification is not  
implied. Exposure to any absolute maximum rating for  
extended periods may affect device performance and  
reliability.  
Voltage on any Pin with  
Respect to Ground(1) ............. -2.0V to +VCC +2.0V  
V
CC with Respect to Ground ................ -2.0V to +7.0V  
Package Power Dissipation  
Capability (TA = 25°C) ................................... 1.0W  
Lead Soldering Temperature (10 secs) ............ 300°C  
Output Short Circuit Current(2) ........................ 100 mA  
RELIABILITY CHARACTERISTICS  
SymbolParameter  
Reference  
Test  
Method  
Min  
Typ  
Max  
Units  
(3)  
NEND  
Endurance  
MIL-STD-883, Test Method 1033  
MIL-STD-883, Test Method 1008  
MIL-STD-883, Test Method 3015  
JEDEC Standard 17  
1,000,000  
100  
Cycles/Byte  
Years  
Volts  
(3)  
TDR  
Data Retention  
ESD Susceptibility  
Latch-Up  
(3)  
VZAP  
2000  
(3)(4)  
ILTH  
100  
mA  
D.C. OPERATING CHARACTERISTICS  
= +1.8V to +6.0V, unless otherwise specified.  
V
CC  
SymbolParameter  
Test  
Conditions  
Min  
Typ  
Max  
Units  
ICC1  
ICC2  
ISB1  
ISB2  
Power Supply Current  
fSK = 1MHz  
VCC = 5.0V  
3
mA  
(Write)  
Power Supply Current  
(Read)  
fSK = 1MHz  
VCC = 5.0V  
500  
10  
µA  
µA  
µA  
Power Supply Current  
(Standby) (x8 Mode)  
CS = 0V  
ORG=GND  
Power Supply Current  
(Standby) (x16Mode)  
CS=0V  
ORG=Float or VCC  
0
10  
ILI  
Input Leakage Current  
VIN = 0V to VCC  
1
1
µA  
µA  
ILO  
Output Leakage Current  
(Including ORG pin)  
VOUT = 0V to VCC  
,
CS = 0V  
VIL1  
VIH1  
VIL2  
VIH2  
VOL1  
Input Low Voltage  
Input High Voltage  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
4.5V ≤ VCC < 5.5V  
4.5V ≤ VCC < 5.5V  
1.8V ≤ VCC < 4.5V  
1.8V ≤ VCC < 4.5V  
-0.1  
0.8  
VCC + 1  
VCC x 0.2  
VCC+1  
0.4  
V
V
V
V
V
2
0
VCC x 0.7  
4.5V ≤ VCC < 5.5V  
IOL = 2.1mA  
VOH1  
VOL2  
Output High Voltage  
Output Low Voltage  
4.5V ≤ VCC < 5.5V  
IOH = -400µA  
2.4  
V
V
1.8V ≤ VCC < 4.5V  
0.2  
IOL = 1mA  
VOH2  
Output High Voltage  
1.8V ≤ VCC < 4.5V  
IOH = -100µA  
VCC - 0.2  
V
Note:  
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC  
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.  
CC  
CC  
(2) Output shorted for no more than one second. No more than one output shorted at a time.  
(3) This parameter is tested initially and after a design or process change that affects the parameter.  
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.  
CC  
Doc. No. 1088, Rev. N  
2
CAT93C56/57  
PIN CAPACITANCE  
SymbolTest  
Conditions  
Min  
Typ  
VOUT=0V  
VIN=0V  
Max  
Units  
(2)  
COUT  
Output Capacitance (DO)  
5
5
pF  
pF  
(2)  
CIN  
Input Capacitance (CS, SK, DI, ORG)  
INSTRUCTION SET  
Address  
Data  
Device Start  
Instruction  
Type  
Bit Opcode  
x8  
A8-A0  
A7-A0  
A8-A0  
A7-A0  
A8-A0  
A7-A0  
x16  
A7-A0  
A6-A0  
A7-A0  
A6-A0  
A7-A0  
A6-A0  
x8  
x16  
Comments  
Read Address AN– A0  
READ  
93C56(1)  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
10  
10  
11  
11  
01  
01  
00  
00  
00  
00  
00  
00  
00  
00  
93C57  
93C56(1)  
93C57  
93C56(1)  
93C57  
93C56(1)  
93C57  
93C56(1)  
93C57  
93C56(1)  
93C57  
93C56(1)  
93C57  
ERASE  
WRITE  
EWEN  
EWDS  
ERAL  
Clear Address AN– A0  
D7-D0 D15-D0 Write Address AN– A0  
D7-D0 D15-D0  
Write Enable  
11XXXXXXX  
11XXXXXX  
00XXXXXXX  
00XXXXXX  
10XXXXXXX  
10XXXXXX  
01XXXXXXX  
01XXXXXX  
11XXXXXX  
11XXXXX  
00XXXXXX  
00XXXXX  
10XXXXXX  
10XXXXX  
01XXXXXX  
01XXXXX  
Write Disable  
Clear All Addresses  
WRAL  
D7-D0 D15-D0 Write All Addresses  
D7-D0 D15-D0  
A.C. CHARACTERISTICS  
Limits  
VCC  
=
VCC  
=
VCC =  
1.8V-6V  
2.5V-6V  
4.5V-5.5V  
Test  
SymbolParameter  
Conditions  
Min Max Min  
Max Min  
Max  
Units  
ns  
tCSS  
tCSH  
tDIS  
CS Setup Time  
CS Hold Time  
DI Setup Time  
DI Hold Time  
200  
0
100  
50  
0
0
ns  
ns  
400  
400  
200  
200  
100  
100  
tDIH  
tPD1  
tPD0  
ns  
Output Delay to 1  
1
1
0.5  
0.5  
200  
10  
0.25  
0.25  
100  
10  
µs  
µs  
ns  
Output Delay to 0  
CL = 100pF  
(3)  
(1)  
tHZ  
Output Delay to High-Z  
400  
10  
tEW  
Program/Erase Pulse Width  
Minimum CS Low Time  
Minimum SK High Time  
Minimum SK Low Time  
ms  
µs  
µs  
µs  
µs  
kHz  
tCSMIN  
tSKHI  
tSKLOW  
tSV  
1
1
1
0.5  
0.5  
0.5  
0.25  
0.25  
0.25  
Output Delay to Status Valid  
Maximum Clock Frequency  
1
0.5  
0.25  
SKMAX  
DC  
250  
DC  
500  
DC  
1000  
Note:  
(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE  
and ERASE commands.  
(2) This parameter is tested initially and after a design or process change that affects the parameter.  
Doc. No. 1088, Rev. N  
3
CAT93C56/57  
(1)(2)  
POWER-UP TIMING  
SymbolParameter  
Max  
Units  
tPUR  
tPUW  
Power-up to Read Operation  
Power-up to Write Operation  
1
1
ms  
ms  
A.C. TEST CONDITIONS  
Input Rise and Fall Times  
Input Pulse Voltages  
Timing Reference Voltages  
Input Pulse Voltages  
Timing Reference Voltages  
NOTE:  
≤ 50ns  
0.4V to 2.4V  
0.8V, 2.0V  
0.2VCC to 0.7VCC  
0.5VCC  
4.5V ≤ VCC ≤ 5.5V  
4.5V ≤ VCC ≤ 5.5V  
1.8V ≤ VCC ≤ 4.5V  
1.8V ≤ VCC ≤ 4.5V  
(1) This parameter is tested initially and after a design or process change that affects the parameter.  
(2) and t are the delays required from the time V is stable until the specified operation can be initiated.  
t
PUR  
PUW  
CC  
(3) The input levels and timing reference points are shown in “AC Test Conditions” table.  
DEVICE OPERATION  
The CAT93C56/57 is a 2048-bit nonvolatile memory  
intended for use with industry standard microproces-  
sors. The CAT93C56/57 can be organized as either  
registers of 16 bits or 8 bits. When organized as X16,  
seven 10-bit instructions for 93C57; seven 11-bit  
instructions for 93C56 control the reading, writing and  
erase operations of the device. When organized as X8,  
seven 11-bit instructions for 93C57; seven 12-bit in-  
structions for 93C56 control the reading, writing and  
erase operations of the device. The CAT93C56/57  
operates on a single power supply and will generate  
on chip, the high voltage required during any write  
operation.  
DO pin are to be tied together to form a common DI/O  
pin.  
The format for all instructions sent to the device is a  
logical"1"startbit, a2-bit(or4-bit)opcode, 7-bitaddress  
(93C57)/ 8-bit address (93C56) (an additional bit when  
organized X8) and for write operations a 16-bit data field  
(8-bit for X8 organizations).  
Read  
Upon receiving a READ command and an address  
(clocked into the DI pin), the DO pin of the CAT93C56/  
57 will come out of the high impedance state and, after  
sending an initial dummy zero bit, will begin shifting out  
the data addressed (MSB first). The output data bits will  
toggle on the rising edge of the SK clock and are stable  
after the specified time delay (tPD0 or tPD1).  
Instructions, addresses, and write data are clocked into  
the DI pin on the rising edge of the clock (SK). The DO  
pin is normally in a high impedance state except when  
reading data from the device, or when checking the  
ready/busy status after a write operation.  
Write  
After receiving a WRITE command, address and the  
data, the CS (Chip Select) pin must be deselected for a  
minimum of tCSMIN. The falling edge of CS will start the  
self clocking clear and data store cycle of the memory  
location specified in the instruction. The clocking of the  
SK pin is not necessary after the device has entered the  
self clocking mode. The ready/busy status of the  
CAT93C56/57canbedeterminedbyselectingthedevice  
and polling the DO pin. Since this device features Auto-  
Clear before write, it is NOT necessary to erase a  
memory location before it is written into.  
The ready/busy status can be determined after the start  
of a write operation by selecting the device (CS high)  
and polling the DO pin; DO low indicates that the  
write operation is not completed, while DO high indi-  
cates that the device is ready for the next instruction. If  
necessary, the DO pin may be placed back into a high  
impedance state during chip select by shifting a dummy  
“1” into the DI pin. The DO pin will enter the high  
impedance state on the falling edge of the clock (SK).  
Placing the DO pin into the high impedance state is  
recommended in applications where the DI pin and the  
Doc. No. 1088, Rev. N  
4
CAT93C56/57  
Figure 1. Sychronous Data Timing  
t
t
t
SKLOW  
SKHI  
CSH  
SK  
t
t
t
DIS  
DIH  
VALID  
VALID  
DI  
t
CSS  
CS  
t
t
t
DIS  
PD0, PD1  
CSMIN  
DO  
DATA VALID  
Figure 2. Read Instruction Timing  
SK  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CS  
DI  
Don't Care  
A
A
A
0
N
N–1  
1
1
0
HIGH-Z  
DO  
Dummy 0  
D
D
Address + 1 Address + 2 Address + n  
15 . . .  
0
or  
D
D
D
D
D
15 . . .  
0
15 . . .  
0
15 . . .  
D
D
0
or  
or  
D
or  
7 . . .  
D
D
D
D
7 . . .  
7 . . .  
0
7 . . .  
0
Figure 3. Write Instruction Timing  
SK  
t
CSMIN  
STATUS  
STANDBY  
CS  
VERIFY  
A
A
A
0
D
D
0
N
N-1  
N
DI  
1
0
1
t
t
SV  
HZ  
BUSY  
HIGH-Z  
DO  
READY  
HIGH-Z  
t
EW  
Doc. No. 1088, Rev. N  
5
CAT93C56/57  
Erase All  
Erase  
UponreceivinganERALcommand,theCS(ChipSelect)  
pin must be deselected for a minimum of tCSMIN. The  
falling edge of CS will start the self clocking clear cycle  
of all memory locations in the device. The clocking of the  
SK pin is not necessary after the device has entered the  
self clocking mode. The ready/busy status of the  
CAT93C56/57canbedeterminedbyselectingthedevice  
and polling the DO pin. Once cleared, the contents of all  
memory bits return to a logical “1” state.  
Upon receiving an ERASE command and address, the  
CS (Chip Select) pin must be deasserted for a minimum  
oftCSMIN.ThefallingedgeofCSwillstarttheselfclocking  
clearcycleoftheselectedmemorylocation.Theclocking  
of the SK pin is not necessary after the device has  
enteredtheselfclockingmode.Theready/busystatusof  
the CAT93C56/57 can be determined by selecting the  
deviceandpollingtheDOpin. Oncecleared, thecontent  
of a cleared location returns to a logical “1” state.  
Write All  
Erase/Write Enable and Disable  
Upon receiving a WRAL command and data, the CS  
(Chip Select) pin must be deselected for a minimum of  
tCSMIN. The falling edge of CS will start the self clocking  
data write to all memory locations in the device. The  
clocking of the SK pin is not necessary after the device  
has entered the self clocking mode. The ready/busy  
status of the CAT93C56/57 can be determined by  
selecting the device and polling the DO pin. It is not  
necessary for all memory locations to be cleared before  
the WRAL command is executed.  
The CAT93C56/57 powers up in the write disable state.  
Any writing after power-up or after an EWDS (write  
disable) instruction must first be preceded by the EWEN  
(write enable) instruction. Once the write instruction is  
enabled, it will remain enabled until power to the device  
is removed, or the EWDS instruction is sent. The EWDS  
instruction can be used to disable all CAT93C56/57  
write and clear instructions, and will prevent any  
accidental writing or clearing of the device. Data can be  
read normally from the device regardless of the write  
enable/disable status.  
Figure 4. Erase Instruction Timing  
SK  
STANDBY  
STATUS VERIFY  
CS  
t
CS  
A
A
0
A
N
N-1  
DI  
1
1
1
t
t
SV  
HZ  
HIGH-Z  
DO  
BUSY  
EW  
READY  
HIGH-Z  
t
Doc. No. 1088, Rev. N  
6
CAT93C56/57  
Figure 5. EWEN/EWDS Instruction Timing  
SK  
CS  
STANDBY  
DI  
1
0
0
*
* ENABLE=11  
DISABLE=00  
Figure 6. ERAL Instruction Timing  
SK  
CS  
STATUS VERIFY  
STANDBY  
t
CS  
DI  
1
0
0
1
0
t
t
SV  
HZ  
HIGH-Z  
DO  
BUSY  
READY  
HIGH-Z  
t
EW  
Figure 7. WRAL Instruction Timing  
SK  
CS  
STATUS VERIFY  
t
STANDBY  
CSMIN  
D
D
DI  
1
0
0
0
1
N
0
t
t
SV  
HZ  
DO  
BUSY  
READY  
HIGH-Z  
t
EW  
Doc. No. 1088, Rev. N  
7
CAT93C56/57  
ORDERING INFORMATION  
Prefix  
Device #  
Suffix  
S
-1.8  
Rev E(2)  
CAT  
93C56  
TE13  
I
Optional  
Company ID  
Product  
Number  
93C56: 2K  
Temperature Range  
Tape & Reel  
Blank = Commercial (0°C - 70°C)  
I = Industrial (-40°C - 85°C)  
A = Automotive (-40°C - 105°C)  
E = Extended (-40°C to + 125°C)  
93C57: 2K  
Die Revision  
93C56: E  
93C57: E  
Operating Voltage  
Package  
Blank (V =2.5 to 6.0V)  
cc  
P = PDIP  
1.8 (V =1.8 to 6.0V)  
S = SOIC (JEDEC)  
J = SOIC (JEDEC)  
K = SOIC (EIAJ)  
U= TSSOP  
cc  
RD4 = TDFN (3x3mm)  
ZD4 = TDFN (3x3mm, Lead free, Halogen free)  
L = PDIP (Lead free, Halogen free)  
V = SOIC, JEDEC (Lead free, Halogen free)  
W= SOIC, JEDEC (Lead free, Halogen free)  
X = SOIC, EIAJ (Lead free, Halogen free)  
Y = TSSOP (Lead free, Halogen free)  
Notes:  
(1) The device used in the above example is a 93C56SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,  
Tape & Reel)  
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE.) For additional  
information, please contact your Catalyst sales office.  
Doc. No. 1088, Rev. N  
8
REVISION HISTORY  
Date  
Revision Comments  
05/14/04  
L
New Data Sheet Created From CAT93C46/56/57/66/86. Parts  
CAT93C56, CAT93C56, CAT93C57, CAT93C66, CAT93C76 and  
CAT93C86 have been separtated into single data sheets  
10/7/04  
M
N
Updated Instruction Set  
Updated Description  
03/18/05  
Copyrights, Trademarks and Patents  
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:  
DPP ™  
AE2 ™  
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents  
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.  
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS  
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE  
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING  
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.  
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or  
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a  
situation where personal injury or death may occur.  
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets  
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.  
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate  
typical semiconductor applications and may not be complete.  
Catalyst Semiconductor, Inc.  
Corporate Headquarters  
1250 Borregas Avenue  
Sunnyvale, CA 94089  
Phone: 408.542.1000  
Fax: 408.542.1200  
Publication #: 1088  
Revison:  
N
Issue date:  
03/18/05  
www.catalyst-semiconductor.com  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 211
-
VISHAY
©2020 ICPDF网 联系我们和版权申明