ISG2000DS [CEL]
Telecom Circuit, 1-Func, 3.400 X 2 INCH, 0.500 INCH HEIGHT, PACKAGE;
| 型号： | ISG2000DS |
| 厂家： | 
CALIFORNIA EASTERN LABS |
| 描述： | Telecom Circuit, 1-Func, 3.400 X 2 INCH, 0.500 INCH HEIGHT, PACKAGE 电信 电信集成电路 |
| 文件： | 总6页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISG2000DS
5 V CATV MODEM RF TRANSCEIVER
FEATURES
DESCRIPTION AND APPLICATIONS
The ISG2000DS is a complete RF transceiver designed for
use in cable modem applications. The transceiver integrates
a diplex filter, double conversion receiver and transmit AGC
amplifier (see Figure 1). The diplex filter provides over 40 dB
of isolation between the TX band and the RX band. The
receiver converts QAM signals in the RX band down to the IF
sampling frequency and provides the necessary gain control
input power to the DSP. The RF transmitter section provides
40 dB gain control under all conditions, while maintaining
excellent linearity performance.
• TWO WAY MCNS COMPLIANT:
91-860 MHz Downstream
5-42 MHz Upstream
• INTERFACES DIRECTLY WITH QAM DEMOD/MOD ICs
• BUILT IN RF TRANSMITTER:
50 dB AGC Driver
• LOW PHASE NOISE:
-85 dBc/Hz @ 10 KHz
• BUSINESS CARD SIZE:
3.4" x 2.0" x 0.5"
• RUGGED/NO MICROPHONICS:
All SMD Components, "Coiless"
• EUROPEAN AND US VERSIONS AVAILABLE
• LOW POWER CONSUMPTION:
RX: 1.2 Watts, TX: 0.6 Watts
ELECTRICAL CHARACTERISTICS (VCC = 5 V, VCC2 = 24 V, TA = 25°C)
PART NUMBER
ISG2000DS
TYP
SYMBOLS
PARAMETERS
UNITS
MIN
MAX
RF Performance (RX)
fOP
Operating Frequency Range
MHz
dBmV
dB
91
-20
25
0
860
15
Input Signal Level
Gain Range
75
VAGC
VAGC
Automatic Gain Control Voltage RF
Automatic Gain Control Voltage IF
Noise Figure (Max Gain)
Phase Noise at 10 kHz Offset
LO Radiation at RF Input
Resolution
3.3
3.3
10
0
NFMAX
dB
dBc/Hz
dBm
KHz
µsec.
ohms
dB
8
-85
-60
62.5
600
75
-83
Lock Time
Input Impedance (Nominal)
Input Return Loss
RLIN
6
Channel Bandwidth USA
Output Frequency1
Passband Ripple
MHz
MHz
dB
6
43.75
1
43.70
50
43.80
2
Image Rejection
dB
Inband Group Delay
CSO2
ns
100
45
45
dBc
dBc
KHz
CTB2
Frequency Offset
-50
+50
Notes:
1. Optional Output 43.75 MHz Available
2. 110 Channels at +15 dBmV/tone
California Eastern Laboratories
ISG2000DS
ELECTRICAL CHARACTERISTICS (VCC = 5 V, VCC2 = 24 V, TA = 25°C)
PART NUMBER
ISG2000DS
TYP
SYMBOLS
PARAMETERS
UNITS
MIN
MAX
RF Performance (TX)
fOP
Operating Frequency Range
MHz
dB
5
55
Gain (VAGC = 0 V)
35
Gain (VAGC = 3.3 V)
dB
-30
VAGC
Automatic Gain Control Voltage
2nd Harmonic Level (Single Tone, POUT = +58 dBmV)
3rd Harmonic Level (Single Tone, POUT = +58 dBmV)
Output Return Loss
V
0
3.3
6
dBc
dBc
dB
-53
-53
-56
-56
10
12
5
RLOUT
TX ON
On/Off Setting Time
µS
TX OFF
On/Off Setting Time
µS
Power Requirements
Supply Voltage V1 RX
Supply Voltage V2 RX
Supply Current
V
V
4.5
22
5
5.5
24
31.5
Supply Voltage V1 TX
Supply Current 1 (RX)
Supply Current 2 (RX)
Supply Current 1 (TX)
V
4.5
5
9
ICC1 (RX)
ICC2 (RX)
ICC1 (TX)
mA
mA
mA
240
1.5
80
320
2
110
Physical Interface
To the CATV Network
Female
F-Connector
16 Pin Header
To the Motherboard
Physical Dimensions
L x W x H
3.4 x 2.0 x 0.5"
Environmental Specs
TOP
Operating Temperature
Storage Temperature
°C
°C
-5
60
75
TSTG
-40
ABSOLUTE MAXIMUM RATINGS
(TC = 25 °C unless otherwise noted)
SYMBOLS
VIN
PARAMETERS
RF Input Voltage
UNITS
dBmV
V
RATINGS
60
VCC1 (RX)
VCC2 (RX)
VCC (TX)
TOP
Supply Voltage 1 (RX)
Supply Voltage 2 (RX)
Supply Voltage (TX)
Operating Temperature
Storage Temperature
Soldering Temperature
Soldering Time
6
35
V
V
10
°C
-10 to 60
-55 to 150
260
TSTG
°C
TSOL
°C
tSOL
sec.
4
Note:
1. Operation in excess of any one of these parameters may result
in permanent damage.
ISG2000DS
PIN FUNCTIONS
Pin No.
Pin Name
Description
Equivalent Circuit
The RFAGC pin is used to adjust gain in the
dual conversion tuner. This pin has a
positive gain vs. AGC slope. 20 dB of gain
control is available by varying the voltage
from 0.5 V to 3.3 V.
1
RFAGC
1 K
1
1 K
0.1 µF
2
3
VCC (TX)
The VCC (TX) pin powers the TX amplifier. A
5 V bias is required and nominal current is
125 mA.
The TXEN pin is used to enable/disable the
TX amplifier. When TXEN is set LOW, the
TX amplifier is disabled. In this state, a
standby current of 3 mA is required from
VCC (TX). When TXEN is set HIGH, the TX
amplifier is enabled. In this state, a
nomimal current of 125 mA is required from
VCC (TX).
TXEN
10 K
3
TXIN- is the inverting input to the TX
amplifier. The input frequency range spans
covers 5-55 MHz.
4
5
TXIN-
4
4
5
5
TXIN+
TXIN+ is the non-inverting input to the TX
amplifier. The input frequency range spans
covers 5-55 MHz.
The TXAGC pin is used to adjust gain in the
TX amplifier. The pin has a positive gain vs.
AGC slope. 50 dB of gain control is
available by varying the voltage from 0.5 V
to 3.0 V.
6
TXAGC
The VCC2 (RX) pin powers the loop filter for
the first LO. A bias of 24 V - 30 V is
required and maximum current draw is
2 mA.
7
8
9
VCC2 (RX)
VCC1 (RX)
IFAGC
The VCC1 (RX) pin powers the entire RX
section. A bias of 5 V is required and
nominal current draw is
250 mA.
The IFAGC pin is used to adjust gain in the
final downconverter stage of the RX section.
The pin has a positive gain vs. AGC slope.
30 dB of gain control is available by varying
the voltage from 0.5 to 2.0 V.
1 K
9
1000 p
10
GND
Ground.
ISG2000DS
PIN FUNCTIONS
Pin No.
Pin Name
Description
Equivalent Circuit
111
CK
Clock pin for the dual PLL. High impedance
CMOS input. Data for the various latches is
clocked in on the rising edge into a 20-bit
shift register.
Serial data pin for the dual PLL. High
impedance CMOS input. MSB entered first.
The last two bits are the control bits.
121
131
DATA
LE
Latch enable pin for the dual PLL. High
impedance CMOS input. When LE goes
HIGH, data stored in the shift registers is
loaded into one of the 4 latches determined
by the 2 control bits.
14
15
GND
Ground.
Inverting final IF output.
5.6 µH 15
240
IFOUT-
16
IFOUT+
Non-inverting final IF output.
5.6 µH 16
240
Note:
1. For programming information, refer to National LMX2336 data sheet (http://www.national.com)
FIGURE 1
43.75 MHz
91-860 MHz
RX OUT
DUAL PLL
CK DATA LE
TX IN
CABLE
IN/OUT
5-42 MHz
ISG2000DS
OUTLINE DIMENSIONS (Units in mm [inches])
ISG2000
16 Pin Header Connections/Location
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16
1: RFAGC 5: TXIN-
9: IFAGC 13: LE
2: VCC (T
3: TXEN
4: TXIN+
X)
6: TXAGC
7: VCC2(R
8: VCC1(R
10: GND
) 11: CK
) 12: DATA 16: IFOUT+
14: GND
15: IFOUT-
X
X
4.1 [.161]
6.4 [.252]
18.9 [.744]
5.0 [.197] DIA
27.8 [1.094]
14.25 [5.61]
3.8 [.150]
2.2 [.087]
87.3 [3.437]
50.2 [1.976]
15.9 [.626]
Pin 1
5.6 [.220]
2.54
[.100]
.5 [.020]
54.8 [2.157]
+
+
+
F Connector
26.6 [1.047]
90.5 [3.563]
Table 1. Programmable Modes
Notes:
1. The ICPO LOW Current State = 1/4 x ICPO HIGH
Current.
C1 C2
R16
R17
R18
RF2 DO
TRI-STATE
R19
R20
0
0
RF2 Phase RF2 ICPO
Detector
Polarity
RF1 Phase RF1 ICPO
Detector
Polarity
RF2 LD RF2 FO
2. Activitation of the RF2 PLL or RF1 PLL powerdown
modes result in the disabling of the respective N counter
divider and debiasing of its respective fIN inputs (to a
high impedance state). The powerdown function is
gated by the charge pump to prevent unwanted
frequency jumps. Once the powerdown program mode
is loaded, the part will go into powerdown mode when
the charge pump reaches a TRI-STATE condition. The
R counter and Oscillator functionality does not become
disabled until both RF2 and RF1 powerdown bits are
activated. The OSCIN is connected to VCC through a 100
kΩ resistor and the OSCOUT goes HIGH when this con-
dition exists. The MICROWAVETM control register re-
mains active and capable of loading and latching data
during all the powerdown modes.
0
1
RF1DO
TRI-STATE
RF1 LD RF1 FO
C1
1
1
C2
0
N19
RF2 Prescaler
RF1 Prescaler
N20
Pwdn RF2
Pwdn RF1
1
Table 2. Mode Select Truth Table
1
O
Phase DO TRI-STATE ICP
Detector
Polarity3
RF1
RF2
Pwdn2
Prescaler Prescaler
0 Negative
Normal
Operation
LOW 64/65
64/65 pwrd up
3. Phase Detector Polarity
Depending upon VCO characteristics, the R16 bits
should be set accordingly:
1
Positive TRI-STATE HIGH 128/129 128/129 pwrd dn
When VCO characteristics are positive like (1), R16
should be set HIGH, when VCO characteristics are
negative like (2), R16 should be set LOW.
ISG2000DS
VCO CHARACTERISTICS
Serial Data Input Timing
(1)
DATA N20: WSB
(R20: WSB)
N19
N10
N9
C2
C1: LSB
(R19)
(R10) (R9) (R8) (C2)
(C1: LSB)
CLOCK
tCWL
LE
t
ES
t
CS
t
CH
t
CWH
tEW
OR
LE
(2)
Notes:
VCO Input Voltage
Table 3. The FOLD Output Truth Table
RF1 R (19) RF2 R (19) RF1 R (20) RF2 R (20)
1. Parenthesis data indicates programmable reference
divider data.
2. Data shifted into register on clock rising edge.
3. Data is shifted in MSB first.
FOLD
(RF1 LD) (RF2 LD)
(RF1 FO)
(RF2 FO) Output State
0
0
0
1
0
0
0
0
Disabled1
Test Conditions:
RF2 Lock
The Serial Data Input Timing is tested using a symmetrical
waveform around VCC/2. The test waveform has an edge
rate of 0.6V/ns with amplitudes of 2.2 V @ VCC = 2.7 V and
2.6 V @ VCC = 5.5 V.
Detect2
1
1
0
1
0
0
1
0
0
0
1
0
0
0
1
0
1
RF1 Lock
Detect2
RF1/RF2
Lock Detect2
RF2 Reference
Divider Output
RF1 Reference
Divider Output
RF2
Phase Comparator and Internal Charge Pump Character-
istics.
X
X
X
Programmable
Divider Output
RF1
f
r
f
p
X
1
1
0
Programmable
Divider Output
Fastlock3
For internal
use only
LD
0
0
0
1
1
1
1
1
H
D
o
Z
L
1
1
0
1
1
1
1
1
For internal
use only
Counter Reset4
f
> f
f
= f
f
< f
f
< f
f < f
r p
r
p
r
p
r
p
r
p
X - Don’t care condition
Notes:
1. Phase difference detection range: -2π to +2π
Notes:
1. When the FOLD output is disabled, it is actively pulled to a
low logic state.
2. The minimum width pump up and pump down current pulses
occur at the DO pin when the loop is locked.
2. Lock detect output provided to indicate when the VCO fre-
quency is in “lock”. When the loop is locked and a lock
detect mode is selected, the pin's output is HIGH, with nar-
row pulses LOW. In the RF1/RF2 lock detect mode a locked
condition is indicated when RF2 and RF1 are both locked.
3. The Fastlock mode utilized the FOLD output pin to switch a
second loop filter damping resistor to ground during fastlock
operation. Activation of Fastlock occurs whenever the RF
loop’s Icpo magnitude bit #17 is selected HIGH (while the
#19 and #20 mode bits are set for Fastlock).
4. The Counter Reset mode bits R19 and R20 when activated
reset all counters. Upon removal of the Reset bits the N
counter resumes counting in “close” alignment with R
counter. (The maximum error is one prescaler cycle). If
the Reset bits are activated the R counter is also forced to
Reset, allowing smooth acquisition upon powering up.
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DATA SUBJECT TO CHANGE WITHOUT NOTICE
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