CS5101EDW16 [CHERRY]
Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters; 次级侧后稳压器的AC / DC和DC / DC多路输出转换器
| 型号： | CS5101EDW16 |
| 厂家： | 
CHERRY SEMICONDUCTOR CORPORATION |
| 描述： | Secondary Side Post Regulator for AC/DC and DC/DC Multiple Output Converters |
| 文件： | 总7页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS5101
Secondary Side Post Regulator for AC/DC
and DC/DC Multiple Output Converters
Description
Features
The CS5101 is a bipolar monolithic
The CS5101 features include a totem
pole output with 1.5A peak output
current capability, externally pro-
grammable overcurrent protection,
an on chip 2% precision 5V refer-
ence, internally compensated error
amplifier, externally synchronized
switching frequency, and a power
switch drain voltage monitor. It is
available in a 14 lead plastic DIP or
a 16 lead wide body SO package.
1.5A Peak Output
■
secondary side post regulator
(SSPR) which provides tight regula-
tion of multiple output voltages in
AC-DC or DC-DC converters.
Leading edge pulse width modula-
tion is used with the CS5101.
(Grounded Totem Pole)
8V to 75V Gate Drive Voltage
8V to 45V Supply Voltage
300ns Propagation Delay
■
■
■
■
1% Error Amplifier
Reference Voltage
The CS5101 is designed to operate
over an 8V to 45V supply voltage
(VCC) range and up to a 75V drive
voltage (VC).
Lossless Turn On and
Turn Off
■
Sleep Mode: < 100µA
■
■
Overcurrent Protection with
Dedicated Differential Amp
Application Diagram
Synchronization to External
Clock
■
■
V
External Power Switch
Drain Voltage Monitor
SY
L1
C
R4
V
4
R10
3
OUT
1
Q1
TR
5
R8
R9
R11
R12
R13
R14
Gnd
6
+
Package Options
C6
C
R5
R5
R6
14L PDIP
1
VD
SYNC
VCC
VC
C
R1
VREF
LGnd
VFB
VG
C5
PGnd
IS COMP
IS-
R1
R2
C
R3
R7
COMP
RAMP
IS+
V
V
D
SYNC
V
V
C
CC
CS5101
SSPR
V
V
16L SO Wide
G
REF
C
R3
R2
LGnd
PGnd
C4
1
VD
SYNC
VCC
V
IS COMP
FB
VC
IS-
COMP
RAMP
+
IS+
R4
C2
C3
VREF
VG
C1
DGnd
PGnd
PGnd
IS COMP
IS-
2
AGnd
VFB
C
R
COMP
RAMP
IS+
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
Rev. 3/31/97
1
A
¨
Company
Absolute Maximum Ratings
Power Supply Voltage, VCC .....................................................................................................................................-0.3V to 45V
VSYNC and Output Supply Voltages, VC, VG, VSYNC, VD.....................................................................................-0.3V to 75V
VIS+, VIS- (VCC Ð 4V, up to 24V)..................................................................................................................................-0.3 to 24V
VREF, VFB, VCOMP, VRAMP, VISCOMP............................................................................................................................-0.3 to 10V
Operating Junction Temperature, TJ .......................................................................................................................-40 to 150¡C
Operating Temperature Range ..................................................................................................................................-40 to 85¡C
Storage Temperature Range ....................................................................................................................................-65 to 150¡C
Output Energy (capacitive load per cycle).............................................................................................................................5µJ
ESD Human Body ....................................................................................................................................................................2kV
ESD Machine Model...............................................................................................................................................................200V
Lead Temperature Soldering
Wave Solder (through hole styles only)....................................................................................10 sec. max, 260¡C peak
Reflow (SMD styles only).....................................................................................60 sec. max above 183¡C, 230¡C peak
-40¡C ² TA ² 85¡C; -40¡C ² TJ ² 150¡C; 10V < VCC < 45V; 8V < VC <75V unless otherwise specified.
Electrical Characteristics:
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
■ Error Amplifier
Input Voltage Initial Accuracy
V
FB = VCOMP; VCC = 15V;
1.98
1.94
2.00
2.00
2.02
V
T = 25¡C (Note 1)
Input Voltage
VFB = VCOMP, includes line and temp
2.06
500
V
Input Bias Current
Open Loop Gain
Unity Gain Bandwidth
Output Sink Current
Output Source Current
VCOMP High
VFB = 0V; IVFB flows out of pin
1.5V < VCOMP < 3.0V
nA
dB
60
0.7
2
70
1.0
8
1.5V < VCOMP < 3.0V; (Note 1)
MHz
V
COMP = 2.0V; VFB = 2.2V
COMP = 2.0V; VFB = 1.8V
mA
mA
V
V
2
6
VFB = 1.8V
3.3
0.85
60
3.5
1.0
70
3.7
VCOMP Low
VFB = 2.2V
1.15
V
PSRR
10V < VCC < 45V;
dB
VFB = VCOMP (Note 1)
■ Voltage Reference
Output Voltage Initial Accuracy VCC = 15V; T = 25¡C (Note 1)
4.9
4.8
5.0
5.0
10
5.1
5.2
60
V
Output Voltage
Line Regulation
Load Regulation
Current Limit
0A < IREF < 8mA
V
10V < VCC < 45V; IREF = 0A
0A < IREF < 8mA
mV
mV
mA
V
20
60
VREF = 4.8V
10
50
VREF_OK FAULT V
VSYNC = 5V; VREF = VLOAD
VSYNC = 5V; VREF = VLOAD
4.10
4.30
40
4.40
4.50
100
4.60
4.80
250
VREF_OK V
V
VREF_OK Hysteresis
mV
■ Current Sense Amplifier
IS COMP High V
IS COMP Low V
Source Current
Sink Current
IS+ = 5V; ISÐ = IS COMP
IS+ = 0V; ISÐ = IS COMP
IS+ = 5V; ISÐ = 0V
4.7
0.5
2.0
10
5.0
1.0
10
20
80
80
80
0.8
5.3
1.3
V
V
mA
mA
dB
dB
dB
MHz
IS- = 5V; IS+ = 0V
Open Loop Gain
CMRR
1.5V ² VCOMP ² 4.5V; RL = 4k½
(Note 1)
60
60
PSRR
10V < VCC < 45V, (Note 1)
60
Unity Gain Bandwidth
1.5V ² VCOMP ² 4.5V; RL = 4k½ (Note 1) 0.5
2
Electrical Characteristics: continued
TEST CONDITIONS MIN
PARAMETER
TYP
MAX
UNIT
■ Current Sense Amplifier: continued
Input Offset Voltage
VIS+ = 2.5V; VIS- = VISCOMP
-8
0
8
mV
nA
nA
V
Input Bias Currents
Input Offset Current (IS+, IS-)
VIS+ = VIS- = 0V; IIS flows out of pins
20
0
250
250
-250
-0.3
Input Signal Voltage Range
(Note 1)
V
CC-4.0
■ RAMP/SYNC Generator
Ramp Source Current Initial
Accuracy
V
SYNC = 5V, VRAMP = 2.5V ; T = 25¡C
0.18
0.20
0.22
0.24
mA
(Note 1)
Ramp Source Current
Ramp Sink Current
VSYNC = 5V; VRAMP = 2.5V
0.16
1.0
3.3
1.4
1.7
0.3
2.3
0.20
4.0
3.5
1.5
2.0
0.6
2.5
1
mA
mA
V
V
SYNC = 0V; VRAMP = 2.5V
SYNC = 5V
RAMP Peak Voltage
RAMP Valley Voltage
RAMP Dynamic Range
V
3.7
1.6
2.3
1.0
2.7
20
VSYNC = 0V
RAMPDR = VRAMPPK Ð VRAMPVY
V
V
V
RAMP Sleep Threshold Voltage VRAMP @ VREF < 2.0V
V
SYNC Threshold
VSYNC @ VRAMP > 2.5V
V
SYNC Input Bias Current
VSYNC = 0V; ISYNC flows out of pin
µA
■ Output Stage
VG, High
VSYNC = 5V; IVG = 200mA, VC Ð VG
VSYNC = 0V; IVG = 200mA
1.6
0.9
30
2.5
1.5
75
V
VG, Low
V
VG Rise Time
Switch VSYNC High; CG = 1nF;
ns
VCC = 15V; measure 2V to 8V
VG Fall Time
Switch VSYNC Low; CG = 1nF
VCC = 15V; measure 8V to 2V
40
100
100
ns
VG Resistance to Gnd
VD Resistance to Gnd
Remove supplies; VG = 10V
Remove supplies; VD = 10V
50
k½
½
500
1500
■ General
I
I
CC, Operating
CC in UVL
VSYNC = 5V
12
300
80
20
4
18
500
200
50
8
mA
µA
µA
µA
mA
VCC = 6V
ICC in Sleep Mode High
CC In Sleep Mode Low
VRAMP = 0V; VCC = 45V
VRAMP = 0V; VCC = 10V
I
IC, Operating High
VSYNC = 5V; VFB = VISÐ = 0V;
VC = 75V
IC, Operating Low
UVLO Start Voltage
UVLO Stop Voltage
UVLO Hysteresis
VSYNC = 5V; VFB = VISÐ = 0V; VC = 8V
3
6
mA
V
7.4
6.4
0.8
8.0
7.0
1.0
280
750
9.2
8.3
1.2
V
V
Leading Edge, tDELAY
Trailing Edge, tDELAY
VSYNC = 2.5V to VG = 8V
VSYNC = 2.5V to VG = 2V
ns
ns
Note 1: Guaranteed by design. Not 100% tested in production.
3
Package Pin Description
PIN SYMBOL
PACKAGE PIN #
14L PDIP 16L SO Wide
FUNCTION
1
2
1
2
3
SYNC
VCC
Synchronization input.
Logic supply (10V to 45V).
3
VREF
LGnd
VFB
5.0V voltage reference.
4
Logic level ground (Analog and digital ground tied).
Error amplifier inverting input.
5
6
7
6
COMP
RAMP
IS+
Error amplifier output and compensation.
RAMP programmable with the external capacitor.
Current sense amplifier non-inverting input.
Current sense amplifier inverting input.
Current sense amplifier compensation and output.
Power ground.
7
8
8
9
9
10
11
12, 13
14
15
16
5
IS-
10
11
12
13
14
IS COMP
PGnd
VG
External power switch gate drive.
Output power stage supply voltage (8V to 75V).
External FET DRAIN Voltage Monitor.
Analog Ground.
VC
VD
AGnd
DGnd
4
Digital Ground.
Circuit Description
Block Diagram
VCC
VD
VC
VCC
REF
+
+
Ð
+
Q1
Q2
+
SLEEP
Ð
VREF
5V
OK
UVL
VG
+
8V/7V
LGnd
0.7V
Ð
PGnd
Ð
IS COMP
VCC
5V
EA
5V
24.6k
Ð
+
IS-
IS
VFB
Ð
+
IS+
Ð
VC
5V
10k
10k
BUF
Ð
Ð
+
+
PWM
+
+
2V
Q3
Ð
+
2.4V
5V
COMP
RAMP
Ð
5V
Q
Q
S
R
I = 200mA
LATCH
+
Ð
0.7V
+
5V
Ð
1.5V
Ð
_
VCC OK
+
+
5V
RAMP
+
Ð
Q4
G1
_
REF OK
+
Ð
Ð
1.65V
VCC
5V
+
4.5V/4.4V
Ð
SYNC
+
G2
SYNC
Ð
+
Ð
2.5V
4
Circuit Description: continued
The logic state of the LATCH can be changed only when
Theory of Operation
both the voltage level of the trailing edge of the power
pulse at the SYNC pin is less than the threshold voltage of
the SYNC comparator (2.5V) and the RAMP voltage is
less than the threshold voltage of the RAMP comparator
(1.65V). On the negative going transition of the secondary
side pulse VSY, gate G2 output goes high, resetting the
latch at time t3. Capacitor CR is discharged through tran-
sistor Q4. CRÕs output goes low disabling the output stage,
and the external power switch (an N-FET) is turned off.
The CS5101 is designed to regulate voltages in multiple
output power supplies. Functionally, it is similar to a
magnetic amplifier, operating as a switch with a delayed
turn-on. It can be used with both single ended and dual
ended topologies.
The VFB voltage is monitored by the error amplifier EA. It
is compared to an internal reference voltage and the
amplified differential signal is fed through an inverting
amplifier into the buffer, BUF. The buffered signal is com-
pared at the PWM comparator with the ramp voltage
generated by capacitor CR. When the ramp voltage VR,
exceeds the control voltage VC, the output of the PWM
comparator goes high, latching its state through the
LATCH, the output stage transistor Q1 turns on, and the
external power switch, usually an N-FET, turns on.
RAMP Function
The value of the ramp capacitor CR is based on the
switching frequency of the regulator and the maximum
duty cycle of the secondary pulse VSY
.
If the RAMP pin is pulled externally to 0.3V or below, the
SSPR is disabled. Current drawn by the IC is reduced to
less than 100µA, and the IC is in SLEEP mode.
SYNC Function
The SYNC circuit is activated at time t1 (Figure 1) when
the voltage at the SYNC pin exceeds the threshold level
(2.5V) of the SYNC comparator. The external ramp capac-
itor CR is allowed to charge through the internal current
source I (200µA). At time t2, the ramp voltage intersects
with the control voltage VC and the output of the PWM
comparator goes high, turning on the output stage and
the external power switch. At the same time, the PWM
comparator is latched by the RS latch, LATCH.
FAULT Function
The voltage at the VCC pin is monitored by the undervolt-
age lockout comparator with hysteresis. When VCC falls
below the UVL threshold, the 5V reference and all the cir-
cuitry running off of it is disabled. Under this condition
the supply current is reduced to less than 500µA.
The VCC supply voltage is further monitored by the
VCC OK comparator. When VCC is reduced below
_
VREF - 0.7V, a fault signal is sent to gate G1. This fault sig-
nal, which determines if VCC is absent, works in conjunc-
tion with the ramp signal to disable the output, but only
after the current cycle has finished and the RS latch is reset.
Therefore this fault will not cause the output to turn off
during the middle of an on pulse, but rather will utilize
lossless turn-off. This feature protects the FET from over-
voltage stress. This is accomplished through gate G1 by
driving transistor Q4 on.
V
SY
V
SY
1
2
0V
V
V
C
RAMP
V
+ V
SY
D
V
DS
3
0V
V
SY
V
D
_
An additional fault signal is derived from the REF OK
V
V
S
4
0V
comparator. VREF is monitored so to disable the output
through gate G1 when the VREF voltage falls below the
V
Ð V
OUT
SY
V
L1
G
_
_
OK threshold. As in the VCC OK fault, the REF OK fault
disables the output after the current cycle has been com-
pleted. The fault logic will operate normally only when
_
0V
V
+ V
D
OUT
V
5
+ V
SY
C
D
V
V
REF voltage is within the specification limits of REF OK.
6
0V
Ground Level
(Gate doesn't go
below Gnd)
t
t
t
3
t
4
t
1
1
2
DRAIN Function
The drain pin, VD monitors the voltage on the drain of the
power switch and derives energy from it to keep the out-
put stage in an off state when VC or VCC is below the min-
imum specified voltage.
Figure 1. Waveforms for CS5101. The number to the left of each curve
refers to a node on the Application Diagram.
5
Circuit Description: continued
S1
8V – 45V
C1
1mF
SW SPST
R1
100k
R2
100k
V1
100kHz
0V to 5V Square Wave
V
V
D
SYNC
V
V
CC
C
CS5101
14 L PDIP
V
V
REF
G
C2
0.1mF
C3
1nF
LGnd
PGnd
R3
5k
V
IS COMP
IS-
FB
COMP
RAMP
IS+
R4
2.2k
C4
0.1mF
R7
10k
R5
10k
R6
10k
C5
680pF
CS5101 bench test
6
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES)
PACKAGE THERMAL DATA
D
Thermal Data
16L SOIC
14L PDIP
Lead Count
Metric
English
RQJC
RQJA
typ
typ
23
105
48
85
ûC/W
ûC/W
Max
Min
18.67
10.10
Max
.775
.413
Min
.735
.398
14L PDIP
16L SO Wide
19.69
10.50
Plastic DIP (N); 300 mil wide
7.11 (.280)
6.10 (.240)
1.77 (.070)
1.14 (.045)
8.26 (.325)
7.62 (.300)
2.54 (.100) BSC
3.68 (.145)
2.92 (.115)
0.39 (.015)
MIN.
.356 (.014)
.203 (.008)
.558 (.022)
.356 (.014)
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
REF: JEDEC MS-001
D
All specs are the same.
Surface Mount Wide Body (DW); 300 mil wide
7.60 (.299)
7.40 (.291)
10.65 (.419)
10.00 (.394)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
2.49 (.098)
2.24 (.088)
2.65 (.104)
2.35 (.093)
0.32 (.013)
0.23 (.009)
1.27 (.050)
0.40 (.016)
0.30 (.012)
0.10 (.004)
D
REF: JEDEC MS-013
Ordering Information
Part Number
CS5101EN14
CS5101EDW16
Description
14L PDIP
16L SO Wide
Ch erry Sem icon du ctor Corporation reserves th e
righ t to m ake ch an ges to th e specification s with ou t
n otice. Please con tact Ch erry Sem icon du ctor
Corporation for th e latest available in form ation .
CS5101EDWR16
16L SO Wide (tape & reel)
PATENTS PENDING
© 1999 Cherry Semiconductor Corporation
Rev. 3/31/97
7
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