CH7010B-T-TR_技术文档

CH7010B

Chrontel

CHRONTEL

C

CHHRROONNTTEELL

CH7010 DVI / TV Output Device

1. FEATURES

2. GENERAL DESCRIPTION

The CH7010 is a display controller device which accepts a

digital graphics input signal, and encodes and transmits data

through a DVI (DFP can also be supported) or TV output

(analog composite, s-video or RGB). The device accepts data

over one 12-bit wide variable voltage data port which supports

five different data formats including RGB and YCrCb.

• DVI Transmitter up to 165M pixels/second

• DVI low jitter PLL

• DVI hot plug detection

• TV output supporting graphics resolutions up to

1024 x768 pixels

• Programmable digital interface supports RGB and

YCrCb

• True scale rendering engine supports underscan in all TV

The DVI processor includes a low jitter PLL for generation of

the high frequency serialized clock, and all circuitry required

to encode, serialize and transmit data. The CH7010 comes in

versions able to drive a DVI display at a pixel rate of up to

165MHz, supporting UXGA resolution displays. No scaling

of input data is performed on the data output to the DVI

device.

output resolutions

• Enhanced text sharpness and adaptive flicker removal

with up to 7 lines of filtering

• Support for all NTSC and PAL formats

• Provides CVBS, S-Video and SCART (RGB) outputs

• TV connection detection

The TV-Out processor performs non-interlace to interlace

conversion with scaling and flicker filters, and encode the data

into any of the NTSC or PAL video standards. The scaling and

flicker filter is adaptive and programmable to enable superior

text display. Eight graphics resolutions are supported up to

1024 by 768 with full vertical and horizontal underscan

capability in all modes. A high accuracy low jitter phase

locked loop is integrated to create outstanding video quality.

Support is provided for RGB bypass mode which enables

driving a VGA CRT with the input data.

• Programmable power management

• 10-bit video DAC outputs

• Fully programmable through serial port

• Complete Windows and DOS driver support

• Low voltage interface support to graphics device

• Offered in a 64-pin LQFP package

DVI PLL

TLC,TLC*

Clock

2

Driver

XCLK, XCLK*

D[11:0]

2

TDC0,TDC0*

DVI

2

DVI

TDC1,TDC1*

Encode

Serialize

Driver

24

3

TDC2,TDC2*

Data

Latch,

Demux

12

3

VSWING

HPDET

GPIO[1:0]

24

2

H, V, DE

Latch

H,V,DE

VREF

AS

Serial

port

3

2

SPC

SPD

Control

BCO

XI/FIN,XO

P-OUT/TLDET*

PLL3

RESET*

C/H SYNC

ISET

Timing

CVBS^(DAC3)

Y/G(DAC1)

Scaling

Four

10-bit

DAC’s

3

24

Scan

Conv

TV

Encode

C/R(DAC2)

Flicker Filt

CVBS/B(DAC0)

24

Figure 1. Functional Block Diagram

201-0000-038 Rev 3.1, 11/4/2004

1

CHRONTEL

CH7010B

3. PIN DESCRIPTIONS

3.1 Package Diagram

DVDD

DE

VREF

H

V

DGND

C / H SYNC

BCO / V SYNC

P-OUT/TLDET*

DVDDV

AVDD

XO

XI / FIN

AGND

GND

CVBS / B

C / R

Y / G

CVBS

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

2

3

4

5

6

GPIO[1] / TLDET*

GPIO[0]

HPDET

AS

7

Chrontel

8

CH7010

9

10

11

12

13

14

15

16

DGND

DVDD

RESET*

SPD

SPC

AGND

ISET

GND

VDD

Figure 2. 64-Pin LQFP

2

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

3.2 Pin Description

Table 1. Pin Description

64-Pin

# Pins Type

Symbol Description

LQFP

2

1

In

DE

Data Enable

This pin accepts a data enable signal which is high when active video data

is input to the device, and low all other times. The levels are 0 to

DVDDV, and the VREF signal is used as the threshold level. This input is

used by the DVI. The TV-Out function uses H and V sync signals as

reference to active video.

3

4

1

In

VREF

H

Reference Voltage Input

The VREF pin inputs a reference voltage of DVDDV / 2. The signal is

derived externally through a resistor divider and decoupling capacitor,

and will be used as a reference level for data, sync, data enable and clock

inputs.

In/Out

Horizontal Sync Input / Output

When the SYO bit is low, this pin accepts a horizontal sync input for use

with the input data. The amplitude will be 0 to DVDDV, and the VREF

signal is used as the threshold level.

When the SYO bit is high, the device will output a horizontal sync pulse,

64 pixels wide. The output is driven from the DVDD. This output is only

for use with the TV-Out function.

Vertical Sync Input / Output

When the SYO bit is low, this pin accepts a vertical sync input for use

with the input data. The amplitude will be 0 to DVDDV, and the VREF

signal is used as the threshold level.

5

7

1

2

In/Out

V

When the SYO bit is high, the device will output a vertical sync pulse one

line wide. The output is driven from the DVDD supply. This output is

only for use with the TV-Out function.

GPIO[1] / General Purpose Input - Output[1] /

DVI Detect Output (Open drain or internal weak pull-up)

TLDET*

This pin provides a general purpose I/O controlled via the serial port.

When the GPIO[1] pin is configured as an output, this pin can be used to

output the DVI detect signal (pulls low when a termination change has

been detected on the

input). This is an open drain output. The output is released through

serial port control.

General Purpose Input - Output[0]

(Open drain or internal weak pull-up)

This pin provides a general purpose I/O controlled via the serial port.

This allows an external switch to be used to select NTSC or PAL at

power-up.

Hot Plug Detect (internal pull-down)

8

9

2

1

In/Out

In

GPIO[0]

HPDET

This input pin determines whether the DVI is connected to a DVI

monitor. When terminated, the monitor is required to apply a voltage

greater than 2.4 volts. Changes on the status of this pin will be relayed to

the graphics controller via the P-OUT/TLDET* or GPIO[1]/TLDET* pin

pulling low.

When the HPDET is pulled low, the DVI output driver will be shut down.

10

1

In

AS

Address Select (Internal pull-up)

This pin determines the serial port address of the device

(1,1,1,0,1,AS*,AS).

201-0000-038 Rev 3.1, 11/4/2004

3

CHRONTEL

CH7010B

Table 1. Pin Description (continued)

64-Pin

# Pins Type

Symbol Description

LQFP

13

14

15

1

In

RESET*

SPD

Reset * Input (Internal pull-up)

When this pin is low, the device is held in the power-on reset condition.

When this pin is high, reset is controlled through the serial port register.

In/Out

In

Serial Port Data Input / Output

This pin functions as the serial port data pin of the serial port interface,

and uses the DVDD supply.

SPC

Serial Port Clock Input

This pin functions as the clock pin of the serial port interface, and uses

the DVDD supply.

DVI Swing Control

19

1

In

VSWING

This pin sets the swing level of the DVI outputs. A 2.4K ohm resistor

should be connected between this pin and TGND using short and wide

traces.

DVI Data Channel 0 Outputs

22, 21

25, 24

2

Out

TDC0,

These pins provide the DVI differential outputs for data channel 0 (blue).

DVI Data Channel 1 Outputs

TDC0*

TDC1,

These pins provide the DVI differential outputs for data channel 1

TDC1*

(green).

28, 27

30, 31

2

Out

TDC2,

DVI Data Channel 2 Outputs

These pins provide the DVI differential outputs for data channel 2 (red).

DVI Clock Outputs

TDC2*

TLC,

These pins provide the differential clock output for the DVI interface

TLC*

corresponding to data on the TDC[0:2] outputs.

35

36

37

1

In

ISET

Current Set Resistor Input

This pin sets the DAC current. A 140 ohm resistor should be connected

between this pin and GND (DAC ground) using short and wide traces.

Out

CVBS

Y/G

Composite Video

This pin outputs a composite video signal capable of driving a 75 ohm

doubly terminated load.

Luma / Green Output

This pin outputs a selectable video signal. The output is designed to drive

a 75 ohm doubly terminated load. The output can be selected to be s-

video luminance or green.

Chroma / Red Output

This pin outputs a selectable video signal. The output is designed to drive

a 75 ohm doubly terminated load. The output can be selected to be s-

video chrominance or red.

Composite Video / Blue Output

This pin outputs a selectable video signal. The output is designed to drive

a 75 ohm doubly terminated load. The output can be selected to be

composite video or blue.

Crystal Input / External Reference Input

38

39

42

1

Out

In

C/R

CVBS/B

XI / FIN

A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached

between this pin and XO. However, an external clock can drive the

XI/FIN input.

64-Pin

LQFP

# Pins Type

Symbol Description

4

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

Table 1. Pin Description (continued)

43

1

In

XO

Crystal Output

A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached

between this pin and XI / FIN. However, if an external CMOS clock is

attached to XI/FIN, XO should be left open.

Pixel Clock Output / DVI Detect Output

When the CH7010 is operating as a VGA to TV encoder in master clock

mode, this pin provides a pixel clock signal to the VGA controller which

is used as a reference frequency. The output is selectable between 1X or

2X of the pixel clock frequency. The output driver is driven from the

DVDDV supply. This output has a programmable tri-state. The

capacitive loading on this pin should be kept to a minimum.

46

1

Out

P-OUT /

TLDET*

When the CH7010 is operating as a DVI transmitter, this pin provides an

open drain output which pulls low when a termination change has been

detected on the HPDET input. The output is released through serial port

control.

47

48

1

Out

BCO/

Buffered Clock Output / Vertical Sync Output

This output pin provides a buffered clock output, driven by the DVDD

V SYNC

supply. The output clock can be selected using the BCO register.

This pin can also be used as VSYNC output.

Composite / Horizontal Sync Output

Out

C/H

This pin can be selected to output a TV composite sync, TV horizontal

sync, or a buffered version of the VGA horizontal sync. The output is

driven from the DVDD supply.

Data[11] through Data[0] Inputs

These pins accept the 12 data inputs from a digital video port of a

graphics controller. The levels are 0 to DVDDV, and the VREF signal

is used as the threshold level.

External Clock Inputs

SYNC

50 – 55, 12

58 – 63

In / Out

In

D[11] -

D[0]

57, 56

2

XCLK,

XCLK*

These inputs form a differential clock signal input to the CH7010 for

use with the H, V, DE and D[11:0] data. If differential clocks are not

available, the XCLK* input should be connected to VREF.

The output clocks from this pad cell are able to have their polarities

reversed under the control of the MCP bit (in register 1Ch).

Digital Supply Voltage (3.3V-3.6V)

Digital Ground

I/O Supply Voltage (3.3V to 1.1V)

DVI Transmitter Supply Voltage (3.3V-3.6V)

DVI Transmitter Ground

1, 12, 49

6, 11, 64

45

23, 29

20, 26,

3

1

2

3

Power

DVDD

DGND

DVDDV

TVDD

TGND

32

18, 44

16, 17,

2

3

Power

AVDD

AGND

PLL Supply Voltage (3.3V-3.6V)

PLL Ground

41

33

1

2

Power

VDD

GND

DAC Supply Voltage (3.3V-3.6V)

DAC Ground

34, 40

201-0000-038 Rev 3.1, 11/4/2004

5

CHRONTEL

CH7010B

4. MODES OF OPERATION

The CH7010 is capable of being operated as a single DVI output, or as a VGA to TV encoder. The two modes of

operation cannot be used simultaneously. Descriptions of each of the operating modes, with a block diagram of the data

flow within the device is shown below.

4.1 DVI Output

In DVI Output mode, multiplexed input data, sync and clock signals are input to the CH7010 from the graphics

controller’s digital output port. Data will be 2X multiplexed, and the clock inputs can be 1X or 2X times the pixel rate.

Some examples of modes supported are shown in the table below, and a block diagram of the CH7010 is shown on the

following page. For the table below, clock frequencies for given modes were taken from VESA DISPLAY MONITOR

TIMING SPECIFICATIONS if they were detailed there, not VESA TIMING DEFINITION FOR FLAT PANEL MONITORS. The

device is not dependent upon this set of timing specifications. Any value of pixels/line, lines/frame and clock rate are

acceptable, as long as the pixel rate remains below 165MHz. In the block diagram, all blocks are shown. Those blocks

which are non-active are shown as shaded. The clock and data paths which are in use are highlighted. Although the block

diagram does not show this path as being active, the data input can be selected to be output by the DACs as a VGA type

output. For correct DVI operation, the input data format must be selected to be one of the RGB input formats.

Table 2. DVI Output

Graphics

Active

Pixel Aspect RefreshRate

XCLK

DVI

Resolution Aspect Ratio

Ratio

(Hz)

Frequency

(MHz)

<35.5

<31.5

<36

Frequency

(MHz)

<355

<315

<360

270

720x400

640x400

640x480

4:3

8:5

4:3

1.35:1.00

1:1

<85

1:1

<85

720x480¹

9:8

15:12

59.94

50

27

720x576²

800x600

4:3

270

4:3

1:1

<85

<60

<85

<60

<57

<570

1024x768

1280x720

1280x1024

1600x1200

1920x1080

4:3

<95

<950

16:9

4:3

<67

<670

<158

<165

<140

<1580

<1650

<1400

4:3

<30²

16:9

1

2

These DVD compatible modes are input in a non-interlaced RGB data format.

30Hz in progressive scan modes, 60Hz in interlaced modes.

6

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

Clock

Driver

DVI PLL

TLC,TLC*

2

XCLK, XCLK*

2

TDC0,TDC0*

DVI

2

TDC1,TDC1*

Encode

Serialize

Driver

24

3

TDC2,TDC2*

Data

Latch,

Demux

D[11:0]

12

VSWING

HPDET

GPIO[1:0]

AS

SPC

SPD

24

2

H, V, DE

Latch

H,V,DE

3

Serial

port

VREF

3

2

Control

XI/FIN,XO

P-OUT/TLDET*

PLL3

RESET*

C/H SYNC

ISET

Timing

BCO

Scaling

CVBS^(DAC3)

Four

10-bit

DAC’s

TV

Scan

Conv

Y/G(DAC1)

3

Encode

C/R(DAC2)

Flicker Filt

24

CVBS/B(DAC0)

24

Figure 3. DVI Output

201-0000-038 Rev 3.1, 11/4/2004

7

CHRONTEL

CH7010B

4.2 TV Output

In TV Output mode, multiplexed input data, sync and clock signals are input to the CH7010 from the graphics controller’s

digital output port. A P-OUT clock can be output as a frequency reference to the graphics controller, which is

recommended to ensure accurate frequency generation. Horizontal and vertical sync signals are normally sent to

the CH7010 from the graphics controller, but can be output to the graphics controller as an option. This method should

not be used for pixel frequencies above 50 MHz. Data will be 2X multiplexed, and the XCLK clock signal can be 1X or

2X times the pixel rate. The input data will be encoded into the selected video standard, and output from the video

DAC’s. The modes supported for TV output are shown in the table below, and a block diagram of the CH7010 is shown

on the following page. In the block diagram, all blocks are shown. Those blocks which are non-active are shown as

shaded. The clock and data paths which are in use are highlighted.

Table 3. TV Output Modes

Graphics

Active Aspect

Pixel Aspect

TV Output

Scaling Ratios

Resolution

512x384

720x400

640x400

640x480

Ratio

4:3

8:5

4:3

Ratio

Standard

1:1

PAL

5/4, 1/1

1:1

NTSC

PAL

1.35:1.00

1:1

5/4, 1/1

NTSC

PAL

5/4, 1/1

1:1

NTSC

PAL

5/4, 1/1, 7/8

5/4, 1/1, 5/6

1/1, 7/8, 5/6

1/1

1:1

NTSC

720x480¹

720x480²

720x576¹

9:8

NTSC

PAL

1/1, 7/8, 5/6

1/1

1/1, 5/6, 5/7

3/4, 7/10, 5/8

5/7, 5/8, 5/9

5/8, 5/9, 1/2

15:12

720x576²

800x600

1024x768

1:1

PAL

NTSC

PAL

NTSC

1

2

These DVD modes operate with interlaced input, scan conversion and flicker filter are bypassed.

These DVD modes operate with non-interlaced input, scan conversion is not bypassed.

In order to minimize the hazard of ESD, a set of protection diodes

MUST BE used for each DAC connecting to TV (Refer to AN-38 for details).

8

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

XCLK, XCLK*

2

TLC,TLC*

DVI PLL

Clock

Driver

2

TDC0,TDC0*

DVI

2

DVI

TDC1,TDC1*

Encode

Serialize

Driver

2

24

3

TDC2,TDC2*

Data

Latch,

Demux

D[11:0]

12

VSWING

HPDET

24

GPIO[1:0]

2

H,V,DE

3

H, V, DE

Latch

AS

SPC

SPD

Serial

Port

VREF

3

2

Control

XI/FIN,XO

P-OUT/TLDET*

PLL3

RESET*

C/H SYNC

ISET

Timing

BCO

CVBS^(DAC3)

Scaling

Four

10-bit

DAC’s

TV

Y/G(DAC1)

Scan Conv

Flicker Filt

3

24

Encode

C/R(DAC2)

CVBS/B(DAC0)

24

Figure 4. TV Output Modes

201-0000-038 Rev 3.1, 11/4/2004

9

CHRONTEL

CH7010B

5. INPUT INTERFACE

Two distinct methods of transferring data to the CH7010 are described. They are:

•

Multiplexed data, clock input at 1X pixel rate

Multiplexed data, clock input at 2X pixel rate

For the multiplexed data, clock at 1X pixel rate, the data applied to the CH7010 is latched with both edges of the clock

(also referred to as dual-edge transfer mode). For the multiplexed data, clock at 2X pixel rate, the data applied to the

CH7010 is latched with one edge of the clock. The polarity of the pixel clock can be reversed under serial port control.

5.1 Input Clock and Data Timing Diagram

The figure below shows the timing diagram for input data and clocks. The first XCLK/XCLK* waveform represents the

input clock for the multiplexed data, clock at 2X pixel rate method. The second XCLK/XCLK* waveform represents the

input clock for the multiplexed data, clock at 1X pixel rate method.

XCLK

D[11:0]

DE

64 P-OUT

H

1 VGA Line

V

Figure 5. Interface Timing

Regarding the CH7010 timing specifications, please see Figure 18 - Figure 20 for details.

10

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

5.2 Input Clock and Data Formats

The 12 data inputs support 5 different multiplexed data formats, each of which can be used with a 1X clock latching data

on both clock edges, or a 2X clock latching data with a single edge. The data received by the CH7010 can be used to drive

the DVI output, the VGA to TV encoder, or directly drive the DAC’s. The multiplexed input data formats are (IDF[2:0]):

IDF

0

1

Description

12-bit multiplexed RGB input (24-bit color), (multiplex scheme 1)

12-bit multiplexed RGB2 input (24-bit color), (multiplex scheme 2)

8-bit multiplexed RGB input (16-bit color, 565)

2

3

8-bit multiplexed RGB input (15-bit color, 555)

4

8-bit multiplexed YCrCb input (24-bit color), (Y, Cr and Cb are multiplexed)

For multiplexed input data formats, either both transitions of the XCLK/XCLK* clock pair, or each rising or falling edge

of the clock pair (depending upon MCP bit, rising refers to a rising edge on the XCLK signal, a falling edge on the

XCLK* signal) will latch data from the graphics chip. The multiplexed input data formats are shown in the figures below.

The Pixel Data bus represents a 12-bit or 8-bit multiplexed data stream, which contains either RGB or YCrCb formatted

data. The input data rate is 2X the pixel rate, and each pair of Pn values (eg; P0a and P0b) will contain a complete pixel

encoded as shown in the tables below. It is assumed that the first clock cycle following the leading edge of the incoming

horizontal sync signal contains the first word (Pxa) of a pixel, if an active pixel was present immediately following the

horizontal sync. This does not mean that active data should immediately follow the horizontal sync, however. When the

input is a YCrCb data stream the color-difference data will be transmitted at half the data rate of the luminance data, with

the sequence being set as Cb, Y, Cr, Y, where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples and

the following Y1 byte refers to the next luminance sample, per CCIR-656 standards (the clock frequency is dependent

upon the current mode, and is not 27MHz as specified in CCIR-656). All non-active pixels should be 0 in RGB formats,

and 16 for Y and 128 for CrCb in YCrCb formats.

201-0000-038 Rev 3.1, 11/4/2004

11

CHRONTEL

CH7010B

HS

XCLK

(2X)

SAV

XCLK

(1X)

P0a

P0b

P1a

P1b

P2a

P2b

D[11:0]

The following data is latched for IDF = 0

The following data is latched for IDF = 1

P[23:16]

P0b[11:4]

P0b[3:0], P0a[11:8]

P0a[7:0]

P1b[11:4]

P2b[11:4]

P2b[3:0],

(Red Data)

P[15:8]

P1b[3:0], P1a[11:8]

P1a[7:0]

P2a[11:8]

(Green Data)

P[7:0]

P2a[7:0]

(Blue Data)

P2b[11:7]

P2b[3:1]

P[23:16]

P0b[11:7], P0b[3:1]

P1b[11:7], P1b[3:1]

(Red Data)

P0b[6:4], P0a[11:9],

P0b[0], P0a[3]

P1b[6:4], P1a[11:9],

P1b[0], P1a[3]

P[15:8]

(Green Data)

P2a[8:4]

P2a[2:0]

P[7:0]

P0a[8:4], P0a[2:0]

P1a[8:4], P1a[2:0]

(Blue Data)

Figure 6. Multiplexed Input Data Formats (IDF = 0, 1)

12

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

HS

XCLK

(2X)

SAV

XCLK

(1X)

P0a

P0b

P1a

P1b

P2a

P2b

D[11:0]

The following data is latched for IDF = 2

The following data is latched for IDF = 3

The following data is latched for IDF = 4

P[23:19]

P0b[11:7]

P0b[6:4], P0a[11:9]

P0a[8:4]

P1b[11:7]

P2b[11:7]

P2b[6:4],

(Red Data)

P[15:10]

P1b[6:4], P1a[11:9]

P1a[8:4]

P2a[11:9]

(Green Data)

P[7:3]

P2a[8:4]

(Blue Data)

P[23:19]

P0b[10:6]

P0b[5:4], P0a[11:9]

P0a[8:4]

P1b[10:6]

P1b[5:4], P1a[11:9]

P1a[8:4]

P2b[10:6]

(Red Data)

P2b[5:4],

P2a[11:9]

P[15:11]

(Green Data)

P[7:3]

P2a[8:4]

(Blue Data)

CRA

(internal signal)

P[23:16]

P0b[7:0]

P0a[7:0]

GND

P1b[7:0]

P1a[7:0]

GND

P2b[7:0]

P2a[7:0]

GND

(Y Data)

P[15:8]

(CrCb Data)

P[7:0]

(ignored)

Figure 7. Multiplexed Input Data Formats (IDF = 2, 3, 4)

201-0000-038 Rev 3.1, 11/4/2004

13

CHRONTEL

CH7010B

Table 4. Multiplexed Input Data Formats (IDF = 0, 1)

IDF =

0

1

Format =

12-bit RGB (12-12)

Pixel #

Bus Data

P0a

P0b

P1a

P1b

P0a

P0b

P1a

P1b

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

G0[3]

G0[2]

G0[1]

G0[0]

B0[7]

B0[6]

B0[5]

B0[4]

B0[3]

B0[2]

B0[1]

B0[0]

R0[7]

R0[6]

R0[5]

R0[4]

R0[3]

R0[2]

R0[1]

R0[0]

G0[7]

G0[6]

G0[5]

G0[4]

G1[3]

G1[2]

G1[1]

G1[0]

B1[7]

B1[6]

B1[5]

B1[4]

B1[3]

B1[2]

B1[1]

B1[0]

R1[7]

R1[6]

R1[5]

R1[4]

R1[3]

R1[2]

R1[1]

R1[0]

G1[7]

G1[6]

G1[5]

G1[4]

G0[4]

G0[3]

G0[2]

B0[7]

B0[6]

B0[5]

B0[4]

B0[3]

G0[0]

B0[2]

B0[1]

B0[0]

R0[7]

R0[6]

R0[5]

R0[4]

R0[3]

G0[7]

G0[6]

G0[5]

R0[2]

R0[1]

R0[0]

G0[1]

G1[4]

G1[3]

G1[2]

B1[7]

B1[6]

B1[5]

B1[4]

B1[3]

G1[0]

B1[2]

B1[1]

B1[0]

R1[7]

R1[6]

R1[5]

R1[4]

R1[3]

G1[7]

G1[6]

G1[5]

R1[2]

R1[1]

R1[0]

G1[1]

Table 5. Multiplexed Input Data Formats (IDF = 2, 3)

IDF =

2

3

Format =

Pixel #

RGB 5-6-5

RGB 5-5-5

P1a

P0a

P0b

P1a

P1b

P0a

P0b

X

P1b

X

Bus Data

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

G0[4]

G0[3]

G0[2]

B0[7]

B0[6]

B0[5]

B0[4]

B0[3]

R0[7]

R0[6]

R0[5]

R0[4]

R0[3]

G0[7]

G0[6]

G0[5]

G1[4]

G1[3]

G1[2]

B1[7]

B1[6]

B1[5]

B1[4]

B1[3]

R1[7]

R1[6]

R1[5]

R1[4]

R1[3]

G1[7]

G1[6]

G1[5]

G0[5]

G0[4]

G0[3]

B0[7]

B0[6]

B0[5]

B0[4]

B0[3]

G1[5]

G1[4]

G1[3]

B1[7]

B1[6]

B1[5]

B1[4]

B1[3]

R0[7]

R0[6]

R0[5]

R0[4]

R0[3]

G0[7]

G0[6]

R1[7]

R1[6]

R1[5]

R1[4]

R1[3]

G1[7]

G1[6]

Table 6. Multiplexed Input Data Formats (IDF = 4)

IDF =

4

Format =

Pixel #

YCrCb 8-bit

P2a

P0a

P0b

P1a

P1b

P2b

P3a

P3b

Bus Data

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

Cb0[7]

Cb0[6]

Cb0[5]

Cb0[4]

Cb0[3]

Cb0[2]

Cb0[1]

Cb0[0]

Y0[7]

Y0[6]

Y0[5]

Y0[4]

Y0[3]

Y0[2]

Y0[1]

Y0[0]

Cr0[7]

Cr0[6]

Cr0[5]

Cr0[4]

Cr0[3]

Cr0[2]

Cr0[1]

Cr0[0]

Y1[7]

Y1[6]

Y1[5]

Y1[4]

Y1[3]

Y1[2]

Y1[1]

Y1[0]

Cb2[7]

Cb2[6]

Cb2[5]

Cb2[4]

Cb2[3]

Cb2[2]

Cb2[1]

Cb2[0]

Y2[7]

Y2[6]

Y2[5]

Y2[4]

Y2[3]

Y2[2]

Y2[1]

Y2[0]

Cr2[7]

Cr2[6]

Cr2[5]

Cr2[4]

Cr2[3]

Cr2[2]

Cr2[1]

Cr2[0]

Y3[7]

Y3[6]

Y3[5]

Y3[4]

Y3[3]

Y3[2]

Y3[1]

Y3[0]

14

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

When IDF = 4 (YCrCb mode), the data inputs can also be used to transmit sync information to the device. In this mode,

the embedded sync will follow the VIP2 convention, and the first byte of the ‘video timing reference code’ will be

assumed to occur when a Cb sample would occur, if the video stream was continuous. This is shown below:

Table 7. Embedded Sync

IDF =

4

Format =

YCrCb 8-bit

Pixel #

Bus Data

P0a

FF

P0b

00

P1a

00

P1b

S[7]

S[6]

S[5]

S[4]

S[3]

S[2]

S[1]

S[0]

P2a

Cb2[7]

P2b

P3a

P3b

Dx[7]

Dx[6]

Dx[5]

Dx[4]

Dx[3]

Dx[2]

Dx[1]

Dx[0]

Y2[7]

Y2[6]

Y2[5]

Y2[4]

Y2[3]

Y2[2]

Y2[1]

Y2[0]

Cr2[7]

Cr2[6]

Cr2[5]

Cr2[4]

Cr2[3]

Cr2[2]

Cr2[1]

Cr2[0]

Y3[7]

Y3[6]

Y3[5]

Y3[4]

Y3[3]

Y3[2]

Y3[1]

Y3[0]

Cb2[6]

Cb2[5]

Cb2[4]

Cb2[3]

Cb2[2]

Cb2[1]

Cb2[0]

In this mode, the S[7..0] byte contains the following data:

S[6]

S[5]

S[4]

=

F

V

H

=

1 during field 2, 0 during field 1

1 during field blanking, 0 elsewhere

1 during EAV (synchronization reference at the end of active video)

0 during SAV (synchronization reference at the start of active video)

Bits S[7] and S[3..0] are ignored.

201-0000-038 Rev 3.1, 11/4/2004

15

CHRONTEL

CH7010B

5.3 NTSC and PAL Operation

Composite and S-Video outputs are supported in either NTSC or PAL format. The general parameters used to characterize

these outputs are listed in Table 9 and shown in Figure 8. (See Figures 11 through 16 for illustrations of composite and S-

Video output waveforms).

Table 8. NTSC/PAL Composite Output Timing Parameters (in ms)

Symbol

Description

Level (mV)

Duration (uS)

NTSC

PAL

A

Front Porch

Horizontal Sync

Breezeway

Color Burst

Back Porch

Black

1.49 - 1.51

4.69 - 4.72

0.59 - 0.61

2.50 - 2.53

1.55 - 1.61

0.00 - 7.50

37.66 - 52.67

0.00 - 7.50

1.48 - 1.51

4.69 - 4.71

0.88 - 0.92

2.24 - 2.26

2.62 - 2.71

0.00 - 8.67

34.68 - 52.01

0.00 - 8.67

A

B

C

D

E

F

287

0

300

0

287

340

300

Active Video

Black

G

H

1. Durations vary slightly in different modes due to the different clock frequencies used.

2. Active video and black (F, G, H) times vary greatly due to different scaling ratios used in different modes.

3. Black times (F and H) vary with position controls.

A

B

C

D

E

F

G

H

Figure 8. NTSC / PAL Composite Output

16

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

SSTTAARRTT

OOFF

VVSSYYNNCC

AANNAALLOOGG

Start of

field 1

FFIIEELLDD 11

12

99

10

77

11

88

523

524

525

9

66

1

2

6

33

7

44

8

55

3

4

11

5

22

552200 552211 552222 552233 552244 552255

Pre-equalizing

pulse interval

Post-equalizing

pulse interval

Vertical sync

pulse interval

Line

Reference

FFIIEELLDD 22

color field 1

AANNAALLOOGG

vertical

interval

sub-carrier phase

t +V

1

263

262

264

270

261

265

266

267

268

269

271

272

273

274

275

225588 225599 226600 226611 226622 226633 226644 226655 226666 226677 226688 226699 227700 227711 227722

Start of

field 2

START

OF

VSYNC

RAe ArLeOncGe

_suN_bf_-e_{carrier phase}

FIELD 1

t +V

color field 2

2

523

11

10

12

9

524

2

7

8

9

525

522

1

3

525

6

3

4

1

5

2

520

521

523

524

4

5

6

7

8

Start of

field 3

Ref

A

er

N

e

A

nc

L

e

OG

^subF^-cI^aE^rL^riD^{er p}2^hase

color field 3

t +V

3

261

262

269

270

272

273

270

263

260

264

261

265

262

266

263

267

264

268

265

271

268

274

271

275

272

258

259

266

267

269

Start of

field 4

Reference

sub-carrier phase

color field 4

Figure 9. Interlaced NTSC Video Timing

201-0000-038 Rev 3.1, 11/4/2004

17

CHRONTEL

CH7010B

START

OF

VSYNC

ANALOG

FIELD 1

620

621

622

623

624

625

1

2

3

4

5

6

7

8

9

10

ANALOG

FIELD 2

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

AANNA GG

ALO

FIEL

FIELD 3

620

621

622

623

624

625

1

2

3

4

5

6

7

8

9

10

ANALOG

FIELD 4

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

BURST

BLANKING

INTERVALS

BURST

4

3

BLANKING

°

BURST PHASE = REFERENCE PHASE = 135 RELATIVE TO U

PAL SWITCH = 0, +V COMPONENT

2

1

°

RELATIVE TO U

BURST PHASE = REFERENCE PHASE+90

°

= 225

BURST PHASE = REFERENCE PHASE + 90 = 225 RELATIVE TO U

PAL SWITCH = 1, - V COMPONENT

Figure 10. Interlaced PAL Video Timing

18

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

Color bars:

Color/Level

mA

V

White

Yellow

26.66

24.66

1.000

0.925

Cyan

Green

21.37

19.37

0.801

0.726

Magenta

Red

16.22

14.22

0.608

0.533

Blue

11.08

9.08

0.415

0.340

Black

Blank

7.65

0.287

Sync

0.00

0.000

Figure 11. NTSC Y (Luminance) Output Waveform (DACG = 0)

Color bars:

Color/Level

mA

V

White

Yellow

26.75

24.62

1.003

0.923

Cyan

Green

21.11

18.98

0.792

0.712

Magenta

Red

15.62

13.49

0.586

0.506

Blue

10.14

8.00

0.380

0.300

Blank/ Black

Sync

0.00

0.000

Figure 12. PAL Y (Luminance) Video Output Waveform (DACG = 1)

201-0000-038 Rev 3.1, 11/4/2004

19

CHRONTEL

CH7010B

Color bars:

Color/Level

mA

V

Cyan/Red

Green/Magenta 25.01

25.80

0.968

0.938

Yellow/Blue

22.44

0.842

Peak Burst

Blank

18.08

14.29

0.678

0.536

Peak Burst

10.51

0.394

3.579545 MHz Color Burst

(9 cycles)

Yellow/Blue

6.15

0.230

Green/Magenta

Cyan/Red

3.57

2.79

0.134

0.105

Figure 13. NTSC C (Chrominance) Video Output Waveform (DACG = 0)

Color bars:

Color/Level

mA

V

Cyan/Red

27.51

1.032

1.000

Green/Magenta 26.68

Yellow/Blue

23.93

0.897

Peak Burst

Blank

19.21

15.24

0.720

0.572

Peak Burst

11.28

0.423

4.433619 MHz Color Burst

(10 cycles)

Yellow/Blue

6.56

0.246

Green/Magenta

Cyan/Red

3.81

2.97

0.143

0.111

Figure 14. PAL C (Chrominance) Video Output Waveform (DACG = 1)

20

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

Color/Level

Peak Chrome 32.88

mA

V

1.233

Color bars:

White

26.66

1.000

Peak Burst

11.44

0.429

Black

Blank

9.08

7.65

0.340

0.287

Peak Burst

Sync

4.45 0.145

0.00 0.000

3.579545 MHz Color Burst

(9 cycles)

Figure 15. Composite NTSC Video Output Waveform (DACG = 0)

mA

Color/Level

V

1.249

Color bars:

Peak Chrome 33.31

White

26.75

1.003

Peak Burst

Blank/Black

11.97

8.00

0.449

0.300

Peak Burst

Sync

4.04

0.00

0.151

0.000

4.433619 MHz Color Burst

(10 cycles)

Figure 16. Composite PAL Video Output Waveform (DACG = 1)

201-0000-038 Rev 3.1, 11/4/2004

21

CHRONTEL

CH7010B

5.4 Hot Plug Detection

The CH7010 has the capability of signaling to the graphics controller when the termination of the DVI outputs has

changed. The operation of this circuit is as follows. The HPDET input pin of the CH7010 should be connected to pin 16

of the DVI connector. When a DVI monitor is connected to the DVI connector, this pin will be pulled high (above 2.4

volts). When a DVI monitor is not connected to the DVI connector, the internal pull-down on the HPDET pin will pull

low. When the HPDET is low, the DVI output driver will be shut down. The CH7010 will detect any transition at the

HPDET pin. When the HPIE (Hot Plug Interrupt Enable) bit in serial port register 1Eh is high, the CH7010 will pull low

on the P-OUT / TLDET* pin. When the HPIE2 (Hot Plug Interrupt Enable 2) bit in serial port register 20h is high, the

CH7010 will pull low on the GPIO[1] / TLDET* pin. This should signal the driver to read the DVIT bit in register 20h to

determine the state of the HPDET pin. The P-OUT / TLDET pin will continue to pull low until the driver sets the HPIR

(Hot Plug Interrupt Reset) bit in register 1Eh high. The driver should then set the HPIR bit low. In order to reset the HPIR

bit high, DVIP and DVIL bits of register 49h[7:6] must first be set to ’11’.

6. REGISTER CONTROL

The CH7010 is controlled via a serial port. The serial port bus uses only the SPC clock to latch data into registers, and

does not use any internally generated clocks so that the device can be written to in all power down modes. The device

retains all register states.

The CH7010 contains a total of 37 registers for user control. A listing of non-Macrovision control bits is given below

with a brief description of each.

6.1 Non-Macrovision Control Registers Map

The non-Macrovision controls are listed below, divided into four sections: general controls, input / output controls, DVI

controls, and VGA to TV controls. A register map and register description follows.

• General Controls

ResetIB

ResetDB

PD[7:0]

VID[7:0]

DID[7:0]

TSTP[1:0]

Software serial reset

Software datapath reset

Power down controls (DVIP, DVIL, , TVD, DACPD[1:0], Full, Partial)

Version ID register

Device ID register

Enable/select test pattern generation (color bar, ramp)

• Input/Output Controls

XCM

XCLK 1X, 2X select

XCMD[7:0]

MCP

Delay adjust between XCLK and D[11:0]

XCLK polarity control

PCM

P-OUT 1X, 2X select

POUTP

POUTE

HPIE, HPIE2

HPIR

P-OUT clock polarity

P-OUT enable

Hot plug detect interrupt enable

Hot plug detect interrupt reset

IDF[2:0]

IBS

Input data format

Input buffer select

DES

Decode embedded sync (TV-Out data only)

H/V sync direction control (for TV-Out modes only)

V sync polarity control (sync polarity to DVI is not changed)

H sync polarity control (sync polarity to DVI is not changed)

Termination detect/check (DVI, DACT3, DACT2, DACT1, DACT0, SENSE)

Enable BCO Output

SYO

VSP

HSP

TERM[5:0]

BCOEN

BCO[2:0]

BCOP

Select output signal for BCO pin

BCO polarity

GPIOL[1:0]

GOENB[1:0]

SYNCO[1:0]

DACG[1:0]

DACBP

XOSC[2:0]

Read or write level for GPIO pins

Direction control for GPIO pins

Enables/selects sync output for Scart and bypass modes

DAC gain control

DAC bypass

Crystal oscillator adjustments

22

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

• DVI Controls

TPPD[2:0]

TPCP[1:0]

TPVT[5:0]

TPVCO[10:0]

TPD[5:0]

DVI PLL phase detector trim

DVI PLL charge pump trim

DVI PLL VDD trim

DVI PLL VCO trim

DVI PLL divider

TLPF[3:0]

DVID[3:0]

CTL[3:0]

DVI PLL low pass filter

DVI transmitter drive strength

DVI control inputs

TERM [2]

DVI hot plug detection

• TV-Out Controls

IR[2:0]

Input data resolution (when used for TV-Out)

VOS[1:0]

TV-Out video standard

SR[2:0]

TV-Out scaling ratio

CFF[1:0]

YFFT[1:0]

YFFNT[1:0]

CVBWB

CBW

Chroma flicker filter setting

Luma text enhancement flicker filter setting

Luma flicker filter setting (Non-text)

CVBS DAC receives black&white (S-Video luminance) signal

Chroma video bandwidth

YSV[1:0]

YCV[1:0]

TE[2:0]

S-Video luma bandwidth

Composite video luma bandwidth

Text enhancement (sharpness)

CFRB

M/S*

SAV [8:0]

BLCK[7:0]

HP[8:0]

Chroma sub-carrier free run (bar) control

TV-Out PLL reference input control

Horizontal start of active video (delay from leading edge of H sync to active video)

TV-Out Black level control

TV-Out horizontal position control

TV-Out vertical position control

VP[8:0]

VOF

CE[2:0]

TV-Out video format (s-video & composite, RGB)

TV-Out contrast enhancement

PLLTVM[8:0]

PLLTVN[9:0]

FSCI[32:0]

CIVEN

CIVC[1:0]

CIV[25:0]

CIVPN

TV-Out PLL M divider

TV-Out PLL N divider

Sub-carrier generation increment value (when ACIV=0)

Calculated sub-carrier enable (was called ACIV)

Calculated sub-carrier control (hysteresis,

Calculated sub-carrier increment value read out

Select PAL-Nc (Argentina) when in a CIV mode

Memory sense amp reference adjust

Vertical blanking interval defeat

MEM[2:0]

VBID

PLLCPI

TV-Out PLL charge pump current control

PLLCAP

TV-Out PLL capacitor control

201-0000-038 Rev 3.1, 11/4/2004

23

CHRONTEL

CH7010B

6.2 Registers Read/Write

Regarding the CH7010 registers read/write operation, please see applications note AN-41 for details.

6.3 Non-Macrovision Control Registers Description

Table 9. Serial Port Register Map w/o Macrovision

Register

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

31h

32h

33h

34h

35h

36h

37h

48h

49h

4Ah

4Bh

Bit 7

IR2

Bit 6

IR1

Bit 5

IR0

Bit 4

VOS1

CFF0

CBW

HP8

Bit 3

VOS0

YFFT1

YSV1

VP8

Bit 2

Bit 1

Bit 0

SR2

SR1

SR0

VOF0

CFRB

CFF1

CVBWB

SAV8

SAV5

HP5

YFFT0

YSV0

TE2

YFFNT1

YCV1

TE1

YFFNT0

YCV0

TE0

VBID

SAV7

HP7

VP7

BL7

SAV6

HP6

VP6

BL6

SAV4

HP4

SAV3

HP3

SAV2

HP2

SAV1

HP1

SAV0

HP0

VP5

VP4

VP3

VP2

VP1

VP0

BL5

BL4

BL3

BL2

BL1

BL0

CE2

CE1

CE0

MEM2

M7

MEM1

M6

MEM0

M5

N9

N8

M8

PLLCPI

M1

PLLCAP

M0

M4

M3

M2

N7

N6

N5

N4

N3

N2

N1

N0

FSCI31

FSCI23

FSCI15

FSCI7

FSCI30

FSCI22

FSCI14

FSCI6

FSCI29

FSCI21

FSCI13

FSCI5

CIV25

CIV21

CIV13

CIV5

FSCI28

FSCI20

FSCI12

FSCI4

CIV24

CIV20

CIV12

CIV4

FSCI27

FSCI19

FSCI11

FSCI3

CIVC1

CIV19

CIV11

CIV3

FSCI26

FSCI18

FSCI10

FSCI2

CIVC0

CIV18

CIV10

CIV2

MCP

XCMD2

HPIE

IDF2

DACT1

FSCI25

FSCI17

FSCI9

FSCI1

PALN

CIV17

CIV9

CIV1

PCM

FSCI24

FSCI16

FSCI8

FSCI0

CIVEN

CIV16

CIV8

CIV23

CIV15

CIV7

CIV22

CIV14

CIV6

CIV0

M/S*

XCM

XCMD0

POUTP

IDF0

XCMD3

HPIR

HSP

XCMD1

POUTE

IDF1

GOENB1 GOENB0 GPIOL1

GPIOL0

VSP

IBS

DES

SYO

HPIE2

XOSC1

SHF2

XOSC2

XOSC0

SHF1

DVIT

DACT3

DACT2

DACT0

DACG0

BCO1

SENSE

DACBP

BCO0

SYNCO1 SYNCO0 DACG1

SHF0

BCOEN

BCOP

BCO2

HPDD

TPPD3

TPPD2

TPVCO6

DVID1

TPPD1

TPPD0

CTL3

CTL2

CTL1

CTL0

TPVCO7

DVID2

TPVCO5

DVID0

TPVCO4

TPVCO3

TPPSD1

TPFBD3

TPVT3

TPVCO2

TPPSD0

TPFBD2

TPVT2

TPVCO1

TPCP1

TPFBD1

TPVT1

TPVCO0

TPCP0

TPFBD0

TPVT0

TPFFD1

TPVT5

TPFFD0

TPVT4

TPLPF0

TPLPF3

TPLPF2

TPVCO10 TPVCO9

TPLPF1

TPVCO8

ResetIB

ResetDB

DVIP

VID7

DID7

DVIL

VID6

DID6

TV

DACPD3 DACPD2 DACPD1 DACPD0 FPD

VID5

DID5

VID4

DID4

VID3

DID3

VID2

DID2

VID1

DID1

VID0

DID0

All register bits not defined in the register map are reserved bits, and should be left at the default value.

Table 9 shows the CH7010 non-Macrovision register map. The details are described as follows:

Display Mode Register

Symbol:

DM

Address:

00h

Bits:

8

BIT

7

6

IR1

R/W

1

5

IR0

R/W

1

4

VOS1

R/W

0

3

VOS0

R/W

1

2

SR2

R/W

0

1

SR1

R/W

1

0

SR0

R/W

0

SYMBOL

IR2

TYPE

DEFAULT

R/W

0

24

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

Register DM provides programmable control of the CH7010 VGA to TV display mode, including input resolution

(IR[2:0]), video output standard (VOS[1:0]), and scaling ratio (SR[2:0]). The mode of operation is determined according

to Table 10 below. For entries in which the output standard is shown as PAL, PAL-B,D,G,H,I,N,N_Ccan be supported

through proper selection of the chroma sub-carrier. For entries in which the output standard is shown as NTSC, NTSC-M,

J and PAL-M can be supported through proper selection of VOS[1:0] and chroma sub-carrier.

Table 10. Display Mode

Mode

IR[2:0]

VOS

[1:0]

SR[2:0] Input Data Total Pixels/Line

Output

Standard

[TV

Scaling

Percent

Overscan

Pixel Clock

(MHz)

Format

(Active

x Total

Lines/Frame

Video)

Standard]

PAL

0

000

001

010

011

100

101

110

111

101

100

00

01

00

01

00

01

00

01

00

01

00

01

00

01

000

001

000

001

000

001

000

001

000

001

000

001

010

000

001

011

001

010

011

001

010

011

001

011

100

001

011

100

110

111

101

100

101

110

101

110

111

000

512x384

720x400

640x400

640x480

720x480

720x576

800x600

1024x768

720x576

720x480

840x500

840x625

800x420

784x525

1125x500

1152x625

945x420

936x525

1000x500

1008x625

840x420

832x525

840x600

840x500

840x625

840x750

784x525

784x600

800x630

882x525

882x600

900x630

882x625

900x750

900x875

944x625

960x750

960x875

1040x700

1064x750

1040x840

1400x875

1400x1000

1400x1125

1160x840

1160x945

1168x1050

864x625

858x525

5/4

1/1

5/4

1/1

5/4

1/1

5/4

1/1

5/4

1/1

5/4

1/1

7/8

5/4

1/1

5/6

1/1

7/8

5/6

1/1

7/8

5/6

1/1

5/6

5/7

1/1

5/6

5/7

3/4

7/10

5/8

5/7

5/8

5/9

5/8

5/9

1/2

1/1

-17

-33

0

21.000000

26.250000

20.139860

24.671329

28.125000

36.000000

23.790210

29.454545

25.000000

31.500000

21.146854

26.181819

30.209791

21.000000

26.250000

31.500000

24.671329

28.195805

30.209790

27.755245

31.720280

33.986015

27.562500

33.750000

39.375000

29.500000

36.000000

42.000000

43.636364

47.832169

52.363637

61.250000

70.000000

78.750000

58.405595

65.706295

73.510491

13.500000

1

PAL

2

NTSC

PAL

3

-20

-13

-30

+4

-16

-13

-30

+4

-17

-27

+4

-17

-30

0

-13

-18

0

-13

-18

0

-18

-30

+4

-14

-27

-6

-14

-22

-4

4

5

PAL

6

NTSC

PAL

7

8

9

PAL

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

NTSC

PAL

NTSC

PAL

NTSC

PAL

-16

-25

0

NTSC

PAL

-10

-20

0

NTSC

0

201-0000-038 Rev 3.1, 11/4/2004

25

CHRONTEL

CH7010B

Table 11. Video Output Standard Selection

VOS[1:0]

00

01

10

11

Output Format

PAL

NTSC

PAL-M

NTSC-J

Flicker Filter Register

Symbol:

FF

01h

8

Address:

Bits:

BIT

7

6

5

4

3

2

1

0

SYMBOL

TYPE

VOF

R/W

0

CFF1

CFF0 YFFT1 YFFT0 YFFNT1 YFFNT0

R/W

1

R/W

0

R/W

0

R/W

1

R/W

1

R/W

1

DEFAULT

Bits 1-0 of register FF control the filter used in the scaling and flicker reduction block applied to the non-text portion of

the luminance signal as shown in Table 12 below.

Bits 3-2 of register FF control the filter used in the scaling and flicker reduction block applied to the text portion of the

luminance signal as shown in Table 12 below.

Bits 5-4 of register FF control the filter used in the scaling and flicker reduction block applied to the chrominance signal

as shown in Table 13 below. A setting of ‘11’ applies a dot crawl reduction filter which can reduce the ‘hanging dots’

effect of an NTSC composite video signal when displayed on a TV with a comb filter.

Table 12. Luma Flicker Filter Control

YFFT and YFFNT Flicker Filter Settings (lines)

Scaling Ratio

00

2

01

3

10

3

11

3

5/4

1/1, 7/8, 5/6, 3/4, 5/7, 7/10

2

3

4

5

5/8

5/9

1/2

2

3

4

6

3

4

5

6

3

5

7

Table 13. Chroma Flicker Filter Control

CFF Flicker Filter Settings (lines)

Scaling Ratio

00

2

01

3

10

3

11

3

5/4

1/1, 7/8, 5/6, 3/4, 5/7, 7/10

2

3

4

5

5/8

5/9

1/2

2

3

4

5

3

4

5

6

3

5

7

Bit 6 of register FF controls the video output format. A value of ‘0’ generates composite and S-Video outputs. A

value of ‘1’ generates RGB outputs.

Video Bandwidth Register

Symbol:

Address:

Bits:

VBW

02h

8

BIT

7

6

5

4

CBW

R/W

1

3

YSV1

R/W

1

2

1

0

SYMBOL

VBID

R/W

1

CFRB CVBWB

YSV0

R/W

1

YCV1

R/W

1

YCV0

R/W

0

TYPE

DEFAULT

R/W

0

R/W

0

26

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

YCV[1:0] (bits 1-0) of register VBW control the filter used to limit the bandwidth of the luma signal in the CVBS

output signal. A table of –3dB bandwidth values is given below.

YSV[1:0] (bits 3-2) of register VBW control the filter used to limit the bandwidth of the luma signal in the S-Video

output signal. A table of –3dB bandwidth values is given below.

CBW (bit 4) of register VBW controls the filter used to limit the bandwidth of the chroma signal in the CVBS and

S-Video output signals. A table of –3dB bandwidth values is given below.

Bit 5 of register VBW controls the signal output on the CVBS signal. CVBW = ’0’ disables the chroma signal being

added to the CVBS signal, CVBW = ’1’ enables the chroma signal being added to the CVBS signal.

Table 14. Video Bandwidth

Mode

CBW

YSV[1:0] and YCV[1:0]

01

0

1

00

10

11

0

0.620

0.775

0.529

0.648

0.831

1.060

0.703

0.870

0.738

0.930

0.624

0.773

0.892

0.620

0.775

0.930

0.648

0.740

0.793

0.856

1.070

0.730

0.894

1.150

1.470

0.970

1.200

1.020

1.280

0.862

1.070

1.230

0.856

1.070

1.280

0.894

1.020

1.100

1.010

1.150

1.230

0.999

1.220

1.430

1.070

1.310

1.520

1.190

1.300

1.420

1.110

1.270

1.430

1.060

1.190

1.330

0.979

0.643

2.300

2.880

1.960

2.410

3.080

3.950

2.610

3.230

2.740

3.460

2.320

2.870

3.310

2.300

2.880

3.460

2.410

2.750

2.950

2.710

3.090

3.310

2.690

3.290

3.840

2.880

3.510

4.100

3.190

3.500

3.830

2.990

3.410

3.840

2.850

3.200

3.580

2.630

1.730

2.690

3.360

2.290

2.810

3.600

4.610

3.040

3.770

3.200

4.030

2.710

3.350

3.870

2.690

3.360

4.030

2.810

3.210

3.440

3.160

3.610

3.870

3.140

3.840

4.480

3.360

4.100

4.780

3.720

4.080

4.470

3.480

3.980

4.480

3.320

3.740

4.180

3.070

2.020

3.540

4.430

3.020

3.700

4.750

6.080

4.010

4.970

4.220

5.320

3.570

4.420

5.100

3.540

4.430

5.320

3.700

4.230

4.530

4.160

4.760

5.100

4.130

5.060

5.910

4.430

5.400

6.300

4.910

5.380

5.890

4.590

5.250

5.910

4.380

4.930

5.510

4.050

2.660

5.880

7.350

5.010

6.140

7.870

10.100

6.660

8.240

7.000

8.820

5.920

7.330

8.450

5.880

7.350

8.820

6.140

7.010

7.510

6.900

7.890

8.450

6.860

8.400

9.790

7.340

8.960

10.400

8.140

8.920

9.770

7.620

8.710

9.790

7.260

8.170

9.140

6.720

4.410

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

0.729

0.833

0.892

0.724

0.886

1.030

0.774

0.945

1.100

0.859

0.942

1.030

0.804

0.919

1.030

0.767

0.862

0.965

0.709

0.466

Bit 6 of register VBW controls whether the chroma sub-carrier free-runs, or is locked to the video signal. A ‘1’ causes the

sub-carrier to lock to the TV vertical rate, and should be used when the CIVEN bit (register 10h) is set to ‘0’. A ‘0’ causes

the sub-carrier to free-run, and should be used when the CIVEN bit is set to ‘1’.

Bit 7 of register VBW controls the vertical blanking interval defeat function. A ‘1’ in this register location forces the

flicker filter to minimum filtering during the vertical blanking interval. A ‘0’ in this location causes the flicker filter to

201-0000-038 Rev 3.1, 11/4/2004

27

CHRONTEL

CH7010B

remain at the same setting inside and outside of the vertical blanking interval.

Text Enhancement Register

Symbol:

Address:

Bits:

TE

03h

6

BIT

7

6

5

SAV8

R/W

0

4

HP8

R/W

0

3

VP8

R/W

0

2

1

TE1

R/W

0

TE0

R/W

1

SYMBOL

TYPE

TE2

R/W

1

DEFAULT

Bits 2-0 of register TE control the text enhancement circuitry within the CH7010. A value of ‘000’ minimizes the

enhancement feature, while a value of ‘111’ maximizes the enhancement.

Bits 5-3 of register TE contain the MSB values for the start of active video, horizontal position and vertical position

controls. They are described in detail in the SAV, HP and VP register descriptions.

Start of Active Video Register

Symbol:

Address:

Bits:

SAV

04h

8

BIT

7

SAV7

R/W

0

6

5

SAV5

R/W

0

4

SAV4

R/W

1

3

SAV3

R/W

0

2

1

0

SAV0

R/W

0

SYMBOL

TYPE

SAV6

R/W

1

SAV2

R/W

0

SAV1

R/W

0

DEFAULT

Register SAV controls the delay, in pixel increments, from leading edge of horizontal sync to start of active video. The

entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value contained in the Text Enhancement

register, bit SAV8. This is decoded as a whole number of pixels, which can be set anywhere between 0 and 511 pixels.

Therefore, in any 2X clock mode the number of 2X clocks from the leading edge of sync to the first active data must be a

multiple of two clocks.

Horizontal Position Register

Symbol:

Address:

Bits:

HP

05h

8

BIT

7

6

5

HP5

R/W

0

4

HP4

R/W

1

3

HP3

R/W

0

2

1

HP1

R/W

0

HP0

R/W

0

SYMBOL

HP7

R/W

0

HP6

R/W

1

HP2

TYPE

DEFAULT

R/W

0

Register HP is used to shift the displayed TV image in a horizontal direction ( left or right) to achieve a horizontally

centered image on screen. The entire bit field, HP[8:0], is comprised of this register HP[7:0] plus the MSB value

contained in the Text Enhancement register, bit HP8. Increasing values move the displayed image position right, and

decreasing values move the image position left.

Vertical Position Register

Symbol:

Address:

Bits:

VP

06h

8

28

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

BIT

7

6

VP6

R/W

0

5

VP5

R/W

0

4

VP4

R/W

0

3

VP3

R/W

0

2

VP2

R/W

0

1

VP1

R/W

0

VP0

R/W

0

SYMBOL

VP7

R/W

0

TYPE

DEFAULT

Register VP is used to shift the displayed TV image in a vertical direction ( up or down) to achieve a vertically centered

image on screen. The entire bit field, VP[8:0], is comprised of this register HP[7:0] plus the MSB value contained in the

Text Enhancement register, bit VP8. The value represents the TV line number (relative to the VGA vertical sync) used to

initiate the generation and insertion of the TV vertical interval (i.e. the first sequence of equalizing pulses). Increasing

values delay the output of the TV vertical sync, causing the image position to move up on the TV screen. Decreasing

values, therefore, move the image position DOWN. Each increment moves the image position by one TV lines

(approximately 2 input lines). The maximum value that should be programmed into the VP[8:0] value is the number of

TV lines per field minus one half (262 or 312). When panning the image up, the number should be increased until

(TVLPF-1/2) is reached, the next step should be to reset the register to zero. When panning the image down the screen,

decrement the VP[8:0] value until the value zero is reached. The next step should set the register to TVLPF-1/2, and then

decrement for further changes.

Black Level Register

Symbol:

Address:

Bits:

BL

07h

8

BIT

7

6

BL6

R/W

0

5

BL5

R/W

0

4

BL4

R/W

0

3

BL3

R/W

0

2

1

BL1

R/W

1

0

BL0

R/W

1

SYMBOL

BL7

BL2

TYPE

DEFAULT

R/W

0

1

Register BL controls the black level. The luminance data is added to this black level, which must be set between 51

and 208. When the input data format is zero through three the default values are 131 for NTSC and PAL-M, 110 for

PAL and 102 for NTSC-J. When the input data format is four the default values are 112 for NTSC and PAL-M, 94

for PAL and 88 for NTSC-J.

201-0000-038 Rev 3.1, 11/4/2004

29

CHRONTEL

CH7010B

Contrast Enhancement Register

Symbol:

Address:

Bits:

CE

08h

3

BIT

7

6

5

4

3

2

1

CE1

R/W

1

0

CE0

R/W

1

SYMBOL

TYPE

CE2

R/W

0

DEFAULT

Bits 2-0 of register CE control contrast enhancement feature of the CH7010, according to the figure below. A

setting of ‘0’ results in reduced contrast, a setting of ‘1’ leaves the image contrast unchanged, and values beyond ‘1’

result in increased contrast.

512

444

376

308

<i>

Yout

n

240

256

172

104

36

32

36

104

172

240

Yin

308

376

444

512

32

n

Figure 17. Contrast Enhancement diagram

30

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

TV PLL Control Register

Symbol:

Address:

Bits:

TPC

09h

5

BIT

7

6

5

IBI

R/W

0

4

N9

3

N8

2

1

0

SYMBOL

MEM2

R/W

1

MEM1

R/W

0

M8 PLLCPI PLLCAP

TYPE

DEFAULT

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit 0 of register TPC controls the TV PLL loop filter capacitor. A recommended listing of PLLCAP setting versus mode

is listed in Table 15 below.

Table 15. PLLCAP setting vs Display Mode

Mode

PLLCAP

Mode

PLLCAP

Value

1

Value

0

1

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

0

1

0

1

0

1

0

1

2

0

3

0

4

1

5

1

6

0

7

1

8

0

9

1

10

11

12

13

14

15

16

17

18

19

0

1

0

1

0

Bit 1 of register TPC should be left at the default value.

Bits 4-2 of register TPC contain the MSB values for the TV PLL divider ratio’s. These controls are described in detail in

the PLLM and PLLN register descriptions.

Bit 5 of register TPC controls the input latch bias current. The default value is recommended.

Bits 7-6 of register TPC control the memory sense amp reference level. The default value is recommended.

TV PLL M Value Register

Symbol:

Address:

Bits:

PLLM

0Ah

8

BIT

7

6

M6

R/W

0

5

M5

R/W

1

4

M4

R/W

1

3

M3

R/W

1

2

1

M1

R/W

1

0

M0

R/W

1

SYMBOL

M7

M2

TYPE

DEFAULT

R/W

0

1

201-0000-038 Rev 3.1, 11/4/2004

31

CHRONTEL

CH7010B

Register PLLM controls the division factor applied to the 14.31818MHz frequency reference clock before it is input

to the TV PLL phase detector when the CH7010 is operating in master clock mode. The entire bit field, M[8:0], is

comprised of this register M[7:0] plus the MSB value contained in the TV PLL Control register, bit M8. In slave

clock mode, an external pixel clock is used instead of the 14.31818MHz frequency reference, and the division factor

is determined by the XCM value in register 1Dh. A table of values versus display mode is given following the

PLLN register description.

TV PLL N Value Register

Symbol:

Address:

Bits:

PLLN

0Bh

8

BIT

7

6

N6

5

N5

4

N4

3

N3

2

1

N1

0

N0

SYMBOL

N7

N2

TYPE

DEFAULT

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

0

1

Register PLLN controls the division factor applied to the VCO output before being applied to the PLL phase

detector, when the CH7010 is operating in master clock mode. The entire bit field, N[9:0], is comprised of this

register N[7:0] plus N[9:8] contained in the TV PLL Control register (09h, bits 3 and 4). In slave clock mode, the

value of ‘N’ is internally set to 1. The pixel clock generated in clock master modes is calculated according to the

equation Fpixel = Fref * [(N+2) / (M+2)]. When using a 14.31818MHz frequency reference, the required M and N

values for each mode are shown in Table 16 below:

Table 16. TV PLL M and N values vs Display Mode

VGA Resolution,

TV Standard,

VGA Resolution,

TV Standard,

Mode

N

M

Mode

N

10-

bits

M

9-bits

10-

9-bits

Scaling Ratio

bits

20

9

0

512x384, PAL, 5:4

512x384, PAL, 1:1

512x384, NTSC, 5:4

512x384, NTSC, 1:1

720x400, PAL, 5:4

720x400, PAL, 1:1

720x400, NTSC, 5:4

720x400, NTSC, 1:1

640x400, PAL, 5:4

640x400, PAL, 1:1

640x400, NTSC, 5:4

640x400, NTSC, 1:1

640x400, NTSC, 7:8

640x480, PAL, 5:4

640x480, PAL, 1:1

640x480, PAL, 5:6

640x480, NTSC, 1:1

640x480, NTSC, 7:8

640x480, NTSC, 5:6

720x480, NTSC, 1:1

13

4

20

21

22

23

720x480, NTSC, 7:8

720x480, NTSC, 5:6

720x480, PAL, 1:1

720x480, PAL, 5:6

720x480, PAL, 5:7

800x600, PAL, 1:1

800x600, PAL, 5:6

800x600, PAL, 5:7

800x600, NTSC, 3:4

142 63

214 89

1

2

126 89

110 63

75

31

9

38

12

2

3

4

53

86

26

33

24

25

5

647 313

6

106 63

26

27

28

29

30

31

32

33

34

35

36

37

38

86

42

62

33

13

19

7

70

33

8

108 61

9

3

800x600, NTSC, 7:10 302 89

10

11

12

13

14

15

16

17

18

19

94

62

63

33

800x600, NTSC, 5/8

1024x768, PAL, 5:7

1024x768, PAL, 5:8

1024x768, PAL, 5:9

126 33

75

42

20

16

7

190 89

20

9

13

4

2

1024x768, NTSC, 5:8 565 137

1024x768, NTSC, 5:9 333 71

1024x768, NTSC, 1:2 917 177

9

3

110 63

126 63

190 89

124 63

720x576, PAL, 1:1

720x480, NTSC, 1:1

31

33

32

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

Sub-carrier Value Register

Symbol:

Address:

FSCI

0Ch –

0Fh

Bits:

8 each

BIT

7

6

5

FSCI#

R/W

4

FSCI#

R/W

3

FSCI#

R/W

2

1

0

FSCI#

R/W

SYMBOL

FSCI#

R/W

FSCI#

R/W

FSCI#

R/W

FSCI#

R/W

TYPE

DEFAULT

Registers FSCI contain a 32-bit value which is used as an increment value for the ROM address generation circuitry when

CIVEN=0. The bit locations are specified as follows:

Register

Contents

0Ch

0Dh

0Eh

0Fh

FSCI[31:24]

FSCI[23:16]

FSCI[15:8]

FSCI[7:0]

When the CH7010 is used in the master clock mode, the tables below should be used to set the FSCI registers. When

using these values, the CIVEN bit in register 10h should be set to ‘0’, and the CFRB bit in register 02h should be set to

‘1’.

Table 17. FSCI Values (525-Line TV-Out Modes)

Mode

NTSC

PAL-M

“Normal Dot Crawl”

763,363,328

623,153,737

574,429,782

463,962,517

646,233,505

521,957,831

452,363,454

623,153,737

545,259,520

508,908,885

553,914,433

484,675,129

452,363,454

469,762,048

428,554,851

391,468,373

526,457,468

467,962,193

418,281,276

569,408,543

“No Dot Crawl”

763,366,524

623,156,346

574,432,187

463,964,459

646,236,211

521,960,019

452,365,347

623,156,346

545,261,803

508,911,016

553,916,752

484,677,158

452,365,347

469,764,015

428,556,645

391,470,012

526,459,671

467,964,152

418,283,027

569,410,927

“Normal Dot Crawl”

762,524,467

622,468,953

573,798,541

463,452,668

645,523,358

521,384,251

451,866,351

622,468,953

544,660,334

508,349,645

553,305,736

484,142,519

451,866,351

469,245,826

428,083,911

391,038,188

525,878,943

467,447,949

417,821,626

568,782,819

2

3

6

7

10

11

12

16

17

18

19

20

21

28

29

30

34

35

36

38

201-0000-038 Rev 3.1, 11/4/2004

33

CHRONTEL

CH7010B

Table 18. FSCI Values (625-Line TV-Out Modes)

Mode

PAL

PAL-Nc (Argentina)

“Normal Dot Crawl”

806,021,060

644,816,848

601,829,058

470,178,951

677,057,690

537,347,373

806,021,060

644,816,848

537,347,373

690,875,194

564,214,742

483,612,636

645,499,916

528,951,320

453,386,846

621,787,675

544,064,215

483,612,636

705,268,427

“Normal Dot Crawl”

651,209,077

520,967,262

486,236,111

379,871,962

547,015,625

434,139,385

651,209,077

520,967,262

434,139,385

558,179,209

455,846,354

390,725,446

521,519,134

427,355,957

366,305,106

502,361,288

439,566,127

390,725,446

569,807,942

0

1

4

5

8

9

13

14

15

22

23

24

25

26

27

31

32

33

37

CIV Control Register

Symbol:

Address:

Bits:

CIVC

10h

6

BIT

7

6

5

CIV25

R/W

0

4

CIV24

R/W

0

3

CIVC1

R/W

0

2

1

0

CIVEN

R/W

SYMBOL

TYPE

CIVC0

R/W

0

PALN

R/W

0

DEFAULT

1

Bit 0 of register CIVC controls whether the FSCI value is used to set the sub-carrier frequency, or the automatically

calculated (CIV) value. When the CIVEN value is 1, the number calculated and present at the CIV registers will

automatically be used as the increment value for sub-carrier generation. Whenever this bit is set to 1, the CFRB bit should

be set to 0. It is recommended to use the FSCI registers, and not the CIVEN mode for Macrovision applications.

Bit 1 of register CIVC forces the CIV algorithm to generate the PAL-Nc (Argentina) sub-carrier frequency when it is set

to ‘1’. When this bit is set to ‘0’, the VOS[1:0] value is used by the CIV algorithm to determine which sub-carrier

frequency to generate.

Bits 3-2 of register CIVC control the hysteresis circuit which is used to calculate the CIV value. The default value should

be used.

Bits 5-4 of register CIVC contain the MSB values for the calculated increment value (CIV) readout. This is described in

detail in the CIV register description.

34

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

Calculated Increment Value Register

Symbol:

Address:

CIV

11h –

13h

Bits:

8 each

BIT

7

CIV#

R

6

CIV#

R

5

CIV#

R

4

CIV#

R

3

CIV#

R

2

1

0

CIV#

R

SYMBOL

TYPE

CIV#

R

CIV#

R

DEFAULT

X

Registers CIV contain the value that was calculated by the CH7010 as the sub-carrier increment value. The entire bit

field, CIV[25:0], is comprised of these three registers plus the MSB values contained in the CIV Control register, bits

CIV25 and CIV24. This value is used when the CIVEN bit is set to ‘1’. The bit locations are specified below. CIV

registers are Read Only.

Register Contents

10hCIV[25:24]

11hCIV[23:16]

12hCIV[15:8]

13hCIV[7:0]

Clock Mode Register

Symbol:

Address:

Bits:

CM

1Ch

4

BIT

7

6

5

4

3

M/S*

R/W

0

2

1

PCM

R/W

0

XCM

R/W

0

SYMBOL

TYPE

MCP

R/W

0

DEFAULT

Bit 0 of register CM signifies the XCLK frequency. A value of ‘0’ is used when the XCLK is at the pixel frequency (dual

edge clocking mode) and a value of ‘1’ is used when the XCLK is twice the pixel frequency (single edge clocking mode).

Bit 1 of register CM controls the P-OUT clock frequency. A value of ‘0’ generates a clock output at the pixel frequency,

while a value of ‘1’ generates a clock at twice the pixel frequency.

Bit 2 of register CM controls the phase of the XCLK clock input to the CH7010. A value of ‘1’ inverts the XCLK signal

at the input of the device. This control is used to select which edge of the XCLK signal to use for latching input data.

Bit 3 of register CM controls whether the device operates in master or slave clock mode. In master mode (M/S* = ‘1’),

the 14.31818MHz clock is used as a frequency reference in the TV PLL, and the M and N values are used to determine the

TV PLL’s operating frequency. In slave mode (M/S* = ‘0’) the XCLK input is used as a reference to the TV PLL. The M

and N TV PLL divider values are forced to one.

201-0000-038 Rev 3.1, 11/4/2004

35

CHRONTEL

CH7010B

Input Clock Register

Symbol:

Address:

Bits:

IC

1Dh

4

BIT

7

6

5

4

3

2

1

0

SYMBOL

Reserved Reserved Reserved Reserved XCMD3 XCMD2 XCMD1 XCMD0

TYPE

DEFAULT

R/W

1

R/W

0

R/W

0

R/W

0

R/W

1

R/W

0

R/W

0

R/W

0

Bits 3-0 of register IC controls the delay applied to the XCLK signal before latching input data D[11:0] per the following

table.

Table 19. Delay applied to XCLK before latching input data D[11:0]

XCMD3

XCMD2

XCMD1

XCMD0

Adjust phase of Clock relative to Data

0 * t_STEP, XCLK ahead of Data

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1 * t_STEP, XCLK ahead of Data

2 * t_STEP, XCLK ahead of Data

3 * t_STEP, XCLK ahead of Data

4 * t_STEP, XCLK ahead of Data

5 * t_STEP, XCLK ahead of Data

6 * t_STEP, XCLK ahead of Data

7 * t_STEP, XCLK ahead of Data

0 * t_STEP, XCLK behind Data

1 * t_STEP, XCLK behind Data

2 * t_STEP, XCLK behind Data

3 * t_STEP, XCLK behind Data

4 * t_STEP, XCLK behind Data

5 * t_STEP, XCLK behind Data

6 * t_STEP, XCLK behind Data

7 * t_STEP, XCLK behind Data

GPIO Control Register

Symbol:

Address:

Bits:

GPIO

1Eh

8

BIT

7

6

5

4

3

HPIR

R/W

0

2

1

0

SYMBOL

GOENB1 GOENB0 GPIOL1 GPIOL0

HPIE POUTE

POUTP

R/W

0

TYPE

DEFAULT

R/W

1

R/W

1

R/W

0

R/W

0

R/W

0

R/W

0

Bit 0 of register GPIO controls the polarity of the P-OUT signal. A value of ‘0’ does not invert the clock at the output pad.

Bit 1 of register GPIO enables the P-OUT signal. A value of ‘1’ drives the P-OUT clock signal out of the

P-OUT / TLDET* pin. A value of ‘0’ disables the P-OUT signal.

36

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

Bit 2 of register GPIO enables the hot plug interrupt detection signal to be output from the P-OUT pin. A value of ‘1’

allows the hot plug detect circuit to pull the P-OUT / TLDET* pin low when a change of state has taken place on the hot

plug detect pin. A value of ‘0’ disables the interrupt signal. The two control bits HPIE and POUTE should not be enabled

(set to ‘1’) at the same time.

Bit 3 of register GPIO resets the hot plug detection circuitry. A value of ‘1’ causes the CH7010 to release the

P-OUT / TLDET* pin. When a hot plug interrupt is asserted by the CH7010 (P-OUT / TLDET*) the CH7010 driver

should read register 20h to determine the state of the DVI termination. After having read this register, the HPIR bit should

be set high to reset the circuitry, and then set low again.

Bits 5-4 of register GPIO control the GPIO pins. When the corresponding GOENB bits are low, these register values are

driven out of the corresponding GPIO pins. When the corresponding GOENB bits are high, these register values can be

read to determine the level forced into the corresponding GPIO pins.

Bits 7-6 of register GPIO control the direction of the GPIO pins. A value of ‘1’ sets the corresponding GPIO pin to an

input, and a value of ‘0’ sets the corresponding pin to an output.

201-0000-038 Rev 3.1, 11/4/2004

37

CHRONTEL

CH7010B

Input Data Format Register

Symbol:

Address:

Bits:

IDF

1Fh

8

BIT

7

6

5

SYO

R/W

0

4

VSP

R/W

0

3

HSP

R/W

0

2

1

0

IDF0

R/W

0

SYMBOL

IBS

R/W

0

DES

R/W

0

IDF2

R/W

0

IDF1

R/W

0

TYPE

DEFAULT

Bits 2-0 of register IDF select the input data format. See Input Interface on page 10 for a listing of available formats.

Bit 3 of register IDF controls the horizontal sync polarity. A value of ‘0’ defines the horizontal sync to be active low, and

a value of ‘1’ defines the horizontal sync to be active high.

Bit 4 of register IDF controls the vertical sync polarity. A value of ‘0’ defines the vertical sync to be active low, and a

value of ‘1’ defines the vertical sync to be active high.

Bit 5 of register IDF controls the sync direction. A value of ‘0’ defines sync to be input to the CH7010, and a value of ‘1’

defines sync to be output from the CH7010. The CH7010 can only output sync signals when operating as a VGA to TV

encoder, not when operating as a DVI transmitter.

Bit 6 of register IDF signifies when the CH7010 is to decode embedded sync signals present in the input data stream

instead of using the H and V pins. This feature is only available for input data format four. A value of ‘0’ selects the H

and V pins to be used as the sync inputs, and a value of ‘1’ selects the embedded sync signal.

Bit 7 of register IDF selects the input buffer used for the data, sync and clock input pins.

Connection Detect Register

Symbol:

Address:

Bits:

CD

20h

6

BIT

7

6

5

4

3

2

1

0

SENSE

R/W

SYMBOL

HPIE2 Reserved

DVIT DACT3 DACT2 DACT1 DACT0

TYPE

DEFAULT

R/W

0

R/W

0

R

0

R

X

R

X

R

X

R

X

0

The Connection Detect Register provides a means to sense the connection of a TV to the four DAC outputs, and to

determine the status of the DVI hot plug detect pin. The status bits, DACT[3:0] correspond to the termination of the four

DAC outputs. However, the values contained in these STATUS BITS ARE NOT VALID until a sensing procedure is

performed. Use of this register requires a sequence of events to enable the sensing of outputs, then reading out the

applicable status bits. The detection sequence works as follows:

1) Set the power management register to enable all DAC’s.

2) Set the SENSE bit to a 1. This forces a constant output from the DAC’s. Note that during SENSE = 1, these 4 analog

outputs are at steady state and no TV synchronization pulses are asserted.

3) Reset the SENSE bit to 0. This triggers a comparison between the voltage present on these analog outputs and the

reference value. During this step, each of the four status bits corresponding to individual DAC outputs will be set if they

are CONNECTED.

4) Read the status bits. The status bits, DACT[3:0] now contain valid information which can be read to determine which

outputs are connected to a TV. Again, a “1” indicates a valid connection, a “0” indicates an unconnected output.

Bit 5 of register CD can be read at any time to determine the level of the hot plug detect pin. When the hot plug detect pin

changes state, and the DVI output is selected, the P-OUT / TLDET* output pin will be pulled low signifying a change in

the DVI termination. At this point, the HPIR bit in register 1Eh should be set high, then low to reset the hot plug detect

circuit.

38

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

Bit 6 of register CD contains the MSB value for the crystal oscillator adjustment. This control is described in detail in the

DC register description (register 21h).

Bit 7 of register CD enables the hot plug interrupt detection signal output from the GPIO[1] pin. A value of ‘1’ allows the

hot plug detect circuit to pull the GPIO[1] / TLDET* pin low when a change of state has taken place on the hot plug detect

pin. A value of ‘0’ disables the interrupt signal. The GOENB1 control bit in register 1Eh should be set to ‘1’ when

HPIE2 is set to ‘1’.

DAC Control Register

Symbol:

Address:

Bits:

DC

21h

6

BIT

7

6

5

4

3

2

1

0

SYMBOL

XOSC1 XOSC0

SYNCO1 SYNCO0 DACG1 DACG0

DACBP

R/W

0

TYPE

DEFAULT

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit 0 of register DC selects the DAC bypass mode. A value of ‘1’ outputs the incoming data directly at the DAC[2:0]

outputs.

Bits 2-1 of register DC control the DAC gain. DACG0 should be set low for NTSC and PAL-M video standards, and high

for PAL and NTSC-J video standards. DACG1 should be low when the input data format is RGB (IDF = 0-3), and high

when the input data format is YCrCb (IDF = 4).

Bits 4-3 of register DC select the signal to be output from the C/H Sync pin according to Table 20 below.

Table 20. Composite / Horizontal Sync Output

SYNCO[1:0]

C/H Sync Output

No Output

00

01

10

11

VGA Horizontal Sync

TV Composite Sync

TV Horizontal Sync

Bits 7-6 of register DC controls the crystal oscillator. The default value is recommended.

Buffered Clock Output Register

Symbol:

Address:

Bits:

BCO

22h

8

BIT

7

SHF2

R/W

0

6

SHF1

R/W

0

5

4

3

BCOP

R/W

0

2

1

0

SYMBOL

TYPE

SHF0 BCOEN

BCO2

R/W

0

BCO1

R/W

0

BCO0

R/W

0

R/W

0

R/W

0

DEFAULT

Bits 2-0 of register BCO select the signal output at the BCO pin, according to Table 21 below:

Table 21. BCO Output Signal

BCO[2:0]

000

Buffered Clock Output

The 14MHz crystal

(for test use only)

VCO divided by K3

Field ID

BCO[2:0]

100

Buffered Clock Output

(for test use only)

VGA Vertical Sync

TV Vertical Sync

001

101

010

110

011

111

201-0000-038 Rev 3.1, 11/4/2004

39

CHRONTEL

CH7010B

Bit 3 of register BCO selects the polarity of the BCO output. A value of ‘1’ does not invert the signal at the output pad.

Bit 4 of register BCO enables the BCO output. When BCOEN is high, the BCO pin will output the selected signal. When

BCOEN is low, the BCO pin will be held in tri-state mode.

Bits 7-5 of register BCO select the K3 divider, according to Table 22 below.

Table 22. K3 Selection

SHF[2:0]

000

K3

2.5

3.0

3.5

4.0

4.5

5.0

6.0

7.0

001

010

011

100

101

110

111

Termination Register

Symbol:

Address:

Bits:

TERM

23h

1

BIT

7

6

5

4

3

2

1

0

SYMBOL

Reserved Reserved Reserved Reserved Reserved

HPDD Reserved Reserved

TYPE

DEFAULT

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

HPDD (bit 2) of register TERM disables the hardware hot plug detection function. This function

(default on) tri-states the DVI outputs when the hot plug detect pin (HPDET) is pulled low in accor-

dance with the DVI specification, revision 1.0. This function is independent of the hot plug interrupt

function (HPIE, register 1Eh, bit 2 and HPIE2, register 20h, bit 7) controlled via the SPP interface.

HPDD = 0 => hardware hot plug interrupt is enabled

= 1 => hardware hot plug interrupt is disabled

DVI Control Input Register

Symbol:

Address:

Bits:

TCTL

31h

8

BIT

7

6

5

4

3

CTL3

R/W

0

2

1

0

SYMBOL

TPPD3 TPPD 2 TPPD 1 TPPD 0

CTL2

R/W

0

CTL1

R/W

0

CTL0

R/W

0

TYPE

DEFAULT

R/W

1

R/W

0

R/W

0

R/W

0

Bits 3-0 of register TCTL set the DVI control inputs applied to the green and red channels during sync intervals. It is

recommended to leave these controls at the default value.

Bits 7-4 of register TCTL control the DVI PLL phase detector. The default value is recommended.

DVI PLL VCO Control Register

Symbol:

Address:

TVCO

32h

40

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

Bits:

8

BIT

7

6

5

4

3

2

1

0

SYMBOL

TPVCO7 TPVCO6 TPVCO5 TPVCO4 TPVCO3 TPVCO2 TPVCO1 TPVCO0

TYPE

DEFAULT

R/W

1

R/W

0

R/W

1

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Register TVCO controls the state of the DVI PLL VCO, and should be set according to Table 23.

DVI PLL Charge Pump Control Register

Symbol:

Address:

Bits:

TPCP

33h

7

BIT

7

6

5

4

3

2

1

0

SYMBOL

TYPE

DVID2 DVID1 DVID0 Reserved TPPSD1 TPPSD0

TPCP1

R/W

0

TPCP0

R/W

0

R/W

1

R/W

1

R/W

1

R/W

0

R/W

0

R/W

1

DEFAULT

Bits 1-0 of register TPCP control the DVI PLL charge pump. The default value shown on Table 23 is recommended.

Bits 3-2 of register TPCP control the DVI PLL post scale divider. (see Table 23).

Bits 7-5 of register TPCP control the DVI transmitter output drive level. The default value shown on Table 23 is

recommended.

DVI PLL Divider Register

Symbol:

Address:

Bits:

TPD

34h

6

BIT

7

6

5

4

3

2

1

0

SYMBOL

Reserved Reserved TPFFD1 TPFFD0 TPFBD3 TPFBD2 TPFBD1 TPFBD0

TYPE

DEFAULT

R/W

0

R/W

0

R/W

0

R/W

1

R/W

0

R/W

1

R/W

1

R/W

0

Bits 3-0 of register TPD control the DVI PLL feedback divider. (see table 22).

Bits 5-4 of register TPD control the DVI PLL feed forward divider. (see table 22).

DVI PLL Supply Control Register

Symbol:

Address:

Bits:

TPVT

35h

6

BIT

7

6

5

4

3

2

1

0

SYMBOL

TYPE

Reserved Reserved TPVT5 TPVT4 TPVT3 TPVT2 TPVT1

TPVT0

R/W

0

R/W

0

R/W

0

R/W

1

R/W

1

R/W

0

R/W

0

R/W

0

DEFAULT

Bits 5-0 of register TPVT control the DVI PLL supply voltage. (see Table 22).

201-0000-038 Rev 3.1, 11/4/2004

41

CHRONTEL

CH7010B

Bits 7-6 of register TPVT are reserved bits, and should be left at the default value.

Please see Table 23 for the default values in terms of the frequency ranges.

42

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

DVI PLL Filter Register

Symbol:

Address:

Bits:

TLPF

36h

4

BIT

7

6

5

4

3

2

1

0

SYMBOL

TPLPF3 TPLPF2 TPLPF1 TPLPF0 Reserved Reserved Reserved Reserved

TYPE

DEFAULT

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bits 3-0 of register TPT are reserved bits, and should be left at the default value.

Bits 7-4 of register TPT control the DVI PLL low pass filter. The default value is recommended.

DVI PLL VCO Control Overflow Register

Symbol:

Address:

Bits:

TCT

37h

3

BIT

7

6

5

4

3

2

1

0

SYMBOL

TYPE

TPVCO10 TPVCO9 TPVCO8 Reserved Reserved Reserved Reserved Reserved

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

DEFAULT

Bits 4-0 of register TCT are reserved bits, and should be left at the default value.

Bits 7-5 of register TCT contain the MSB values for the DVI PLL VCO control. (see Table 22).

Table 23. The Registers Default Settings In Terms Of The Frequency Ranges

Register

50MHz +/- 25MHz

100MHz +/- 25MHz 140MHz +/- 25MHz

31h

32h

33h

34h

35h

36h

37h

TCTL

TVCO

TPCP

TPD

0x00

0x23

0x08

0x16

0x30

0x60

0x00

0x23

0x04

0x26

0x30

0x60

0x00

0x2D

0x07

0x26

0x30

0xE0

0x00

TPVT

TPF

TVCOO

201-0000-038 Rev 3.1, 11/4/2004

43

CHRONTEL

CH7010B

Reset Register

Symbol:

Address:

Bits:

RES

48h

2

BIT

7

6

5

4

3

2

1

0

Reserved Reserved Reserved

SYMBOL

TYPE

ResetIB ResetDB Reserved Reserved Reserved

R/W

0

R/W

0

R/W

0

R/W

1

R/W

1

R/W

0

R/W

0

R/W

0

DEFAULT

Bit 3 of register RES controls the datapath reset signal. A value of ‘0’ holds the datapath in a reset condition, while a

value of ‘1’, places the datapath in normal mode. The datapath is also reset at power on by an internally generated power

on reset signal.

Bit 4 of register RES resets all control registers (addresses page 0:00h - 7Fh and page 1:00h - 61h). A value of ‘0’ holds

the serial port registers in a reset condition, while a value of ‘1’, places the serial port registers in normal mode. The serial

port registers are also reset at power on by an internally generated power on reset signal.

Power Management Register

Symbol:

Address:

Bits:

PM

49h

8

BIT

SYMBOL DVIP

TYPE R/W

DEFAULT 0

7

6

5

4

3

2

1

0

DVIL

R/W

0

TV

R/W

0

DACPD3 DACPD2 DACPD1 DACPD0 FPD

R/W

0

R/W

0

R/W

0

R/W

0

R/W

1

FPD (bit0) of register PM controls power down of the entire chip except the serial port.

DACPD[3:0] (bits 4-1) of register PM control DAC0 through DAC3 Power Down. DAC0 through DAC3 will be turned

on only if FPD bit is set to ’0’. If FPD bit is set to ’1’, then DAC0 through DAC3 will be in power down state regardless

of DACPD0 through DACPD3 state.

TV (bit 5) of the PM register enables the TV path.

DVIP and DVIL (bits 7-6) of the PM register controls the DVI path.

Register PM controls which circuitry within the CH7010 is operating, according to Table 24 below.

Table 24. Power Management

DVIP DVIL TV

DACPD[3:0] FPD Operating State

Functional Description

X

1

1001

0111or

1110

0

Composite Off, S-video on Composite DACs are off

Composite On/S-video off S-Video DACs are off

Either pin 39 CVBS/B or pin 36

CVBS can be used for composite out

X

1

X

1

0000

XXXX

0

Normal (On)

VGA to TV Encoder Off

DVI Encode, Serialize,

Both composite and s-video are on

TV off

0

X

DVI is in normal function

Transmitter, and PLL on

Full Power Down

X

XXXX

1

All circuitry is powered down except

serial port

44

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

Version ID Register

Symbol:

Address:

Bits:

VID

4Ah

8

BIT

7

6

VID6

R

5

VID5

R

4

VID4

R

3

VID3

R

2

1

0

VID0

R

SYMBOL

TYPE

VID7

VID2

VID1

R

0

R

1

R

0

DEFAULT

0

1

Register VID is a read only register containing the version ID number of the CH7010.

Device ID Register

Symbol:

Address:

Bits:

DID

4Bh

8

BIT

7

DID7

R

6

DID6

R

5

DID5

R

4

DID4

R

3

DID3

R

2

1

0

DID0

R

SYMBOL

TYPE

DID2

DID1

R

1

R

1

DEFAULT

0

1

0

Register DID is a read only register containing the device ID number of the CH7010.

201-0000-038 Rev 3.1, 11/4/2004

45

CHRONTEL

CH7010B

7. ELECTRICAL SPECIFICATIONS

Table 25. Absolute Maximum Ratings

Symbol

Description

Min

- 0.5

Typ

Max

Units

DVDD, AVDD, TVDD, VDD relative to GND

5.0

V

1

Input voltage of all digital pins

GND - 0.5

VDD + 0.5

V

Sec

°C

T_SC

T_AMB

TSTOR

TJ

Analog output short circuit duration

Ambient operating temperature

Storage temperature

Indefinite

0

85

- 65

150

260

245

225

Junction temperature

TVPS

Vapor phase soldering (5 seconds)

Vapor phase soldering (11 seconds)

Vapor phase soldering (60 seconds)

Notes:

1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These

are stress ratings only. Functional operation of the device at these or any other conditions above those indicated under

the normal operating condition of this specification is not recommended. Exposure to absolute maximum rating

conditions for extended periods may affect reliability. The temperature requirements of vapor phase soldering apply to

all standard and lead free parts.

2. The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive device.

Voltage on any signal pin that exceeds the power supply voltages by more than ± 0.5V can induce destructive latch.

Table 26. Recommended Operating Conditions

Symbol

VDD

AVDD

Description

DAC power supply voltage

Analog supply voltage

Digital supply voltage

Min

3.1

Typ

3.3

Max

3.6

Units

V

3.6

DVDD,

TVDD

Digital supply voltage (P-OUT pin)

Output load to DAC outputs

1.1

1.8

37.5

3.6

DVDDV

RL

V

Ω

o

Table 27. Electrical Characteristics (Operating Conditions: T = 0 C - 70 C, VDD, AVDD,

A

DVDD, TVDD = 3.3V ± 5%)

Symbol

Description

Video D/A resolution

Full scale output current

Video level error

4 DAC’s Enabled

3 DAC’s Enabled

DVI PLL Disabled

DVI PLL Enabled (85 MHz Pixel Clock)

TV-Out Enabled, DVI Disabled

TV-Out Disbled, DVI Enabled (85 MHz Pixel Clock)

Pixel Clock = 85 MHz

Min

10

Typ

10

33.9

Max

10

Units

Bits

mA

%

mA

10

145

110

7

22

150

70

I_VDD

130

100

5

17

85

50

70

4

I_AVDD

I_DVDD

I_TVDD

90

DVDDV (1.8V) curent (15pF load)

46

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

Table 28. DC Specifications

Symbol

Description

Test Condition

Min

Typ

Max

Unit

SPD (serial port data) Output

Low Voltage

I

= 2.0 mA

0.4

DVDD + 0.5

1.4

V

V_SDOL

OL

Serial Port (SPC, SPD) Input

High Voltage

2.7

V

V_SPIH

V_SPIL

Serial Port (SPC, SPD) Input

Low Voltage

GND-0.5

D[0-11] Input High Voltage

D[0-11] Input Low Voltage

Vref+0.25

GND-0.5

2.7

DVDD + 0.5

Vref-0.25

V

V_DATAIH

V_DATAIL

V_MISCIH

GPIOx, AS, RESET*, HPDET

Input High Voltage

GPIO, AS, RESET*, HPDET

Input Low Voltage

DVDD=3.3V

DVDD + 0.5

GND-0.5

0.5

0.6

5

V

V_MISCIL

I_MISCPU

I_MISCPD

Pull Up Current

V

I

= 0V

uA

IN

(GPIO, AS, RESET*)

Pull Down Current

(HPDET)

= 3.3V

0.5

5

IN

GPIO, C/HSYNC, BCO, H, V

Output High Voltage

= -400 uA

= 3.2mA

DVDD-0.2

V

V_MISCAOH

V_MISCAOL

V_MISCBOH

OH

OL

OH

GPIO, C/HSYNC, BCO, H, V

Output Low Voltage

I

0.2

P-OUT

= - 400 uA

DVDDV-0.2

Output High Voltage

P-OUT

I

= 3.2 mA

0.2

V

V_MISCBOL

V_H

OL

Output Low Voltage

DVI Single Ended Output

High voltage

TVDD = 3.3V +/- 5%

TVDD - 0.01

TVDD + 0.01

R

50 ohm +/- 1%

TERM

DVI Single Ended Output Low

Voltage

TVDD - 0.6

400

TVDD - 0.4

600

V

mVp-p

V

R

2400 ohm +/- 1%

V_L

SWING

DVI Single Ended Output Swing

Voltage

V_SWING

V_OFF

DVI Single Ended Standby Out-

put Voltage

TVDD - 0.01

TVDD + 0.01

Note:

V

_DATA- refers to all digital data (D[11:0]), clock (XCLK, XCLK*), sync (H, V) and DE inputs. V_MISCA- refers to GPIOx, RESET*, AS and

HPDET inputs and GPIOx, BCO/VSYNC, CHSYNC and H, V when configured as outputs (SYO=1). V_MISCB- refers to P-OUT.

201-0000-038 Rev 3.1, 11/4/2004

47

CHRONTEL

CH7010B

Table 29: AC Specifications

Symbol

f_XCLK

Description

Test Condition

Min

Typ

Max

Unit

Input (XCLK) frequency

25

165

MHz

Pixel time period

6.06

30

40

ns

%

t_PIXEL

DC_XCLK

t_XJIT

Input (XCLK) Duty Cycle

XCLK clock jitter tolerance

T

f

+ T < 1.2ns

70

S

H

= 75MHz

2

ns

ps

XCLK

DVI Output Rise Time

(20% - 80%)

f

= 165MHz

75

242

t_DVIR

XCLK

DVI Output Fall Time

(20% - 80%)

f

= 165MHz

ps

t_DVIF

XCLK

DVI Output intra-pair skew

f

= 165MHz

90

1.2

150

ps

ns

ps

ns

t_SKDIFF

t_SKCC

t_DVIJIT

t_S

XCLK

DVI Output inter-pair skew

DVI Output Clock Jitter

Setup Time: D[11:0], H, V and DE

to XCLK, XCLK*

XCLK = XCLK* to

D[11:0], H, V, DE =

Vref

0.5

Hold Time: D[11:0], H, V and DE

to XCLK, XCLK*

D[11:0], H, V, DE =

Vref to XCLK =

XCLK*

ns

t_H

t_R

Pout, H and V (when configured

as outputs)

15pF load

1.50

80

VDDV = 3.3V

Output Rise Time

(20% - 80%)

Pout, H and V (when configured

as outputs)

15pF load

ns

ps

t_F

VDDV = 3.3V

Output Fall Time

(20% - 80%)

De-skew time increment

50

t_STEP

48

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

8. TIMING INFORMATION

8.1 Clock - Master, Sync - Master Mode

V_OH

P-OUT

V_OL

t_F

t_R

t3

H

V_OH

64 PIXELS

V_OL

V

V_OH

1 VGA

Line

V_OL

t_R

t_F

t1

V _IH

XCLK

V _IL

V _IH

XCLK*

V _IL

t_H

t_S

P0b

V _IH

D[11:0]

P0a

P1a

P1b P2a

P2b

t2

V _IL

V _IH

DE

V _IL

t_S

Figure 18: Timing for Clock - Master, Sync - Master Mode

Table 30. Timing and Voltage Levels for Clock - Master, Sync - Master Mode

Symbol

Parameter

Min

Typ

see Table 29

1

Max

Unit

t_S

t_H

t_R

t_F

t1

t2

t3

Setup Time: D[11:0], H, V and DE to XCLK, XCLK*

Hold Time: D[11:0], H, V and DE to XCLK, XCLK*

Pout, H, V (when configured as outputs) Output Rise Time

Pout, H, V (when configured as outputs) Output Fall Time

XCLK & XCLK* rise/fall time w/15pF load

ns

D[11:0] & DE rise/fall time w/15pF load

1

Hold time:

1.5

P-OUT to HSYNC, VSYNC delay

201-0000-038 Rev 3.1, 11/4/2004

49

CHRONTEL

CH7010B

8.2 Clock - Slave, Sync - Slave Mode

t1

V _IH

XCLK

V _IL

V _IH

XCLK*

V _IL

t_H

t_S

V _IH

D[11:0]

P0a P0b P1a

P1b P2a

P2b

t2

V _IL

t_S

t_H

V _IH

DE

V _IL

t_S

V _IH

H

64 PIXELS

V _IL

V _IH

V

1 VGA

Line

V _IL

t2

Figure 19: Timing for Clock - Slave, Sync - Slave Mode

Table 31: Timing for Clock - Slave, Sync - Slave Mode

Symbol

Parameter

Min

Typ

Max

Unit

t_S

t_H

t1

t2

Setup Time: D[11:0], H, V and DE to XCLK, XCLK*

Hold Time: D[11:0], H, V and DE to XCLK, XCLK*

XCLK & XCLK* rise/fall time w/15pF load

D[11:0], H, V & DE rise/fall time w/ 15pF load

see Table 29

1

ns

50

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

8.3 Clock - Master, Sync - Slave Mode

V_OH

P-OUT

V_OL

t_POUTR

t_POUTF

t1

V_IH

XCLK

V_IL

V_IH

XCLK*

V_IL

t_H

t_S

P0a P0b P1a

V _IH

D[11:0]

P1b P2a

P2b

t2

V _IL

t_S

t_H

V _IH

DE

V _IL

t_S

V _IH

H

64 PIXELS

V _IL

V _IH

V

1 VGA

Line

V _IL

t2

Figure 20: Timing for Clock - Master, Sync - Slave Mode

Table 32. Timing for Clock - Master, Sync - Slave Mode

Symbol Parameter

Min

Typ

see Table 29

1

Max

Unit

t_S

t_H

t_R

t_F

t1

t2

Setup Time: D[11:0], H, V and DE to XCLK, XCLK*

Hold Time: D[11:0], H, V and DE to XCLK, XCLK*

Pout Output Rise Time

Pout Output Fall Time

XCLK & XCLK* rise/fall time w/15pF load

D[11:0], H, V & DE rise/fall time w/15pF load

ns

1

201-0000-038 Rev 3.1, 11/4/2004

51

CHRONTEL

CH7010B

9. PACKAGE DIMENSIONS

64-pin LQFP

A

B

I

1

A

B

H

C

D

J

LEAD

CO-PLANARITY

F

E

.004 “

G

Table of Dimensions

No. of Leads

SYMBOL

A

B

C

D

E

F

G

H

I

J

64 (10 X 10 mm)

MIN

MAX

11.80

12.20

0.17

0.27

1.35

1.45

0.05

0.15

0.45

0.75

0.09

0.20

0°

7°

Milli-

0.50

1.00

meters

10.00

Notes:

1. Conforms to JEDEC standard JESD-30 MS-026D.

2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm.

3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side.

52

201-0000-038 Rev 3.1, 11/4/2004

CHRONTEL

CH7010B

10. REVISION HISTORY

Rev. #

1.0

3.0

Date

11/01/01

09/06/02

Section

All

Description

First official release of CH7010A datasheet, rev. 1.0

CH7010A changed to CH7010B

Pin description of table 1 updated.

Table 28 added into datasheet.

Register map updated.

3.2

Register Map

All

Default bit values and public bits changed on various registers. 02h,

0Bh, 23h, 31h, 32h, 33h, 34h, 35h, 36h, 37h, 38h.

7

8

Electrical Specifications changed: AC specifications added.

Timing information tables updated.

7/12/04

Section 5.4

Updated DVI hotplug description

201-0000-038 Rev 3.1, 11/4/2004

53

CHRONTEL

Disclaimer

This document provides technical information for the user. Chrontel reserves the right to make changes at any time with-

out notice to improve and supply the best possible product and is not responsible and does not assume any liability for

misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products

and assume no liability for errors contained in this document. The customer should make sure that they have the most

recent data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe

upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to

infringe upon such rights.

Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT

SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF

Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as

directed can reasonably expect to result in personal injury or death.

ORDERING INFORMATION

Part number

CH7010B-T

Package type

Number of pins

Voltage supply

3.3V

LQFP

64

CH7010B-T-TR LQFP in Tape & Reel

3.3V

CH7010B-TF

Lead free LQFP

3.3V

CH7010B-TF-TR

Lead free LQFP

in Tape & Reel

3.3V

Chrontel

2210 O’Toole Avenue, Suite 100,

San Jose, CA 95131-1326

Tel: (408) 383-9328

Fax: (408) 383-9338

www.chrontel.com

E-mail: sales@chrontel.com

Printed in the U.S.A.

54

201-0000-038 Rev 3.1, 11/4/2004


型号：	CH7010B-T-TR
厂家：	CHRONTEL, INC
描述：	Color Signal Encoder, CMOS, PQFP64, 10 X 10 MM, MS-026D, LQFP-64 编码器商用集成电路
文件：	总54页 (文件大小：1366K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CH7010B-T-TR [CHRONTEL]

相关型号：

CH7010B-TF

CH7010B-TF-TR

CH7010UH+/-10%B

CH7010UH+/-10%V

CH7010UH10%V

CH7011A-T

CH7011A-TF-TR

CH7012

CH70120UH+/-10%B

CH70120UH+/-10%V

CH70120UH10%B

CH70120UH10%V