CH7019B-TF [CHRONTEL]
Color Signal Encoder, PQFP128, LEAD FREE, MS-026D, LQFP-128;型号: | CH7019B-TF |
厂家: | CHRONTEL, INC |
描述: | Color Signal Encoder, PQFP128, LEAD FREE, MS-026D, LQFP-128 编码器 商用集成电路 |
文件: | 总79页 (文件大小:844K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CH7019B
Chrontel
CH7019 TV Encoder / LVDS Transmitter
Features
TV-Out:
General Description
The CH7019 is a Display Controller device which accepts two
digital graphics input data streams. One data stream outputs
through an LVDS transmitter to an LCD panel, while the other
data stream is encoded for NTSC or PAL TV and outputs
through a 10-bit high speed DAC. The TV encoder device
encodes a graphics signal up to 1024x768 resolution and
outputs the video signals according to NTSC or PAL standards.
The LVDS transmitter operates at pixel speeds up to 165MHz
per link, supporting 1600x1200 panels at 60Hz refresh rate.
• VGA to TV conversion supporting up to 1024x768
• Macrovision™ 7.1.L1 copy protection support
• Two variable-voltage digital input ports.
• Simultaneous LVDS and TV output.
• True scale rendering engine supports under-scan in all
TV output resolutions †¥
• Enhanced text sharpness and adaptive flicker removal
with up to 7 lines of filtering ¥
• Support for NTSC and PAL TV formats
• Outputs CVBS, S-Video, RGB and YPrPb
• Support for SCART connector
The device can also accept one graphics data stream over two
12-bit wide variable voltage ports which support nine different
data formats including RGB and YCrCb (RGB must be used
for LVDS output). A maximum of 330M pixels per second can
be output through dual LVDS links.
• TV / Monitor connection detect
• Output video switch for easy wiring to connectors
LVDS-Out:
• Single / Dual LVDS transmitter
• Dual LVDS supports pixel rate up to 330Mpixels/sec.
when both 12-bit input ports are ganged together
• LVDS low jitter PLL accepts emission reduction input
• LVDS 18-bit output
• 2D dither engine
• Panel protection and power down sequencing
• Programmable power management
The TV-Out processor will perform non-interlaced to interlaced
conversion with scaling, flicker filtering, and encoding into any
of the NTSC or PAL video standards. The scaler and flicker
filter are adaptive and programmable for superior text display.
Eight graphics resolutions are supported up to 1024 by 768
with full vertical and horizontal under-scan capability in all
modes. A high accuracy low jitter phase locked loop is
integrated to create outstanding video quality. Support is
provided for MacrovisionTM. In addition to TV encoder modes,
bypass modes are included which allow the TV DACs to be
used as a second CRT DAC.
• Support for second CRT DAC bypass mode
• Four 10-bit video DAC outputs
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Variable voltage interface to graphics device
• Offered in a 128-pin LQFP package
The LVDS transmitter includes a programmable dither
function for support of 18-bit panels. Data is encoded into
commonly used formats, including those detailed in the
OpenLDI and the SPWG specifications. Serialized data
outputs on three to six differential channels.
† Patent number 5,781,241
¥ Patent number 5,914,753
Clock,
Data,
Sync
Latch &
Demux
XCLK1,XCLK1*
H1,V1, DE1
TV PLL
P-OUT
2
3
BCO/VSYNC
C/HSYNC
TV Timing
2
FLD1
Four
10-bit
DAC's
Deflicker / Text Enhancement /
Scaling / Scan Conversion /
TV Encode
DACA[3:0]
DACB[3:0]
D1[11:0]
4
12
4
Clock,
Data,
Sync
Latch &
Demux
XCLK2,XCLK2*
H2,V2, DE2
FLD2
2
3
LVDS PLL
LDC[2:0],LDC*[2:0]
LL1C,LL1C*
ENAVDD, ENABKL
LDC[6:4],LDC*[6:4]
LL2C, LL2C*
6
2
2
6
2
LVDS
Transmit
LVDS Encode /
Dither Engine
D2[11:0]
12
Serialize
VREF1
Serial Port Control and Misc. Functions
XTAL
XI/FIN,XO
2
Figure 1: CH7019 Functional Block Diagram
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CHRONTEL
CH7019B
Table of Contents
1.0
1.1
1.2
2.0
2.1
2.2
2.3
2.4
2.5
Pin Assignment__________________________________________________________________________ 3
Package Diagram ______________________________________________________________________ 3
Pin Description ________________________________________________________________________ 4
Overview ______________________________________________________________________________ 7
Input Interface Timing __________________________________________________________________ 7
Input Data Formats ____________________________________________________________________ 10
TV-Out _____________________________________________________________________________ 16
LVDS-Out __________________________________________________________________________ 25
Power Down _________________________________________________________________________ 30
Register Control ________________________________________________________________________ 31
Non-Macrovision Control Registers Index__________________________________________________ 31
Non-Macrovision Control Registers Description _____________________________________________ 34
Non-Macrovision Control Registers Description _____________________________________________ 36
Recommended Settings_________________________________________________________________ 67
Electrical Specifications __________________________________________________________________ 68
Absolute Maximum Ratings _____________________________________________________________ 68
Recommended Operating Conditions______________________________________________________ 68
3.0
3.1
3.2
3.3
3.4
4.0
4.1
4.2
4.3
4.4
4.5
4.6
5.0
6.0
Electrical Characteristics (Operating Conditions: TA = 0°C – 70°C, VDD =3.3V ± 5%)__________ 69
Digital Inputs / Outputs_________________________________________________________________ 70
AC Specifications_____________________________________________________________________ 71
Timing Information ___________________________________________________________________ 72
Package Dimensions_____________________________________________________________________ 77
Revision History________________________________________________________________________ 78
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CHRONTEL
CH7019B
1.0 Pin Assignment
Disclaimer: The information contained in this document is preliminary and subject to change without notice.
Chrontel Inc. bears no responsibility for any errors in this document. Please contact Chrontel Inc. for design reviews
prior to finalize your design.
1.1 Package Diagram
V2
H2
LPLL_VDD
LPLLCAP
LPLL_GND
LGND
LL2C
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
DGND
D2[11]
D2[10]
D2[9]
D2[8]
D2[7]
D2[6]
XCLK2
DGND
XCLK2*
D2[5]
D2[4]
D2[3]
D2[2]
D2[1]
D2[0]
DVDD
DVDD
D1[11]
D1[10]
3
4
5
LL2C*
LVDD
N/C
N/C
LGND
LDC6
LDC6*
LVDD
LDC5
LDC5*
LGND
LDC4
LDC4*
LVDD
LVDD
N/C
N/C
LGND
LL1C
LL1C*
LVDD
LDC2
LDC2*
LGND
LDC1
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Chrontel
CH7019
80 D1[9]
79 D1[8]
78 D1[7]
77 D1[6]
76 XCLK1
75 DGND
74 XCLK1*
73
72
71
70
69
68
67
66
65
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
DGND
H1
LDC1*
LVDD
LDC0
LDC0*
LGND
VSWING
DAC_VDD
ISET
V1
Figure 2: CH7019 128 Pin LQFP Package (Top View)
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CHRONTEL
CH7019B
1.2 Pin Description
Table 1: Pin Description
Pin #
# of Pins Type
Symbol
Description
66, 101
2
2
2
In/Out
In/Out
In
H1, H2
Horizontal Sync Input / Output
When the SYO control bit is low, these pins accept a horizontal sync inputs
for use with the input data. The amplitude will be 0 to VDDV. VREF1 is
the threshold level for these inputs. These pins must be used as inputs in
RGB Bypass mode.
When the SYO control bit is high, the TV encoder will output a horizontal
sync pulse 64 pixels wide to one of these pins. The output is driven from
the DVDD supply. This output is valid only when TV-Out is in operation.
65, 102
V1, V2
Vertical Sync Input / Output
When the SYO control bit is low, these pins accept a vertical sync inputs
for use with the input data. The amplitude will be 0 to VDDV. VREF1
signal is the threshold level. These pins must be used as inputs in RGB
Bypass mode.
When the SYO control bit is high, the TV encoder will output a vertical
sync pulse one line wide to one of these pins. The output is driven from the
DVDD supply. This output is valid only when TV-Out is in operation.
63, 104
DE1, DE2
Data Enable
These pins accept a data enable signal which is high when active video data
is input to the device, and remains low during all other times. The levels
are 0 to VDDV. VREF1 is the threshold level. The TV-Out function uses
H and V sync signals and values in the SAV register as reference to active
video.
62, 105
107
2
1
Out
FLD1,
FLD2
TV Field Signal
These outputs can be programmed to be a TV Field output from the TV
encoder. These outputs are tri-stated upon power up.
In/Out
SPD
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port and can
operate with inputs from VDDV to DVDD. Outputs are driven from 0 to
VREF2.
108
1
In
SPC
Serial Port Clock Input
This pin functions as the clock input of the serial port and can operate with
inputs from VDDV to DVDD.
106
111
1
1
In
In
AS
Address Select (Internal Pull-up)
This pin determines the device address of the serial port.
Reference Voltage 2
VREF2
Used to generate the output supply level for SPD port. This pin should be
tied externally to the maximum voltage seen by the ports. (1.5V to 3.3V).
123-126, 56,
57
6
In/Out
GPIO[5:0]
General Purpose Input / Output [5:0]
These pins provide general purpose I/O and are controlled via the serial
port. (3.3V). See description of GPIO Controls for I/O configuration.
127
128
36
1
1
1
Out
Out
In
ENAVDD
ENABLK
VSWING
Panel Power Enable
Enable panel VDD. (3.3V)
Back Light Enable
Enable Back-Light of LCD Panel. (3.3V)
LVDS Voltage Swing Control
This pin sets the swing level of the LVDS outputs. A 2.4K Ohm resistor
should be connected between this pin and LGND (pin 35) using short and
wide traces.
58
1
In
RESET*
Reset * Input (Internal Pull-up)
When this pin is low, the device is held in the power on reset condition.
When this pin is high, reset is controlled through the serial port.
4
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CHRONTEL
CH7019B
Table 1: Pin Description (continued)
Pin #
# of Pins Type
Symbol
Description
2
1
Analog
LPLLCAP
LVDS PLL Capacitor
This pins allows coupling of any signal to the on-chip loop filter
capacitor.
5, 24
6, 25
2
2
Out
Out
LL2C, LL1C
Positive LVDS differential Clock2 & Clock1
Negative LVDS differential Clock2 & Clock1
LL2C*,
LL1C*
11, 14, 17
12, 15, 18
27, 30, 33
28, 31, 34
38
3
3
3
3
1
Out
LDC[6:4]
LDC[6:4]*
LDC[2:0]
LDC[2:0]*
ISET
Positive LVDS differential data[6:4]
Negative LVDS differential data[6:4]
Positive LVDS differential data[2:0]
Negative LVDS differential data [2:0]
Current Set Resistor Input
Out
Out
Out
Analog
This pin sets the DAC current. A 140-ohm resistor should be connected
between this pin and DAC_GND (pin 39) using short and wide traces.
40
41
42
43
44
45
46
47
1
1
1
1
1
1
1
1
Out
Out
Out
Out
Out
Out
Out
Out
CVBS
(DACB3)
Composite Video
This pin outputs a composite video signal capable of driving a 75 ohm doubly
terminated load. During bypass modes this output is valid only if the data format
is compatible with one of the TV-Out display modes.
CVBS
(DACA3)
Composite Video
This pin outputs a composite video signal capable of driving a 75 ohm doubly
terminated load. During bypass modes this output is valid only if the data format
is compatible with one of the TV-Out display modes.
Y/G
(DACB1)
Luma / Green Output
This pin outputs a selectable video signal. The output is designed to drive a 75 ohm
doubly terminated load. The output can be selected to be the luminance
component of YPrPb or green (for VGA bypass)
Y/G
(DACA1)
Luma / Green Output
This pin outputs a selectable video signal. The output is designed to drive a 75 ohm
doubly terminated load. The output can be selected to be s-video luminance or
green (for SCART type 1 connections)
Pr/R
(DACB2)
Pr / Red Output
This pin outputs a selectable video signal. The output is designed to drive a 75 ohm
doubly terminated load. The output can be selected to be the Pr component of
YPrPb or red (for VGA bypass)
C/R
(DACA2)
Chroma / Red Output
This pin outputs a selectable video signal. The output is designed to drive a 75 ohm
doubly terminated load. The output can be selected to be s-video chrominance or
red (for SCART type 1 connections)
Pb/B
(DACB0)
Pb / Blue Output
This pin outputs a selectable video signal. The output is designed to drive a 75
ohm doubly terminated load. The output can be selected to the Pb component of
YPrPb or blue (for VGA bypass).
CVBS/B
Composite Video / Blue Output
(DACA0)
This pin outputs a selectable video signal. The output is designed to drive a 75
ohm doubly terminated load. The output can be selected to be composite video or
blue (for SCART type 1 connections)
49
50
1
1
Out
Out
C/HSYNC
Composite / Horizontal Sync
Provides composite sync in TV modes and horizontal sync in bypass
RGB mode. This pin is driven by the DVDD supply.
BCO/VSYNC
Buffered Clock Outputs / Vertical Sync
This output pin provides buffered crystal oscillator clock output or
VSYNC output in bypass RGB mode. This pin is driven by the DVDD
supply.
52
1
In
XI / FIN
Crystal Input / External Reference Input
A parallel resonant 14.31818MHz crystal (+ 20 ppm) should be attached
between this pin and XO. However, an external CMOS compatible
clock can drive the XI/FIN input.
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CHRONTEL
CH7019B
Table 1: Pin Description (continued)
Pin #
# of Pins Type
Symbol
Description
53
1
Out
XO
Crystal Output
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached
between this pin and XI / FIN. However, if an external CMOS clock is
attached to XI/FIN, XO should be left open.
59
61
1
Out
P-Out
Pixel Clock Output
This pin provides a pixel clock signal to the VGA controller which can be
used as a reference frequency. The output is selectable between 1X and
2X of the pixel clock frequency. The output driver is driven from the
VDDV supply (pin 60). This output has a programmable tri-state. The
capacitive loading on this pin should be kept to a minimum.
1
In
VREF1
Reference Voltage Input 1
The VREF1 pin inputs a reference voltage of VDDV / 2. The signal is
derived externally through a resistor divider and decoupling capacitor, and
will be used as a reference level for data, sync and clock inputs.
68-73, 77-82 12
In
In
D1[11:0]
Data1[11] through Data1[0] Inputs
These pins accept the 12 data inputs from a digital video port of a graphics
controller. The levels are 0 to VDDV. VREF1 is the threshold level.
76, 74
2
XCLK1,
XCLK1*
External Clock Inputs
These inputs form a differential clock signal input to the device for use
with the H1, V1 and D1[11:0] data.
If differential clocks are not
available, the XCLK1* input should be connected to VREF1. The clock
polarity can be selected by the MCP1 control bit.
85-90, 94-99
93, 91
12
2
In
In
D2[11:0]
Data2[11] through Data2[0] Inputs
These pins accept the 12 data inputs from a digital video port of a graphics
controller. The levels are 0 to VDDV. VREF1 is the threshold level.
XCLK2,
XCLK2*
External Clock Inputs
These inputs form a differential clock signal input to the device for use
with the H2, V2 and D2[11:0] data.
If differential clocks are not
available, the XCLK2* input should be connected to VREF1. The clock
polarity can be selected by the MCP2 control bit.
64, 83, 84, 103
4
4
1
1
1
1
1
1
6
Power
Power
Power
Power
Power
Power
Power
Power
Power
DVDD
DGND
VDDV
Digital Supply Voltage (3.3V)
Digital Ground
67, 75, 92, 100
60
I/O Supply Voltage (1.1V to 3.3V)
55
TVPLL_VDD TV PLL Supply Voltage (3.3V)
TVPLL_VCC TV PLL Supply Voltage (3.3V)
54
51
TVPLL_GND
DAC_VDD
DAC_GND
LVDD
TV PLL Ground
37
DAC Supply Voltage (3.3V)
DAC Ground
39, 48
7, 13, 19, 20,
26, 32
LVDS Supply Voltage (3.3V)
4, 10, 16, 23,
29, 35
6
Power
LGND
LVDS Ground
1
3
1
Power
Power
LPLL_VDD
LPLL_GND
N/C
LVDS PLL Supply Voltage (3.3V)
LVDS PLL Ground
1
8, 9, 21, 22,
109, 110, 112-
122
17
Not Connected
6
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Rev. 2.4, 12/18/2006
CHRONTEL
CH7019B
2.0 Overview
The CH7019 is a VGA to TV encoder with dual LVDS output for the graphics subsystem. Both TV-Out and LVDS-Out
can operate simultaneously if the two 12-bit input ports are driven from different timing generators. TV timing
requirements are usually different from that of the TFT-LCD panels. If the graphic controller can generate only one set
of timing, simultaneous display on both the TV and the flat panel may not be available for all graphic modes.
Descriptions of each of the operating modes with block diagrams of the data flow within the device are shown below.
The CH7019 also supports 24-bit input mode by ganging D1 and D2 together as a single 24-bit data port. In this case the
timing signals H1, V1, DE1, XCLK1 and XCLK1* are equal to H2, V2, DE2, XCLK2 and XCL2* , respectively.
Video data are sent to either the TV encoder (including RGB bypass) or to the LVDS data path, but not both. Maximum
data rate supported through the dual LVDS links is 330M Pixels /sec. The maximum pixel rate supported by the RGB
bypass mode is 165 Mpixels/sec.
2.1 Input Interface Timing
Four distinct methods of transferring data to the CH7019 are described below. In each of the four modes, DEx is used to
signal active LVDS data for the panel and register SAV value denotes the start of active TV video.
A. 12-bit Multiplexed Data – Dual-edge Transfer
•
•
•
•
Multiplexed data - two 12-bit words per pixel from either D1[11:0] or D2[11:0]
Clock frequency equals 1X pixel rate with 12-bit data transfer at both rising and falling clock edges.
Maximum pixel rate is 165M pixels per second with a 165 MHz pixel clock.
Simultaneous TV and panel display.
X C L K x
X C L K x *
S A V
D x [ 1 1 :0 ]
t S t H
D E x
H x
t S
t H
6 4 P - O U T
> = 1 V G A L in e
V x
Figure 3: Interface Timing for Multiplexed Data – Dual-edge Transfer
B. 12-bit Multiplexed Data – Single-edge Transfer
•
•
Multiplexed data - two 12-bit words per pixel from either D1[11:0] or D2[11:0]
Clock frequency equals 2X pixel rate with 12-bit data transfer at either rising or falling edge of clock
(programmable via serial port).
•
•
Maximum pixel rate is 165M pixels per second with a 330 MHz pixel clock.
Simultaneous TV and panel display.
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CHRONTEL
CH7019B
X C L K x
X C L K x *
S A V
D x [ 1 1 :0 ]
D E x
t S t H
t S
t H
6 4 P - O U T
H x
> = 1 V G A L in e
V x
Figure 4: Interface Timing for Multiplexed Data – Single-edge Transfer
C. 24-bit Ganged Data – Dual-edge Transfer
•
•
•
•
Multiplexed data - two 24-bit words per pixel from both D1[11:0] and D2[11:0]
Clock frequency equals 1/2X pixel rate with 24-bit data transfer at both rising and falling clock edges.
Maximum pixel rate is 330M pixels per second with a 165 MHz pixel clock.
No Simultaneous TV and panel display.
X C L K x
X C L K x *
S A V
D 1 [ 1 1 :0 ]
D 2 [ 1 1 :0 ]
t S t H
D E x
H x
t S
t H
6 4 P - O
U T
> = 1
V G A L in e
V x
Figure 5: Interface Timing for 24-bit Multiplexed Data – Dual-edge Transfer
D. 24-bit Ganged Data – Single-edge Transfer
•
•
Non-multiplexed data - one 24-bit word per pixel from both D1[11:0] and D2[11:0].
Clock frequency equals 1X pixel rate with 24-bit data transfer at either rising or falling edge of clock
(programmable via serial port).
•
•
Maximum pixel rate is 330M pixels per second with a 330 MHz pixel clock.
No simultaneous TV and panel display.
X C L K x
X C L K x *
S A V
D 1 [ 1 1 : 0 ]
D 2 [ 1 1 : 0 ]
t S t H
D E x
H x
t S
t H
6 4 P - O
U T
> = 1
V G A L in e
V x
Figure 6: Interface Timing for Non-multiplexed Data – Single-edge Transfer
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CHRONTEL
CH7019B
Table 2: Interface Timing Specifications
Symbol
tS
tH
Parameter
Setup time
Hold time
Min
Typ
Max
Unit
See section 5.5
nS
See section 5.5
nS
Note: tS, tH, setup time and hold time are programmable through serial port – X1CMD [3:0] and X2CMD[3:0] by delay
or advance of clock relative to data.
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CHRONTEL
CH7019B
2.2 Input Data Formats
2.2.1
12-Bit Multiplexed Data Formats
Multiplexed pixel data inputs to the CH7019 through D1[11:0] or D2[11:0] using data transfer method A or B described
in 3.1. Received data is formatted and sent through an internal data bus P1[23:0] to TV encoder or directly to the TV
DACs, or through bus P2[23:0] to the LVDS data path. The multiplexed input data formats are (IDF1[3:0]=0,1,2,3 and
4 for D1 and IDF2[3:0]=0,1,2,3 and 4 for D2):
IDFx Description
0
1
2
3
4
RGB 8-8-8 (2x12-bit)
RGB 8-8-8 (2x12-bit) or RGB 5-6-5 (2x8-bit)
RGB 5-6-5 (2x8bit)
RGB 5-5-5 (2x8-bit)
YCrCb 8-8 (2x8-bit)
For multiplexed input data formats, data can be latched from the graphics controller by either rising only or falling only
clock edges, or by both rising and falling clock edges. The MCPx bits select the rising or the falling clock edge, where
rising refers to rising edge on the XCLKx signals and falling edge on the XCLKx* signals. The multiplexed input data
formats are shown in Figure 7 below. The input data bus Dx[11:0], where x can be either 1 or 2, transports a 12-bit or
8-bit multiplexed data stream containing either RGB or YcrCb formatted data. The input data rate is 2X the pixel rate
and each pair of Pn values (e.g.; P0a and P0b) contains a complete pixel encoded as shown in the Tables 3 to 6 below
and can be placed onto one or both of the internal pixel buses Py[23:0], where y equals 1 or 2. It is assumed that the first
clock cycle following the leading edge of the incoming horizontal sync signal contains the first word (Pxa) of a pixel, if
an active pixel was present immediately following the horizontal sync. When the input is a YCrCb data stream the
color-difference data will be transmitted at half the data rate of the luminance data with the sequence being set as Cb0,
Y0, Cr0, Y1, where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples and the following Y1 byte
refers to the next luminance sample, per CCIR-656 standards (the clock frequency is dependent upon the current mode,
and is not 27MHz as specified in CCIR-656). All non-active pixels should be 0 in RGB formats, and 16 for Y and 128
for CrCb in YCrCb formats.
Hx
XCLKx
(2X)
SAV
XCLKx
(1X)
DEx
P0a
P0b
P1a
P1b
P2a
P2b
Dx[11:0]
Figure 7: 12-bit Multiplexed Input Data Formats (IDFx = 0,1,2,3,4)
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CHRONTEL
CH7019B
Table 3: Multiplexed Input Data Formats (IDFx = 0, 1)
IDFx =
0
1
Format =
RGB 8-8-8 (2x12-bit)
For TV/Bypass RGB or/and LVDS
RGB 8-8-8 (2x12-bit)
or RGB 5-6-5 (2x8-bit)
For TV/Bypass RGB or/and LVDS
Pixel #
P0a
P0b
P1a
P1b
P0a
P0b
P1a
P1b
Bus Data
Dx[11] G0[3]
Dx[10] G0[2]
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[7]
G0[6]
G0[5]
G0[4]
G1[3]
G1[2]
G1[1]
G1[0]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[7]
G1[6]
G1[5]
G1[4]
G0[4]
G0[3]
G0[2]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
G0[0]
B0[2]
B0[1]
B0[0]
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
G0[7]
G0[6]
G0[5]
R0[2]
R0[1]
R0[0]
G0[1]
G1[4]
G1[3]
G1[2]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
G1[0]
B1[2]
B1[1]
B1[0]
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
G1[7]
G1[6]
G1[5]
R1[2]
R1[1]
R1[0]
G1[1]
Dx[9]
Dx[8]
Dx[7]
Dx[6]
Dx[5]
Dx[4]
Dx[3]
Dx[2]
Dx[1]
Dx[0]
G0[1]
G0[0]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
Table 4: Multiplexed Input Data Formats (IDFx = 2, 3)
IDFx =
Format
=
2
3
RGB 5-6-5 (2x8bit)
for TV/Bypass RGB or/and LVDS
RGB 5-5-5 (2x8-bit)
for TV/Bypass RGB or/and LVDS
Pixel #
Bus
P0a
G0[4]
P0b
R0[7]
P1a
G1[4]
P1b
R1[7]
P0a
G0[5]
P0b
X
P1a
G1[5]
P1b
X
Dx[11]
Data
Dx[10]
Dx[9]
Dx[8]
Dx[7]
Dx[6]
Dx[5]
Dx[4]
G0[3]
G0[2]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
R0[6]
R0[5]
R0[4]
R0[3]
G0[7]
G0[6]
G0[5]
G1[3]
G1[2]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
R1[6]
R1[5]
R1[4]
R1[3]
G1[7]
G1[6]
G1[5]
G0[4]
G0[3]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
G0[7]
G0[6]
G1[4]
G1[3]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
G1[7]
G1[6]
Table 5: Multiplexed Input Data Formats (IDFx = 4)
IDFx =
4
Format =
YCrCb 4:2:2 (2x8-bit)
for TV
Pixel #
P0a
P0b
P1a
P1b
P2a
P2b
P3a
P3b
Bus Data
Dx[7]
Dx[6]
Dx[5]
Dx[4]
Dx[3]
Dx[2]
Dx[1]
Dx[0]
Cb0[7]
Cb0[6]
Cb0[5]
Cb0[4]
Cb0[3]
Cb0[2]
Cb0[1]
Cb0[0]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
Cr0[7]
Cr0[6]
Cr0[5]
Cr0[4]
Cr0[3]
Cr0[2]
Cr0[1]
Cr0[0]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Cb2[7]
Cb2[6]
Cb2[5]
Cb2[4]
Cb2[3]
Cb2[2]
Cb2[1]
Cb2[0]
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
Cr2[7]
Cr2[6]
Cr2[5]
Cr2[4]
Cr2[3]
Cr2[2]
Cr2[1]
Cr2[0]
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]
When IDFx = 4 (YCrCb mode), the data inputs can also be used to transmit sync information to the device. In this
mode, the embedded sync will follow the VIP2 convention, and the first byte of the ‘video timing reference code’ will be
assumed to occur when a Cb sample would occur, if the video stream was continuous. This is shown below:
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CHRONTEL
CH7019B
Table 6: Multiplexed Input Data Formats (IDFx = 4) with Embedded Sync
IDFx =
4
Format =
YCrCb 4:2:2 (2x8-bit) for TV
Pixel #
Bus Data
P0a
1
1
1
1
1
1
1
1
P0b
0
0
0
0
0
0
0
0
P1a
0
0
0
0
0
0
0
0
P1b
S[7]
S[6]
S[5]
S[4]
S[3]
S[2]
S[1]
S[0]
P2a
P2b
P3a
P3b
Dx[7]
Dx[6]
Dx[5]
Dx[4]
Dx[3]
Dx[2]
Dx[1]
Dx[0]
Cb2[7]
Cb2[6]
Cb2[5]
Cb2[4]
Cb2[3]
Cb2[2]
Cb2[1]
Cb2[0]
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
Cr2[7]
Cr2[6]
Cr2[5]
Cr2[4]
Cr2[3]
Cr2[2]
Cr2[1]
Cr2[0]
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]
In this mode, the S[7..0] byte contains the following data:
S[6] = F = 1 during field 2, 0 during field 1
S[5] = V = 1 during field blanking, 0 elsewhere
S[4] = H = 1 during EAV (synchronization reference at the end of active video)
0 during SAV (synchronization reference at the start of active video)
S[7] and S[3:0] are ignored
2.2.2
24-Bit Data Formats
The two 12-bit input data ports, D1[11:0] and D2[11:0], can be grouped together to form a single 24-bit interface to the
graphic controller. In this case the timing signals H1, V1, DE1, XCLK1 and XCLK1* are equal to H2, V2, DE2,
XCLK2 and XCLK2* , respectively. The CH7019 supports 5 different 24-bit data formats. Each of which is used with a
1X pixel rate clock latching data with one of the clock edges (default is falling edge). The 24-bit input data formats are
IDFx[3:0]=5,6,7,8 and 9 (note that IDF1 must be set equal to IDF2) and are illustrated in Figure 8 below.
IDFx Description
5
6
7
8
9
RGB 8-8-8 (1x24-bit) for TV/Bypass RGB
YCrCb 8-8 (1x16-bit with CrCb multiplexed and decimated by 2) for TV
YCrCb 8-8-8 (1x24-bit) for TV
RGB 8-8-8 (2x24-bit) Odd / Even Ganged for LVDS
RGB 8-8-8 (1x24-bit) Normal Ganged for LVDS
The pixel data bus represents a 24-bit or 16-bit data stream containing either RGB or YCrCb formatted data. When the
input is a 16-bit YCrCb data stream the color-difference data will be transmitted at half the data rate of the luminance
data, with the sequence being set as Cb0, Y0 transmitted during one clock cycle, followed by Cr0, Y1 the following
clock cycle, where Cb0, Y0, Cr0 refers to co-sited luminance and color-difference samples and the Y1 data refers to the
next luminance sample, per CCIR-601 sampling. Non-active data must be 0 in RGB format, and 16 for Y, 128 for Cr
and Cb in YCrCb formats.
Hx
XCLKx
SAV
DEx
P0
P1
P2
P3
P4
P5
Dx[11:0]
Figure 8: Non-Multiplexed Input Data Formats (IDFx = 5,6,7,8 and 9)
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Table 7: Non-Multiplexed Data Formats
IDFx =
5
6
7
Format =
24-bit RGB for
TV/Bypass RGB
16-bit YCrCb
FOR TV
24-bit YCrCb
FOR TV
Pixel #
P0
P1
P0
P1
P2
P3
P0 P1
Bus Data
D1[11] R0[7]
D1[10] R0[6]
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[7]
G1[6]
G1[5]
G1[4]
G1[3]
G1[2]
G1[1]
G1[0]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
Cr0[7]
Cr0[6]
Cr0 [5]
Cr0 [4]
Cr0 [3]
Cr0 [2]
Cr0 [1]
Cr0 [0]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Cb0[7]
Cb0[6]
Cb0 [5] Cr2 [5]
Cb0 [4] Cr2 [4]
Cb0 [3] Cr2 [3]
Cb0 [2] Cr2 [2]
Cb0 [1] Cr2 [1]
Cb0 [0] Cr2 [0]
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
Cr2[7]
Cr2[6]
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]
Cb2[7]
Cb2[6]
Cb2 [5] Cr0 [5]
Cb2 [4] Cr0 [4]
Cb2 [3] Cr0 [3]
Cb2 [2] Cr0 [2]
Cb2 [1] Cr0 [1]
Cb2 [0] Cr0 [0]
Cb0[7]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
Cr0[7]
Cr0[6]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Cr1[7]
Cr1[6]
Cr1 [5]
Cr1 [4]
Cr1 [3]
Cr1 [2]
Cr1 [1]
Cr1 [0]
Cb1[7]
Cb1[6]
D1[9]
D1[8]
D1[7]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
R0[5]
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[7]
G0[6]
G0[5]
G0[4]
DVOB
D2[11] G0[3]
D2[10] G0[2]
D2[9]
D2[8]
D2[7]
D2[6]
D2[5]
D2[4]
D2[3]
D2[2]
D2[1]
D2[0]
G0[1]
G0[0]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
DVOC
Cb0[6]
Cb0 [5] Cb1[5]
Cb0 [4] Cb1[4]
Cb0 [3] Cb1[3]
Cb0 [2] Cb1[2]
Cb0 [1] Cb1[1]
Cb0 [0] Cb1[0]
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CH7019B
When IDFx = 6 or 7 (YCrCb modes), the data inputs can be used to transmit sync information to the device. In these
modes the embedded sync follows a subset of the VIP2 convention, and the first byte of the video timing reference code
is assumed to occur when a Cb sample occurs, if the video stream is continuous. This is shown in Table 8 below.
Table 8: Non-Multiplexed YCrCb modes with Embedded Sync
IDFx =
Format =
6
16-bit YCrCb
for TV
7
24-bit YCrCb
for TV
Pixel #
Bus Data
P0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
P1
P2
P3
P0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
P1
P2
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
P3
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
D1[11]
D1[10]
D1[9]
D1[8]
D1[7]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
D2[11]
D2[10]
D2[9]
D2[8]
D2[7]
D2[6]
D2[5]
D2[4]
D2[3]
D2[2]
D2[1]
D2[0]
S[7]
S[6]
S[5]
S[4]
S[3]
S[2]
S[1]
S[0]
0
0
0
0
0
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
Cr0[7]
Cr0[6]
Cr0 [5]
Cr0 [4]
Cr0 [3]
Cr0 [2]
Cr0 [1]
Cr0 [0]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Cb0[7]
Cb0[6]
Cb0 [5]
Cb0 [4]
Cb0 [3]
Cb0 [2]
Cb0 [1]
Cb0 [0]
S[7]
S[6]
S[5]
S[4]
S[3]
S[2]
S[1]
S[0]
X
X
X
X
X
X
X
X
X
X
X
X
X
Y0[0]
Y1[0]
Cr0[7]
Cr0[6]
Cr0 [5]
Cr0 [4]
Cr0 [3]
Cr0 [2]
Cr0 [1]
Cr0 [0]
Cb0[7]
Cb0[6]
Cb0 [5]
Cb0 [4]
Cb0 [3]
Cb0 [2]
Cb0 [1]
Cb0 [0]
Cr1[7]
Cr1[6]
Cr1[5]
Cr1[4]
Cr1[3]
Cr1[2]
Cr1[1]
Cr1[0]
Cb1[7]
Cb1[6]
Cb1 [5]
Cb1 [4]
Cb1 [3]
Cb1 [2]
Cb1 [1]
Cb1 [0]
0
0
0
X
X
X
In this mode, the S[7..0] byte contains the following data:
S[6] = F = 1 during field 2, 0 during field 1
S[5] = V = 1 during field blanking, 0 elsewhere
S[4] = H = 1 during EAV (synchronization reference at the end of active video)
0 during SAV (synchronization reference at the start of active video)
S[7] and S[3:0] are ignored
Under mode 8 and 9, the CH7019 takes 24-bit data from both D1 and D2 and outputs to the dual LVDS links. A
maximum throughput of 330M pixels per second can be achieved. The timing signals of both input ports shall be
identical. H1, V1 and XCLK1 equal H2, V2 and XCLK2, respectively. Up-scaling and dithering functions are not
available in these modes.
14
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CHRONTEL
CH7019B
Table 9: Ganged Data Formats
IDFx =
8
9
Format =
24-bit RGB
Odd/Even Ganged
for LVDS
24-bit RGB
Normal Ganged
for LVDS
Pixel #
P0
P1
P0
P1
Bus Data
D1[11] G0[3]
D1[10] G0[2]
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[7]
G0[6]
G0[5]
G0[4]
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[7]
G1[6]
G1[5]
G1[4]
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[7]
G0[6]
G0[5]
G0[4]
G0[3]
G0[2]
G0[1]
G0[0]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[7]
G1[6]
G1[5]
G1[4]
G1[3]
G1[2]
G1[1]
G1[0]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
D1[9]
D1[8]
D1[7]
D1[6]
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
G0[1]
G0[0]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
DVOB
D2[11] G1[3]
D2[10] G1[2]
D2[9]
D2[8]
D2[7]
D2[6]
D2[5]
D2[4]
D2[3]
D2[2]
D2[1]
D2[0]
G1[1]
G1[0]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
DVOC
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15
CHRONTEL
CH7019B
2.3 TV-Out
Multiplexed input data, sync and clock signals from the graphics controller inputs to the CH7019 through one of the two
12-bit variable voltage input ports, D1[11:0] or D2[11:0], and is directed to the TV data path. Non-multiplexed 24-bit
input data also inputs through both of the two input ports. Detailed descriptions of the eight input data formats are given
in Section 2.2. Clock signal (P-Out) outputs as a frequency reference to the graphics controller to ensure accurate
frequency generation. Horizontal and vertical sync signals are normally sent to the CH7019 from the graphics controller,
but can be optionally generated by the CH7019 and output to the graphics controller. Using the serial port, the CH7019
can be programmed as the clock master, clock slave, sync master or sync slave. Data will be 2X multiplexed (2x12 bits)
or non-multiplexed (1x24 bits), and the XCLK clock signal can be 1X or 2X times the pixel rate. The input data will be
encoded into the selected video standard, and output from the video DACs.
2.3.1
Display Modes
The CH7019 display mode is controlled by three independent factors: input resolution, TV format, and scale factor,
which are programmed via the display mode register. It is designed to accept input resolutions of 512x384, 640x480,
640x400, 720x400, 720x480, 720x576, 800x600, and 1024x768.
It is designed to support output to either NTSC or PAL television formats. The CH7019 provides interpolated scaling
with selectable factors of 5:4, 1:1, 7:8, 5:6, 3:4, 7:10 and 25:21 in order to support adjustable overscan or underscan
operation when displayed on a TV. The modes supported for TV-Out are shown in the Table 10 below.
Table 10: TV Output Modes
Graphics
Resolution
512x384
512x384
720x400
720x400
640x400
640x400
640x480
640x480
720x4801
720x4802
720x5761
720x5762
800x600
800x600
1024x768
1024x768
Active Aspect
Ratio
4:3
Pixel Aspect
Ratio
1:1
TV Output
Standard
PAL
NTSC
PAL
NTSC
PAL
NTSC
PAL
NTSC
NTSC
NTSC
PAL
PAL
PAL
Scaling Ratios
5/4, 1/1
5/4, 1/1
5/4, 1/1
4:3
4:3
4:3
8:5
8:5
4:3
4:3
4:3
4:3
4:3
4:3
4:3
4:3
4:3
4:3
1:1
1.35:1.00
1.35:1.00
1:1
5/4, 1/1, 25/21
5/4, 1/1
5/4, 1/1, 7/8, 25/21
5/4, 1/1, 5/6, 25/21
1/1, 7/8, 5/6
1/1
1:1
1:1
1:1
9:8
9:8
1/1, 7/8, 5/6
1/1
15:12
15:12
1:1
1:1
1:1
1/1, 5/6, 5/7
1/1, 5/6, 5/7
3/4, 7/10, 5/8
5/7, 5/8, 5/9
5/8, 5/9, 1/2
NTSC
PAL
NTSC
1:1
1 These DVD modes operate with interlaced input. Scan conversion and flicker filter are bypassed.
2 These DVD modes operate with non-interlaced input. Scan conversion and flicker filter are not
bypassed.
2.3.2
Adaptive Flicker Filter
The CH7019 integrates an advanced 2-line, 3-line, 4-line, 5-line, 6-line and 7-line (depending on mode) vertical
deflickering filter circuit to help eliminate the flicker associated with interlaced displays. This flicker circuit provides an
adaptive filter algorithm for implementing flicker reduction with selections of high, medium or low flicker content for
both luma and chroma channels (see register descriptions). In addition, a special text enhancement circuit incorporates
additional filtering for enhancing the readability of test. These modes are fully programmable via serial port interface
using the flicker filter register.
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2.3.3
Color Burst Generation
The CH7019 allows the subcarrier frequency to be accurately generated from a 14.31818 MHz crystal oscillator, leaving
the subcarrier frequency independent of the graphics pixel clock frequency. As a result, the CH7019 may be used with
most VGA chips (with an appropriate digital interface) since the CH7019 subcarrier frequency can be generated without
being dependent on the precise pixel rates of VGA controllers. This feature is important since even a ±0.01% subcarrier
frequency variation is enough to cause some televisions to lose color lock.
In addition, the CH7019 has the capability to genlock the color burst signal to the VGA horizontal sync frequency, which
enables a fully synchronous system between the graphics controller and the television. When genlocked, the CH7019 can
stop “dot crawl” motion (for composite NTSC modes), thus eliminating the annoyance of moving borders. Both of these
features are under programmable control through the register set.
2.3.4
NTSC and PAL Operation
Composite and S-Video outputs are supported in either NTSC or PAL format. The general parameters used to
characterize these outputs are listed in Table 11 and shown in Figure 9. (See Figure 12 through Figure 17 for illustrations
of composite and S-Video output waveforms).
ITU-R BT.470 Compliance
The CH7019 is predominantly compliant with the recommendations called out in ITU-R BT.470. The following are the
only exceptions to this compliance:
•
•
•
The frequencies of Fsc, Fh, and Fv can only be guaranteed in clock/sync master mode, not in clock/sync slave mode
when the graphics device generates these frequencies.
It is assumed that gamma correction, if required, is performed in the graphics device which establishes the color
reference signals.
All modes provide the exact number of lines called out for NTSC and PAL modes respectively, except mode 21,
which outputs 800x600 resolution, scaled by 3:4, to PAL format with a total of 627 lines (vs. 625).
•
•
Chroma signal frequency response will fall within 10% of the exact recommended value.
Pulse widths and rise/fall times for sync pulses, front/back porches, and equalizing pulses are designed to
approximate ITU-R BT.470 requirements, but will fall into a range of values due to the variety of clock frequencies
used to support multiple operating modes.
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Table 11: NTSC/PAL Composite Output Timing Parameters
Symbol Description
Level (mV)
Duration (uS)
NTSC
287
0
PAL
300
0
NTSC
PAL
A
B
C
D
E
F
Front Porch
Horizontal Sync
Breezeway
Color Burst
Back Porch
Black
1.49 - 1.51
4.69 - 4.72
0.59 - 0.61
2.50 - 2.53
1.55 - 1.61
0.00 - 7.50
37.66 - 52.67
0.00 - 7.50
1.48 - 1.51
4.69 - 4.71
0.88 - 0.92
2.24 - 2.26
2.62 - 2.71
0.00 - 8.67
34.68 - 52.01
0.00 - 8.67
287
287
287
340
340
340
300
300
300
300
300
300
G
H
Active Video
Black
For this table and all subsequent figures, key values are:
Note:
1. RSET = 140 ohms; V(ISET) = 1.235V; 75 ohms doubly terminated load. RSET is the resistor
connected to the ISET pin.
2. Durations vary slightly in different modes due to the different clock frequencies used.
3. Active video and black (F, G, H) times vary greatly due to different scaling ratios used in different
modes.
4. Black times (F and H) vary with position controls.
Figure 9: NTSC / PAL Composite Output
N
1
CNY
5
5
5
3
5
1
2
3
5
6
8
9
FILED
A
A
S
5
0
5
23 425 251
AN AOFEI DLG2
3
4
5
6
8
9
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CH7019B
START
OF
VSYNC
Start of
field 1
523
524
9
10
12
525
3
11
1
2
4
6
7
8
5
Pre-equalizing
pulse interval
Post-equalizing
pulse interval
Vertical sync
pulse interval l
Reference
sub-carrier phase
color field 1
Line
vertical
interval
t1 +V
262
263
264
270
261
265
267
268
269
271
272
273
274
275
266
Start of
field 2
Reference
sub-carrier phase
color field 2
t2 +V
523
10
12
524
6
11
525
2
4
5
7
8
9
1
3
Start of
field 3
Reference
sub-carrier phase
color field 3
t3 +V
269
274
265
264
266
267
268
270
272
273
263
261
262
271
275
Start of
field 4
Reference
sub-carrier phase
color field 4
Figure 10: Interlaced NTSC Video Timing
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START
OF
VSYNC
FIELD 1
FIELD 2
FIELD 3
FIELD 4
BURST
BLANKING
4
3
2
INTERVALS
1
Figure 11: Interlaced PAL Video Timing
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Color bars:
Color/Level
mA
V
White
Yellow
26.66
24.66
1.000
0.925
Cyan
Green
21.37
19.37
0.801
0.726
Magenta
Red
16.22
14.22
0.608
0.533
Blue
Black
Blank
11.08
9.08
7.65
0.415
0.340
0.287
Sync
0.00
0.000
Figure 12: NTSC Y (Luminance) Output Waveform (DACG = 0)
Color bars:
Color/Level
mA
V
White
Yellow
26.75
24.62
1.003
0.923
Cyan
Green
21.11
18.98
0.792
0.712
Magenta
Red
15.62
13.49
0.586
0.506
Blue
10.14
8.00
0.380
0.300
Blank/ Black
Sync
0.00
0.000
Figure 13: PAL Y (Luminance) Video Output Waveform (DACG = 1)
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Color bars:
Color/Level
mA
V
Cyan/Red
Green/Magenta 25.01
25.80
0.968
0.938
Yellow/Blue
22.44
0.842
Peak Burst
Blank
18.08
14.29
0.678
0.536
Peak Burst
10.51
0.394
3.579545 MHz Color Burst
(9 cycles)
Yellow/Blue
6.15
0.230
Green/Magenta
Cyan/Red
3.57
2.79
0.134
0.105
Figure 14: NTSC C (Chrominance) Video Output Waveform (DACG = 0)
Color bars:
Color/Level
mA
V
Cyan/Red
Green/Magenta 26.68
27.51
1.032
1.000
Yellow/Blue
23.93
0.897
Peak Burst
Blank
19.21
15.24
0.720
0.572
Peak Burst
11.28
0.423
4.433619 MHz Color Burst
(10 cycles)
Yellow/Blue
6.56
0.246
Green/Magenta
Cyan/Red
3.81
2.97
0.143
0.111
Figure 15: PAL C (Chrominance) Video Output Waveform (DACG = 1)
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Color/Level
mA
V
Color bars:
Peak Chrome 32.88
1.233
White
26.66
1.000
Peak Burst
11.44
0.429
Black
Blank
9.08
7.65
0.340
0.287
Peak Burst
Sync
4.45 0.145
0.00 0.000
3.579545 MHz Color Burst
(9 cycles)
Figure 16: Composite NTSC Video Output Waveform (DACG = 0)
mA
Color/Level
Color bars:
V
Peak Chrome 33.31
1.249
White
26.75
1.003
Peak Burst
Blank/Black
11.97
8.00
0.449
0.300
Peak Burst
Sync
4.04
0.00
0.151
0.000
4.433619 MHz Color Burst
(10 cycles)
Figure 17: Composite PAL Video Output Waveform (DACG = 1)
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2.3.5
TV Encoder / Bypass RGB / Component Video Outputs
The four TV encoder DAC outputs in the CH7019 can be switched to two sets of output pins DACA[3:0] and DACB[3:0]
via video switches. This feature facilitates simple connection to two sets of video connectors as listed in
Table 12 below:
Table 12: TV Output Configurations
2 RCA + 1 S-Video
SCART
DACA0 (pin 47)
DACA1 (pin 43)
DACA2 (pin 45)
DACA3 (pin 41)
CVBS
Y
C
B
G
R
CVBS
CVBS
VGA – Bypass RGB
HDTV
Pb
Y
DACB0 (pin 46)
DACB1 (pin 42)
DACB2 (pin 44)
DACB3 (pin 40)
B
G
R
Pr
CVBS
If the application calls for CVBS/S-video, SCART, RGB and YPrPb to output on the DAC output pins, different
reconstruction filters for each type of signal can be implemented on the break-out cables.
The TV Encoder can be bypassed with input data driving the DACs directly. This mode can go to 165 MP/s. The
CH7019 supports YPrPb output for driving 480i TV sets and SCART RGB for European TV.
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2.4 LVDS-Out
Multiplexed input data, sync and clock signals from the graphics controllers input to the CH7019 through one of the two
12-bit variable voltage input ports, D1[11:0] or D2[11:0]. Non-multiplexed 24-bit input data input through both of the
two input ports. For correct LVDS operation, the input data format must be selected to be IDFx=0, 1, 2, 3, 5, 8 or 9. Note
for 24-bit formats, IDF1 must be set equal to IDF2.
If the two 12-bit input ports are driven from different timing generators then data can be sent to both the LVDS data path
and the DACs in the TV data path. The DACs can output these data at 165 M pixels/sec to drive a second CRT monitor.
2.4.1
Single LVDS Channel Signal Mapping
Table 13: Signal Mapping for Single LVDS Channel
18-bit
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
LDC[0](1)
LDC[0](2)
LDC[0](3)
LDC[0](4)
LDC[0](5)
LDC[0](6)
LDC[0](7)
LDC[1](1)
LDC[1](2)
LDC[1](3)
LDC[1](4)
LDC[1](5)
LDC[1](6)
LDC[1](7)
LDC[2](1)
LDC[2](2)
LDC[2](3)
LDC[2](4)
LDC[2](5)
LDC[2](6)
LDC[2](7)
B4
B5
HSYNC
VSYNC
DE
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2.4.2
Dual LVDS Channel Signal Mapping
Table 14: Signal Mapping for Dual LVDS Channel
18-bit
Ro0
Ro1
Ro2
Ro3
Ro4
Ro5
Go0
Go1
Go2
Go3
Go4
Go5
Bo0
Bo1
Bo2
Bo3
Bo4
Bo5
HSYNC
VSYNC
DE
Re0
Re1
Re2
Re3
Re4
Re5
Ge0
Ge1
Ge2
Ge3
Ge4
Ge5
LDC[0](1)
LDC[0](2)
LDC[0](3)
LDC[0](4)
LDC[0](5)
LDC[0](6)
LDC[0](7)
LDC[1](1)
LDC[1](2)
LDC[1](3)
LDC[1](4)
LDC[1](5)
LDC[1](6)
LDC[1](7)
LDC[2](1)
LDC[2](2)
LDC[2](3)
LDC[2](4)
LDC[2](5)
LDC[2](6)
LDC[2](7)
LDC[4](1)
LDC[4](2)
LDC[4](3)
LDC[4](4)
LDC[4](5)
LDC[4](6)
LDC[4](7)
LDC[5](1)
LDC[5](2)
LDC[5](3)
LDC[5](4)
LDC[5](5)
LDC[5](6)
LDC[5](7)
LDC[6](1)
LDC[6](2)
LDC[6](3)
LDC[6](4)
LDC[6](5)
LDC[6](6)
LDC[6](7)
Be0
Be1
Be2
Be3
Be4
Be5
LCTLE 1
LCTLF 1
LA6RL 1
Note:
1. See description for register 65h.
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2.4.3
Dithering
The dither engine in the CH7019 converts 24-bit per pixel to 18-bit per pixel RGB data before sending to the LVDS
encoder. The 1D or the 2D dither algorithm can be selected via serial port programming. Maximum pixel rate supported
is 165 M Pixels / sec. This function must be bypassed when pixel rate exceeds 165MHz.
2.4.4
Power Sequencing
The CH7019 conforms to SPWG’s requirements on power sequencing. The timing specification shown in Figure 18 is a
superset of the requirements dictated by the SPWG specification. The power sequencing block consists of a state
machine and 5 hardware timers, which are programmable through serial port to suit requirements by different panels. It
provides 2 signals ENAVDD and ENABKL to the LCD panel.
T1 T2
T3 T4
T5
LVDS_RDY
(Internal)
ENAVDD
ENEXBUF
ENABKL
LVDS Clocks
LVDS Data
Valid Clock
Valid Data
Tristate or GND
Tristate or GND
Figure 18: Power Sequencing
Table 15: Power Sequencing
Range
1-512 ms
2-256 ms
2-256 ms
1-512 ms
0-1600 ms
Increment
1 ms
T1
T2
T3
T4
T5
2ms
2ms
1 ms
50ms
Power-on sequence begins when the LVDS software registers are set properly via serial port and the internal PLL lock
detection circuit and the internal Sync detection circuits (see section 2.4.5) indicate that HSYNC, VSYNC and XCLK
are stable. Note that the BKLEN bit (register 66h) must be set in order for the ENABKL signal to be asserted. Power-off
sequence begins when any detection circuits indicate an instability in the timing signals (see section 2.4.5), or through
software programming. Once power-off sequence starts, the internal state machine will complete the sequence and
power-on sequence is allowed only after T5 is passed.
When the LVDS output clock and data signals become invalid, these outputs are tri-stated or grounded depending on the
value of the LODP bit.
2.4.5
Panel Protection
The LCD panel can be damaged if HSYNC is absent from the LVDS link. This situation can happen when there is a
catastrophic failure in the PC or the graphics system. The CH7019 is designed to prevent damage to the panel under such
a failure. If the system fails, the CH7019 does not expect any software instruction from the graphics controller to power
down the panel. Detection circuits are used to monitor the three timing signals – HSYNC, VSYNC and XCLK. If any
one, combination of, or all of these signals becomes unstable, the CH7019 will commence Power Down Sequencing
according to section 2.4.4. A description of these detection circuits is shown in Figure 19.
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XCLK
LVDS
PLL
XCLK
LOCKST
0
LOCK
FIFO
MUX
DETECT
LOCK
1
LPFORC
LPLEN
Register 66h
Note:
1) LOCKST will be logic
low if either XCLK or the
LVDS PLL output is
unstable.
2) SYNCST will be logic
low if either Hsync or
Vsync is unstable or
missing.
PANEN
LSYNCEN
LPLOCK
LPFORC
LPLEN
HSYNC
VSYNC
BKLEN
SYNC
DETECT
SYNCST
LSYNCEN
XCLK
Detect
CLKDETD
FOSC (from oscillator)
ENAVDD
ENABKL
Power Sequencing
Figure 19: Detection Circuits for Panel Protection
The power up sequence can occur only if (a) XCLK is not missing, (b) there are no missing HSYNC and VSYNC, (c)
the PLL CLOCK is stable, and (d) PANEN is set to 1. The power down sequence happens if any of those conditions fails.
The power up sequence can also occur if the panel protection circuitry is bypassed.
The panel protection circuitry is comprised of a LOCKDET block, which detects an unstable clock from the LVDS PLL,
a SYNCDET block, which detects missing inputs HSYNC and VSYNC, and an XCLK Detect block, which detects
missing XCLK. XCLK stability (assuming it is not missing) is determined by the number of PLL unlock signals
generated within one frame. This number is programmable via serial port using the BGLMT register (register 7Fh).
The SYNCDET block consists of counters to count HSYNC and VSYNC pulses. One counter is used to count the
number of HSYNC pulses per frame over 3 frames. The end counts for all 3 frames must be equal to enable the power up
sequence. In addition, the SYNCDET block checks for the presence of VSYNC and HSYNC. If VSYNC is missing for 2
frames or if HSYNC is missing for 32us the power up sequence is disabled. Conversely, if the panel has already been
enabled and if the check of the number of HSYNC pulses over 3 frames yields different counts for any frame or if
VSYNC is missing for 2 frames or if HSYNC is missing for 32us the CH7019 will go into a power down sequence.
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The XCLK Detect block detects if XCLK is missing for more than approximately 1.2us.
The LOCKDET block and SYNCDET block can be defeated or bypassed independently through the LPMC register
(register 66h) controls. To defeat the LOCKDET block set LPFORC to ‘1’ and LPLEN to ‘1’; to defeat the SYNCDET
block set LSYNCEN to 1. The XCLK Detect block can be defeated or bypassed independently through the CLKDETD
bit in register 14h, bit 2. To defeat the XCLK Detect block set CLKDETD to ‘1’.
The order of programming the control registers for the power up sequence is very important. Both LPLOCK and
SYNCST must read as 1 before setting PANEN to 1. Doing so will eliminate unexpected results on the LCD panel.
2.4.6
Clock for Emission Reduction
LVDS data path can support a +- 2.5% spread spectrum clock to reduce EMI emission. The frequency and amplitude of
the spread spectrum triangle waveform can be programmed via the serial port. Please refer to AN-59 for details.
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2.5 Power Down
The CH7019 can be powered down under software control to achieve very low standby current. The matrix in table 16
shows the function of all the power down control bits for the CH7019. For a complete description of each individual bit
please refer to the appropriate register description in sections 3.1 and 3.3.
Table 16: Power Down Control Bits
T
V
P
D
A
C
P
D
3
D
A
C
P
D
2
D
A
C
P
D
1
D
A
C
P
D
0
L
V
D
S
P
D
L
O
D
P
D
B
1
L
O
D
P
D
B
0
Description
D
1
0
X
1
X
1
X
1
X
0
1
1
X
X
X
X
Full Power Down
TV path powered up, DAC 0 on, DACs 1, 2, 3 off.
LVDS path powered down.
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
X
X
0
X
X
0
TV path powered up, DAC 0 off, DACs 1, 2, 3 on.
LVDS path powered down.
0
0
0
0
TV path powered up, DACs 0, 1, 2, 3 on.
LVDS path powered down
X
X
X
X
0
X
X
X
X
0
X
X
X
X
0
X
X
X
X
0
TV path powered down
LVDS path powered up. Both channels off..
0
1
TV path powered down.
LVDS path powered up. Channel A on, channel B off.
1
0
TV path powered down.
LVDS path powered up. Channel A off, channel B on.
1
1
TV path powered down.
LVDS path powered up. Channel A on, channel B on.
1
1
TV path powered up, DACs 0, 1, 2, 3 on.
LVDS path powered up. Channel A on, channel B on.
Note:
1. X = do not care.
2. TV bit (register 49h, bit 5) enables the TV path but does not control power down. In order for the TV path to
function, TV must be set to 1 and TVPD set to 0.
3. An input channel which is routing data to an inactive path (TV or LVDS) is automatically powered down. For
example, if PTSEL[1:0] = 10 (D1 input routed to TV and D2 input routed to LVDS) and if TVPD = 1 (TV path
powered down) then data channel D1 is automatically powered down.
4. LDEN[1:0] (register 73h, bits 4-3) enable the LVDS outputs but do not control power down. In order for an LDVS
channel to be active LVDSPD must be set to 0, the channel must be powered up (LODPDBx=1) and enabled
(LDENx=1).
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3.0 Register Control
The CH7019 is controlled via a serial control port. The serial bus uses only the SPC clock to latch data into registers,
and does not use any internally generated clocks so that the device can be written to in all power down modes. The
device should retain all register values during power down modes.
3.1 Non-Macrovision Control Registers Index
The non-Macrovision controls are listed below, divided into four sections: General & Power Down controls,
Input/Output controls, LVDS controls, TV-Out controls.
GENERAL & POWER DOWN CONTROLS
Address
49h
4Bh
DACPD[3:0]
DID[7:0]
DAC Power Down
Device ID register
LODPDB[1:0]
LVDSPD
LVDS Output Driver Power Down control
LVDS Power Down
76h
63h
PANEN
Panel Enable (0 – begin Power off sequence, 1 Power-on)
Software SPP (serial port) reset
Software datapath reset
Enables FLD2 and FLD1 pins
Controls FLD2 and FLD1 output to VGA controller
Timer – Black Light Disable (T3)
Timer – Black Light Enable (T2)
Timer – Power Off (T4)
Timer - Power On (T1)
Timer – Power Cycle (T5)
Enable/select test pattern generation (color bar, ramp)
TV Data and Channel select
66h
48h
48h
10h
60h
69h
68h
69h-6Ah
67h-68h
6Bh
48h
49h
RESETIB
RESETDB
STFDEN[1:0]
STFDS[1:0]
TPBLD [6:0]
TPBLE [6:0]
TPOFF [8:0]
TPON [8:0]
TPPWD [5:0]
TSTP[1:0]
TV
TVPD
TV Out Power Down
49h
VID[7:0]
Version ID register
4Ah
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INPUT/OUTPUT CONTROLS
Address
BCO[2:0]
BCOEN
Select output signal for BCO pin
Enable BCO Output
22h
22h
BCOP
BCO polarity
22h
BGBST
Bandgap Boost
14h
C3GP[5:0]
C4GP[5:0]
C5GP[5:0]
DACBP
GPIO Controls
GPIO Controls
GPIO Controls
DAC bypass
6Eh, 6Dh
6Bh-6Dh
5Ch, 65h
21h
DACG[1:0]
DACT[3:0]
DES
GOENB[1:0]
GOENB[5:2]
GPIOL[1:0]
GPIOL[5:2]
GPIODR[5:0]
HSPTV
IBS1
IBS2
IDF1[3:0]
IDF2[3:0]
MCP1
DAC gain control
DAC termination sense
21h
20h
1Fh
1Eh
6Eh
1Eh
6Dh
6Ch
1Fh
1Fh
1Ch
1Fh, 21h
53h
1Ch
Decode embedded sync (TV-Out data only)
Direction control for GPIO pins
Direction control for GPIO pins
Read or Write Data for GPIO pins
Read or Write Data for GPIO pins
GPIO Driver Type – Open Drain or TTL
H sync polarity control TV
Input buffer type select for D1
Input Buffer type select for D2
Input Data Format for D1
Input Data Format for D2
XCLK Polarity Control for D1
XCLK Polarity Control for D2
P-Out 1X, 2X select
MCP2
PCM
1Ch
1Ch
POUTE
P-Out enable
1Eh
POUTP
P-Out clock polarity
1Eh
PTSEL[1:0]
SENSE
Control data path from D1 and D2 to TV and/or or LVDS blocks
TV Sense
03h
20h
SHF[2:0]
SYNCO[1:0]
SYOTV
VSPTV
XCM1
K3 Divider Selection
22h
21h
1Fh
1Fh
1Ch
1Ch
1Dh
53h
21h, 20h
Enables/selects sync output for Scart and bypass modes
H/V sync direction control (for TV-Out modes only)
V sync polarity control for TV
XCLK 1X / 2X select for D1
XCLK 1X / 2X select for D2
Delay adjust between XCLK and D1[11:0]
Delay adjust between XCLK and D2[11:0]
Crystal oscillator adjustments
XCM2
X1CMD[3:0]
X2CMD[3:0]
XOSC[2:0]
32
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CH7019B
LVDS CONTROLS
BGLMT[7:0]
BKLEN
FRSTB
LDD
LDEN[1:0]
LDM2D
LEOSWP
L1ODA[2:0]
L2ODA[2:0]
LODP
LODPE
LODST
LPCP[2:0]
LPFBD[3:0]
LPFFD[1:0]
LPFORC
Address
Bang Limit control of internal LVDS FIFO over/under run
Backlight enable
FIFO Reset Enable
LVDS Dithering Defeat
LVDS Output Driver enable
7Fh
66h
76h
64h
73h
64h
64h
74h
74h
74h
74h
75h
73h
71h
71h
66h
66h
76h
78h
66h
78h
76h
76h
72h
72h
66h
64h
66h
LVDS Dithering Mode – 2D
Odd/even sample output swap on LVDS link
LVDS Output Driver Amplitude control for bank 1
LVDS Output Driver Amplitude control for bank 2
LVDS Output Driver Pull-down
LVDS Output Driver Pre-emphasis
LVDS Output Driver Source Termination control
LVDS PLL Charge pump control
LVDS PLL feed back divider controls
LVDS PLL feed forward divider controls
Bypass LVDS PLL Lock Detect Sentry
Enable Bypass of LVDS PLL Lock Detect
LVDS PLL Loop Filter Resistor Value
LVDS PLL Loop Filter Capacitor Value
LVDS PLL Lock – read only register
LVDS PLL phase detector trim
LVDS PLL Power Down
LVDS PLL Reset
LVDS PLL post scale divider controls
LVDS PLL VCO frequency range controls
Bypass Sync Detection
LPLEN
LPLF[2:0]
LPLF[4:3]
LPLOCK
LPPD[4:0]
LPPDN
LPPRB
LPPSD[1:0]
LPVCO[3:0]
LSYNCEN
LVDSDC
SYNCST
LVDS Dual Channel Select
HSYNC and VSYNC stability status
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33
CHRONTEL
CH7019B
TV-OUT CONTROLS
BL[7:0]
Address
07h
TV-Out Black level control
BLKEN
CBW
Black Level control register update
Chroma video bandwidth
1Dh
02h
CE[2:0]
TV-Out contrast enhancement
08h
CFF[1:0]
CFRB
CIV[25:0]
CIVC[1:0]
CIVEN
Chroma flicker filter setting
01h
02h
10h-13h
10h
10h
Chroma sub-carrier free run (bar) control
Calculated sub-carrier increment value read out
Calculated sub-carrier control (hysteresis)
Calculated sub-carrier enable (was called ACIV)
CVBS DAC receives black&white (S-Video) signal
Defeat External Vsync
CVBW
DVS
02h
47h
FSCI[32:0]
HP[8:0]
IR[2:0]
M/S*
M[8:0]
MEM[2:0]
N[9:0]
PALN
PEDL[7:0]
PEDLEN
PLLCAP
PLLCPI
SAV[8:0]
SR[2:0]
Sub-carrier generation increment value (when CIVEN=0)
TV-Out horizontal position control
Input data resolution (when used for TV-Out)
TV-Out PLL reference input control
TV-Out PLL M divider
Memory sense amp reference adjust
TV-Out PLL N divider
Select PAL-N when in a CIV mode
Pedestal level register
Pedestal Enable
TV-Out PLL Capacitor Control
TV-Out PLL Charge Pump control settings
Horizontal start of active video
TV-Out scaling ratio
0Ch-0Fh
05h, 03h
00h
1Ch
0Ah, 09h
09h
0Bh, 09h
10h
4Fh
23h
09h
09h
04h, 03h
00h
TE[2:0]
Text enhancement
03h
VBID
Vertical blanking interval defeat
TV-Out video format (s-video & composite, YPrPb or RGB)
TV-Out video standard
TV-Out vertical position control
Composite video luma bandwidth
Luma text enhancement flicker filter setting
Luma flicker filter setting (incorporates old FLFF control bit)
S-Video luma bandwidth
02h
01h
00h
06h, 03h
02h
01h
01h
02h
VOF[1:0]
VOS[1:0]
VP[8:0]
YCV[1:0]
YFFH[1:0]
YFFL[1:0]
YSV[1:0]
3.2 Non-Macrovision Control Registers Description
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CH7019B
Table 17: Non-Macrovision Serial Port Register Map
Register
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
47h
48h
49h
4Ah
4Bh
Bit 7
IR2
Bit 6
IR1
Bit 5
IR0
Bit 4
VOS1
CFF0
CBW
HP8
SAV4
HP4
VP4
Bit 3
VOS0
YFFH1
YSV1
VP8
SAV3
HP3
VP3
Bit 2
SR2
Bit 1
SR1
Bit 0
SR0
VOF1
VBID
PTSEL1
SAV7
HP7
VOF0
CFRB
PTSEL0
SAV6
HP6
CFF1
CVBW
SAV8
SAV5
HP5
YFFH0
YSV0
TE2
SAV2
HP2
VP2
BL2
CE2
M8
YFFL1
YCV1
TE1
SAV1
HP1
VP1
BL1
CE1
PLLCPI
M1
YFFL0
YCV0
TE0
SAV0
HP0
VP0
BL0
CE0
PLLCAP
M0
VP7
BL7
VP6
BL6
VP5
BL5
BL4
BL3
MEM2
M7
N7
MEM1
M6
N6
MEM0
M5
N5
N9
M4
N4
N8
M3
N3
M2
N2
N1
N0
FSCI31
FSCI23
FSCI15
FSCI7
STFDEN1
CIV23
CIV15
CIV7
FSCI30
FSCI22
FSCI14
FSCI6
STFDEN0
CIV22
CIV14
CIV6
FSCI29
FSCI21
FSCI13
FSCI5
CIV25
CIV21
CIV13
CIV5
FSCI28
FSCI20
FSCI12
FSCI4
CIV24
CIV20
CIV12
CIV4
FSCI27
FSCI19
FSCI11
FSCI3
CIVC1
CIV19
CIV11
CIV3
FSCI26
FSCI18
FSCI10
FSCI2
CIVC0
CIV18
CIV10
CIV2
CLKDETD
MCP1
X1CMD2
FSCI25
FSCI17
FSCI9
FSCI1
PALN
CIV17
CIV9
CIV1
FSCI24
FSCI16
FSCI8
FSCI0
CIVEN
CIV16
CIV8
CIV0
BGBST
IBS2
MCP2
XCM2
M/S*
X1CMD3
PCM
XCM1
BLKEN
GOENB0
DES
XOSC2
XOSC0
X1CMD1
POUTE
IDF11
DACT0
DACG0
BCO1
X1CMD0
POUTP
IDF10
SENSE
DACBP
BCO0
GOENB1
IBS1
GPIOL1
SYOTV
GPIOL0
VSPTV
DACT3
SYNCO1
BCOEN
HSPTV
DACT2
SYNCO0
BCOP
IDF12
DACT1
DACG1
BCO2
XOSC1
DVS
IDF13
PEDLEN
TVPLLR
TV
VID5
DID5
ResetIB
DACPD3
VID4
ResetDB
DACPD2
VID3
TSTP1
DACPD0
VID1
TSTP0
TVPD
VID0
DID0
DACPD1
VID2
DID2
VID7
DID7
VID6
DID6
DID4
DID3
DID1
4Fh
53h
5Ch
60h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
71h
72h
73h
74h
75h
76h
78h
7Fh
PEDL7
X2CMD3
C5GP2
PEDL6
X2CMD2
C5GP1
STFDS0
LVDSPD
PEDL5
X2CMD1
C5GP0
PEDL4
X2CMD0
PSR
PEDL3
IDF23
PEDL2
IDF22
PEDL1
IDF21
PEDL0
IDF20
STFDS1
LVDS24
C5GP3
LVDSDC
LDD
LA6RL
LPFORC
TPON3
TPBLE3
TPBLD3
TPOFF3
TPPWD3
GPIODR3
GPIOL5
GOENB5
LPFBD3
LPVCO3
LDEN0
LDM2D
LEOSWP
LCNTLE
LSYNCEN
TPON1
TPBLE1
TPBLD1
TPOFF1
TPPWD1
GPIODR1
GPIOL3
GOENB3
LPFBD1
LPVCO1
LPCP1
C5GP5
C5GP4
SYNCST
TPON6
TPBLE6
TPBLD6
TPOFF6
C4GP4
C4GP2
C4GP0
C3GP2
LCNTLF
PANEN
TPON0
BKLEN
TPON5
TPBLE5
TPBLD5
TPOFF5
TPPWD5
GPIODR5
C3GP5
LPLEN
TPON4
LPLOCK
TPON2
TPON7
TPON8
TPOFF8
TPOFF7
C4GP5
C4GP3
C4GP1
C3GP3
TPBLE4
TPBLD4
TPOFF4
TPPWD4
GPIODR4
C3GP4
TPBLE2
TPBLD2
TPOFF2
TPPWD2
GPIODR2
GPIOL4
GOENB4
LPFBD2
LPVCO2
LPCP2
TPBLE0
TPBLD0
TPOFF0
TPPWD0
GPIODR0
GPIOL2
GOENB2
LPFBD0
LPVCO0
LPCP0
C3GP1
C3GP0
LPFFD1
LPPSD1
DAS0
LPFFD0
LPPSD0
LDEN1
L2ODA1
DAS1
LODPE
LODP
LODST
FRSTB
L2ODA2
L2ODA0
L1ODA2
L1ODA1
L1ODA0
LPLF2
LPLF4
BGLMT6
LPLF1
LPLF3
BGLMT5
LPLF0
LPPD4
BGLMT4
LPPDN
LPPD3
BGLMT3
LPPRB
LPPD2
BGLMT2
LODPDB1
LPPD1
BGLMT1
LODPDB0
LPPD0
BGLMT0
BGLMT7
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35
CHRONTEL
CH7019B
3.3 Non-Macrovision Control Registers Description
Display Mode Register
Symbol:
Address:
Bits:
DM
00h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL
IR2
IR1
IR0
VOS1
VOS0
SR2
SR1
SR0
:
TYPE:
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
R/W
0
R/W
1
R/W
0
DEFAUL
Register DM provides programmable control of the CH7019 VGA to TV display mode, including input resolution
(IR[2:0]), video output standard (VOS[1:0]), and scaling ratio (SR[2:0]). The mode of operation is determined according
to Table 18 below. Entries in which the output standard is shown as PAL, PAL-B,D,G,H,I,N,NC can be supported
through proper selection of the chroma sub-carrier. Entries in which the output standard is shown as NTSC, NTSC-M,J
and PAL-M can be supported through proper selection of VOS[1:0] and chroma sub-carrier.
Table 18: Display Modes
Mode
IR[2:0]
VOS
[1:0]
SR[2:0] Input Data
Format
Total
Pixels/Line
x Total
Output
Standard
[TV
Scaling
Percent
Overscan
Pixel Clock (MHz)
(Active
Lines/Frame
Video)
Standard]
0
1
2
3
4
5
6
7
000
000
000
000
001
001
001
001
010
010
010
010
010
011
011
011
011
011
011
100
100
100
101
101
101
110
110
110
110
110
110
00
00
01
01
00
00
01
01
00
00
01
01
01
00
00
00
01
01
01
01
01
01
00
00
00
00
00
00
01
01
01
000 512x384
001 512x384
000 512x384
001 512x384
000 720x400
001 720x400
000 720x400
001 720x400
000 640x400
001 640x400
000 640x400
001 640x400
010 640x400
000 640x480
001 640x480
011 640x480
001 640x480
010 640x480
011 640x480
001 720x480
010 720x480
011 720x480
001 720x576
011 720x576
100 720x576
001 800x600
011 800x600
100 800x600
110 800x600
111 800x600
101 800x600
840x500
840x625
800x420
784x525
1125x500
1152x625
945x420
936x525
1000x500
1008x625
840x420
832x525
840x600
840x500
840x625
840x750
784x525
784x600
800x630
882x525
882x600
900x630
882x625
900x750
900x875
944x625
960x750
960x875
1040x700
1064x750
1040x840
PAL
PAL
NTSC
NTSC
PAL
5/4
1/1
5/4
1/1
5/4
1/1
5/4
1/1
5/4
1/1
5/4
1/1
7/8
5/4
1/1
5/6
1/1
7/8
5/6
1/1
7/8
5/6
1/1
5/6
5/7
1/1
5/6
5/7
¾
-17
-33
0
-20
-13
-30
+4
-16
-13
-30
+4
-17
-27
+4
-17
-30
0
-13
-18
0
-13
-18
0
-18
-30
+4
21.000000
26.250000
20.139860
24.671329
28.125000
36.000000
23.790210
29.454545
25.000000
31.500000
21.146854
26.181819
30.209791
21.000000
26.250000
31.500000
24.671329
28.195805
30.209790
27.755245
31.720280
33.986015
27.562500
33.750000
39.375000
29.500000
36.000000
42.000000
43.636364
47.832169
52.363637
PAL
NTSC
NTSC
PAL
8
9
PAL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NTSC
NTSC
NTSC
PAL
PAL
PAL
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
PAL
PAL
PAL
PAL
PAL
-14
-27
-6
-14
-22
PAL
NTSC
NTSC
NTSC
7/10
5/8
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CHRONTEL
CH7019B
31
32
33
34
35
36
371
381
39
40
41
42
43
44
45
46
47
111
111
111
111
111
111
101
100
001
010
011
100
100
100
101
101
101
00
00
00
01
01
01
00
01
01
01
00
01
01
01
00
00
00
100 1024x768 1400x875
PAL
PAL
PAL
5/7
5/8
5/9
5/8
5/9
1 / 2
1/1
1/1
25/21
25/21
25/21
1/1
-4
-16
-25
0
-10
-20
0
0
-1
-1
-1
61.250000
70.000000
78.750000
58.405595
65.706295
73.510491
13.500000
13.500000
23.790210
21.146854
21.000000
27.692308
28.195805
33.230770
27.750000
33.000000
38.500000
1400x1000
101 1024x768
110 1024x768
1400x1125
101 1024x768 1160x840
110 1024x768 1160x945
NTSC
NTSC
NTSC
PAL
NTSC
NTSC
NTSC
PAL
NTSC
NTSC
NTSC
PAL
1168x1050
864x625
858x525
900x441
800x441
800x525
880x525
784x600
880x630
888x625
880x750
880x875
111 1024x768
000 720x576
000 720x480
111 720x400
111 640x400
111 640x480
101 720x480
110 720x480
111 720x480
101 720x576
110 720x576
111 720x576
0
7/8
5/6
1/1
5/6
-13
-18
0
-18
-30
PAL
PAL
5/7
1 These DVD modes operate with interlaced input. Scan conversion and flicker filter are bypassed.
Table 19: Video Output Standard Selection
VOS[1:0]
00
01
10
11
Output Format
PAL
NTSC
PAL-M
NTSC-J
Flicker Filter Register
Symbol:
Address:
Bits:
FF
01h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
VOF1
VOF0
CFF1
CFF0
R/W
0
YFFH1 YFFH0 YFFL1
YFFL0
TYPE:
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
R/W
1
R/W
1
DEFAULT:
YFFL[1:0] (bits 1-0) of register FF control the filter used in the scaling and flicker reduction block applied to the non-
text portion (low frequency) of the luminance signal as shown in Table 20 below.
YFFH[1:0] (bits 3-2) of register FF control the filter used in the scaling and flicker reduction block applied to the text
portion (high frequency) of the luminance signal as shown in Table 20 below.
Table 20: Luma Flicker Filter Control
YFFH and YFFL Flicker Filter Settings (lines)
Scaling Ratio
5/4
00
2
01
3
10
3
11
3
1/1, 7/8, 5/6, 3/4, 5/7, 7/10
2
3
4
5
5/8
25/21
5/9
½
2
2
3
3
3
3
4
5
4
6
5
5
6
6
6
7
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37
CHRONTEL
CH7019B
CFF[1:0] (bits 5-4) of register FF control the filter used in the scaling and flicker reduction block applied to the
chrominance signal as shown in Table 21 below. A setting of ‘11’ applies a dot crawl reduction filter which can reduce
the ‘hanging dots’ effect of an NTSC composite video signal when displayed on a TV with a comb filter.
Table 21: Chroma Flicker Filter Control
CFF Flicker Filter Settings (lines)
Scaling Ratio
5/4
00
2
01
3
10
3
11
3
1/1, 7/8, 5/6, 3/4, 5/7, 7/10
2
3
4
5
5/8
25/21
5/9
½
2
2
3
3
3
3
4
5
4
4
5
5
5
6
6
7
VOF[1:0] (bits 7-6) of register FF control the video output format. Must be set per the table below:
Table 22: TV Output Configurations
VOF1
VOF0
TV Output Configuration
YCrCb
Composite, S-Video
YPrPb (480I component HDTV set)
SCART + Composite
0
0
1
1
0
1
0
1
For the TV out DAC by-pass for RGB out, refer to DACBP (bit0 of Register 21h).
Refer to Table 12 in section 2.3.5 for TV Output DAC configuration.
Video Bandwidth Register
Symbol:
Address:
Bits:
VBW
02h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
VBID
CFRB
CVBW
CBW
YSV1
YSV0
YCV1
R/W
1
YCV0
TYPE:
R/W
1
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
0
DEFAULT:
YCV[1:0] (bits 1-0) of register VBW control the filter used to limit the bandwidth of the luma signal in the CVBS output
signal. A table of –3dB bandwidth values is given in Table 23 below.
YSV[1:0] (bits 3-2) of register VBW control the filter used to limit the bandwidth of the luma signal in the S-Video
output signal. A table of –3dB bandwidth values is given in Table 23 below.
CBW (bit 4) of register VBW controls the filter used to limit the bandwidth of the chroma signal in the CVBS and S-
Video output signals. A table of –3dB bandwidth values is given in Table 23 below.
38
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CH7019B
Table 23: Video Bandwidth
Mode
CBW
YSV[1:0] and YCV[1:0]
0
1
00
01
10
11
0
1
2
3
4
5
6
7
0.620
0.775
0.529
0.648
0.831
1.060
0.703
0.870
0.738
0.930
0.624
0.773
0.892
0.620
0.775
0.930
0.648
0.740
0.793
0.729
0.833
0.892
0.724
0.886
1.030
0.774
0.945
1.100
0.859
0.942
1.030
0.804
0.919
1.030
0.767
0.862
0.965
0.709
0.466
0.703
0.624
0.620
0.727
0.833
0.892
0.728
0.866
1.010
0.856
1.070
0.730
0.894
1.150
1.470
0.970
1.200
1.020
1.280
0.862
1.070
1.230
0.856
1.070
1.280
0.894
1.020
1.100
1.010
1.150
1.230
0.999
1.220
1.430
1.070
1.310
1.520
1.190
1.300
1.420
1.110
1.270
1.430
1.060
1.190
1.330
0.979
0.643
0.970
0.862
0.856
1.003
1.150
1.231
1.005
1.196
1.395
2.300
2.880
1.960
2.410
3.080
3.950
2.610
3.230
2.740
3.460
2.320
2.870
3.310
2.300
2.880
3.460
2.410
2.750
2.950
2.710
3.090
3.310
2.690
3.290
3.840
2.880
3.510
4.100
3.190
3.500
3.830
2.990
3.410
3.840
2.850
3.200
3.580
2.630
1.730
2.610
2.320
2.300
2.696
3.090
3.309
2.702
3.213
3.748
2.690
3.360
2.290
2.810
3.600
4.610
3.040
3.770
3.200
4.030
2.710
3.350
3.870
2.690
3.360
4.030
2.810
3.210
3.440
3.160
3.610
3.870
3.140
3.840
4.480
3.360
4.100
4.780
3.720
4.080
4.470
3.480
3.980
4.480
3.320
3.740
4.180
3.070
2.020
3.040
2.710
2.690
3.153
3.610
3.870
3.160
3.757
4.384
3.540
4.430
3.020
3.700
4.750
6.080
4.010
4.970
4.220
5.320
3.570
4.420
5.100
3.540
4.430
5.320
3.700
4.230
4.530
4.160
4.760
5.100
4.130
5.060
5.910
4.430
5.400
6.300
4.910
5.380
5.890
4.590
5.250
5.910
4.380
4.930
5.510
4.050
2.660
4.010
3.570
3.540
4.149
4.760
5.093
4.158
4.945
5.769
5.880
7.350
5.010
6.140
7.870
10.100
6.660
8.240
7.000
8.820
5.920
7.330
8.450
5.880
7.350
8.820
6.140
7.010
7.510
6.900
7.890
8.450
6.860
8.400
9.790
7.340
8.960
10.400
8.140
8.920
9.770
7.620
8.710
9.790
7.260
8.170
9.140
6.720
4.410
6.660
5.920
5.880
6.892
7.890
8.459
6.907
8.213
9.582
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
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Rev. 2.4, 12/18/2006
39
CHRONTEL
CH7019B
CVBW (bit 5) of register VBW controls the chroma component of the CVBS signal. CVBW = ‘0’ disables the chroma
signal being added to the CVBS signal, CVBW = ‘1’ enables the chroma signal being added to the CVBS signal.
CFRB (bit 6) of register VBW controls whether the chroma sub-carrier free-runs, or is locked to the video signal. A ‘1’
causes the sub-carrier to lock to the TV vertical rate, and should be used when the CIVEN bit (register 10h) is set to ‘0’.
A ‘0’ causes the sub-carrier to free-run, and should be used when the CIVEN bit is set to ‘1’.
VBID (bit 7) of register VBW controls the vertical blanking interval defeat function. A ‘1’ in this register location
forces the flicker filter to minimum filtering during the vertical blanking interval. A ‘0’ in this location causes the flicker
filter to remain at the same setting inside and outside of the vertical blanking interval.
Text Enhancement Register
Symbol:
Address:
Bits:
TE
03h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
PTSEL1 PTSEL0
SAV8
HP8
VP8
TE2
TE1
TE0
TYPE:
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
DEFAULT:
TE[2:0] (bits 2-0) of register TE control the text enhancement circuitry within the CH7019. A value of ‘000’ minimizes
the enhancement feature, while a value of ‘111’ maximizes the enhancement.
SAV8, HP8 and VP8 (bits 5-3) of register TE contain the MSB values for the start of active video, horizontal position
and vertical position controls. They are described in detail in the SAV (address 04h), HP (address 05h) and VP (address
06h) register descriptions.
PTSEL[1:0] (bits 7-6) of register TE control the data path from D1[11:0] and D2[11:0] inputs to internal TV and LVDS
blocks. These bits allow one to swap the input data paths to internal TV or LVDS blocks. The default setting which
routes D1 input to TV block and D2 input to LVDS block is recommended.
PTSEL1
PTSEL0 Description
0
0
1
1
0
1
0
1
D1 input is routed to both internal TV and LVDS block
D1 input is routed to LVDS and D2 input is routed to TV block
D1 input is routed to TV and D2 input is routed to LVDS block
D2 input is routed to both internal TV and LVDS block
Start of Active Video Register
Symbol:
Address:
Bits:
SAV
04h
8
BIT:
7
SAV7
R/W
0
6
SAV6
R/W
1
5
SAV5
R/W
0
4
SAV4
R/W
1
3
SAV3
R/W
0
2
SAV2
R/W
0
1
SAV1
R/W
0
0
SAV0
R/W
0
SYMBOL:
TYPE:
DEFAULT:
40
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CHRONTEL
CH7019B
Register SAV controls the delay, in pixel increments, from leading edge of horizontal sync to start of active video. The
entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus SAV[8] contained in the Text Enhancement
register (03h, bit 5). This is decoded as a whole number of pixels, which can be set anywhere between 0 and 511 pixels.
Therefore, in any 2X clock mode the number of 2X clocks from the leading edge of Hsync to the first active data must
be a multiple of two clocks.
Horizontal Position Register
Symbol:
Address:
Bits:
HP
05h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
HP7
R/W
0
HP6
R/W
1
HP5
R/W
0
HP4
R/W
1
HP3
R/W
0
HP2
R/W
0
HP1
R/W
0
HP0
R/W
0
DEFAULT:
Register HP is used to shift the displayed TV image in a horizontal direction ( left or right) to achieve a horizontally
centered image on screen. The entire bit field, HP[8:0], is comprised of this register HP[7:0] plus HP[8] contained in the
Text Enhancement register (03h, bit 4). Increasing values move the displayed image position right, and decreasing values
move the image position left.
Vertical Position Register
Symbol:
Address:
Bits:
VP
06h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
VP7
R/W
0
VP6
R/W
0
VP5
R/W
0
VP4
R/W
0
VP3
R/W
0
VP2
R/W
0
VP1
R/W
0
VP0
R/W
0
DEFAULT:
Register VP is used to shift the displayed TV image in a vertical direction (up or down) to achieve a vertically centered
image on screen. The entire bit field, VP[8:0], is comprised of this register VP[7:0] plus VP[8] contained in the Text
Enhancement register (03h, bit 3). The value represents the TV line number (relative to the VGA vertical sync) used to
initiate the generation and insertion of the TV vertical interval (i.e. the first sequence of equalizing pulses). Increasing
values delay the output of the TV vertical sync, causing the image position to move up on the TV screen. Decreasing
values, therefore, move the image position DOWN. Each increment moves the image position by one TV line
(approximately 2 input lines). The maximum value that should be programmed into VP[8:0] is the number of TV lines
per field minus one half (262 or 312). When panning the image up, the number should be increased until (TVLPF-1/2) is
reached, the next step should be to reset the register to zero. When panning the image down the screen, decrement the
VP[8:0] value until the value zero is reached. The next step should set the register to TVLPF-1/2, and then decrement
for further changes.
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41
CHRONTEL
CH7019B
Black Level Register
Symbol:
Address:
Bits:
BL
07h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
BL7
R/W
1
BL6
R/W
0
BL5
BL4
BL3
BL2
BL1
BL0
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
DEFAULT:
Register BL controls the black level. The luminance data is added to this black level, which must be set between 65 and
170. When the input data format is 0 through 3 or 5 the default values are 131 for NTSC and PAL-M with DACG[1:0]
(register 21h) = ‘00’ and 109 for PAL with DACG[1:0]= ’01’ and 102 for NTSC-J with DACG[1:0] = ‘01’. When the
input data format is 4, 6 or 7 the default values are 113 for NTSC and PAL-M with DACG[1:0] = ‘10’, 94 for PAL with
DACG[1:0] = ‘11’ and 88 for NTSC-J with DACG[1:0] = ‘11’. See also the description for the BLKEN bit (register
1Dh, bit 6).
Contrast Enhancement Register
Symbol:
Address:
Bits:
CE
08h
3
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved Reserved Reserved Reserved
CE2
CE1
CE0
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
DEFAULT:
CE[2:0] (bits 2-0) of register CE control the contrast enhancement feature of the CH7019, according to Figure 20 below.
A setting of ‘0’ results in reduced contrast, a setting of ‘1’ leaves the image contrast unchanged, and values beyond ‘1’
result in increased contrast. [Note: The straight line denotes Yout = Yin and therefore no enhancement.]
512
444
376
308
<i>
Yout
n
240
256
172
104
36
32
32
36
104
172
240
Yin
308
376
444
512
n
Figure 20: Contrast Enhancement of the CH7019
42
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Rev. 2.4, 12/18/2006
CHRONTEL
CH7019B
TV PLL Control Register
Symbol:
Address:
Bits:
TPC
09h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
MEM2
MEM1
MEM0
N9
N8
M8
PLLCPI PLLCAP
TYPE:
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
PLLCAP (bit 0) of register TPC controls the TV PLL loop filter capacitor. A recommended listing of PLLCAP settings
versus mode is given in Table 24 below.
Table 24: PLLCAP setting vs. Display Mode
Mode
PLLCAP
Mode
PLLCAP
Value
Value
0
1
2
3
4
5
6
7
8
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
1
1
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
1
0
1
1
1
0
1
1
1
1
0
0
0
1
1
0
0
1
0
0
0
0
0
1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
PLLCPI (bit 1) of register TPC should be left at the default value.
M8 and N[9:8] (bits 4-2) of register TPC contain the MSB values for the TV PLL divider ratio’s. These controls are
described in detail in the PLLM (address 0Ah) and PLLN (address 0Bh) register descriptions.
MEM[0] (bit 5) of register TPC controls the input latch bias current level. The default value is recommended.
MEM[2:1] (bits 7-6) of register TPC control the memory sense amp reference level. The default value is recommended.
201-0000-048
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43
CHRONTEL
CH7019B
TV PLL M Value Register
Symbol:
Address:
Bits:
PLLM
0Ah
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
M7
M6
M5
M4
M3
M2
M1
M0
TYPE:
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DEFAULT:
Register PLLM controls the division factor applied to the 14.31818MHz frequency reference clock before it is input to
the TV PLL phase detector when the CH7019 is operating in clock master mode. The entire bit field, M[8:0], is
comprised of this register M[7:0] plus M[8] contained in the TV PLL Control register (09h, bit2). In slave mode, an
external pixel clock is used instead of the 14.31818MHz frequency reference, but the division factor is also controlled by
M[8:0]. In slave mode, the value of ‘M’ is internally set to 1. A table of values (Table 25) versus display mode is given
following the PLLN register description.
TV PLL N Value Register
Symbol:
Address:
Bits:
PLLN
0Bh
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
N7
N6
N5
N4
N3
N2
N1
N0
TYPE:
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
DEFAULT:
Register PLLN controls the division factor applied to the VCO output before being applied to the PLL phase detector,
when the CH7019 is operating in clock master mode. The entire bit field, N[9:0], is comprised of this register N[7:0]
plus N[9:8] contained in the TV PLL Control register (09h, bits 3 and 4). In slave mode, the value of ‘N’ is internally set
to 1. The pixel clock generated in clock master modes is calculated according to the equation Fpixel = Fref * [(N+2) /
(M+2)]. When using a 14.31818MHz frequency reference, the required M and N values for each mode are shown in
Table 25 below:
Table 25: TV PLL M and N values vs. Display Mode
Mode VGA Resolution,
TV Standard,
N
N
M
M
10-bits 10-bits
(dec)
20
9
126
110
53
86
106
70
9-bits 9-bits
(dec) (hex)
13
4
89
63
26
33
63
33
61
Scaling Ratio
(hex)
0x14
0x09
0x7E
0x6E
0x35
0x56
0x6A
0x46
0x6C
0
1
2
3
4
5
6
7
8
512x384, PAL, 5:4
512x384, PAL, 1:1
512x384, NTSC, 5:4
512x384, NTSC, 1:1
720x400, PAL, 5:4
720x400, PAL, 1:1
720x400, NTSC, 5:4
720x400, NTSC, 1:1
640x400, PAL, 5:4
0x0D
0x04
0x59
0x3F
0x1A
0x21
0x3F
0x21
0x3D
108
44
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Rev. 2.4, 12/18/2006
CHRONTEL
CH7019B
Mode VGA Resolution,
TV Standard,
N
N
M
M
10-bits 10-bits
(dec)
9-bits 9-bits
(dec) (hex)
Scaling Ratio
(hex)
0x09
0x5E
0x40
0xBE
0x14
0x09
0x09
0x6E
0x7E
0xBE
0x7C
0x8E
0xD6
0x4B
0x1F
0x09
0x287
0x56
0x2A
0x3E
0x12E
0x7E
0x4B
0x2A
0x14
0x235
0x14D
0x395
0x1F
0x1F
0x6A
0x5E
0x14
0xAE
0x7E
0x135
0x195
0xF0
0x77
9
640x400, PAL, 1:1
640x400, NTSC, 5:4
640x400, NTSC, 1:1
640x400, NTSC, 7:8
640x480, PAL, 5:4
640x480, PAL, 1:1
640x480, PAL, 5:6
640x480, NTSC, 1:1
640x480, NTSC, 7:8
640x480, NTSC, 5:6
720x480, NTSC, 1:1
720x480, NTSC, 7:8
720x480, NTSC, 5:6
720x480, PAL, 1:1
720x480, PAL, 5:6
720x480, PAL, 5:7
800x600, PAL, 1:1
800x600, PAL, 5:6
800x600, PAL, 5:7
800x600, NTSC, 3:4
800x600, NTSC, 7:10
800x600, NTSC, 5/8
1024x768, PAL, 5:7
1024x768, PAL, 5:8
1024x768, PAL, 5:9
1024x768, NTSC, 5:8
1024x768, NTSC, 5:9
1024x768, NTSC, 1:2
720x576, PAL, 1:1
720x480, NTSC, 1:1
720x480, NTSC, 1:1
640x400, NTSC, 25:21
640x480, PAL,25:21
720x480, NTSC, 1:1
720x480, NTSC, 7:8
720x480, NTSC, 5:6
720x576, PAL, 1:1
720x576, PAL, 5:6
720x576, PAL, 5:7
9
94
62
190
20
3
0x03
0x3F
0x21
0x59
0x0D
0x04
0x03
0x3F
0x3F
0x59
0x3F
0x3F
0x59
0x26
0x0C
0x02
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
63
33
89
13
4
9
9
3
110
126
190
124
142
214
75
31
9
647
86
42
63
63
89
63
63
89
38
12
2
313 0x139
33
13
19
89
33
16
7
0x21
0x0D
0x13
0x59
0x21
0x10
0x07
0x02
62
302
126
75
42
20
565
333
917
31
31
106
94
2
137 0x89
71 0x47
177 0xB1
33
33
63
63
13
89
63
0x21
0x21
0x3F
0x3F
0x0D
0x59
0x3F
20
174
126
309
405
240
119
132 0x84
208 0xD0
103 0x67
43
0x2B
201-0000-048
Rev. 2.4, 12/18/2006
45
CHRONTEL
CH7019B
Sub-carrier Value Register
Symbol:
Address:
Bits:
FSCI
0Ch –0Fh
8 each
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
FSCI#
FSCI#
FSCI#
FSCI#
FSCI#
FSCI#
FSCI#
FSCI#
TYPE:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DEFAULT:
Registers FSCI contain a 32-bit value which is used as an increment value for the ROM address generation circuitry
when CIVEN=0. The bit locations are specified as follows:
Register
0Ch
0Dh
0Eh
0Fh
Contents
FSCI[31:24]
FSCI[23:16]
FSCI[15:8]
FSCI[7:0]
When the CH7019 is used in the clock master mode, the tables below should be used to set the FSCI registers. When
using these values, the CIVEN bit in register 10h should be set to ‘0’, and the CFRB bit in register 02h should be set to
‘1’.
Table 26: FSCI Values (525-Line TV-Out Modes)
Mode
NTSC
“Normal Dot
Crawl”
NTSC
“Normal Dot
Crawl”
NTSC
“No Dot
Crawl”
NTSC
“No Dot
Crawl”
PAL-M
“Normal Dot
Crawl”
PAL-M
“Normal Dot
Crawl”
(dec)
(hex)
(dec)
(hex)
(dec)
(hex)
2
3
6
7
763,363,328
623,153,737
574,429,782
463,962,517
646,233,505
521,957,831
452,363,454
623,153,737
545,259,520
508,908,885
553,914,433
484,675,129
452,363,454
469,762,048
428,554,851
391,468,373
526,457,468
467,962,193
418,281,276
569,408,543
574,429,782
646,233,505
553,173,329
484,675,129
462,644,441
0x2D800000
0x25249249
0x223D1A56
0x1BA78195
0x2684BDA1
0x1F1C71C7
0x1AF684BE
0x25249249
0x20800000
0x1E555555
0x21041041
0x1CE38E39
0x1AF684BE
0x1C000000
0x198B3A63
0x17555555
0x1F611A7C
0x1BE48951
0x18EE773C
0x21F07C1F
0x223D1A56
0x2684BDA1
0x20F8C151
0x1CE38E39
0x1B9364D9
763,366,524
623,156,346
574,432,187
463,964,459
646,236,211
521,960,019
452,365,347
623,156,346
545,261,803
508,911,016
553,916,752
484,677,158
452,365,347
469,764,015
428,556,645
391,470,012
526,459,671
467,964,152
418,283,027
569,410,927
574,432,187
646,236,211
555,175,654
484,677,158
462,646,378
0x2D800C7C
0x25249C7A
0x223D23BB
0x1BA7892B
0x2684C833
0x1F1C7A53
0x1AF68C23
0x25249C7A
0x208008EB
0x1E555DA8
0x21041950
0x1CE39626
0x1AF68C23
0x1C0007AF
0x198B4165
0x17555BBC
0x1F612317
0x1BE490F8
0x18EE7E13
0x21F0856F
0x223D23BB
0x2684C833
0x21174EE6
0x1CE39626
0x1B936C6A
762,524,467
622,468,953
573,798,541
463,452,668
645,523,358
521,384,251
451,866,351
622,468,953
544,660,334
508,349,645
553,305,736
484,142,519
451,866,351
469,245,826
428,083,911
391,038,188
525,878,943
467,447,949
417,821,626
568,782,819
573,798,541
645,523,358
554,563,249
484,142,519
462,136,041
0x2D733333
0x251A1F59
0x2233788D
0x1B9FB9FC
0x2679E79E
0x1F13B13B
0x1AEEEEEF
0x251A1F59
0x2076DB6E
0x1E4CCCCD
0x20FAC688
0x1CDB6DB7
0x1AEEEEEF
0x1BF81F82
0x19840AC7
0x174EC4EC
0x1F58469F
0x1BDCB08D
0x18E773BA
0x21E6EFE3
0x2233788D
0x2679E79E
0x210DF6B1
0x1CDB6DB7
0x1B8BA2E9
10
11
12
16
17
18
19
20
21
28
29
30
34
35
36
38
39
40
42
43
44
46
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CH7019B
Table 27: FSCI Values (625-Line TV-Out Modes)
MODE
PAL
PAL
PAL-N
PAL-N
“Normal Dot
Crawl”
“Normal Dot
Crawl”(hex)
0x300AE7C4
0x266F1FD0
0x23DF2EC2
0x1C065C87
0x285B149A
0x2007452D
0x300AE7C4
0x266F1FD0
0x2007452D
0x292DEB3A
0x21A13BD6
0x1CD357DC
0x26798C0C
0x1F872818
0x1B06225E
0x250FBA1B
0x206DC2D7
0x1CD357DC
0x2A098ACB
0x300AE7C4
0x28E6B08E
0x2264E5EC
0x1D7B0E38
“Normal Dot
Crawl”
“Normal Dot
Crawl”(hex)
0x26D0A975
0x1F0D545E
0x1CFB5FCF
0x16A462DA
0x209ACBC9
0x19E070F9
0x26D0A975
0x1F0D545E
0x19E070F9
0x21452389
0x1B2BF022
0x1749FF46
0x1F15C01E
0x1978EF35
0x15D55F52
0x1DF16CCB
0x1A333F2F
0x1749FF46
0x21F69446
0x26D0A975
0x210B9730
0x1BC9BF22
0x17D17F42
0
1
4
5
8
9
806,021,060
644,816,848
601,829,058
470,178,951
677,057,690
537,347,373
806,021,060
644,816,848
537,347,373
690,875,194
564,214,742
483,612,636
645,499,916
528,951,320
453,386,846
621,787,675
544,064,215
483,612,636
705,268,427
806,021,060
686,207,118
577,037,804
494,603,832
651,209,077
520,967,262
486,236,111
379,871,962
547,015,625
434,139,385
651,209,077
520,967,262
434,139,385
558,179,209
455,846,354
390,725,446
521,519,134
427,355,957
366,305,106
502,361,288
439,566,127
390,725,446
569,807,942
651,209,077
554,407,728
466,206,498
399,605,570
13
14
15
22
23
24
25
26
27
31
32
33
37
41
45
46
47
CIV Control Register
Symbol:
Address:
Bits:
CIVC
10h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
STFDEN1 STFDEN0 CIV25
CIV24
CIVC1
CIVC0
R/W
0
PALN
R/W
0
CIVEN
R/W
1
TYPE:
R/W
0
R/W
0
R
X
R
X
R/W
0
DEFAULT:
CIVEN (bit 0) of register CIVC controls whether the FSCI value is used to set the sub-carrier frequency, or the
automatically calculated (CIV) value. When the CIVEN value is ‘1’, the number calculated and present at the CIV
registers will automatically be used as the increment value for sub-carrier generation. Whenever this bit is set to ‘1’, the
CFRB bit should be set to ‘0’.
PALN (bit 1) of register CIVC forces the CIV algorithm to generate the PAL-N (Argentina) sub-carrier frequency when
it is set to ‘1’. When this bit is set to ‘0’, the VOS[1:0] value is used by the CIV algorithm to determine which sub-
carrier frequency to generate.
CIVC[1:0] (bits 3-2) of register CIVC control the hysteresis circuit which is used to calculate the CIV value. The default
value should be used.
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CH7019B
CIV[25:24] (bits 5-4) of register CIVC contain the MSB values for the calculated increment value (CIV) readout. This
is described in detail in the CIV (address 11h-13h) register description.
STFDEN0 (bit6) of register CIVC enables the FLD1 output on pin 62.
STFDEN0 = 0 => FLD1 pin high impedance
= 1 => Field output depending on the value of the STFDS0 bit in register 60h, bit 6.
STFDEN1 (bit6) of register CIVC enables the FLD2 output on pin 105.
STFDEN1 = 0 => FLD2 pin high impedance
= 1 => Field output depending on the value of the STFDS1 bit in register 60h, bit 7.
Calculated Increment Value Register
Symbol:
Address:
Bits:
CIV
11h –13h
8 each
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
CIV#
CIV#
CIV#
CIV#
CIV#
CIV#
CIV#
CIV#
TYPE:
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
DEFAULT:
Registers CIV contain the value that was calculated by the CH7019 as the sub-carrier increment value. The entire bit
field, CIV[25:0], is comprised of these three registers CIV[23:0] plus CIV[25:24] contained in the CIV Control register
(10h, bits 4 and 5). This value is used when the CIVEN bit is set to ‘1’. The bit locations are specified below.
Register
10h
11h
12h
13h
Contents
CIV[25:24]
CIV[23:16]
CIV[15:8]
CIV[7:0]
Bandgap Boost Register
Symbol:
Address:
Bits:
BGB
14h
2
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
BGBST Reserved Reserved Reserved Reserved CLKDETD Reserved Reserved
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
CLKDETD (bit 2) of register BGB controls the XCLK detection circuit. When CLKDETD is 1, the XCLK detection
circuit is turned off. When CLKDETD is 0, the XCLK detection circuit is turned on.
BGBST (bit 7) of register CB boost the bandgap voltage which controls the DAC output by 6% when set to 1. This has
the effect of boosting the DAC output by about 6%. The recommended value is 1.
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Clock Mode Register
Symbol:
Address:
Bits:
CM
1Ch
7
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved
R/W
0
IBS2
R/W
0
MCP2
XCM2
M/S*
MCP1
PCM
XCM1
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
XCM1 (bit 0) of register CM signifies the XCLK frequency for the D1 input. A value of ‘0’ is used when XCLK1 is at
the pixel frequency (dual edge clocking mode) and a value of ‘1’ is used when XCLK1 is twice the pixel frequency
(single edge clocking mode).
PCM (bit 1) of register CM controls the P-Out clock frequency. A value of ‘0’ generates a clock output at the pixel
frequency, while a value of ‘1’ generates a clock at twice the pixel frequency.
MCP1 (bit 2) of register CM controls the phase of the XCLK clock input for the D1 input. A value of ‘1’ inverts the
XCLK signal at the input of the device. This control is used to select which edge of the XCLK signal to use for latching
input data.
M/S* (bit 3) of register CM controls whether the device operates in master or slave clock mode. In master mode (M/S*
= ‘1’), the 14.31818MHz clock is used as a frequency reference in the TV PLL, and the M and N values are used to
determine the TV PLL’s operating frequency. In slave mode (M/S* = ‘0’) the XCLK input is used as a reference to the
TV PLL. The M and N TV PLL divider values are forced to one.
XCM2 (bit 4) of register CM signifies the XCLK frequency for the D2 input. A value of ‘0’ is used when XCLK2 is at
the pixel frequency (dual edge clocking mode) and a value of ‘1’ is used when XCLK3 is twice the pixel frequency
(single edge clocking mode).
MCP2 (bit 5) of register CM controls the phase of the XCLK clock input for the D2 input. A value of ‘1’ inverts the
XCLK signal at the input of the device. This control is used to select which edge of the XCLK signal to use for latching
input data.
IBS2 (bit 6) of register CM selects the data and clock input buffer type for the D2 data, this bit has to set to “1”
(differential clock and data type).
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Input Clock Register
Symbol:
Address:
Bits:
IC
1Dh
5
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved BLKEN Reserved Reserved X1CMD3 X1CMD2 X1CMD1 X1CMD0
TYPE:
R/W
0
R/W
1
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
DEFAULT:
X1CMD[3:0] (bits 3-0) of register IC control the delay applied to the XCLK1 signal before latching input data D1[11:0]
per the following table. 1 unit is approximately 70 ps worst case.
Table 28: Delay applied to XCLK1 before latching input data D1
X1CMD3 X1CMD2 X1CMD1 X1CMD0 Adjust phase of Clock relative to
Data
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 unit, XCLK1 ahead of Data
1 unit, XCLK1 ahead of Data
2 unit, XCLK1 ahead of Data
3 unit, XCLK1 ahead of Data
4 unit, XCLK1 ahead of Data
5 unit, XCLK1 ahead of Data
6 unit, XCLK1 ahead of Data
7 unit, XCLK1 ahead of Data
0 unit, XCLK1 behind Data
1 unit, XCLK1 behind Data
2 unit, XCLK1 behind Data
3 unit, XCLK1 behind Data
4 unit, XCLK1 behind Data
5 unit, XCLK1 behind Data
6 unit, XCLK1 behind Data
7 unit, XCLK1 behind Data
BLKEN (bit 6) of register IC controls the Black Level control register update during the vertical sync blanking period. A
value of ‘0’ disables the Black Level control register update. A value of ‘1’ enables the Black Level control register
update.
GPIO Control Register
Symbol:
Address:
Bits:
GPIO
1Eh
6
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
GOENB1 GOENB0 GPIOL1 GPIOL0 Reserved Reserved POUTE POUTP
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
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POUTP (bit 0) of register GPIO controls the polarity of the P-Out signal. A value of ‘0’ does not invert the clock at the
output pad.
POUTE (bit 1) of register GPIO enables the P-Out signal. A value of ‘1’ drives the P-Out clock signal out of the
P-Out pin. A value of ‘0’ disables the P-Out signal.
GPIOL[1:0] (bits 5-4) of register GPIO define the GPIO Read or Write Data bits [1:0]. The entire bit field is made up of
these bits GPIOL[1:0] plus GPIOL[5:2] contained in the GPIO Data register (address 6Dh, bits 3-0). Refer to the
description of the GPIOD register (6Dh) for more information.
GOENB[1:0] (bits 7-6) of register GPIO define the GPIO Direction Control bits [1:0]. The entire bit field is made up of
these bits GOENB[1:0] plus GOENB[5:2] contained in the GPIO Direction Control register (address 6Eh, bits 3-0).
Refer to the description of the GPIODC register (6Eh) for more information.
Input Data Format Register
Symbol:
Address:
Bits:
IDF
1Fh
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
IBS1
DES
SYOTV VSPTV HSPTV
IDF12
IDF11
IDF10
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
IDF1[2:0] (bits 2-0) of register IDF select the input data format for the D1 input. The entire bit field, IDF1[3:0], is
comprised of this register IDF1[2:0] plus IDF3 contained in the DAC Control Register (21h, bit5). See Section 3.2 for a
listing of available formats.
HSPTV (bit 3) of register IDF controls the horizontal sync polarity for TV. A value of ‘0’ defines the horizontal sync to
be active low, and a value of ‘1’ defines the horizontal sync to be active high.
VSPTV (bit 4) of register IDF controls the vertical sync polarity for TV. A value of ‘0’ defines the vertical sync to be
active low, and a value of ‘1’ defines the vertical sync to be active high.
SYOTV (bit 5) of register IDF controls the sync direction for TV. A value of ‘0’ defines sync to be input to the CH7019,
and a value of ‘1’ defines sync to be output from the CH7019. The CH7019 can only output sync signals when operating
as a VGA to TV encoder, not when operating as an LVDS transmitter.
DES (bit 6) of register IDF signifies when the CH7019 is to decode embedded sync signals present in the input data
stream instead of using the H and V pins. This feature is only available for input data formats # 4, 6 or 7. A value of ‘0’
selects the H and V pins to be used as the sync inputs, and a value of ‘1’ selects the embedded sync signal.
IBS1 (bit 7) of register IDF selects the data and clock input buffer type for the D1 data, this bit has to set to “1” (differential
clock and data type).
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Connection Detect Register
Symbol:
Address:
Bits:
CD
20h
6
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved XOSC2 Reserved DACT3 DACT2 DACT1 DACT0
SENSE
R/W
0
TYPE:
R/W
0
R/W
1
R
0
R
X
R
X
R
X
R
X
DEFAULT:
DACT[3:0] (bits 4-1) and SENSE (bit 0) of register CD provide a means to sense the connection of a TV to the four
DAC outputs. The status bits, DACT[3:0] correspond to the termination of the four DAC outputs. However, the values
contained in these status bits ARE NOT VALID until a sensing procedure is performed. Use of this register requires a
sequence of events to enable the sensing of outputs, then reading out the applicable status bits. The detection sequence
works as follows:
1) Set the power management register (address 49h) to enable all DAC’s.
2) Set the SENSE bit to a 1. This forces a constant output from the DAC’s. Note that during SENSE = 1, these 4
analog outputs are at steady state and no TV synchronization pulses are asserted.
3) Reset the SENSE bit to 0. This triggers a comparison between the voltage present on these analog outputs and the
reference value. During this step, each of the four status bits corresponding to individual DAC outputs will be reset
to “0” if they are NOT CONNECTED.
4) Read the status bits. The status bits, DACT[3:0] now contain valid information which can be read to determine
which outputs are connected to a TV. Again, a “1” indicates a valid connection, a “0” indicates an unconnected
output.
XOSC2 (bit 6) of register CD contains the MSB value for the XOSC (crystal oscillator gain control) word which is
described in detail in the DC (address 21h) register description.
DAC Control Register
Symbol:
Address:
Bits:
DC
21h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
XOSC1 XOSC0
IDF13 SYNCO1 SYNCO0 DACG1 DACG0 DACBP
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
DACBP (bit 0) of register DC selects the DAC bypass mode. A value of ‘1’ outputs the incoming data directly at the
DAC[3:0] outputs for the VGA-Bypass RGB output. For the other TV output modes such as S-Video, RCA, SCART and
480I HDTV, DACBP bit must be set to 0.
DACG[1:0] (bits 2-1) of register DC control the DAC gain. DACG0 should be set to ‘0’ for NTSC and PAL-M video
standards, and ‘1’ for PAL and NTSC-J video standards. DACG1 should be ‘0’ when the input data format is RGB (IDF
= 0-3, 5, 8 and 9), and ‘1’ when the input data format is YCrCb (IDF = 4, 6 and 7).
SYNCO[1:0] (bits 4-3) of register DC select the signal to be output from the C/H Sync pin according to Table 29 below.
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Table 29: Composite / Horizontal Sync Output
SYNCO[1:0]
Composite / Horizontal Sync Output
No Output
VGA Horizontal Sync
TV Composite Sync
00
01
10
11
TV Horizontal Sync
IDF13 (bit 5) of register DC is the MSB of the IDF1 word which is described in the IDF (address 1Fh) register
description.
XOSC[1:0] (bits 7-6) of register DC control the crystal oscillator. The entire bit field, XOSC[2:0], is comprised of
XOSC[1:0] from this register plus XOSC2 contained in the Connection Detect register (20h, bit 6).The default value is
recommended.
Buffered Clock Output Register
Symbol:
Address:
Bits:
BCO
22h
5
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved Reserved BCOEN
BCOP
BCO2
BCO1
BCO0
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
BCO[2:0] (bits 2-0) of register BCO select the signal output at the BCO pin, according to Table 30 below:
Table 30: BCO Output Signal
BCO[2:0]
000
Buffered Clock Output
The 14MHz crystal
BCO[2:0]
100
Buffered Clock Output
Sine ROM MSB
001
010
011
101
110
111
Cosine ROM MSB
VGA Vertical Sync
TV Vertical Sync
Field ID
BCOP (bit 3) of register BCO selects the polarity of the BCO output. A value of ‘1’ does not invert the signal at the
output pad.
BCOEN (bit 4) of register BCO enables the BCO output pin. When BCOEN is high, the BCO pin will output the
selected signal. When BCOEN is low, the BCO pin will be held in tri-state mode.
Pedestal Enable
Symbol:
Address:
Bits:
PEN
23h
1
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved
R/W
0
Reserved Reserved Reserved Reserved Reserved Reserved PEDLEN
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
PEDLEN (bit 0) of register PEN enables the pedestal (in register 4Fh). When PEDLEN is ‘0’ the pedestal function is
disabled. When PEDLEN is ‘1’ the pedestal is enabled.
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CH7019B
Defeat External Vsync Register
Symbol:
Address:
Bits:
DVS
47h
1
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
DVS
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
DVS (bit 7) of register DVS defeats the input Vertical SYNC signal going into the VSYNC timing block when set to ‘1’.
As a result of this, the internal self generated TV SYNC will be used.
Test Pattern Register
Symbol:
Address:
Bits:
STP
48h
5
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved
Reserved Reserved TVPLLR ResetIB ResetDB
TSTP1
R/W
0
TSTP0
R/W
0
TYPE:
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
0
DEFAULT:
TSTP[1:0] (bits 1:0) of register STP enable and select test pattern generation (color bar, ramp). This test pattern can be
used for both the LVDS output and the TV Output. The pattern generated is determined by the table below:
Table 31: Test Pattern Selection
TSTP1
TSTP0
Test Pattern
0
0
1
1
0
1
0
1
No test pattern – Input data is used
Color Bars
Horizontal Luminance Ramp
Horizontal Luminance Ramp
ResetDB (bit 3) of register STP resets the datapath. When ResetDB is ‘0’ the datapath is reset. When ResetDB is ‘1’ the
datapath is enabled. The datapath is also reset at power on by an internally generated power-on-reset signal.
ResetIB (bit 4) of register STP resets all control registers (addresses 00h – 7Fh). When ResetIB is ‘0’ the control
registers are reset to the default values. When ResetIB is ‘1’ the control registers operate normally. The control registers
are also reset at power on by an internally generated power on reset signal.
TVPLLR (bit 5) of register STP resets the TV PLL. When TVPLLR is ‘1’ the PLL is reset. When TVPLLR is ‘0’ the
PLL is enabled. The PLL is also reset at power on by an internally generated power-on-reset signal. In addition it can be
reset using the ResetDB bit above.
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Power Management Register
Symbol:
Address:
Bits:
PM
49h
6
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved
TV
R/W
0
DACPD3 DACPD2 DACPD1 DACPD0 TVPD
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
DEFAULT:
TVPD (bit 0) of register PM controls the TV Out block power down. When TVPD is ‘0’ the TV block is ON. When
TVPD is ‘1’ the TV block is powered down.
DACPD[3:0] (bits 4:1) of register PM control DAC0 through DAC3 Power Down. DAC0 through DAC3 will be turned
on only if TVPD bit is set to ‘0’. If TVPD bit is set to ‘1’, then DAC0 through DAC3 will be in power down state
regardless of DACPD0 through DACPD3 state.
Table 32: DAC Power Down Control
TVPD
DACPD[3:0]
0000
Functional Description
All DACs on
0
0
0
0
0
1
0001
0010
0100
1000
DAC 0 powered down, DACs 1, 2, 3 on
DAC 1 powered down, DACs 0, 2, 3 on
DAC 2 powered down, DACs 0, 1, 3 on
DAC 3 powered down, DACs 0, 1, 2 on
All DACs powered down
xxxx
TV (bit 5) of register PM enables the TV path. When TV is ‘0’, the TV data path is disabled. When TV is ‘1’ the TV
data path is enabled.
Version ID Register
Symbol:
Address:
Bits:
VID
4Ah
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
TYPE:
R
R
0
R
0
R
0
R
1
R
0
R
0
R
0
DEFAULT:
1
Register VID is a read only register containing the version ID number of the CH7019 family.
Note:
The Current Version ID of CH7019B is 88h.
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Device ID Register
Symbol:
Address:
Bits:
DID
4Bh
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
DID7
DID6
DID5
DID4
DID3
DID2
DID1
DID0
TYPE:
R
0
R
0
R
0
R
1
R
1
R
0
R
0
R
1
DEFAULT:
Register DID is a read only register containing the device ID number of the CH7019 family.
Note:
The Device ID of CH7019B is 19h.
Pedestal Level Control Register
Symbol:
Address:
Bits:
PEDL
4Fh
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
PEDL7
PEDL6
PEDL5
PEDL4
PEDL3
PEDL2
PEDL1
R/W
1
PEDL0
TYPE:
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
DEFAULT:
Register PEDL defines the pedestal level.
XCLK and D2 Adjust & IDF2
Symbol:
Address:
Bits:
XDIDF2
53h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
X2CMD3 X2CMD2 X2CMD1 X2CMD0 IDF23
IDF22
IDF21
IDF20
TYPE:
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
IDF2[3:0] (bits 3-0) of register XDIDF2 select the input data format for the D2 input. See section 3.2 for a listing of
available formats.
X2CMD[3:0] (bits 7-4) of register XDIDF2 control the delay applied to the XCLK2 signal before latching input data
D2[11:0] per the following table. 1 unit is approximately 70 ps worst case.
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Table 33: Delay applied to XCLK2 before latching input data D2
X2CMD3 X2CMD2 X2CMD1 X2CMD0 Adjust phase of Clock relative to Data
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 unit, XCLK2 ahead of Data
1 unit, XCLK2 ahead of Data
2 unit, XCLK2 ahead of Data
3 unit, XCLK2 ahead of Data
4 unit, XCLK2 ahead of Data
5 unit, XCLK2 ahead of Data
6 unit, XCLK2 ahead of Data
7 unit, XCLK2 ahead of Data
0 unit, XCLK2 behind Data
1 unit, XCLK2 behind Data
2 unit, XCLK2 behind Data
3 unit, XCLK2 behind Data
4 unit, XCLK2 behind Data
5 unit, XCLK2 behind Data
6 unit, XCLK2 behind Data
7 unit, XCLK2 behind Data
GPIO Invert
Symbol:
Address:
Bits:
GPIOINV
5Ch
3
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
C5GP2
R/W
0
C5GP1
C5GP0 Reserved Reserved Reserved Reserved Reserved
TYPE:
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
0
DEFAULT:
C5GP[2:0] (bits 7-5) of register GPIOINV define the GPIO C5 Control bits [5:4]. The entire bit field is made up of these
bits C5GP[2:0] plus C5GP[5:3] contained in the LVDS Encoding 2 register (65h, bits 7-5). Refer to the description of
the LVDSE2 register (address 65h) for more information.
Active Pixel Input & Line Output
Symbol:
Address:
Bits:
APILO
60h
2
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
STFDS1 STFDS0 Reserved Reserved Reserved Reserved Reserved Reserved
TYPE:
R/W
1
R/W
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
R/W
0
DEFAULT:
STFDS[1:0] (bits 8-7) of register APILO control FLD2 and FLD1 output to a VGA controller. These bits can be
programmed to be a TV field output from the TV encoder. These outputs are tri-stated upon power up. A value of ‘1’
allows FLD output. STFDS0 controls FLD1 and STFDS1 controls FLD2 output. Note that the FLDx pins must first be
enabled using the STFDENx bits located in register 10h, bits 7-6.
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LVDS Power Down
Symbol:
Address:
Bits:
LPD
63h
1
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved LVDSPD Reserved Reserved Reserved Reserved Reserved Reserved
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
1
DEFAULT:
LVDSPD (bit 6) of register LPD controls the LVDS power down. When LVDSPD is ‘0’ the LVDS path is ON, when
LVDSPD is ‘1’ the LVDS path is powered down.
LVDS Encoding 1 Register
Symbol:
Address:
Bits:
LVDSE1
64h
5
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved LVDS24 LVDSDC LDD
LDM2D LEOSWP Reserved
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
DEFAULT:
LEOSWP (bit 1) of register LVDSE1 provides the added flexibility to swap odd/even samples output on the LVDS link.
LDM2D (bit 2) of register LVDSE1 selects the dithering function to minimize quantization noise by spreading it out
spatially. A ‘1’ turns on the 2D dither function, and a ‘0’ turns off the dither function.
LDD (bit 3) of register LVDSE1 bypasses the dither function. A ‘1’ bypasses the dither function. A ‘0’ does not bypass
the dither function.
LVDSDC (bit 4) of register LVDSE1 allows single or dual channel LVDS to be selected. If the bit is 1, dual channel is
selected. If the bit is 0, single channel is selected.
LVDS24 (bit 5) of register LVDSE1 selects LVDS 24 bit or 18 bit output format. A ‘1’ provides 24- bit output mode
and a ‘ 0’ provides 18- bit output mode.
LVDS Encoding 2 Register
Symbol:
Address:
Bits:
LVDSE2
65h
6
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
C5GP5
C5GP4
C5GP3 Reserved LA6RL Reserved LCNTLE LCNTLF
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
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LCNTLF and LCNTLE (bits 1-0) of register LVDSE2 are OpenLDI miscellaneous control signals, Cntl F and Cntl E,
for the Display Source Serializer respectively. Refer to the OpenLDI specification v0.95. See section 2.4.2.
LA6RL (bit 3) of register LVDSE2 is an OpenLDI reserved bit for future use and may take any value. Refer to the
OpenLDI specification v0.95, P5. See section 2.4.2.
C5GP[5:3] (bits 7-5) of register LVDSE2 define the GPIO C5 Control bits [5:3]. The entire bit field is made up of these
bits C5GP[5:3] plus C5GP[2:0] contained in the GPIO Invert register (5Ch, bits 7-5). C5GP[5:0] invert the data output
on the GPIO[5:0] pins when the pins are configured in output mode. When the corresponding GOENB bits
(GOENB[5:0], see GPIODC register, address 6Eh, bits 3-0 and GPIO register, address 1Eh, bits 7-6) are ‘0’ and the
corresponding C5GP bits are ‘1’ the values in GPIOL[5:0] are driven out inverted at the corresponding GPIO pins.
LVDS PLL Miscellaneous Control Register
Symbol:
Address:
Bits:
LPMC
66h
7
BIT:
7
6
3
4
3
2
1
0
SYMBOL:
Reserved SYNCST BKLEN LPLEN LPFORC LPLOCK LSYNCEN PANEN
TYPE:
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
1
DEFAULT:
The LMPC register controls panel protection circuits which control the LVDS panel power up and down sequence. Refer
to section 3.4.5 and to Figure 19.
PANEN (bit 0) of the LPMC register controls the LVDS panel enable.
PANEN
= 0 => Begin Power off sequence
= 1 => Power-on
LSYNCEN (bit 1) of the LMPC register controls the Sync Detection Bypass
LSYNCEN = 0 => Normal Operation. HSYNC and VSYNC detection enabled.
= 1 => HSYNC and VSYNC detection circuit is bypassed enabling forced power up sequence.
LPLOCK (bit 2) of the LMPC register indicates the status of the PLL Lock
LPLOCK = 0 => PLL is not stable.
= 1 => PLL is stable and properly locked.
LPFORC (bit 3) of the LMPC register : Bypass LVDS Lock Detect Sentry
Bit 3
= 0 => Lock detect sentry is active.
= 1 => Lock detect sentry is overridden if LPLEN is set to ‘1’.
LPLEN (bit 4) of the LMPC register controls LVDS PLL Lock Enable between LPLOCK and LPFORC.
LPLEN
= 0 => Select LPLOCK (normal operation)
= 1 => Select LPFORC (Lock detect sentry is overridden if LPFORC is set to ‘1’)
BKLEN (bit 5) of the LMPC register enables the panel backlight.
BKLEN
= 0 => Disable Backlight
=1 => Enable Backlight
SYNCST(bit 6) of the LMPC register is the Hsync and Vsync stability status bit. Refer to section 3.4.5.
SYNCST = 0 => Hsync or Vsync are not stable
= 1 => Hsync and Vsync are stable
Note: The order of programming the control registers for the power up sequence is very important. Both
LPLOCK and SYNCST must read as 1 before setting PANEN to 1. Doing so will eliminate unexpected results on
the LCD panel.
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Power Sequencing T1
Symbol:
Address:
Bits:
PST1
67h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TPON7 TPON6
TPON5 TPON4 TPON3 TPON2 TPON1
TPON0
R/W
0
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
This register defines Power On time (T1), the time duration between LVDS_RDY (internal signal) to valid LVDS Clock
and Data. The entire bit field, TPON[8:0], is comprised of these bits TPON[7:0] plus TPON8 contained in the PST2
Power Sequencing T2 register (68h). Refer to Figure 18 and Table 15 in section 2.4.4. The range of T1 is 1ms to 512ms
in increments of 1ms.
Power Sequencing T2
Symbol:
Address:
Bits:
PST2
68h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TPON8 TPBLE6 TPBLE5 TPBLE4 TPBLE3 TPBLE2 TPBLE1 TPBLE0
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
TPBLE[6:0] (bits 6:0) of register PST2 define the Back Light Enable time (T2), the waiting time after valid LVDS Clock
and Data before enabling the LVDS panel back light. Refer to Figure 18 and Table 15 in section 2.4.4. The range of T2
is 2ms to 256ms in increments of 2ms.
TPON8 (bit 7) of register PST2 defines the MSB of the Power On time (T1). The entire bit field, TPON[8:0], is
comprised of this bit, TPON8, plus TPON[7:0] contained in the Power Sequencing T1 register (address 67h). Refer to
the description of the PST1 register (address 67h) for more information.
Power Sequencing T3
Symbol:
Address:
Bits:
PST3
69h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TP0FF8 TPBLD6 TPBLD5 TPBLD4 TPBLD3 TPBLD2 TPBLD1 TPBLD0
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
TPBLD[6:0] (bits 6-0) of register PST3 define the Back Light Disable time (T3), the required time after disabling the
back light before the valid LVDS Clock and Data become tri-stated or disabled. Refer to Figure 18 and Table 15 in
section 2.4.4. The range of T3 is 2ms to 256ms in increments of 2ms.
TPOFF8 (bit 7) of register PST3 defines the MSB of the Power Off time (T4). The entire bit field, TPOFF[8:0], is
comprised of this bit, TPOFF8, plus TPOFF[7:0] contained in the Power Sequencing T4 register (address 6Ah). Refer to
the description of the PST4 register (address 6Ah) for more information.
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Power Sequencing T4
Symbol:
Address:
Bits:
PST4
6Ah
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TPOFF7 TPOFF6 TPOFF5 TPOFF4 TPOFF3 TPOFF2 TPOFF1 TPOFF0
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
Register PST4 defines the Power Off time (T4), the required time prior to power off after the valid LVDS Clock and
Data become tri-stated or disabled. The entire bit field, TPOFF[8:0], is comprised of these bits, TPOFF[7:0], plus
TPOFF8 contained in the Power Sequencing T3 register (address 69h. Refer to Figure 18 and Table 15 in section 2.4.4.
The range is 1ms to 512ms in increments of 1ms.
Power Sequencing T5
Symbol:
Address:
Bits:
PST5
6Bh
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
C4GP5
R/W
1
C4GP4 TPPWD5 TPPWD4 TPPWD3 TPPWD2 TPPWD1 TPPWD0
TYPE:
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
DEFAULT:
TPPWD[5:0] (bits 5-0) of register PST5 define the Power Cycle time (T5), the waiting time required prior to enabling
power on after power has been off. Refer to Figure 18 and Table 15 in section 2.4.4. The range is 0 to 1600ms in
increments of 50ms.
C4GP[5:4] (bits 7-6) of register PST5 define the GPIO C4 Control bits [5:4]. The entire bit field is made up of these bits
C4GP[5:4] plus C4GP[3:2] contained in the GPIO Driver Type register (6Ch, bits 7-6) and C4GP[1:0] contained in the
GPIO Data [5:2] register (6Dh, bits 7-6). Refer to the description of the GPIOD register (6Dh) for more information.
GPIO Driver Type
Symbol:
Address:
Bits:
GPIODR
6Ch
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
C4GP3
R/W
1
C4GP2 GPIODR5 GPIODR4 GPIODR3 GPIODR2 GPIODR1 GPIODR0
TYPE:
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DEFAULT:
GPIODR[5:0] (bits 5:0) of register GPIODR defines the output driver type for pins GPIO[5:0] – CMOS or Open Drain.
A value of ‘0’ sets corresponding GPIO output to CMOS output type , and a value of ‘1’ sets corresponding GPIO output
to Open Drain type.
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C4GP[3:2] (bits 7-6) of register GPIODR define the GPIO C4 Control bits [3:2]. The entire bit field is made up of these
bits C4GP[3:2] plus C4GP[5:4] contained in the Power Sequencing T5 register (6Bh, bits 7-6) and C4GP[1:0] contained
in the GPIO Data [5:2] register (6Dh, bits 7-6). Refer to the description of the GPIOD register (6Dh) for more
information.
GPIO Data
Symbol:
Address:
Bits:
GPIOD
6Dh
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
C4GP1
R/W
1
C4GP0
C3GP5
C3GP4 GPIOL5 GPIOL4 GPIOL3 GPIOL2
TYPE:
R/W
1
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
DEFAULT:
GPIOL[5:2] (bits 3-0) of register GPIOD define the GPIO Read or Write Data bits [5:2]. The entire bit field is made up
of these bits GPIOL[5:2] plus GPIOL[1:0] contained in the GPIO Control register (1Eh, bits 5-4). GPIOL[5:0] define the
state of the GPIO[5:0] pins in read or write mode.
When the corresponding GOENB bits (GOENB[5:0], see GPIO Control register, address 1Eh, bits 7-6 and GPIO
Direction Control register, address 6Eh, bits 3-0) are ‘0’, the values in GPIOL[5:0] are driven out at the corresponding
GPIO pins. When the corresponding GOENB bits are ‘1’, the values in GPIOL[5:0] can be read to determine the level
forced into the corresponding GPIO pins. Note that the default state of GPIOLx depends on the state of the GPIOx pins
since by default these pins are configured as inputs. With no external pullup or pulldown the internal pullup created by
C4GPx being ‘1’ causes GPIOLx to be ‘1’.
When the corresponding GOENB bits are ‘0’ and the corresponding C5GP bits (C5GP[5:0], see GPIOINV register,
address 5Ch, bits 7-5 and LVDSE2 register, address 65h, bits 7-5) are ‘1’ the values in GPIOL[5:0] are driven out
inverted at the corresponding GPIO pins.
C3GP[5:4] (bits 5-4) of register GPIOD define the GPIO C3 Control bits [5:4]. The entire bit field is made up of these
bits C3GP[5:4] plus C3GP[3:0] contained in the GPIO Direction Control register (6Eh, bits 7-4). C3GP[5:0] control the
weak pull-down (approximately 1MΩ) for the pins GPIO[5:0]. A value of ‘0’ means no pull-down, a value of ‘1’ means
the pull-down is active.
C4GP[1:0] (bits 7-6) of register GPIOD define the GPIO C4 Control bits [1:0]. The entire bit field is made up of these
bits C4GP[1:0] plus C4GP[5:4] contained in the Power Sequencing T5 register (6Bh, bits 7-6) and C4GP[3:2] contained
in the GPIO Driver Type register (6Ch, bits 7-6). C4GP[5:0] control the weak pull-up (approximately 1MΩ) for the pins
GPIO[5:0]. A value of ‘0’ means no pull-up, a value of ‘1’ means the pull-up is active.
GPIO Direction Control
Symbol:
Address:
Bits:
GPIODC
6Eh
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
C3GP3
C3GP2
C3GP1
C3GP0 GOENB5 GOENB4 GOENB3 GOENB2
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
DEFAULT:
GOENB[5:2] (bits 3-0) of register GPIODC define the GPIO Direction Control bits [5:2]. The entire bit field is made up
of these bits GOENB[5:2] plus GOENB[1:0] contained in the GPIO Control register (address 1Eh, bits 7-6).
GOENB[5:0] control the direction of the GPIO[5:0] pins. A value of ‘1’ sets the corresponding GPIO pin to an input,
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and a value of ‘0’ sets the corresponding pin to a non-inverting output. The level at the output depends on the value of
the corresponding bit GPIOL[5:0]. Refer to the description for the GPIOD register (address 6Dh) for more information.
C3GP[3:0] (bits 7-4) of register GPIODC define the GPIO C3 Control bits [3:0]. The entire bit field is made up of these
bits C3GP[3:0] plus C3GP[5:4] contained in the GPIO Data [5:2] register (6Dh, bits 5-4). Refer to the description of the
GPIOD register (address 6Dh) for more information.
LVDS PLL Feed Back Divider Control
Symbol:
Address:
Bits:
LPFBDC
71h
6
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved LPFFD1 LPFFD0 LPFBD3 LPFBD2 LPFBD1
LPFBD0
TYPE:
R/W
1
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
DEFAULT:
LPFBD[3:0] (bits 3-0) of register LPFBDC define the LVDS PLL Feed-Back Divider Control. The recommended
settings are shown in Table 39 in section 3.4.
LPFFD[1:0] (bits 5:4) of register LPFBDC define the LVDS PLL Feed-Forward Divider Control. The recommended
settings are shown in Table 39 in section 3.4.
LVDS PLL VCO Control Register
Symbol:
Address:
Bits:
LPVC
72h
6
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved LPPSD1 LPPSD0 LPVCO3 LPVCO2 LPVCO1 LPVCO0
TYPE:
R/W
1
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
1
R/W
0
DEFAULT:
LPVCO[3:0] (bits 3-0) of register LPVC determine the LVDS PLL VCO open-loop frequency range. The recommended
settings are shown in Table 39 in section 3.4.
LPPSD[1:0] (bits 5:4) of register LPVC define the LVDS PLL post scale divider controls. The recommended settings are
shown in Table 39 in section 3.4.
Outputs Enable Register
Symbol:
Address:
Bits:
OUTEN
73h
7
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved DAS1
DAS0
LDEN1 LDENO LPCP2
LPCP1
LPCP0
TYPE:
R/W
1
R/W
1
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
DEFAULT:
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LPCP[2:0] (bits 2-0) of register LPCPC control the LVDS PLL Charge Pump current value. The recommended settings
are shown in Table 39.
LDEN[1:0] (bits 4-3) of register LPCPC control the output drivers of LVDS output Channel A (LDC[2:0], LDC*[2:0],
LL1C and LL1C*) ,and Channel B ( LDC[6:4], LDC*[6:4], LL2C and LL2C*) per the following table:
Table 34: LVDS Output Drivers Enable
LDEN1
LDEN0
Description
0
0
1
1
0
1
0
1
Both LVDS Channel A and B are Off
LVDS Channel A is ‘On’ and B is ‘Off’
LVDS Channel A is ‘Off’ and B is ‘On’
Both LVDS Channel A and B are ‘On’
DAS[1:0] (bits 6-5) of register OUTEN control the TV DAC (DACA and DACB ) analog switch per the following table.
Refer also to Table 12.
Table 35: TV DAC Analog Switch Control
DAS1
DAS0
DACA path DACB path
0
0
1
1
0
1
0
1
Off
Off
On
On
Off
On
Off
On
LVDS Output Driver Amplitude control
Symbol:
Address:
Bits:
LODA
74h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
LODP
LODPE L2ODA2 L2ODA1 L2ODA0 L1ODA2 L1ODA1 L1ODA0
TYPE:
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
L1ODA[2:0] (bits 2-0) of register LODA control the Output Driver Amplitude for LVDS Bank 1. See Table 36 below.
L2ODA[2:0] (bits 5-3) of register LODA control the Output Driver Amplitude for LVDS Bank 2. See Table 36 below.
Table 36: LVDS Output Driver Amplitude
LxODA2
LxODA1
LxODA0 Output Driver Amplitude (mV)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
305
285
265
245
225
410
370
330
LODPE (bit 6) of register LODA controls LVDS Output Driver Pre-Emphasis for both LDC[6:4] and LDC[2:0] by
simultaneous Pull-up and Pull-down diode currents.
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LODPE = 0 =>
= 1 =>
Pull up reduced by 33% and pull down reduced by 66%.
Default value
LODP (bit 7) of register LODA activates the LVDS Outputs Driver Pull-Down during power-down.
LODP
= 0 =>
= 1 =>
Pull-down devices not active
Pull-down devices active
LVDS PLL Spread Spectrum Control
Symbol:
Address:
Bits:
LPSSC
75h
1
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
LODST Reserved Reserved Reserved Reserved Reserved Reserved Reserved
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
LODST (bit 7) of register LPSSC controls the LVDS Output Drive Source Termination.
LODST = 0 => 100Ω (typ.) shunt disabled between LVDS outputs LDCx and LDCx*, also LLxC and LLxC*
= 1 => 100Ω (typ.) shunt enabled between LVDS outputs LDCx and LDCx*, also LLxC and LLxC*
LVDS Power Down & Loop Filter Resister
Symbol:
Address:
Bits:
LPDLFR
76h
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
FRSTB
LPLF2
LPLF1
LPLF0
LPPDN LPPRB LODPDB1 LODPDB0
TYPE:
R/W
1
R/W
0
R/W
1
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
DEFAULT:
LODPDB[1:0] (bits 1-0) of register LPDLFR control the LVDS Output Power Down per the following table:
Table 37: LVDS Output Power Down
LODPDB1 LODPDB0 LDC[6:4] & LL2C , LL2C* path LDC[2:0] , LL1C & LL1C* path
0
0
1
1
0
1
0
1
Power Down 1
Power Down 1
Power On
Power Down 1
Power On
Power Down 1
Power On
Power On
Note 1: Outputs are tri-stated in power down mode unless LODP (address 74h, bit 7) is ‘1’, in which case outputs are
pulled to ground.
LPPRB (bit 2) of register LPDLFR controls the LVDS PLL Reset.
LPPRB = 0 =>
= 1 =>
LVDS PLL is reset
Normal operation
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LPPDN (bit 3) of register LPDLFR controls the LVDS PLL Power Down.
LPPDN = 0 =>
= 1 =>
LVDS PLL is powered down
Normal operation
LPLF[2:0] (bits 6-4) of register LPDLFR control the LVDS PLL Loop Filter Resistor per the following table:
Table 38: LVDS PLL Loop Filter Resistor
LPLF2
LPLF1
LPLF0
PLL Loop Filter Resistor Value (Ohm)
1800
2600
1000
3200
21,800
42,600
11,000
73,200
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FRSTB (bit 7) of register LPDLFR controls the FIFO reset.
FRSTB = 0 =>
= 1 =>
Enable FIFO Reset
Normal Operation
LVDS Control 2
Symbol:
Address:
Bits:
LVCTL2
78h
7
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved LPLF4
LPLF3
R/W
1
LPPD4
LPPD3
LPPD2
LPPD1
LPPD0
TYPE:
R/W
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
DEFAULT:
LPPD[4:0] (bits 4-0) of register LVCTL2 define the LVDS PLL Phase Detector Control. The recommended values are
shown in Table 39 in section 3.4.
LPLF[4:3] (bits 6-5) of register LVCTL2 control the LVDS PLL Loop Filter Capacitor. The recommended settings are
shown in Table 39.
Bang Limit Control
Symbol:
Address:
Bits:
BGLMT
7Fh
8
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
BGLMT7 BGLMT6 BGLMT5 BGLMT4 BGLMT3 BGLMT2 BGLMT1 BGLMT0
TYPE:
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
This register limits the allowable occurrences of internal LVDS FIFO over and under-runs within one VGA frame.
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3.4 Recommended Settings
The recommended values for the LVDS PLL are shown in Table 39 below.
Table 39: LVDS Divider Control Settings
25MHz to 50MHz operation
Address/Bit
7
6
5
4
3
2
1
0
71h
72h
73h
78h
1
1
0
0
1
0
1
0
0
0
0
1
0
0
1
1
0
0
0
1
0
0
50MHz to 100MHz operation
Address/Bit
7
6
5
4
3
2
1
0
71h
72h
73h
78h
1
1
0
0
1
0
1
0
0
0
0
1
0
0
1
1
0
0
0
1
0
0
100MHz to 160MHz operation (dual panel)
Address/Bit
7
6
5
4
3
2
1
0
71h
72h
73h
78h
1
1
0
0
0
1
0
1
0
0
1
0
1
0
1
1
1
0
1
1
0
0
100MHz to 160MHz operation (single panel)
Address/Bit
7
6
5
4
3
2
1
0
71h
72h
73h
78h
1
0
0
1
0
1
0
1
0
0
1
0
1
0
1
1
1
0
1
1
0
0
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4.0 Electrical Specifications
4.1 Absolute Maximum Ratings
Symbol
Description
Min
-0.5
Typ
Max
Units
V
All power supplies relative to GND
Input voltage of all digital pins
Analog output short circuit duration
Ambient operating temperature
Storage temperature
5.0
GND – 0.5
VDD + 0.5
V
T
SC
Indefinite
Sec
°C
T
AMB
-55
-65
85
T
STOR
150
150
260
246
225
°C
T
J
Junction temperature
°C
T
VPS
Vapor phase soldering (5 seconds)
Vapor phase soldering (11 seconds)
Vapor phase soldering (60 seconds)
°C
T
VPS
°C
T
VPS
°C
Note:
1) Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions above those
indicated under the normal operating condition of this specification is not recommended. Exposure to absolute
maximum rating conditions for extended periods may affect reliability. The temperature requirements of vapor
phase soldering apply to all standard and lead free parts.
2) The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive
device. Voltage on any signal pin that exceeds the power supply voltages by more than ± 0.5V can induce
destructive latchup.
4.2 Recommended Operating Conditions
Symbol
Description
Min
3.1
3.1
3.1
3.1
3.1
3.1
3.1
1.1
Typ
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.8
Max
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
Units
TVPLL_VDD
TV PLL Digital Power Supply Voltage
TV PLL Analog Power Supply Voltage
DAC Power Supply Voltage
LVDS PLL Power Supply Voltage
Digital Power Supply Voltage
LVDS Power Supply Voltage
Generic for all of the above supplies
I/O Power Supply Voltage
V
V
V
V
V
V
V
V
Ω
TVPLL_VCC
DAC_VDD
LPLL_VDD
DVDD
LVDD
VDD
VDDV
R
L
Output load to DAC Outputs
37.5
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4.3 Electrical Characteristics (Operating Conditions: TA = 0°C – 70°C, VDD =3.3V ± 5%)
Symbol
Description
Min
Typ
10
Max
Units
bits
Video D/A Resolution
Full scale output current
Video level error
10
10
33.9
mA
10
%
I
Gang Mode @ 165MHz (TV path off)
412
600
mA
VDD
Total supply current
I
VDD
1 DVO input for TV @ 78 MHz
1 DVO input for LVDS@165 MHz
LVDS output @ 165 MHz
Total supply current
mA
mA
I
VDD
1 DVO input for TV @ 78 MHz
1 DVO input for LVDS@80 MHz
LVDS output @ 80 MHz
520
I
I
VDDV (1.8V) current (15pF load)
Total Power Down Current
4
mA
mA
VDDV
PD
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4.4 Digital Inputs / Outputs
Symbol
Description
Test Condition
Min
Typ
Max
Unit
VSDOL
SPD (serial port data) Output
Low Voltage
I
= 2.0 mA
0.4
V
OL
VSPIH
VSPIL
Serial Port (SPC, SPD) Input
High Voltage
1.0
VDD + 0.5
0.4
V
V
Serial Port (SC, SD) Input Low
Voltage
GND-0.5
VHYS
Hysteresis of Inputs
0.25
Vref1+0.25
GND-0.5
2.7
V
V
V
V
VDATAIH
VDATAIL
VMISCAIH
D[0-11] Input High Voltage
D[0-11] Input Low Voltage
DVDD+0.5
Vref1-0.25
VDD + 0.5
GPIO, AS, RESET*
Input High Voltage
DVDD=3.3V
DVDD=3.3V
VIN = 0V
VMISCAIL
IMISCAPU
VMISCAOH
GPIO, AS, RESET*
Input Low Voltage
GND-0.5
0.5
0.6
5
V
uA
V
Pull Up Current
(GPIO, AS, RESET*)
GPIO, ENAVDD, ENABKL,
C/HSYNC, BCO/VSYNC, H, V
Output High Voltage
I
I
= - 400 uA
= 3.2mA
VDD-0.2
OH
OL
GPIO, ENAVDD, ENABKL,
C/HSYNC, BCO/VSYNC, H, V
Output Low Voltage
VMISCAOL
0.2
0.2
V
VMISCBOH
VMISCBOL
P-OUT, FLD1, FLD2
Output High Voltage
IOH = - 400 uA
IOL = 3.2 mA
VDDV-0.2
V
V
P-OUT, FLD/STL1, FLD/STL2
Output Low Voltage
Note :
VDATA - refers to all digital pixel, clock, data enable and sync inputs. VMISCA - refers to GPIOx, AS and RESET* inputs and GPIOx,
ENAVDD, ENABKL, C/HSYNC, BCO/VSYNC outputs and Hx, Vx when configured as outputs (SYOTV=1). VMISCB - refers to P-OUT,
FLD/STL1 and FLD/STL2 outputs.
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4.5 AC Specifications
Symbol
fXCLK
tPIXEL
DCXCLK
tXJIT
Description
Test Condition
Min
25
Typ
Max
165
40
Unit
MHz
ns
Input (XCLK) frequency
Pixel time period
6.06
30
Input (XCLK) Duty Cycle
XCLK clock jitter tolerance
TS + TH < 1.2ns
70
%
2
ns
Setup Time: D[11:0], H, V and
DE to XCLK, XCLK*
tS
XCLK = XCLK* to
D[11:0], H, V, DE =
Vref1
0.5
0.5
ns
Hold Time: D[11:0], H, V and
DE to XCLK, XCLK*
tH
D[11:0], H, V, DE =
Vref1 to XCLK =
XCLK*
ns
ns
tR
Pout, H and V (when
configured as outputs)
15pF load
1.50
1.50
80
DVDD, VDDV = 3.3V
Output Rise Time
(20% - 80%)
tF
Pout, H and V (when
configured as outputs)
15pF load
ns
ps
VDDV = 3.3V
Output Fall Time
(20% - 80%)
tSTEP
De-skew time increment
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4.6 LVDS Output Specifications
The LVDS specifications meet the requirements of ANSI/EIA/TIA-644. Refer to Figure 21 for definitions of parameters.
Symbol
Description
Test Condition
100Ω differential load
100Ω differential load
100Ω differential load
Min
247
247
Typ
Max
453
453
50
Unit
mV
mV
mV
Steady State Differential
Output Magnitude for logic 1
Steady State Differential
Output Magnitude for logic 0
Steady State Magnitude of
Difference between Logic 1
and 0 Outputs
| Vt |
| Vt *|
| Vt | - | Vt *|
|VOS
|
Steady State Magnitude of
Offset Voltage for Logic 1
Measured at center-
tap of two 50Ω
1.125
1.125
1.375
1.375
50
V
resistors connected
between outputs
|VOS* |
Steady State Magnitude of
Offset Voltage for Logic 0
Measured at center-
tap of two 50Ω
V
resistors connected
between outputs
|VOS | - |VOS* |
Steady State Magnitude of
Offset Difference between
Logic States
Measured at center-
tap of two 50Ω
mV
resistors connected
between outputs
fLLC
LVDS Output Clock
Frequency
25
108 1
5.7
MHz
ns
tUI
LVDS data unit time interval
25MHz < fLLC
108MHz
<
1.3
tR
LVDS data rise time
100Ω and 5pF
differential load
t
UI > 5ns
0.3* tUI
1.5
ns
ns
20% -> 80% VSWING
1.3ns < tUI < 5ns
tF
LVDS data fall time
100Ω and 5pF
differential load
t
UI > 5ns
0.3* tUI
1.5
ns
ns
80% -> 20% VSWING
1.3ns < tUI < 5ns
VRING
Voltage ringing after transition 100Ω and 5pF
20%
differential load
VSWING
Note 1: Corresponds to maximum pixel rate fXCLK for single channel operation. Dual channel operation is required for
pixel rates greater than 108MHz.
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4.7 Timing Information
Note:
CH7019B
In the figures and tables in the following sections XCLK, XCLK*, D[11:0], H, V and DE refer respectively to XCLK1
and XCLK2, XCLK1* and XCLK2*, D1[11:0] and D2[11:0], H1 and H2, V1 and V2, DE1 and DE2.
4.7.1
LVDS Output Timing
Vring
+/-20% Vswing
0.8 Vswing
+Vt
Vswing
tj
0V Differential
-Vt
0.2 Vswing
tr
tf
tui
Figure 21: AC Timing for LVDS Outputs
Table 40: AC Timing for LVDS Outputs
Symbol
Parameter
Min
Typ
Max
Steady State Differential Output Magnitude
| Vt |
see section 5.6
Voltage Difference between the two Steady State Values of Output
VSWING
Unit time interval
Rise time
tUi
tr
see section 5.6
see section 5.6
see section 5.6
tf
Fall time
tj
Jitter peak to peak1
350ps
Note 1: Maximum jitter with EMI reduction turned off.
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4.7.2
Clock - Slave, Sync - Slave Mode
t1
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
XCLK
XCLK*
D[11:0]
DE
tH
tS
P0a P0b P1a
P1b P2a
P2b
t2
tS
tH
tS
H
64 PIXELS
V IL
V IH
V
1 VGA
Line
V IL
t2
t2
Figure 22:
Timing for Clock - Slave, Sync - Slave Mode
Table 41: Timing for Clock - Slave, Sync - Slave Mode
Symbol
Parameter
Min
Typ
Max
Unit
Setup Time: D[11:0], H, V and DE to XCLK, XCLK*
Hold Time: D[11:0], H, V and DE to XCLK, XCLK*
tS
see section 4.5
tH
t1
t2
see section 4.5
XCLK & XCLK* rise/fall time w/15pF load
D[11:0], H, V & DE rise/fall time w/ 15pF load
1
1
ns
ns
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4.7.3
Clock - Master, Sync - Slave Mode
VOH
VOL
P-OUT
tPOUTR
tPOUTF
t1
VIH
VIL
VIH
VIL
V IH
V IL
V IH
V IL
V IH
XCLK
XCLK*
D[11:0]
DE
tH
tS
P0a P0b P1a
P1b P2a
P2b
t2
tS
tH
tS
H
64 PIXELS
V IL
V IH
V
1 VGA
Line
V IL
t2
t2
Figure 23:
Timing for Clock - Master, Sync - Slave Mode
Table 42: Timing for Clock - Master, Sync - Slave Mode
Symbol
Parameter
Min
Typ
Max
Unit
Setup Time: D[11:0], H, V and DE to XCLK, XCLK*
Hold Time: D[11:0], H, V and DE to XCLK, XCLK*
tS
tH
see section 4.5
see section 4.5
see section 4.5
tR
tF
t1
t2
Pout Output Rise Time
see section 4.5
Pout Output Fall Time
XCLK & XCLK* rise/fall time w/15pF load
1
1
ns
ns
D[11:0], H, V & DE rise/fall time w/15pF load
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5.5.3
Clock - Master, Sync - Master Mode
VOH
VOL
P-OUT
H
tF
tR
t3
VOH
VOL
VOH
VOL
64 PIXELS
V
1 VGA
Line
tR
tF
t1
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
XCLK
XCLK*
D[11:0]
DE
tH
tS
P0a P0b P1a
P1b P2a
P2b
t2
tS
Figure 24:
Clock - Master, Sync - Master Mode
Table 43: Timing for Clock - Master, Sync - Master Mode
Symbol
Parameter
Min
Typ
Max
Unit
Setup Time: D[11:0], H, V and DE to XCLK, XCLK*
Hold Time: D[11:0], H, V and DE to XCLK, XCLK*
tS
tH
see section 4.5
see section 4.5
see section 4.5
tR
tF
t1
t2
Pout, H, V (when configured as outputs) Output Rise Time
see section 4.5
Pout, H, V (when configured as outputs) Output Fall Time
XCLK & XCLK* rise/fall time w/15pF load
1
1
ns
ns
D[11:0] & DE rise/fall time w/15pF load
Hold time:
P-OUT to HSYNC, VSYNC delay
t3
1.5
ns
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5.0 Package Dimensions
A1
B1
I
128
103
1
102
A2 B2
38
65
H
39
64
C
D
J
LEAD
F
E
.004
G
Table of Dimensions
No. of Leads
SYMBOL
A1
A2
B1
14
B2
20
C
D
E
F
G
H
I
J
128 (14X20)
MIN
MAX
0.17
0.27
1.35
1.45
0.05
0.15
0.45
0.75
0.09
0.20
0°
7°
Milli-
meters
16
22
0.50
1.00
Notes:
1. Conforms to JEDEC standard JESD-30 MS-026D.
2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm.
Dimension B does not include allowable mold protrusions up to 0.25 mm per side.
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6.0 Revision History
Rev. #
Date
Section
Description
1.0
3/7/02
First release derived from 7017 revision 1.6
1.2
7/6/02
Added back register 5Ch (deleted in error).
Added spec. number
4.2
Moved CLM[7:0] from 4Fh to 56h
Added PEDL[7:0] register at 4Fh
Added PEDLEN bit at 23h , bit 0
Added hex values
Changed CIV bits to read only
Renamed register to GPIO Invert (GPIOINV)
Swapped descriptions for modes 8 and 9. Swapped modes 6 and 7.
Changed Figure 9 and associated text. Swapped order of Cr and
Cb in Table 7 and 8. Cr precedes Cb.
Register 4Fh
Register 23h
Table 25, 26, 27
Register 10h – 13h
Register 5Ch
2.2.2
Register 49h
2.3.4
Swapped DACPD bits 0 and 3.
Added explanation of RSET in note 1.
Register 1Eh and 6h
Table 39
Changed default value and description of GPIOLx bits
Added table.
Register 02h
Register 14h
Register 47h
Table 1
Table 1
2.1
Changed default value of VBID from 0 to 1.
Made BGBST a public bit.
Made DVS a public bit.
Updated table to include H and V as outputs
Changed all references of DVDDV to VDDV
Edited Figure 3, Figure 4, Figure 5, Figure 6 and Table 2 to
change t1 and t2 to tS and tH.
Various
Second set of DAC outputs added back. Renumbered DACs. Put
names in Figure 2. Changed register 49h.
Rewrote sections. Replaced Figure 19 with the figure from register
66h description
2.4.4 and 2.4.5
Corrected pin-out in Figure 2. LDC3 and LDC3* replaced by
LDC4 and LDC4*
2.0
10/1/02
Corrected entry for register 73h by adding DAS1 and DAS0.
Corrected LODPD[1:0] to LODPDB[1:0] in register 76h
Updated to include second set of DAC outputs
Corrected N value for mode 11 from 64 to 62.
Added section for AC specs.
Changed black level range
Changed black level default settings
Updated description on black level default settings
Added Table of Contents
Added section 4.6, 4.7.1, and table 42
Figure 1
Table 25
Section 4.5
Register 07h
Register 07h
Register 07h
2.1
12/30/02
2.11
1/29/03
6/23/03
1/19/04
10/20/04
12/18/06
2.2
2.3
2.4
4.6, 4.7.1, Table 42
4
3.3
Add Vapor phase soldering information.
Corrected bit setting description for IBS2 (bit 6) and IBS1 (bit 7).
Register 1Ch and 1Fh
78
201-0000-048
Rev. 2.4, 12/18/2006
CHRONTEL
CH7019B
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at any time
without notice to improve and supply the best possible product and is not responsible and does not assume any liability
for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our
products and assume no liability for errors contained in this document. The customer should make sure that they have
the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does not
infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist
others to infringe upon such rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as
directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Part Number
CH7019B-TF
Package Type
Number of Pins
128
Voltage Supply
3.3V
LQFP, Lead free
LQFP, Lead free,
Tape&Reel
CH7019B-TF-TR
128
3.3V
Chrontel
2210 O’Toole Avenue, Suite 100,
San Jose, CA 95131-1326
Tel: (408) 383-9328
Fax: (408) 383-9338
www.chrontel.com
E-mail: sales@chrontel.com
©2006 Chrontel, Inc. All Rights Reserved.
Printed in the U.S.A.
201-0000-048
Rev. 2.4, 12/18/2006
79
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