CH7026A-TF [CHRONTEL]
Color Signal Encoder;
| 型号： | CH7026A-TF |
| 厂家： | 
CHRONTEL, INC |
| 描述： | Color Signal Encoder 编码器 商用集成电路 |
| 文件： | 总11页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CH7025/CH7026
Chrontel
Brief Datasheet
CH7025/CH7026 TV/VGA Encoder
Features
General Description
The CH7025/CH7026 is a semiconductor device
targeting for handheld market, surveillance camera
and automobile multimedia system. This device
accepts digital video signals through its 24-bit
input bus and generates NTSC, PAL, VGA or
HDTV (480p, 576p, 720p and 1080i) video signal
by its 10-bit DACs. In addition, CH7025/26 has an
embedded 16-Mbit SDRAM to support the CPU
interface.
•
TV encoder targets for handheld device, surveillance camera
and automobile market.
•
Supports multiple output formats such as analog TV (NTSC and
PAL), VGA and HDTV ( 480p,576p,720p, 1080i). Sync signals
can be provided in separated or composite manner.
•
Three on-chip 10-bit high speed DACs providing flexible output
capabilities such as single, double or triple CVBS output, YPbPr
output, RGB output and simultaneous CVBS and S-video
output.
•
•
90/180/270 degree image rotation and vertical or horizontal flip.
16-Mbit SDRAM is used as a frame buffer for frame rate
conversion.
CH7025/26 has incorporated an advanced
technology that can perform real-time video
rotations and frame rate conversions for incoming
video stream. These complicated tasks are
achieved by storing video data to the internal
SDRAM and applying scaling process if required.
CH7025/26 provides great flexibility for accepting
different video data formats including RGB and
YcbCr (e.g. RGB565, RGB 666, RGB 888, ITU
656).
•
•
Flexible up and down scaling.
Programmable 24-bit/18-bit/16-bit/15-bit/12-bit/8-bit digital
input interface supports various RGB (RGB888, RGB666,
RGB565 and etc), YCbCr (4:4:4 YcbCr, ITU656) and 2x or 3x
multiplexed input. CPU interface is also supported.
•
•
Supports flexible input resolution up to 800x800 and 1024x680.
Pixel by pixel brightness, contrast, hue and saturation
adjustment for each output is supported. (For RGB output, only
brightness and contrast adjustment is supported).
The CH7025/26 is available in BGA or QFP
package.
•
•
•
Pixel by pixel horizontal position adjustment and line by line
vertical position adjustment.
Supports MacrovisionTM 7.1 L1 in CH7025. CH7026 is a Non-
Macrovision version of the CH7025
Supports MacrovisionTM copy protection for progressive scan
TV (480p, 576p) in CH7025
•
•
Supports CGMS-A for analog TV and HDTV
TV/Monitor connection detection capability. DAC can be
switched off based on detection result.
•
•
Programmable power management.
Flexible pixel clock frequency from graphics controller is
supported. (2.3MHz –120MHz)
•
Flexible input clock from crystal or oscillator is supported.
(2.3MHz – 64MHz)
•
•
Supports slave input clock mode only.
Fully programmable through serial port.
• IO and SPC/SPD voltage supported is from 1.2V to 3.3V.
• Offered in BGA or QFP package.
Note: the above feature list is subject to change without notice. Please contact Chrontel for
more information and current updates.
209-0000-088
Rev. 1.0,
3/5/2008
1
CHRONTEL
CH7025/CH7026
SDRAM
Input
data
RGB/YCbCr
format
decoder
HUE
SAT
BRI
CON
VP
CSC
(YCbCr
to RGB)
CSC
(RGB to
YUV)
TV
MUX
Scaler
MUX
formater
CSB
WEB
HP
CPU
VSYNC
DIN
interface
MUX
SPC
SPD
Serial
port
R/Y/CVBS/Y_Svideo
DAC 1
BRI
CON
VP
G/Pb/CVBS/C-Svideo
DAC 2
XI
HP
G/Pr/CVBS
DAC 3
PLL
XO
CSYNC
VSYNC
HSYNC
SYNC
position
adjust
Composite
sync
generation
H,V,DE
Figure 1: CH7025/CH7026 block diagram
2
209-0000-088
Rev. 1.0,
3/5/2008
CHRONTEL
1.0 Pin-out
CH7025/CH7026
1.1 Package diagram
1.1.1
The 80-pin BGA Package Diagram
1
2
3
4
5
6
7
8
9
A
A
B
C
D
E
F
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
1
2
3
4
5
6
7
8
9
Figure 2: 80-pin BGA package
209-0000-088
Rev. 1.0, 3/5/2008
3
CHRONTEL
CH7025/CH7026
1.1.2
The 80-pin LQFP Package Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
D[8]
60
HSO
VSO
CSYNC
ATPG
AS
ResetB
AGND
AVDD
D[7]
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
GNDQ_MEM
VDDQ_MEM
AGND
D[0]
Chrontel
CH7025/CH7026
VDDIO
GCLK
AVDD
AGND
GND_MEM
GND_MEM
VDD_MEM
VDD_MEM
NC
AVDD
GND_MEM
VDD_MEM
NC
NC
NC
VDDQ_MEM
GNDQ_MEM
NC
NC
NC
Figure 3: 80-pin LQFP package
4
209-0000-088
Rev. 1.0,
3/5/2008
CHRONTEL
CH7025/CH7026
1.2 Pin description
Table 1: Pin name description (BGA package)
Pin #
Type
Symbol
Description
A3, E4, B4, A4,
E5, B5, A5, D4,
D5, D6, A7, E6,
B7, A8, F6, B8,
B9, C9, C8, D9,
D8, E8, F7, E9
C2
In(F)
D[23:0]
Data[0] through Data[23] Inputs
These pins accept the 24 data inputs from a digital video
port of a graphics controller. The swing is defined by
VDDIO.
Inout
V
Vertical Sync Input / Output
When the SYO control bit is low, this pin accepts a vertical
sync input for use with the input data. The amplitude will
be 0 to VDDIO.
When the SYO control bit is high, the device will output a
vertical sync pulse. The output is driven from the VDDIO
supply.
B3
Inout
H/WEB
Horizontal Sync Input / Output
When the SYO control bit is low, this pin accepts a
horizontal sync input for use with the input data. The
amplitude will be 0 to VDDIO.
When the SYO control bit is high, the device will output a
horizontal sync pulse. The output is driven from the
VDDIO supply.
It is also the WEB signal of CPU interface.
Data Input Indicator
A2
In
DE/CSB
When the pin is high, the input data is active.
When the pin is low, the input data is blanking.
It is also the CSB signal of CPU interface
The amplitude will be 0 to VDDIO.
Address select
D2
F5
In
In
AS
ATPG
ATPG Enable
(Internally pull-down)
This pin should be left open or pulled low with a 10k
resistor in the application. This pin configures the pre-
condition for scan chain and boundary scan test when high.
Otherwise it should be low. Voltage level is 0 to 3.3V.
Reserved pin.
C1
In
ResetB
Reset * Input
When this pin is low, the device is held in the hardware
reset condition. When this pin is high, reset is controlled
through the serial port.
K9
L9
Inout
In
SPD
SPC
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial
port. External pull-up resister is required.
Serial Port Clock Input
This pin functions as the clock pin of the serial port.
External pull-up resister is required.
CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3v
CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3v
L4
L3
Out
Out
DAC0
DAC1
209-0000-088
Rev. 1.0, 3/5/2008
5
CHRONTEL
CH7025/CH7026
Pin #
Type
Symbol
Description
L2
Out
DAC2
CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3v
L5
In
In
ISET
XI
Current Set Resistor Input
This pin sets the DAC current. A 1.2k ohm, 1% tolerance
resistor should be connected between this pin and
AGND_DAC using short and wide traces.
Crystal Input / External Reference Input
For master mode and some situation of the slave mode, a
parallel resonance crystal (± 20 ppm) should be attached
between this pin and XO. However, an external 3.3V
CMOS compatible clock can drive the XI/FIN input.
Crystal Output
For master mode and some situation of the slave mode, a
parallel resonance crystal (± 20 ppm) should be attached
between this pin and XI / FIN. However, if an external
CMOS clock is attached to XI/FIN, XO should be left open.
External Clock Inputs
K7
K8
F9
Out
In
XO
GCLK
The input is the clock signal input to the device for use with
the H, V, DE and D[23:0] data.
B1
Out
VSO
Vertical sync signal output
B2
Out
HSO
Horizontal sync signal output
A1
F8
B6
Out
CSYNC
VDDIO
DVDD
Composite sync output
IO supply voltage (1.2-3.3V)
Digital supply voltage (1.8V)
Analog supply voltage (2.5 – 3.3V)
PLL supply voltage (1.8V)
DAC power supply (2.5 – 3.3V)
SDRAM output buffer supply voltage
(1.8V or 2.5V)
Power
Power
Power
Power
Power
Power
D1, F1, L7, G9
K6
K4
E2, H1
AVDD
AVDD_PLL
AVDD_DAC
VDDQ_MEM
G2, J8, H6
A6
F4, F2, L6, G8
K5
K3
E1, J1
Power
Power
Power
Power
Power
Power
Power
VDD_MEM
DGND
AGND
AGND_PLL
AGND_DAC
GNDQ_MEM
GND_MEM
SDRAM device supply voltage (2.5V)
Digital supply ground
Analog supply ground
PLL supply ground
DAC supply ground
SDRAM output buffer supply ground
SDRAM device supply ground
F3, H9, H8
6
209-0000-088
Rev. 1.0,
3/5/2008
CHRONTEL
CH7025/CH7026
Table 2: Pin name descriptions (LQFP80 package)
Pin #
Type
Symbol
Description
52 - 67
70 - 77
In
D[23:0]
Data[0] through Data[23] Inputs
These pins accept the 24 data inputs from a digital video port of a
graphics controller. The swing is defined by VDDIO.
Vertical Sync Input / Output
When the SYO control bit is low, this pin accepts a vertical sync input
for use with the input data. The amplitude will be 0 to VDDIO.
79
Inout
Inout
V
When the SYO control bit is high, the device will output a vertical
sync pulse. The output is driven from the VDDIO supply.
Horizontal Sync Input / Output
78
H/WEB
When the SYO control bit is low, this pin accepts a horizontal sync
input for use with the input data. The amplitude will be 0 to VDDIO.
When the SYO control bit is high, the device will output a horizontal
sync pulse. The output is driven from the VDDIO supply.
It is also the WEB signal of CPU interface.
Data Input Indicator
80
In
DE/CSB
When the pin is high, the input data is active.
When the pin is low, the input data is blanking.
CSB signal input of CPU interface
The amplitude will be 0 to VDDIO.
5
4
In
In
AS
Chip address select
0: 76h
1: 75h
ATPG Enable
ATPG
(Internally pull-down)
This pin should be left open or pulled low with a 10k resistor in the
application. This pin configures the pre-condition for scan chain and
boundary scan test when high. Otherwise it should be low. Voltage
level is 0 to 3.3V.
Reserved pin.
6
In
ResetB
Reset * Input
When this pin is low, the device is held in the power-on reset
condition. When this pin is high, reset is controlled through the serial
port.
38
39
Inout
In
SPD
SPC
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port.
External pull-up resister is required.
Serial Port Clock Input
This pin functions as the clock pin of the serial port. External pull-up
resister is required.
29
27
25
31
Out
Out
Out
In
DAC0
DAC1
DAC2
ISET
CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3v
CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3v
CVBS, S-video, YPbPr or Analog RGB output
Full swing is up to 1.3v
Current Set Resistor Input
This pin sets the DAC current. A 1.2k ohm, 1% tolerance resistor
should be connected between this pin and AGND_DAC using short
and wide traces.
35
In
XI
Crystal Input / External Reference Input
For master mode and some situation of the slave mode, a parallel
209-0000-088
Rev. 1.0, 3/5/2008
7
CHRONTEL
CH7025/CH7026
Pin #
Type
Symbol
Description
resonance crystal (± 20 ppm) should be attached between this pin and
XO. However, an external 3.3V CMOS compatible clock can drive the
XI/FIN input.
36
Out
XO
Crystal Output
For master mode and some situation of the slave mode, a parallel
resonance crystal (± 20 ppm) should be attached between this pin and
XI / FIN. However, if an external CMOS clock is attached to XI/FIN,
XO should be left open.
50
In
GCLK
External Clock Inputs
The input is the clock signal input to the device for use with the H, V,
DE and D[23:0] data.
2
1
3
Out
Out
Out
VSO
Vertical sync signal output,
The amplitude of this pin is from 0 to AVDD
Horizontal sync signal output,
The amplitude of this pin is from 0 to AVDD
Composite sync output,
HSO
CSYNC
The amplitude of this pin is from 0 to AVDD
51
69
8
Power
Power
Power
VDDIO
DVDD
AVDD
IO supply voltage (1.2-3.3V)
Digital supply voltage (1.8V)
Analog supply voltage
12
37
49
33
24
28
10
18
14
44
45
68
7
Power
Power
AVDD_PLL
AVDD_DAC
PLL supply voltage
DAC power supply
Power
Power
VDDQ_MEM
VDD_MEM
SDRAM output buffer supply voltage
SDRAM device supply voltage
Power
Power
DGND
AGND
Digital supply ground
Analog supply ground
11
34
48
32
26
30
9
19
13
46
47
Power
Power
AGND_PLL
AGND_DAC
PLL supply ground
DAC supply ground
Power
Power
GNDQ_MEM
GND_MEM
SDRAM output buffer supply ground
SDRAM device supply ground
8
209-0000-088
Rev. 1.0,
3/5/2008
CHRONTEL
CH7025/CH7026
2.0 Package Dimensions
A1 Conrer
A1 Conrer
9
8
7
6
5
4
3
2
1
1
2
3
4
6
7
8
9
5
A
B
C
D
E
F
A
B
C
D
E
F
D
A
C
G
H
J
G
H
J
K
L
K
L
F
(
Top View )
E
B
(
Bottom View )
K
H
I
J
G
Figure 4: 80 Pin BGA Package
Table of Dimensions
No. of Leads
SYMBOL
80 (5 X 6 mm)
A
B
C
D
E
F
G
H
I
J
K
Milli-
meters
Min
Max
0.22
0.30
6.00
5.00
5.00
0.50
4.00
0.50
0.30 0.60 0.30
1.20
Notes:
1. All dimensions conform to JEDEC standard MO-216.
209-0000-088
Rev. 1.0, 3/5/2008
9
CHRONTEL
CH7025/CH7026
A
B
I
1
B
A
H
C
D
J
LEAD
CO-PLANARITY
F
E
.004 “
G
Figure 5: 80 Pin LQFP Package
Table of Dimensions
No. of Leads
SYMBOL
A
B
C
D
E
F
G
H
I
J
80 (10 X 10 mm)
Milli-
meters
MIN
MAX
11.90
12.10
9.90
0.13
0.23
1.35
1.45
0.05
0.15
0.45
0.75
0.09
0.20
0°
7°
0.40
1.00
10.10
Notes:
1. Conforms to JEDEC standard JESD-30 MS-026D.
2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm.
3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side.
10
209-0000-088
Rev. 1.0,
3/5/2008
CHRONTEL
CH7025/CH7026
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at
any time without notice to improve and supply the best possible product and is not responsible and does not
assume any liability for misapplication or use outside the limits specified in this document. We provide no
warranty for the use of our products and assume no liability for errors contained in this document. The
customer should make sure that they have the most recent data sheet version. Customers should take
appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel, Inc.
respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such
rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE
SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC
WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and
whose failure to perform when used as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Copy
Protection
Part Number
Package Type
Operating Temperature Range
CH7025A-GF
CH7025A-GFI
CH7025A-TF
CH7025A-TFI
CH7026A-GF
CH7026A-GFI
CH7026A-TF
CH7026A-TFI
80TFBGA, Lead-free
80TFBGA, Lead-free
80LQFP, Lead-free
80LQFP, Lead-free
80TFBGA, Lead-free
80TFBGA, Lead-free
80LQFP, Lead-free
80LQFP, Lead-free
Macrovision™
Commercial : -20 to 70°C
Industrial : -40 to 85°C
Commercial : -20 to 70°C
Industrial : -40 to 85°C
Commercial : -20 to 70°C
Industrial : -40 to 85°C
Commercial : -20 to 70°C
Industrial : -40 to 85°C
Macrovision™
Macrovision™
Macrovision™
None
None
None
None
Chrontel
2210 O’Toole Avenue, Suite 100,
San Jose, CA 95131-1326
Tel: (408) 383-9328
Fax: (408) 383-9338
www.chrontel.com
E-mail: sales@chrontel.com
©2008 Chrontel, Inc. All Rights Reserved.
Printed in the U.S.A.
209-0000-088
Rev. 1.0, 3/5/2008
11
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