CH7036A-BFI [CHRONTEL]
Consumer Circuit, 10 X 10 MM, LEAD FREE, MO-220, QFN-88;
| 型号： | CH7036A-BFI |
| 厂家： | 
CHRONTEL, INC |
| 描述： | Consumer Circuit, 10 X 10 MM, LEAD FREE, MO-220, QFN-88 商用集成电路 |
| 文件： | 总7页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CH7036
Chrontel
Brief Datasheet
Chrontel CH7036 RGB/HDMI/LVDS Encoder
F
EATURES
Single channel 18-bit/24-bit LVDS receiver and
transmitter support display resolution up to 1366x768
GENERAL DESCRIPTION
The CH7036 is specifically designed for Consumer Electronics
Devices and Personal Computers that require High Definition
(HD) Content video playback on the external displays such as
HDMI/DVI monitors.
•
•
•
•
•
•
•
•
•
HDMI encoder supports up to 1080p
Supports VGA display up to 1080p
Supports HDMI repeater function
DDC master for reading EDID
The CH7036’s HDMI transmitter is designed to support 1080p
HDTV and the HDMI repeater function. For desktop monitors
that do not have the HDMI input, the CH7036 has the capability
to disable HDMI mode and output DVI signal or analog RGB
signal (VGA). To support multi-display, the CH7036 can output
either HDM/DVI or Analog RGB signals together with LVDS
signal pass-through.
Supports Hot Plug Detection (HPD) for HDMI/DVI
Optional HDCP version 1.1 function
Three 10-bit high speed DACs
DACs can be switched off through programming
internal registers. A separated composite sync is
supported
The CH7036’s single channel LVDS receiver/transmitter
complies with the SPWG specification, a popular LVDS
standard used by panel manufacturers. Each input/output
LVDS interface is equipped with 4/1 pairs of differential signal
buses to support video data and clock. The built-in dithering
mechanism can be applied to approximate true 24-bit color
video data if system manufacturers use less expensive 18-bit
panels. Conversely, if input data is only 18-bit color, the
simulation to 24-bit color for high-end TFT LCD is also
supported.
•
Monitor connection detection capability. Connection
status can be retrieved through device’s internal
registers
•
•
•
Pixel-level color enhancement for brightness and
contrast (analog RGB only)
SPDIF audio interface supports up to 20-bit data
stream 192kHz/2ch
Supports I2S digital audio input up to 24-bit data
stream (32kHz/2ch, 44.1kHz/2ch, 48kHz/2ch,
88.2kHz/2ch, 96kHz/2ch, 176.4kHz/2ch and
192kHz/2ch)
The device’s LVDS receiver can accept maximum video clock
frequency for up to 85MHz or 1366x768 resolution in 24-bit
color per pixel. A powerful scaling engine working together
with other video processing circuits, will convert the captured
LVDS signal stored in the internal SDRAM into High
Definition Content video data. The built-in mixer will combine
this HD digital RGB signal with decoded audio stream into
HDMI format data, which will be serialized for output display
by the CH7036 TMDS encoder.
•
•
•
On-chip frame buffer allows flexible input LVDS
video timing.
Capable of converting input video frame rate to
satisfy external displays’ refresh rate requirements
Advanced scaling engine to upsize/downsize display
resolution for HDMI, DVI and analog RGB outputs
•
•
Programmable adaptive de-flickering filter
The CH7036 supports both SPDIF and 2-channel I2S digital
audio inputs. Its high fidelity audio decoder engine has the
capability of sampling audio frequencies for up to 192kHz for 2
channels.
Image display rotation supports for HDMI/DVI and
analog RGB outputs. The screen display can be
rotated 90/180/270 degree or flipped either
horizontally or vertically
Utilizing its high speed internal frame buffer, the CH7036’s
scaling engine can increase the flexibility of the screen display.
The video enhancement includes resizing the HDMI/DVI and
RGB output display resolution, performing Frame Rate
Conversion a well as rotating display orientation. Other video
fine tuning, such as brightness control or contrast adjustment
can be used to improve the display on the analog RGB monitor.
•
•
Horizontal/vertical position shifting for the VGA
display is programmable
Flexible crystal or oscillator clock input frequency for
analog RGB output (2.3MHz – 64MHz). 27 MHz
external crystal is recommended for HDMI output.
•
•
•
IO and SPC/SPD supply voltages from 1.8V to 3.3V
Programmable power management
When CH7036 is powered up, its MCU is able to automatically
execute the device configuration software in the device’s
internal memory. When the firmware in the memory is
programmed to support EDID communication and HPD, the
MCU will toggle DDC bus lines to retrieve the display timing
from the HDMI/DVI monitor if HPD is asserted. Furthermore
an interrupt signal can be generated by MCU to host while the
CH7036’s HPD is high.
The device’s configuration parameters can be
programmed through serial port
•
Offered in 88-pin QFN package
A
Netbooks
PPLICATIONS
MIDs
Tablet PCs
Industrial PCs
The CH7036 supports the optional HDCP feature for preventing
illegally copy High Definition Contented media.
209-1000-011 Rev. 1.23, 03/24/2011
1
CHRONTEL
CH7036
SPC/SPD
IIS
SPDIF
IIS
Decoder
SPDIF
Decoder
HPD
SDRAM
DDC
MCU
EEPROM
HDMI/DVI
Core
HDMI/
DVI
LVDS
LVDS
Receiver
Image
Enhance
Scaler
VGA
DAC
LVDS
Transmitter
LVDS
Dithering
Figure 1: Functional Block Diagram
2
209-1000-011
Rev. 1.23,
03/24/2011
CHRONTEL
CH7036
1.0 PIN-OUT
1.1 Package Diagram
AVDD_PLL
1
2
3
4
RESERVED
DDC_SD
DDC_SC
GNDMQ
VDDMQ
VDDMS
GNDMS
VSO
HSO
DVDD
DGND
GNDMQ
VDDMQ
I2S_D/SPDIF
I2S_WS
I2S_CK
AGND
66
65
64
63
62
61
AGND_PLL
RESERVED
VDDMS
GNDMS
VSSH
5
6
7
8
9
10
11
TLCB
TLC
TDC0B
TDC0
VDDH
VDDH
TDC1B
TDC1
TDC2B
TDC2
VSSH
60
59
58
57
56
55
54
53
52
51
12
13
14
15
16
17
CH7036
50
49
48
47
46
45
DGND
DVDD
AVDD_PLL
18
19
20
PDB
AUDDAC
PWM
AVDD
VSST
AGND_PLL
VSSR
21
22
Figure 2: Pin Out
1.2 Pin Description
Table 1: Pin Description
Pin #
3
Type
In
Symbol
RESERVED
Description
Reserved Pin.
This pin should be pulled low with a 10 kΩ resistor
HDMI Clock Outputs
These pins provide the differential clock output for the HDMI
HDMI Data Channel 0 Outputs
These pins provide the HDMI differential outputs for data channel 0
HDMI Data Channel 1 Outputs
These pins provide the HDMI differential outputs for data channel 1
HDMI Data Channel 2 Outputs
These pins provide the HDMI differential outputs for data channel 2
LVDS Data Channel 0 Inputs
These pins provide the LVDS differential inputs for data channel 0
LVDS Data Channel 1 Inputs
These pins provide the LVDS differential inputs for data channel 1
LVDS Data Channel 2 Inputs
These pins provide the LVDS differential inputs for data channel 2
7,8
Out
Out
Out
Out
In
TLCB/TLC
9,10
TDC0B/TDC0
TDC1B/TDC1
TDC2B/TDC2
RX0/RX0B
13,14
15,16
24,25
26,27
28,29
In
RX1/RX1B
In
RX2/RX2B
209-1000-011
Rev. 1.23, 03/24/2011
3
CHRONTEL
CH7036
30,31
32,33
34,35
36,37
38,39
41,42
43,44
In
RX3/RX3B
LVDS Data Channel 3 Inputs
These pins provide the LVDS differential inputs for data channel 3
LVDS Clock Inputs
In
RXC/RXCB
LDC0/LDC0B
LDC1/LDC1B
LDC2/LDC2B
LDC3/LDC3B
LLC/LLCB
These pins provide the LVDS differential input clocks
LVDS Data Channel 0 Outputs
Out
Out
Out
Out
Out
These pins provide the LVDS differential outputs for data channel 0
LVDS Data Channel 1 Outputs
These pins provide the LVDS differential outputs for data channel 1
LVDS Data Channel 2 Outputs
These pins provide the LVDS differential outputs for data channel 2
LVDS Data Channel 3 Outputs
These pins provide the LVDS differential outputs for data channel 3
LVDS Clock Outputs
These pins provide the LVDS differential output clocks
Backlight Brightness Adjustment
47
48
49
Out
PWM[1]
AUDDAC[1]
PDB
Out
Audio Control Output Pin
Input
Power Down the Whole Chip
High: Power on CH7036; Low: Power down CH7036
I2S Clock Signal
51
52
53
In
In
In
I2S_CK
I2S_WS
I2S Channel Select Signal
I2S_D/SPDIF
SPDIF Audio Signal Input.
In default, this pin is configured to SPDIF audio signal input
I2S Data Input.
I2S audio input can be configured through programming CH7036
registers
58
59
64
Out
Out
In
HSO
Analog RGB Horizontal Sync Output
VSO
Analog RGB Vertical Sync Output
DDC_SC[2]
Serial Port Clock Output to DDC
This pin functions as the clock bus of the serial port to DDC receiver.
This pin will require a pull-up 1.8 kΩ resistor to +5V
Serial Port Data to DDC
65
In/Out
DDC_SD[2]
This pin functions as the bi-directional data pin of the serial port to DDC
receiver. This pin will require a pull-up 1.8 kΩ Resistor to +5V
Reserved Pin.
This pin should be floating or pull low with 10 kΩ resistor
Crystal Input / External Reference Input
A parallel resonance crystal should be attached between this pin and
XO. However, an external 3.3V CMOS compatible clock can drive the
XI Input
66
67
In/Out
In
RESERVED
XI
68
Out
XO
Crystal Output
A parallel resonance crystal should be attached between this pin and XI /
FIN. However, if an external CMOS clock is attached to XI/FIN, XO
should be left open
70
72
74
76
Out
Out
Out
In
DAC2
DAC1
DAC0
ISET
Analog B Output
Full swing is up to 0.7V
Analog G Output
Full swing is up to 0.7V
Analog R Output
Full swing is up to 0.7V
Current Set Resistor Input
This pin sets the DAC current. A 1.2 kΩ, 1% tolerance resistor should
be connected between this pin and AGND_DAC using short and wide
traces
77
Out
GPIO2
General Purpose Output Pin
4
209-1000-011
Rev. 1.23,
03/24/2011
CHRONTEL
Out
CH7036
78
GPIO1
General Purpose Output Pin
Serial Port Data to E2PROM
80
In/Out
PROM_SD
This pin functions as the bi-directional data pin of the serial port to
E2PROM receiver. This pin requires a pull-up 5.6 kΩ Resistor to the
desired voltage level
81
In
PROM_SC
Serial Port Clock Output to E2PROM
This pin functions as the clock bus of the serial port to E2PROM
receiver. This pin requires a pull-up 5.6 kΩ Resistor to the desired
voltage level
83
84
85
In
RSTB
VCC_EN
IRQ
Reset Pin
Low for reset
In
Panel Power Enable
Active high. When it is low, all the output will be turned off.
Programmed Interrupt Output.
Out
Default output 3.3V CMOS level, and this pin could work as open drain
structure for other voltages.
86
87
88
In
SPC
SPD
HPD
Serial Port Clock Output
This pin functions as the clock pin of the serial port. External pull-up 6.8
kΩ Resistor is required
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port.
External pull-up 6.8 kΩ Resistor is required
Hot Plug Detect
In/Out
In
This input pin determines whether the HDMI output driver is connected
to a HDMI monitor.
1,20
4,61
11,12
19,57
23
Power
Power
Power
Power
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
AVDD_PLL
VDDMS
VDDH
PLL Power Supply(1.8V)
SDRAM Device Power Supply(3.3V)
HDMI Power Supply(3.3V)
Digital Power Supply(1.8V)
LVDS Input Power Supply (3.3V)
LVDS Output Power Supply (3.3V)
Analog Power Supply(3.3V)
SDRAM Buffer Power Supply(3.3V)
DAC Power Supply (2.5~3.3V)
PLL Ground
DVDD
VDDR
40
VDDT
46,79
54,62
69,73
2,21
5,60
6,17
18,56
22
AVDD
VDDMQ
AVDD_DAC
AGND_PLL
GNDMS
VSSH
SDRAM Device Ground
HDMI Ground
DGND
Digital Ground
VSSR
LVDS Input Ground
45
VSST
LVDS Output Ground
Analog Ground
50,82
55,63
71,75
AGND
GNDMQ
AGND_DAC
SDRAM Buffer Ground
DAC Ground
Notes:
1. Default 3.3V CMOS level output.
2. If DDC is not used, both pins DDC_SC/DDC_SD should be connected to ground by 10kΩ resistor.
209-1000-011
Rev. 1.23, 03/24/2011
5
CHRONTEL
CH7036
2.0 PACKAGE
DIMENSIONS
TOP VIEW
BOTTOM VIEW
B
A
B/2
22
1
1
22
88
23
23
88
Pin 1
3
A
C
C/2
44
67
44
F
67
4
66
45
45
66
E
D
(4x)
2
I
G
H
Figure 3: 88 pin QFN package(10x10mm)
Table 2: Dimensions
No. of Leads
SYMBOL
88 (10 X 10 mm)
A
B
C
D
E
F
G
H
I
Milli-
meters
MIN
6.60
6.90
6.60
6.90
0.15
0.25
0.35
0.60
0.80
0.90
0.00
0.05
10.00
0.40
0.20
MAX
Notes:
1. Conforms to JEDEC standard JESD-30 MO-220.
2. Side of body may be square or curved.
3. Exposed pad may have chamfer in area of Pin 1.
4. Pins may protrude from edge of body by 0.05 mm.
6
209-1000-011
Rev. 1.23,
03/24/2011
CHRONTEL
CH7036
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at any time
without notice to improve and supply the best possible product and is not responsible and does not assume any
liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use
of our products and assume no liability for errors contained in this document. The customer should make sure that
they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the
products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not
infringe upon or assist others to infringe upon such rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used
as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Minimum
Order Quantity
Part Number
Package Type
Operating Temperature Range
CH7036A-BF
CH7036A-BFI
88QFN, Lead-free
88QFN, Lead-free
168/Tray
Commercial : -20 to 70°C
Commercial : -40 to 85°C
168/Tray
Chrontel
Chrontel International Limited
129 Front Street, 5th floor,
Hamilton, Bermuda HM12
www.chrontel.com
E-mail: sales@chrontel.com
2010 Chrontel. All Rights Reserved.
Printed in the U.S.A.
209-1000-011
Rev. 1.23, 03/24/2011
7
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