CH7304A-TF [CHRONTEL]
Consumer Circuit, CMOS, PQFP64, 10 X 10 MM, LEAD FREE, LQFP-64;
| 型号： | CH7304A-TF |
| 厂家： | 
CHRONTEL, INC |
| 描述： | Consumer Circuit, CMOS, PQFP64, 10 X 10 MM, LEAD FREE, LQFP-64 |
| 文件： | 总33页 (文件大小：355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CH7304
Chrontel
CH7304 Single LVDS Transmitter
Features
General Description
The CH7304 is a Display Controller device, which accepts
a graphics data stream over one 12-bit wide variable
voltage (1.1V to 3.3V) port. The data stream outputs
through an LVDS transmitter to an LCD panel. A
maximum of 100M pixels per second can be output
through a single LVDS link.
• Single LVDS transmitter
• Supports pixel rate up to 100M pixels/sec
• Supports up to SXGA resolution (1280 x 1024)
• LVDS low jitter PLL
• LVDS 18-bit output
• 2D dither engine
The LVDS transmitter includes a programmable dither
function for support of 18-bit panels. Data is encoded into
commonly used formats, including those detailed in the
OpenLDI and the SPWG specification. Serialized data
output on four differential channels.
• Panel protection and power down sequencing
• Programmable power management
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Variable voltage interface to graphics device
• Offered in a 64-pin LQFP package
LVDS PLL
Clock,
Data,
Sync
Latch &
XCLK,XCLK*
2
LDC[3:0],LDC*[3:0]
LLC,LLC*
ENAVDD, ENABKL
6
Color
Space
Conversion
H,V, DE
LVDS
Transmit
3
2
2
LVDS
Encode /
Serialize
Dither
Engine
Demux
D[11:0]
VREF
12
Serial Port Control and Misc. Functions
XTAL
XI/FIN,XO
2
Figure 1: Functional Block Diagram
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CHRONTEL
CH7304
Table of Contents
1.0
1.1
1.2
2.0
2.1
2.2
2.3
Pin Assignment__________________________________________________________________________ 3
Pin Diagram __________________________________________________________________________ 3
Pin Description ________________________________________________________________________ 4
Functional Description ____________________________________________________________________ 6
Input Data Formats _____________________________________________________________________ 6
LVDS-Out ___________________________________________________________________________ 9
Power Down _________________________________________________________________________ 12
Register Control ________________________________________________________________________ 13
Control Registers Index ________________________________________________________________ 13
Control Registers Description____________________________________________________________ 14
Control Registers Description____________________________________________________________ 15
Recommended Settings_________________________________________________________________ 25
Electrical Specifications __________________________________________________________________ 26
Absolute Maximum Ratings _____________________________________________________________ 26
Recommended Operating Conditions______________________________________________________ 26
Electrical Characteristics _______________________________________________________________ 26
Digital Inputs / Outputs_________________________________________________________________ 27
AC Specifications_____________________________________________________________________ 27
Timing Information ___________________________________________________________________ 29
Package Dimensions_____________________________________________________________________ 31
Revision History________________________________________________________________________ 32
3.0
3.1
3.2
3.3
3.4
4.0
4.1
4.2
4.3
4.4
4.5
4.6
5.0
6.0
1.0
2
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CHRONTEL
CH7304
Pin Assignment
1.1 Pin Diagram
ENABKL
ENAVDD
NC
VDDV
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RESET*
DE
NC
VREF
H
LVDD
NC
V
NC
DVDD
SPD
Chrontel
CH7304
LGND
NC
SPC
9
NC
CONFIG
LPLL_VDD
LPLL_CAP
LPLL_GND
10
11
12
13
14
15
16
LVDD
NC
NC
LGND
DGND
XI
NC
NC
XO
Figure 2: 64 Pin LQFP Package (Top View)
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CH7304
1.2 Pin Description
Table 1: Pin Description
Pin #
# of Pins Type
Symbol
Description
1
1
Out
ENABLK
Back Light Enable
Enable Back-Light of LCD Panel. Output is driven from 0 to DVDD.
2
1
Out
ENAVDD
NC
Panel Power Enable
Enable panel VDD. Output is driven from 0 to DVDD.
No Connect
3,4,6,7,9,10,
12,13,15,16
10
-
20, 21
2
4
4
1
Out
Out
Out
In
LLC, LLC*
LDC[3:0]
LDC[3:0]*
VSWING
LVDS Differential Clock
Positive LVDS differential data[3:0]
Negative LVDS differential data [3:0]
LVDS Voltage Swing Control
17,23,26,29
18,24,27,30
32
This pin sets the swing level of the LVDS outputs. A 2.4K Ohm resistor
should be connected between this pin and LGND (pin 31) using short and
wide traces.
33
34
1
1
Out
In
XO
XI
Crystal Output
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached
between this pin and XI. However, if an external CMOS clock is attached
to XI, XO should be left open.
Crystal Input / External Reference Input
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached
between this pin and XO. However, an external CMOS compatible clock
can drive the XI input.
37
39
40
1
1
1
Analog
In/Out
In
LPLL_CAP
CONFIG
SPC
LVDS PLL Capacitor
This pin allows coupling of any signal to the on-chip loop filter capacitor.
Configure / Output
This pin configures the device ID.
Serial Port Clock Input
This pin functions as the clock input of the serial port and can operate with
inputs from 1.1V ~ 3.3V. The serial port address of the CH7304 is 75h. For
more details on CH7304 serial port read/write operations, please refer to
AN61.
41
1
In/Out
SPD
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port and can
operate with inputs from 1.1V ~ 3.3V. Outputs are driven from 0 to VDDV.
The serial port address of the CH7304 is 75h. For more details on CH7304
serial port read/write operations, please refer to AN61.
Vertical Sync Input
This pin accepts a vertical sync input for use with the input data. The
amplitude will be 0 to VDDV. VREF signal is the threshold level.
Horizontal Sync Input
43
44
45
1
1
1
In
In
In
V
H
This pin accepts a horizontal sync input for use with the input data. The
amplitude will be 0 to VDDV. VREF is the threshold level for this input.
Reference Voltage Input
VREF
The VREF pin inputs a reference voltage of VDDV / 2. The signal is
derived externally through a resistor divider and decoupling capacitor, and
will be used as a reference level for data, sync and clock inputs.
Data Enable
This pin accepts a data enable signal which is high when active video data
is input to the device, and remains low during all other times. The levels
are 0 to VDDV. VREF is the threshold level.
46
47
1
1
In
In
DE
RESET*
Reset * Input (Internal Pull-up)
When this pin is low, the device is held in the power on reset condition.
When this pin is high, reset is controlled through the serial port.
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CH7304
Table 1: Pin Description (continued)
Pin #
# of Pins Type
Symbol
Description
50-55, 58-63 12
In
D[11:0]
Data[11] through Data[0] Inputs
These pins accept the 12 data inputs from a digital video port of a graphics
controller. The levels are 0 to VDDV. VREF is the threshold level.
56, 57
2
In
XCLK,
XCLK*
External Clock Inputs
These inputs form a differential clock signal input to the device for use with
the H, V and D[11:0] data. If differential clocks are not available, the
XCLK* input should be connected to VREF. The clock polarity can be
selected by the MCP control bit (Register 1Ch).
42, 64
35, 49
48
5,11,22,28
8,14,19,25,31
38
2
2
1
4
5
1
1
Power
Power
Power
Power
Power
Power
Power
DVDD
DGND
VDDV
LVDD
LGND
Digital Supply Voltage (3.3V)
Digital Ground
I/O Supply Voltage (1.1V to 3.3V)
LVDS Supply Voltage (3.3V)
LVDS Ground
LPLL_VDD LVDS PLL Supply Voltage (3.3V)
LPLL_GND
36
LVDS PLL Ground
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CH7304
2.0 Functional Description
2.1
Input Data Formats
2.1.1
Overview
Two distinct methods of transferring data to the CH7304 are described. They are:
•
•
Multiplexed data, clock input at 1X the pixel rate
Multiplexed data, clock input at 2X the pixel rate
For the multiplexed data, clock at 1X pixel rate, the data applied to the CH7304 is latched with both edges of the clock
(also referred to as dual edge transfer mode or DDR). For the multiplexed data, clock at 2X pixel rate the data applied to
the CH7304 is latched with one edge of the clock (also known as single edge transfer mode or SDR). The polarity of the
pixel clock can be reversed under serial port control. In single edge transfer modes, the clock edge used to latch data is
programmable. In dual edge transfer modes, the clock edge used to latch the first half of each pixel is programmable.
2.1.2
Interface Voltage Levels
The graphics controller interface can operate at a variable voltage level controlled by the voltage on the VDDV pin. This
should be set to the maximum voltage of the interface (typically 3.3V or adjustable between 1.1 and 1.8V). The VREF
pin is the voltage reference for the data, data enable, clock and sync inputs and must be tied to VDDV/2. This is typically
done using a resistor divider.
2.1.3
Input Clock and Data Timing Diagram
Figure 3 shows the timing diagram for input data and clocks. The first XCLK/XCLK* waveform represents the input
clock for single edge transfer (SDR) methods. The second XCLK/XCLK* waveform represents the input clock for the
dual edge transfer (DDR) method. The timing requirements are given in Section 4.5.
XCLK/
2X
XCLK*
XCLK/
1X
XCLK*
D[15:0]
H
V
64 pixels
1 VGA Line
Figure 3: Clock, Data and Interface Timing
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CH7304
2.1.4
Data De-skew Feature
The de-skew feature allows adjustment of the input setup and hold time. The input data D[11:0] can be latched slightly
before or after the latching edge of XCLK depending on the amount of the de-skew. Note that the XCLK is not changed,
only the time at which the data is latched relative to XCLK. The de-skew is controlled using the XCMD[3:0] bits located
in Register 1Dh. The delay tCD between clock and data is given by the following formula:
tCD = - XCMD[3:0] * tSTEP for 0 ≤ XCMD[3:0] ≤ 7
tCD = (XCMD[3:0] – 8) * tSTEP for 8 ≤ XCMD[3:0] ≤ 15
where XCMD is a number between 0 and 15 represented as a binary code
tSTEP is the adjustment increment (see Section 4.5)
The delay is also tabulated in Table 8.
2.1.5
Input Data Formats
The CH7304 supports 5 different multiplexed data formats, each of which can be used with a 1X clock latching data on
both clock edges, or a 2X clock latching data with a single edge (rising or falling depending on the value of the MCP bit
– rising refers to a rising edge on the XCLK signal, a falling edge on the XCLK* signal). Received data is formatted and
sent through an internal data bus P[23:0] to the LVDS data path. The input data formats are (IDF[2:0] = 0, 1, 2, 3 and 4):
IDF
0
Description
RGB 8-8-8 (2x12-bit)
1
2
RGB 8-8-8 (2x12-bit) or RGB 5-6-5 (2x8-bit)
RGB 5-6-5 (2x8bit)
3
RGB 5-5-5 (2x8-bit)
4
YCrCb 8-8 (2x8-bit)
(refer to Register 31h, bit 0)
The input data format is shown in Figure 4. The Pixel Data bus represents a 12-bit or 8-bit multiplexed data stream,
which contains either RGB or YCrCb formatted data. The input data rate is 2X the pixel rate, and each pair of Pn values
(e.g.; P0a and P0b) will contain a complete pixel encoded as shown in Table 2 through Table 4.
For multiplexed input data formats, data can be latched from the graphics controller by either rising only or falling only
clock edges, or by both rising and falling clock edges. The MCP bit selects the rising or the falling clock edge, where
rising refers to rising edge on the XCLK signals and falling edge on the XCLK*. It is assumed that the first clock cycle
following the leading edge of the incoming horizontal sync signal contains the first word (Pxa) of a pixel, if an active
pixel was present immediately following the horizontal sync. This does not mean that active data should immediately
follow the horizontal sync, however. When the input is a YCrCb data stream the color-difference data will be
transmitted at half the data rate of the luminance data, with the sequence being set as Cb, Y, Cr, Y, where Cb0,Y0,Cr0
refers to co-sited luminance and color-difference samples and the following Y1 byte refers to the next luminance sample,
per ITU-R BT.656 standards (the clock frequency is dependent upon the current mode, and is not 27MHz as specified in
ITU-R BT.656). All non-active pixels should be 0 in RGB formats, and 16 for Y, 128 for Cr and Cb in YCrCb formats.
H
XCLK
(2X)
XCLK
(1X)
DE
P0a
P0b
P1a
P1b
P2a
P2b
D[11:0]
Figure 4: 12-bit Multiplexed Input Data Formats (IDF = 0,1,2,3, 4)
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CHRONTEL
CH7304
Table 2: Multiplexed Input Data Formats (IDF = 0, 1)
IDF =
0
1
Format =
RGB 8-8-8 (2x12-bit)
RGB 8-8-8 (2x12-bit)
or RGB 5-6-5 (2x8-bit)
Pixel #
P0a
P0b
P1a
P1b
P0a
P0b
P1a
P1b
Bus Data
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
G0[3]
G0[2]
G0[1]
G0[0]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[7]
G0[6]
G0[5]
G0[4]
G1[3]
G1[2]
G1[1]
G1[0]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[7]
G1[6]
G1[5]
G1[4]
G0[4]
G0[3]
G0[2]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
G0[0]
B0[2]
B0[1]
B0[0]
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
G0[7]
G0[6]
G0[5]
R0[2]
R0[1]
R0[0]
G0[1]
G1[4]
G1[3]
G1[2]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
G1[0]
B1[2]
B1[1]
B1[0]
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
G1[7]
G1[6]
G1[5]
R1[2]
R1[1]
R1[0]
G1[1]
Table 3: Multiplexed Input Data Formats (IDF = 2, 3)
IDF =
2
3
Format =
RGB 5-6-5 (2x8bit)
RGB 5-5-5 (2x8-bit)
Pixel #
P0a
P0b
P1a
P1b
P0a
P0b
P1a
P1b
Bus Data
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
G0[4]
G0[3]
G0[2]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
G0[7]
G0[6]
G0[5]
G1[4]
G1[3]
G1[2]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
G1[7]
G1[6]
G1[5]
G0[5]
G0[4]
G0[3]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
X
G1[5]
G1[4]
G1[3]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
X
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
G0[7]
G0[6]
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
G1[7]
G1[6]
Table 4: Multiplexed Input Data Formats (IDF = 4)
IDF =
4
Format =
YCrCb 8-bit
Pixel #
P0a
P0b
P1a
P1b
P2a
P2b
P3a
P3b
Bus Data
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Cb0[7]
Cb0[6]
Cb0[5]
Cb0[4]
Cb0[3]
Cb0[2]
Cb0[1]
Cb0[0]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
Cr0[7]
Cr0[6]
Cr0[5]
Cr0[4]
Cr0[3]
Cr0[2]
Cr0[1]
Cr0[0]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Cb2[7]
Cb2[6]
Cb2[5]
Cb2[4]
Cb2[3]
Cb2[2]
Cb2[1]
Cb2[0]
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
Cr2[7]
Cr2[6]
Cr2[5]
Cr2[4]
Cr2[3]
Cr2[2]
Cr2[1]
Cr2[0]
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]
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CH7304
2.2 LVDS-Out
2.2.1
Single LVDS Channel Signal Mapping
Table 5: Signal Mapping for Single LVDS Channel
24-bit LDI
R2
24-bit SPWG
R0
18-bit
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
HSYNC
VSYNC
DE
N/A
N/A
N/A
N/A
N/A
N/A
LDC[0](1)
LDC[0](2)
LDC[0](3)
LDC[0](4)
LDC[0](5)
LDC[0](6)
LDC[0](7)
LDC[1](1)
LDC[1](2)
LDC[1](3)
LDC[1](4)
LDC[1](5)
LDC[1](6)
LDC[1](7)
LDC[2](1)
LDC[2](2)
LDC[2](3)
LDC[2](4)
LDC[2](5)
LDC[2](6)
LDC[2](7)
LDC[3](1)
LDC[3](2)
LDC[3](3)
LDC[3](4)
LDC[3](5)
LDC[3](6)
LDC[3](7)
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B7
B5
HSYNC
VSYNC
DE
R0
R1
G0
G1
B0
B1
N/A
HSYNC
VSYNC
DE
R6
R7
G6
G7
B6
B7
N/A
N/A
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CH7304
2.2.2
Dithering
The CH7304 has a dither engine that can convert the 24-bit pixel data to 18-bit pixel data for better image quality on 18-
bit panels. Maximum pixel rate supported is 100M Pixels / sec.
2.2.3
Power Sequencing
The CH7304 conforms to SPWG’s requirements on power sequencing. The timing specification shown in Figure 5 is a
superset of the requirements dictated by the SPWG specification. The power sequencing block consists of a state
machine and 5 hardware timers, which are programmable through the serial port to suit requirements by different panels.
It provides 2 signals ENAVDD and ENABKL to the LCD panel.
T1 T2
T3 T4
T5
LVDS_RDY
(Internal)
ENAVDD
ENEXBUF
ENABKL
LVDS Clocks
LVDS Data
Valid Clock
Valid Data
Tristate or GND
Tristate or GND
Figure 5: Power Sequencing
Table 6: Power Sequencing
Range
2-512 ms
2-256 ms
2-256 ms
2-512 ms
2-1600 ms
Increment
1 ms
T1
T2
T3
T4
T5
2ms
2ms
1 ms
50ms
Power-on sequence begins when the LVDS software registers are set properly via the serial port and the internal PLL
lock detection circuit and the internal Sync detection circuits (see Section 2.2.4) indicate that HSYNC, VSYNC and
XCLK are stable. Note that the BKLEN bit (Register 66h) must be set in order for the ENABKL signal to be asserted.
Power-off sequence begins when any detection circuits indicate an instability in the timing signals (see Section 2.2.4), or
through software programming. Once the power-off sequence starts, the internal state machine will complete the
sequence and the power-on sequence is allowed only after T5 is passed.
When the LVDS output clock and data signals become invalid, these outputs are tri-stated or grounded depending on the
value of the LODP bit.
2.2.4
Panel Protection
The LCD panel can be damaged if HSYNC is absent from the LVDS link. This situation can happen when there is a
catastrophic failure in the PC or the graphics system. The CH7304 is designed to prevent damage to the panel under such
a failure. If the system fails, the CH7304 does not expect any software instruction from the graphics controller to power
down the panel. Detection circuits are used to monitor the three timing signals – HSYNC, VSYNC and XCLK. If any
one, combination of, or all of these signals becomes unstable, the CH7304 will commence Power Down Sequencing
according to Section 2.2.3. A description of these detection circuits is shown in Figure 6.
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CH7304
XCLK
LVDS
PLL
XCLK
LOCKST
0
LOCK
FIFO
MUX
DETECT
LOCK
1
LPFORC
LPLEN
Register 66h
Note:
1) LOCKST will be logic
low if either XCLK or the
LVDS PLL output is
unstable.
2) SYNCST will be logic
low if either Hsync or
Vsync is unstable or
missing.
PANEN
LSYNCEN
LPLOCK
LPFORC
LPLEN
HSYNC
VSYNC
BKLEN
SYNC
DETECT
SYNCST
LSYNCEN
XCLK
Detect
XCLK
CLKDETD
Reg. 14h [2]
FOSC (from oscillator)
ENAVDD
ENABKL
Power Sequencing
Figure 6: Detection Circuits for Panel Protection
The power up sequence can occur only if (a) XCLK is not missing, (b) there are no missing HSYNC and VSYNC, (c)
the PLL CLOCK is stable, and (d) PANEN is set to 1. The power down sequence happens if any of those conditions fails.
The power up sequence can also occur if the panel protection circuitry is bypassed.
The panel protection circuitry is comprised of a LOCKDET block, which detects an unstable clock from the LVDS PLL,
a SYNCDET block, which detects missing inputs HSYNC and VSYNC and an XCLK Detect block which detects
missing XCLK. XCLK stability (assuming it is not missing) is determined by the number of PLL unlock signals
generated within one frame. This number is programmable via serial port using the BGLMT register (Register 7Fh).
The SYNCDET block consists of counters to count HSYNC and VSYNC pulses. One counter is used to count the
number of HSYNC pulses per frame over 3 frames. The end counts for all 3 frames must be equal to enable the power up
sequence. In addition, the SYNCDET block checks for the presence of VSYNC and HSYNC. If VSYNC is missing for 2
frames or if HSYNC is missing for 32us the power up sequence is disabled.
The XCLK Detect block detects if XCLK is missing for more than approximately 1.2us.
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The LOCKDET block and SYNCDET block can be defeated or bypassed independently through the LPMC register
(Register 66h) controls. To defeat the LOCKDET block set LPFORC to ‘1’ and LPLEN to ‘1’; to defeat the SYNCDET
block set LSYNCEN to 1. The XCLK Detect block can be defeated or bypassed independently through the CLKDETD
bit in Register 14h, bit 2. To defeat the XCLK Detect block set CLKDETD to ‘1’.
2.2.5
Emission Reduction Clock
LVDS data path can support a +- 2.5% emission reduction clock to reduce EMI emission. The frequency and amplitude
of the emission reduction triangle waveform can be programmed via the serial port.
For further details, please contact Chrontel Applications Group.
2.3 Power Down
The CH7304 can be powered down via software control to achieve very low standby current. For a complete description
of each individual bit please refer to the appropriate register description in Registers 63h and 76h.
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3.0 Register Control
The CH7304 is controlled via a serial port. The serial bus uses only the SC clock to latch data into registers, and does
not use any internally generated clocks so that the device can be written to in all power down modes. The device should
retain all register values during power down modes. For registers read/write operation, please refer to applications note
AN-61 for details.
3.1 Control Registers Index
The register controls are listed below, divided into three sections: General & Power Down controls, Input/Output
controls, and LVDS controls.
GENERAL & POWER DOWN CONTROLS
Address
14h
4Bh
CLKDETD
DID[7:0]
XCLK Detection Defeat
Device ID register
LODPDB[1:0]
LVDSPD
LVDS Output Driver Power Down control
LVDS Power Down
76h
63h
PANEN
RESETIB
Panel Enable (0 – begin Power off sequence, 1 Power-on)
Software SPP (serial port) reset
Software datapath reset
Timer – Black Light Disable (T3)
Timer – Black Light Enable (T2)
Timer – Power Off (T4)
Timer - Power On (T1)
Timer – Power Cycle (T5)
Enable/select test pattern generation (color bar, ramp)
Version ID register
66h
48h
48h
69h
RESETDB
TPBLD [6:0]
TPBLE [6:0]
TPOFF [8:0]
TPON [8:0]
TPPWD [5:0]
TSTP[1:0]
VID[7:0]
68h
69h-6Ah
67h-68h
6Bh
48h
4Ah
INPUT/OUTPUT CONTROLS
Address
1Fh
IBS
Input buffer type select
IDF[2:0]
MCP
RGB
Input Data Format
XCLK Polarity Control
YCrCb to RGB
1Fh
1Ch
31h
XCM
XCLK 1X / 2X select
1Ch
XCMD[3:0]
Delay adjust between XCLK and D[11:0]
1Dh
LVDS CONTROLS
BGLMT[7:0]
BKLEN
FRSTB
LDD
Address
7Fh
66h
76h
64h
64h
73h
64h
74h
74h
74h
75h
73h
71h
71h
66h
66h
Bang Limit control of internal LVDS FIFO over/under run
Backlight enable
FIFO Reset Enable
LVDS Dithering Defeat
Open LDI mode
LDI
LDEN[1:0]
LEOSWP
LODA[2:0]
LODP
LODPE
LODST
LPCP[2:0]
LPFBD[3:0]
LPFFD[1:0]
LPFORC
LPLEN
LVDS Output Driver enable
Odd/even sample output swap on LVDS link
LVDS Output Driver Amplitude control for bank 1
LVDS Output Driver Pull-down
LVDS Output Driver Pre-emphasis
LVDS Output Driver Source Termination control
LVDS PLL Charge pump control
LVDS PLL feed back divider controls
LVDS PLL feed forward divider controls
Bypass LVDS PLL Lock Detect Sentry
Enable Bypass of LVDS PLL Lock Detect
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LPLF[2:0]
LPLF[4:3]
LPLOCK
LPPD[4:0]
LPPDN
LVDS PLL Loop Filter Resistor Value
LVDS PLL Loop Filter Capacitor Value
LVDS PLL Lock – read only register
LVDS PLL phase detector trim
LVDS PLL Power Down
76h
78h
66h
78h
76h
76h
72h
72h
66h
64h
66h
LPPRB
LVDS PLL Reset
LPPSD[1:0]
LPVCO[3:0]
LSYNCEN
LVDS24
LVDS PLL post scale divider controls
LVDS PLL VCO frequency range controls
Bypass Sync Detection
Select 24 bit format
HSYNC and VSYNC stability status
SYNCST
3.2 Control Registers Description
Table 7: Serial Port Register Map
Register Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
14h
1Ch
1Dh
1Fh
31h
48h
4Ah
4Bh
63h
64h
66h
67h
68h
69h
6Ah
6Bh
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VID6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VID5
Reserved
Reserved
Reserved
Reserved
Reserved
ResetIB
VID4
Reserved
Reserved
XCMD3
Reserved
Reserved
ResetDB
VID3
DID3
Reserved
LDD
LPFORC
TPON3
TPBLE3
TPBLD3
TPOFF3
TPPWD3
CLKDETD Reserved
Reserved
XCM
XCMD0
IDF0
RGB
TSTP0
VID0
DID0
Reserved
LDI
Reserved
Reserved
IBS
Reserved
Reserved
VID7
MCP
XCMD2
IDF2
Reserved
XCMD1
IDF1
Reserved
Reserved
VID2
Reserved
TSTP1
VID1
DID7
DID6
DID5
DID4
DID2
DID1
Reserved
Reserved
Reserved
TPON7
TPON8
TPOFF8
TPOFF7
Reserved
LVDSPD
Reserved
SYNCST
TPON6
TPBLE6
TPBLD6
TPOFF6
Reserved
Reserved
LVDS24
BKLEN
TPON5
TPBLE5
TPBLD5
TPOFF5
TPPWD5
Reserved
Reserved
LPLEN
TPON4
TPBLE4
TPBLD4
TPOFF4
TPPWD4
Reserved
Reserved
LPLOCK
TPON2
TPBLE2
TPBLD2
TPOFF2
TPPWD2
Reserved
LEOSWP
LSYNCEN PANEN
TPON1
TPON0
TPBLE1
TPBLD1
TPOFF1
TPPWD1
TPBLE0
TPBLD0
TPOFF0
TPPWD0
71h
72h
73h
74h
75h
76h
78h
7Fh
Reserved
Reserved
Reserved
LODP
LODST
FRSTB
Reserved
Reserved
Reserved
LODPE
Reserved
LPLF2
LPFFD1
LPPSD1
Reserved
Reserved
Reserved
LPLF1
LPFFD0
LPPSD0
LDEN1
Reserved
Reserved
LPLF0
LPFBD3
LPVCO3
LDEN0
Reserved
Reserved
LPPDN
LPFBD2
LPVCO2
LPCP2
LODA2
Reserved
LPPRB
LPFBD1
LPVCO1
LPCP1
LODA1
Reserved
LODPDB1
LPPD1
LPFBD0
LPVCO0
LPCP0
LODA0
Reserved
LODPDB0
LPPD0
LPCP3
BGLMT7
LPLF4
BGLMT6
LPLF3
BGLMT5
LPPD4
BGLMT4
LPPD3
BGLMT3
LPPD2
BGLMT2
BGLMT1
BGLMT0
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3.3 Control Registers Description
Clock Detect Defeat
Symbol:
Address:
CDD
14h
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved Reserved Reserved Reserved CLKDETD Reserved Reserved
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
DEFAULT:
CLKDETD (bit 2) of Register CDD controls the XCLK detection circuit. When CLKDETD is ‘1’ the XCLK detection
circuit is turned off, when CLKDETD is 0 the XCLK detection is on.
Clock Mode Register
Symbol:
Address:
CM
1Ch
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved Reserved Reserved Reserved
MCP
Reserved
XCM
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
XCM (bit 0) of Register CM signifies the XCLK frequency for the D[11:0] input. A value of ‘0’ is used when XCLK is
at the pixel frequency (dual edge clocking mode) and a value of ‘1’ is used when XCLK is twice the pixel frequency
(single edge clocking mode).
MCP (bit 2) of Register CM controls the phase of the XCLK clock input for the D[11:0] input. A value of ‘1’ inverts
the XCLK signal at the input of the device. This control is used to select which edge of the XCLK signal to use for
latching input data.
Input Clock Register
Symbol:
Address:
IC
1Dh
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved Reserved Reserved XCMD3 XCMD2 XCMD1 XCMD0
TYPE:
R/W
0
R/W
1
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
DEFAULT:
XCMD[3:0] (bits 3-0) of Register IC control the delay applied to the XCLK signal before latching input data D[11:0]
per the following table. tSTEP is given in Section 4.5.
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Table 8: Delay applied to XCLK before latching input data
XCMD3
XCMD2
XCMD1
XCMD0
Adjust phase of Clock relative to Data
0 * tSTEP, XCLK ahead of Data
1 * tSTEP, XCLK ahead of Data
2 * tSTEP, XCLK ahead of Data
3 * tSTEP, XCLK ahead of Data
4 * tSTEP, XCLK ahead of Data
5 * tSTEP, XCLK ahead of Data
6 * tSTEP, XCLK ahead of Data
7 * tSTEP, XCLK ahead of Data
0 * tSTEP, XCLK behind Data
1 * tSTEP, XCLK behind Data
2 * tSTEP, XCLK behind Data
3 * tSTEP, XCLK behind Data
4 * tSTEP, XCLK behind Data
5 * tSTEP, XCLK behind Data
6 * tSTEP, XCLK behind Data
7 * tSTEP, XCLK behind Data
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input Data Format Register
Symbol:
Address:
IDF
1Fh
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
IBS
Reserved Reserved Reserved Reserved
IDF2
IDF1
IDF0
TYPE:
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
IDF[2:0] (bits 2-0) of Register IDF select the input data format for the input. See Section 2.1.5 for a listing of available
formats.
IBS (bit 7) of Register IDF selects the data and clock input buffer type for the D[11:0] data according to the following
table:
Table 9: D[11:0] Input Buffer Type Selection
IBS
0
1
D[11:0] Input Buffer Type
CMOS, single ended type for clock and data
Differential (clock) and comparator (data) type
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Color Space Control
Symbol:
Address:
CSC
31h
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
RGB
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
RGB (bit 0) of Register CSC enables the YCrCb to RGB color space conversion for IDF4. This bit must be set to 1 to
enable YCrCb to RGB conversion.
RGB
=
=
0 => Disable YCrCb to RGB conversion
1 => Enable YCrCb to RGB conversion
Test Pattern Register
Symbol:
Address:
STP
48h
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved Reserved
Reserved
R/W
0
ResetIB ResetDB
TSTP1
R/W
0
TSTP0
R/W
0
TYPE:
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
DEFAULT:
TSTP[1:0] (bits 1:0) of Register STP enable and select test pattern generation (color bar, ramp). This test pattern can be
used for both the LVDS output and the TV Output. The pattern generated is determined by the table below:
Table 10: Test Pattern Selection
TSTP1
TSTP0
Test Pattern
0
0
1
1
0
1
0
1
No test pattern – Input data is used
Color Bars
Horizontal Luminance Ramp
Black screen
ResetDB (bit 3) of Register STP resets the datapath. When ResetDB is ‘0’ the datapath is reset. When ResetDB is ‘1’
the datapath is enabled. The datapath is also reset at power on by an internally generated power-on-reset signal.
ResetIB (bit 4) of Register STP resets all control registers. When ResetIB is ‘0’ the control registers are reset to the
default values. When ResetIB is ‘1’ the control registers operate normally. The control registers are also reset at power
on by an internally generated power on reset signal.
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Version ID Register
Symbol:
Address:
VID
4Ah
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
TYPE:
R
R
0
R
0
R
0
R
0
R
0
R
0
R
1
DEFAULT:
1
Register VID is a read only register containing the version ID number of the CH7304 family.
Product Number
Version ID
CH7304
81h
Device ID Register
Symbol:
Address:
DID
4Bh
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
DID7
DID6
DID5
DID4
DID3
DID2
DID1
DID0
TYPE:
R
0
R
0
R
X
R
1
R
1
R
0
R
1
R
X
DEFAULT:
Register DID is a read only register containing the device ID number of the CH7304 family. The Device ID depends on
the state of the CONFIG pin, pin39 (bit 5 and bit 0 of register 4Bh will update accordingly).
Product Number
CH7304
CONFIG
Device ID
3Ah
0
1
CH7304
1Bh
LVDS Power Down
Symbol:
Address:
LPD
63h
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved
R/W
0
Reserved Reserved Reserved Reserved Reserved Reserved
LVDSPD
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
LVDSPD (bit 6) of Register LPD controls the LVDS power down. When LVDSPD is ‘0’ the LVDS path is ON, when
LVDSPD is ‘1’ the LVDS path is powered down.
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LVDS Encoding Register
Symbol:
Address:
LVDSE
64h
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved
Reserved
Reserved
LDI
LVDS24
LDD
LEOSWP
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
DEFAULT:
LDI (bit 0) of register LVDSE controls OpenLDI specification selection. A ‘1’ corresponds to OpenLDI, and a ‘0’
corresponds to SPWG.
LEOSWP (bit 1) of Register LVDSE provides the added flexibility to swap odd/even samples output on the LVDS link.
LDD (bit 3) of Register LVDSE bypasses the dither function. A ‘1’ bypasses the dither function. A ‘0’ does not bypass
the dither function.
LVDS24 (bit 5) of Register LVDSE selects LVDS 24 bit or 18 bit output format. A ‘1’ provides 24-bit output mode
and a ‘ 0’ provides 18- bit output mode.
LVDS PLL Miscellaneous Control Register
Symbol:
Address:
LPMC
66h
BIT:
7
6
3
4
3
2
1
0
SYMBOL:
Reserved SYNCST BKLEN LPLEN LPFORC LPLOCK LSYNCEN PANEN
TYPE:
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
R/W
1
DEFAULT:
The LPMC register controls panel protection circuits which control the LVDS panel power up and down sequence.
Refer to Section 2.2.4 Panel Protection and to Figure 6 for more details.
PANEN (bit 0) of the LPMC register controls the LVDS panel enable.
PANEN
= 0 => Begin Power off sequence
= 1 => Power-on
LSYNCEN (bit 1) of the LPMC register controls the Sync Detection Bypass
LSYNCEN = 0 => Normal Operation. HSYNC and VSYNC detection enabled.
= 1 => HSYNC and VSYNC detection circuit is bypassed enabling forced power up sequence.
LPLOCK (bit 2) of the LPMC register indicates the status of the PLL Lock
LPLOCK = 0 => PLL is not stable.
= 1 => PLL is stable and properly locked.
LPFORC (bit 3) of the LPMC register: Bypass LVDS Lock Detect Sentry
Bit 3
= 0 => Lock detect sentry is active.
= 1 => Lock detect sentry is overridden if LPLEN is set to ‘1’.
LPLEN (bit 4) of the LPMC register controls LVDS PLL Lock Enable between LPLOCK and LPFORC.
LPLEN
= 0 => Select LPLOCK (normal operation)
= 1 => Select LPFORC (Lock detect sentry is overridden if LPFORC is set to ‘1’)
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BKLEN (bit 5) of the LPMC register enables the panel backlight.
BKLEN
= 0 => Disable Backlight
= 1 => Enable Backlight
SYNCST(bit 6) of the LPMC register is the Hsync and Vsync stability status bit. Refer to Section 2.2.4.
SYNCST = 0 => Hsync or Vsync are not stable
= 1 => Hsync and Vsync are stable
Power Sequencing T1
Symbol:
Address:
PST1
67h
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TPON7 TPON6 TPON5 TPON4 TPON3 TPON2 TPON1 TPON0
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
This register defines Power On time (T1), the time duration between LVDS_RDY (internal signal) to valid LVDS Clock
and Data. The entire bit field, TPON[8:0], is comprised of these bits TPON[7:0] plus TPON8 contained in the PST2
Power Sequencing T2 register (Register 68h, bit 7). Refer to Figure 5 and Table 6 in Section 2.2.3. The range of T1 is
2ms to 512ms in increments of 1ms.
Power Sequencing T2
Symbol:
Address:
PST2
68h
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TPON8 TPBLE6 TPBLE5 TPBLE4 TPBLE3 TPBLE2 TPBLE1 TPBLE0
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
TPBLE[6:0] (bits 6:0) of Register PST2 define the Back Light Enable time (T2), the waiting time after valid LVDS
Clock and Data before enabling the LVDS panel back light. Refer to Figure 5 and Table 6 in Section 2.2.3. The range
of T2 is 2ms to 256ms in increments of 2ms.
TPON8 (bit 7) of Register PST2 defines the MSB of the Power On time (T1). The entire bit field, TPON[8:0], is
comprised of this bit, TPON8, plus TPON[7:0] contained in the Power Sequencing T1 register (Register 67h). Refer to
the description of the PST1 register (Register 67h) for more information.
Power Sequencing T3
Symbol:
Address:
PST3
69h
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TP0FF8 TPBLD6 TPBLD5 TPBLD4 TPBLD3 TPBLD2 TPBLD1 TPBLD0
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
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TPBLD[6:0] (bits 6-0) of Register PST3 define the Back Light Disable time (T3), the required time after disabling the
back light before the valid LVDS Clock and Data become tri-stated or disabled. Refer to Figure 5 and Table 6 in
Section 2.2.3. The range of T3 is 2ms to 256ms in increments of 2ms.
TPOFF8 (bit 7) of Register PST3 defines the MSB of the Power Off time (T4). The entire bit field, TPOFF[8:0], is
comprised of this bit, TPOFF8, plus TPOFF[7:0] contained in the Power Sequencing T4 register (Register 6Ah). Refer
to the description of the PST4 register (Register 6Ah) for more information.
Power Sequencing T4
Symbol:
Address:
PST4
6Ah
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TPOFF7 TPOFF6 TPOFF5 TPOFF4 TPOFF3 TPOFF2 TPOFF1 TPOFF0
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
Register PST4 defines the Power Off time (T4), the required time prior to power off after the valid LVDS Clock and
Data become tri-stated or disabled. The entire bit field, TPOFF[8:0], is comprised of these bits, TPOFF[7:0], plus
TPOFF8 contained in the Power Sequencing T3 register (Register 69h, bit 7). Refer to Figure 5 and Table 6 in
Section 2.2.3.
The range is 2ms to 512ms in increments of 1ms.
Power Sequencing T5
Symbol:
Address:
PST5
6Bh
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved TPPWD5 TPPWD4 TPPWD3 TPPWD2 TPPWD1 TPPWD0
TYPE:
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
DEFAULT:
TPPWD[5:0] (bits 5-0) of Register PST5 define the Power Cycle time (T5), the waiting time required prior to enabling
power on after power has been off. Refer to Figure 5 and Table 6 in Section 2.2.3. The range is 2ms to 1600ms in
increments of 50ms.
LVDS PLL Feed Back Divider Control
Symbol:
Address:
LPFBDC
71h
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved LPFFD1 LPFFD0 LPFBD3 LPFBD2 LPFBD1 LPFBD0
TYPE:
R/W
1
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
DEFAULT:
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CH7304
LPFBD[3:0] (bits 3-0) of Register LPFBDC define the LVDS PLL Feed-Back Divider Control. The recommended
settings are shown in Table 15 in Section 0.
LPFFD[1:0] (bits 5:4) of Register LPFBDC define the LVDS PLL Feed-Forward Divider Control. The recommended
settings are shown in Table 15 in Section 0.
LVDS PLL VCO Control Register
Symbol:
Address:
LPVC
72h
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved LPPSD1 LPPSD0 LPVCO3 LPVCO2 LPVCO1 LPVCO0
TYPE:
R/W
1
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
1
R/W
0
DEFAULT:
LPVCO[3:0] (bits 3-0) of Register LPVC determine the LVDS PLL VCO open-loop frequency range. The
recommended settings are shown in Table 15 in Section 0.
LPPSD[1:0] (bits 5:4) of Register LPVC define the LVDS PLL post scale divider controls. The recommended settings
are shown in Table 15 in Section 0.
Outputs Enable Control Register
Symbol:
Address:
OUTEN
73h
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved Reserved Reserved
LDENO LPCP2
LPCP1
LPCP0
TYPE:
R/W
1
R/W
1
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
DEFAULT:
LPCP[2:0] (bits 2-0) of Register OUTEN control the LVDS PLL Charge Pump current value. The recommended
settings are shown in Table 15 in Section 0.
LDEN[1:0] (bits 4-3) of Register OUTEN control the output drivers of the LVDS output (LDC[3:0], LDC*[3:0], LLC
and LLC*) per the following table:
Table 11: LVDS Output Drivers Enable
LDEN0
Description
0
1
LVDS Output Drivers disabled
LVDS Output Drivers enabled
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CH7304
LVDS Output Driver Amplitude control
Symbol:
Address:
LODA
74h
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
Reserved Reserved Reserved
LODP
LODPE
LODA2 LODA1 LODA0
TYPE:
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
LODA[2:0] (bits 2-0) of Register LODA controls the Output Driver Amplitude. See Table 12.
Table 12: LVDS Output Driver Amplitude
LODA2
LODA1
LODA0
Output Driver Amplitude (mV)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
305
285
265
245
225
410
370
330
LODPE (bit 6) of Register LODA controls LVDS Output Driver Pre-Emphasis for both LDC[7:4] and LDC[3:0] by
simultaneous Pull-up and Pull-down diode currents.
LODPE = 0 =>
= 1 =>
Pull up reduced by 33% and pull down reduced by 66%.
Default value
LODP (bit 7) of Register LODA activates the LVDS Outputs Driver Pull-Down during power-down.
LODP
= 0 =>
= 1 =>
Pull-down devices not active
Pull-down devices active
LVDS Source Termination
Symbol:
Address:
LST
75h
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
LODST Reserved Reserved Reserved Reserved Reserved Reserved Reserved
TYPE:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
LODST (bit 7) of Register LST controls the LVDS Output Drive Source Termination.
LODST = 0 =>
= 1 =>
100Ω shunt disabled between LVDS outputs LDCx and LDCx*, also LLC and LLC*
100Ω shunt enabled between LVDS outputs LDCx and LDCx*, also LLC and LLC*
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CH7304
LVDS Power Down
Symbol:
Address:
LPD
76h
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
FRSTB
R/W
1
LPLF2
R/W
0
LPLF1
LPLF0
LPPDN LPPRB Reserved LODPDB0
TYPE:
R/W
1
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
DEFAULT:
LODPDB[1:0] (bits 1-0) of Register LPD control the LVDS Output Power Down per the following table:
Table 13: LVDS Output Power Down
LODPDB0 LDC[3:0] , LLC & LLC* path
0
1
Power Down
Power On
Note: Outputs are tri-stated in power down mode unless LODP (Register 74h, bit 7) is ‘1’, in which case outputs are
pulled to ground.
LPPRB (bit 2) of Register LPD controls the LVDS PLL Reset.
LPPRB = 0 =>
= 1 =>
LVDS PLL is reset
Normal operation
LPPDN (bit 3) of Register LPD controls the LVDS PLL Power Down.
LPPDN = 0 =>
= 1 =>
LVDS PLL is powered down
Normal operation
LPLF[2:0] (bits 6-4) of Register LPD control the LVDS PLL Loop Filter Resistor per the following table:
Table 14: LVDS PLL Loop Filter Resistor
LPLF2
LPLF1
LPLF0
PLL Loop Filter Resistor Value (Ohm)
1800
2600
1000
3200
21,800
42,600
11,000
73,200
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
The recommended setting is shown in Table 15 in Section 0.
FRSTB (bit 7) of Register LPD controls the FIFO reset.
FRSTB = 0 =>
= 1 =>
Enable FIFO Reset
Normal Operation
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CH7304
LVDS Control
Symbol:
Address:
LVCTL
78h
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
LPCP3
LPLF4
LPLF3
LPPD4
LPPD3
LPPD2
LPPD1
LPPD0
TYPE:
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
DEFAULT:
LPPD[4:0] (bits 4-0) of Register LVCTL define the LVDS PLL Phase Detector Control. The recommended settings are
shown in Table 15 in Section 0.
LPLF[4:3] (bits 6-5) of Register LVCTL control the LVDS PLL Loop Filter Capacitor. The recommended settings are
shown in Table 15 in Section 0.
LPCP3 (bit 7) of Register LVCTL enables the LVDS PLL Static Phase Error Reduction. The default value is
recommended.
LPCP3
= 0 =>
= 1 =>
Static Phase Error Reduction Disabled
Static Phase Error Reduction Enabled
Bang Limit Control
Symbol:
Address:
BGLMT
7Fh
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
BGLMT7 BGLMT6 BGLMT5 BGLMT4 BGLMT3 BGLMT2 BGLMT1 BGLMT0
TYPE:
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
DEFAULT:
This register limits the allowable occurrences of internal LVDS FIFO over and under-runs within one VGA frame.
The recommended setting is shown in Table 15 in Section 0.
Recommended Settings
The recommended values for the LVDS PLL are shown in Table 15 below.
Table 15: LVDS Control Settings
Address/Bit
800 x 600
1024 x 768
1280 x 1024
71h
72h
73h
74h
76h
78h
7Fh
ADh
ADh
C8h
F6h
ADh
80h
ADh
ADh
C8h
F6h
ADh
80h
A3h
ADh
DBh
F6h
AFh
80h
10h
10h
10h
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CHRONTEL
CH7304
4.0 Electrical Specifications
4.1 Absolute Maximum Ratings
Symbol
Description
Min
-0.5
Typ
Max
5.0
Units
V
All power supplies relative to GND
Input voltage of all digital pins
Analog output short circuit duration
Ambient operating temperature
Storage temperature
GND – 0.5
VDD + 0.5
V
T
SC
Indefinite
Sec
°C
T
AMB
0
85
T
STOR
-65
150
150
260
245
225
°C
T
J
Junction temperature
°C
T
VPS
Vapor phase soldering (5 second )
Vapor phase soldering (11 second )
Vapor phase soldering (60 second )
°C
°C
°C
Note:
1) Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions above those
indicated under the normal operating condition of this specification is not recommended. Exposure to absolute
maximum rating conditions for extended periods may affect reliability. The temperature requirements of vapor
phase soldering apply to all standard and lead free parts.
2) The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive
device. Voltage on any signal pin that exceeds the power supply voltages by more than ± 0.5V can induce
destructive latchup.
4.2 Recommended Operating Conditions
Symbol
LPLL_VDD
DVDD
Description
Min
3.1
3.1
3.1
3.1
1.1
Typ
3.3
3.3
3.3
3.3
1.8
Max
3.6
Units
LVDS PLL Power Supply Voltage
Digital Power Supply Voltage
LVDS Power Supply Voltage
Generic for all of the above supplies
I/O Power Supply Voltage
V
V
V
V
V
3.6
LVDD
3.6
VDD
3.6
VDDV
3.6
4.3 Electrical Characteristics
(Operating Conditions: TA = 0°C – 70°C, VDD =3.3V ± 5%)
Symbol
Description
Min
Typ
Max
Units
Total supply current
I
VDD
VDD
1 DVO input for LVDS @ 162 MHz
LVDS output @ 162 MHz
Total supply current
210
280
mA
I
1 DVO input for LVDS@65 MHz
LVDS output @ 65 MHz
130
175
0.1
mA
I
I
VDDV (1.8V) current (15pF load)
Total Power Down Current
4
mA
mA
VDDV
PD
0.01
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CH7304
4.4 Digital Inputs / Outputs
Symbol
Description
Test Condition
Min
Typ
Max
Unit
VSDOL
SPD (serial port data) Output
Low Voltage
I
= 2.0 mA
0.4
V
OL
VSPIH
VSPIL
Serial Port (SPC, SPD) Input
High Voltage
1.0
VDD + 0.5
0.4
V
V
Serial Port (SPC, SPD) Input
Low Voltage
GND-0.5
VHYS
Hysteresis of Inputs
0.25
Vref+0.25
GND-0.5
2.7
V
V
V
V
VDATAIH
VDATAIL
VMISCAIH
D[11:0] Input High Voltage
D[11:0] Input Low Voltage
DVDD+0.5
Vref-0.25
VDD + 0.5
CONFIG, RESET*
Input High Voltage
DVDD=3.3V
DVDD=3.3V
VIN = 0V
VMISCAIL
IMISCAPU
CONFIG, RESET*
Input Low Voltage
GND-0.5
0.5
0.6
5
V
Pull Up Current
uA
(CONFIG, RESET*)
CONFIG, ENAVDD, ENABKL,
Output High Voltage
VMISCAOH
VMISCAOL
I
I
= -0.4mA
= 3.2mA
VDD-0.2
V
V
OH
OL
CONFIG, ENAVDD, ENABKL,
Output Low Voltage
0.2
4.5 AC Specifications
Symbol
fXCLK
Description
Test Condition
Min
25
Typ
Max
165
40
Unit
MHz
ns
Input (XCLK) frequency
Pixel time period
tPIXEL
DCXCLK
tXJIT
6.06
30
Input (XCLK) Duty Cycle
XCLK clock jitter tolerance
TS + TH < 1.2ns
70
%
2
ns
Setup Time: D[11:0], H, V and
DE to XCLK, XCLK*
tS
XCLK = XCLK* to
D[11:0], H, V, DE =
Vref
0.5
0.5
50
ns
Hold Time: D[11:0], H, V and
DE to XCLK, XCLK*
tH
D[11:0], H, V, DE =
Vref to XCLK =
XCLK*
ns
ps
tSTEP
De-skew time increment
80
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CH7304
4.6 LVDS Output Specifications
The LVDS specifications meet the requirements of ANSI/EIA/TIA-644. Refer to Figure 7 for definitions of parameters.
Symbol
Description
Test Condition
100Ω differential load
100Ω differential load
100Ω differential load
Min
247
247
Typ
Max
453
453
50
Unit
mV
mV
mV
Steady State Differential
Output Magnitude for logic 1
Steady State Differential
Output Magnitude for logic 0
Steady State Magnitude of
Difference between Logic 1
and 0 Outputs
| Vt |
| Vt *|
| Vt | - | Vt *|
|VOS
|
Steady State Magnitude of
Offset Voltage for Logic 1
Measured at center-
tap of two 50Ω
1.125
1.125
1.375
1.375
50
V
resistors connected
between outputs
|VOS* |
Steady State Magnitude of
Offset Voltage for Logic 0
Measured at center-
tap of two 50Ω
V
resistors connected
between outputs
|VOS | - |VOS* |
Steady State Magnitude of
Offset Difference between
Logic States
Measured at center-
tap of two 50Ω
mV
resistors connected
between outputs
fLLC
LVDS Output Clock
Frequency
25
108 1
5.7
MHz
ns
tUI
LVDS data unit time interval
25MHz < fLLC
108MHz
<
1.3
tR
LVDS data rise time
100Ω and 5pF
differential load
t
UI > 5ns
0.3* tUI
1.5
ns
ns
20% -> 80% VSWING
1.3ns < tUI < 5ns
tF
LVDS data fall time
100Ω and 5pF
differential load
t
UI > 5ns
0.3* tUI
1.5
ns
ns
80% -> 20% VSWING
1.3ns < tUI < 5ns
VRING
Voltage ringing after transition 100Ω and 5pF
20%
differential load
VSWING
Note 1: Corresponds to maximum pixel rate fXCLK for single channel operation. Dual channel operation is required for
pixel rates greater than 108MHz.
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CH7304
4.7 Timing Information
4.7.1
LVDS Output Timing
Vring
+/-20% Vswing
0.8 Vswing
+Vt
Vswing
tj
0V Differential
-Vt
0.2 Vswing
tr
tf
tui
Figure 7: AC Timing for LVDS Outputs
Table 16: AC Timing for LVDS Outputs
Symbol
Parameter
Min
Typ
Max
Steady State Differential Output Magnitude
| Vt |
see section 4.6
Voltage Difference between the two Steady State Values of Output
VSWING
Unit time interval
Rise time
tUi
tr
see section 4.6
see section 4.6
see section 4.6
tf
Fall time
tj
Jitter peak to peak1
350ps
Note 1: Maximum jitter with EMI reduction turned off.
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CHRONTEL
CH7304
4.7.2
LVDS Input Timing: Clock - Slave, Sync - Slave Mode
t1
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
XCLK
XCLK*
D[11:0]
DE
tH
tS
P0a P0b P1a
P1b P2a
P2b
t2
tS
tH
tH
tS
H
64 PIXELS
V IL
V IH
t2
V
1 VGA
Line
V IL
t2
t2
Figure 8: Timing for Clock - Slave, Sync - Slave Mode
Table 17: Timing for Clock
Symbol
Parameter
Min
Typ
Max
Unit
Setup Time: D[11:0], H, V and DE to XCLK, XCLK*
Hold Time: D[11:0], H, V and DE to XCLK, XCLK*
tS
see Section 4.5
tH
t1
t2
see Section 4.5
XCLK & XCLK* rise/fall time w/15pF load
D[11:0], H, V & DE rise/fall time w/ 15pF load
1
1
ns
ns
30
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CHRONTEL
CH7304
5.0 Package Dimensions
A
B
I
1
A B
H
D
C
J
LEA
D
CO-
PLANARITY
H
.004 “
F
G
Table of Dimensions
No. of Leads
SYMBOL
64 (10 X 10 mm)
A
B
C
D
E
F
G
H
I
J
Milli-
meters
MIN
MAX
0.17
0.27
1.35
1.45
0.05
0.15
0.45
0.75
0.09
0.20
0°
7°
12
10
0.50
1.00
Figure 9: 64 Pin LQFP Package
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CHRONTEL
CH7304
6.0 Revision History
Rev. #
1.0
1.1
Date
4/8/03
5/15/03
Section
All
Figure 1
4.3
Description
First official release, Revision 1.0
Deleted AS pin from Figure 1
Added supply current limits
Added Table of Contents
Added section 4.6 and 4.7.1.
Corrected description of DID.
6/23/03
2/3/04
1.2
4.6, 4.7.1
Register
4Bh
All
All
Removed all references to the GOENB and GPIOL bits.
Changed pin name of GPIO to CONFIG
Figure 1
1. Renamed GPIO pin to CONFIG
2. Renamed LL1C and LL1C* to LLC and LLC*
3. Removed LDC[7:4], LDC*[7:4], LL2C, and LL2C*
Back Page Added Ordering Information
1.3
1.31
11/09/04
6/14/06
Back Page Added lead free and tape & reel order information
Back Page Corrected part number of lead free and tape & reel.
32
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CHRONTEL
CH7304
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at any time
without notice to improve and supply the best possible product and is not responsible and does not assume any liability
for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our
products and assume no liability for errors contained in this document. The customer should make sure that they have
the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does not
infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist
others to infringe upon such rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as
directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Part Number
CH7304A-T
Package Type
LQFP
Number of Pins
64
Voltage Supply
3.3V
LQFP,
Tape&Reel
CH7304A-T-TR
CH7304A-TF
64
64
64
3.3V
3.3V
3.3V
LQFP, Lead free
LQFP, Lead free,
Tape&Reel
CH7304A-TF-TR
Chrontel
2210 O’Toole Avenue, Suite 100,
San Jose, CA 95131-1326
Tel: (408) 383-9328
Fax: (408) 383-9338
www.chrontel.com
E-mail: sales@chrontel.com
©2006 Chrontel, Inc. All Rights Reserved.
Printed in the U.S.A.
201-0000-053
Rev. 1.31, 6/14/2006
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