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CH7317A-BF [CHRONTEL]

D/A Converter, 1 Func, Serial Input Loading, 8 X 8 MM, 0.80 MM HEIGHT, LEAD FREE, MO-220, QFN-64;
CH7317A-BF
型号： CH7317A-BF
厂家： CHRONTEL, INC    CHRONTEL, INC
描述：

D/A Converter, 1 Func, Serial Input Loading, 8 X 8 MM, 0.80 MM HEIGHT, LEAD FREE, MO-220, QFN-64

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CH7317A  
Chrontel  
CH7317A SDVO◊ / RGB DAC  
Features  
General Description  
High-speed SDVO◊ (1G~2Gbps) AC-coupled serial  
The CH7317A is a Display Controller device which accepts  
a digital graphics high speed AC coupled serial differential  
RGB input signal, and encodes and transmits data through  
analog RGB port. The device accepts one channel of RGB  
data over three pairs of serial data ports.  
•
differential RGB inputs  
•
•
•
•
•
•
•
•
•
Support for VGA RGB bypass  
Output Analog RGB.  
Three 10-bit video DAC outputs  
DAC output CRT RGB connector  
Fully programmable through serial port  
Programmable power management  
Configuration through Intel® SDVO OpCode◊  
Complete Windows driver support  
Offered in 64-pin LQFP and 64-pin QFN package  
CH7317A output VGA style analog RGB for use as a CRT  
DAC. Supported analog video VGA connector.  
◊
Intel® Proprietary.  
AS  
SPC  
Serial  
Port  
Control  
XI/FIN,XO  
PLL  
2
SPD  
RESET*  
BCO/VSYNC  
C/HSYNC  
SC_DDC  
SD_DDC  
Control  
SC_PROM  
SD_PROM  
Clock  
Driver  
DAC 2  
DAC 1  
DAC 0  
SDVO_Clk(+,-)  
2
DACA[2:0]  
ISET  
3
10bit-8bit  
decoder  
Three  
10-bit DAC's  
SDVO_R(+,-)  
SDVO_G(+,-)  
SDVO_B(+,-)  
Data Latch,  
Serial to Parallel  
6
Figure 1: Functional Block Diagram  
201-0000-087  
Rev. 1.2, 12/2/2008  
1
 
CHRONTEL  
CH7317A  
Table of Contents  
1.0 Pin-Out ____________________________________________________________________ 4  
1.1  
1.2  
Package Diagram ___________________________________________________________________4  
Pin Description _____________________________________________________________________6  
2.0 Functional Description________________________________________________________ 8  
2.1  
2.2  
2.3  
2.4  
Input Interface______________________________________________________________________8  
CRT Bypass Operation_______________________________________________________________8  
Command Interface _________________________________________________________________9  
Boundary scan Test__________________________________________________________________9  
3.0 Register Control ____________________________________________________________ 12  
4.0 Electrical Specifications______________________________________________________ 13  
4.1  
4.2  
4.3  
4.4  
4.5  
Absolute Maximum Ratings __________________________________________________________13  
Recommended Operating Conditions___________________________________________________13  
Electrical Characteristics ____________________________________________________________14  
DC Specifications__________________________________________________________________14  
AC Specifications__________________________________________________________________16  
5.0 Package Dimensions_________________________________________________________ 18  
6.0 Revision History ____________________________________________________________ 20  
2
201-0000-087  
Rev. 1.2,  
12/2/2008  
CHRONTEL  
CH7317A  
Figures and Tables  
List of Figures  
Figure 1: Functional Block Diagram .............................................................................................................................1  
Figure 2: 64-Pin LQFP Package....................................................................................................................................4  
Figure 3: 64-Pin QFN Package......................................................................................................................................5  
Figure 4: Control Bus Switch ........................................................................................................................................9  
Figure 5: NAND Tree Connection...............................................................................................................................10  
Figure 6: 64 Pin LQFP Package ..................................................................................................................................18  
Figure 7: 64 Pin QFN Package (8 x 8 x 0.8mm) .........................................................................................................19  
List of Tables  
Table 1: Pin Description................................................................................................................................................6  
Table 2: CH7317A supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns...................................8  
Table 3: Video DAC Configurations for CH7317A......................................................................................................9  
Table 4: Signal Order in the NAND Tree Testing.......................................................................................................10  
Table 5: Signals not be tested in NAND Test besides power pins...............................................................................11  
Table 6: Revisions .......................................................................................................................................................20  
201-0000-087  
Rev. 1.2, 12/2/2008  
3
CHRONTEL  
CH7317A  
1.0 Pin-Out  
1.1 Package Diagram  
1.1.1  
The 64-Pin LQFP Package Diagram  
NC  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
1
2
3
4
5
6
7
8
NC  
SD_DDC  
NC  
SC_DDC  
SD_PROM  
SC_PROM  
DVDD  
NC  
DGND  
NC  
NC  
Chrontel  
CH7317  
RESET*  
AS  
DVDD  
DVDD  
XO  
DGND  
DGND  
SPD  
9
10  
11  
12  
13  
14  
15  
16  
XI/FIN  
DGND  
DGND  
SPC  
DVDD  
BCO/VSYNC  
DVDD  
BSCAN  
NC  
C/HSYNC  
V3V  
VDAC2  
Figure 2: 64-Pin LQFP Package  
4
201-0000-087  
Rev. 1.2,  
12/2/2008  
 
CHRONTEL  
CH7317A  
1.1.2  
The 64-Pin QFN Package Diagram  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
NC  
NC  
NC  
NC  
SD_DDC  
SC_DDC  
1
2
3
DGND  
NC  
SD_PROM  
SC_PROM  
DVDD  
RESET*  
AS  
4
5
NC  
6
DVDD  
DVDD  
XO  
7
Chrontel  
CH7317  
8
DGND  
DGND  
SPD  
9
XI/FIN  
DGND  
DGND  
BCO/VSYNC  
DVDD  
C/HSYNC  
V3V  
10  
11  
12  
13  
14  
15  
16  
SPC  
DVDD  
BSCAN  
NC  
VDAC2  
Figure 3: 64-Pin QFN Package  
201-0000-087  
Rev. 1.2, 12/2/2008  
5
 
CHRONTEL  
CH7317A  
1.2 Pin Description  
Table 1: Pin Description  
Pin #  
Type  
Symbol  
Description  
Routed Serial Port Data Output to DDC  
2
In/Out  
SD_DDC  
This pin functions as the bi-directional data pin of the serial port to DDC receiver. This  
pin will require a 10k pull-up resistor to the desired high state voltage. Leave open if  
unused.  
Routed Serial Port Clock Output to DDC  
3
4
In/Out  
In/Out  
SC_DDC  
This pin functions as the clock bus of the serial port to DDC receiver. This pin will  
require a 10k pull-up resistor to the desired high state voltage. Leave open if unused.  
Routed Data Output to PROM  
This pin functions as the bi-directional data pin of the serial port for PROM on ADD2◊  
card. This pin will require a 10k pull-up resistor to the desired high state voltage. Leave  
open if unused.  
SD_PROM  
Routed Clock Output to PROM  
5
Out  
SC_PROM  
This pin functions as the clock bus of the serial port to PROM on ADD2 card. This pin  
will require a 10k pull-up resistor to the desired high state voltage. Leave open if  
unused.  
7
In  
RESET*  
AS  
Reset* Input (Internal pull-up)  
When this pin is low, the device is held in the power-on reset condition. When this pin  
is high, reset is controlled through the serial port register. This pin is 3.3V compliant.  
8
In  
Address Select (Internal pull-up)  
This pin determines the serial port address of the device (0,1,1,1,0,0,AS*,0). When AS  
is low the address is 72h, when high the address is 70h.  
11  
In/Out  
SPD  
Serial Port Data Input / Output  
This pin functions as the bi-directional data pin of the serial port and operates with  
inputs from 0 to 2.5V. Outputs are driven from 0 to 2.5V. This pin requires an external  
4kΩ - 9 kΩ pull up resistor to 2.5V.  
12  
14  
In/Out  
In  
SPC  
Serial Port Clock  
This pin functions as the clock of the serial port and operates from 0 to 2.5V. This pin  
requires an external 4kΩ - 9kΩ pull up resistor to 2.5V.  
BSCAN  
BSCAN  
(internal pull low)  
This pin should be left open or pulled low with a 10k resistor in the  
application. This pin enables the boundary scan for in-circuit testing. Voltage  
level is 0 to DVDD. This pin should be pulled low during normal operation.  
DAC Output A  
Video Digital-to-Analog outputs. Refer to section 2.2.1 for information regarding  
support for RGB Bypass outputs. Each output is capable of driving a 75-ohm doubly  
terminated load.  
20,24,28 Out  
DACA[2:0]  
NC  
No Connect ( Reserved )  
1,15,18,21,  
22,25,26,  
29,30,43,  
44,46,47,  
48,51  
◊
Intel Proprietary.  
6
201-0000-087  
Rev. 1.2,  
12/2/2008  
 
CHRONTEL  
CH7317A  
Table 1: Pin Description (contd.)  
Pin #  
Type  
Symbol  
Description  
32  
Ref.  
ISET  
Current Set Resistor  
This pin sets the DAC current. A 1.2Kohm (+/- 1%) resistor should be connected  
between this pin and DAC ground (pin 31) using short and wide traces.  
34  
Out  
CHSYNC  
Composite / Horizontal Sync Output  
A buffered version of VGA composite sync as well as horizontal sync can be  
acquired from this pin.  
36  
39  
Out  
In  
VSYNC  
XI/FIN  
VSYNC  
A buffered version of VGA vertical sync can be acquired from this pin.  
Crystal Input / External Reference Input  
A parallel resonant 27MHz crystal (±100 ppm) should be attached between  
this pin and XO. However, an external CMOS clock can drive the XI/FIN  
input.  
40  
Out  
XO  
Crystal Output  
A parallel resonant 27MHz crystal (±100 ppm) should be attached between  
this pin and XI/FIN. However, if an external CMOS clock is attached to the  
XI/FIN input, XO should be left open.  
50  
In  
RPLL  
PLL Resistor Input  
External resistor 10Kohm should be connected between this pin and pin 49.  
53,54,56, In  
57,59,60  
SDVO_R+/-,  
SDVO_G+/-,  
SDVO_B+/-  
SDVO_CLK+/-  
SDVO Data Channel Inputs  
These pins accept 3 AC-coupled differential pair of RGB inputs from a digital video  
port of a graphics controller.  
Differential Clock Input associated with SDVO Data channel  
(SDVO_R+/-, SDVO_G+/-, SDVO_B+/-)  
62,63  
In  
The range of this clock pair is 100~200MHz. For specified pixel rates in specified  
modes this clock pair will run at an integer multiple of the pixel rate. Refer to  
section 2.1.3 for details.  
6,13,35,41, Power  
42  
9,10,37,38, Power  
45  
DVDD  
DGND  
Digital Supply Voltage (2.5V)  
Digital Ground  
16  
17  
19  
23  
27  
31  
Power  
Power  
Power  
Power  
Power  
Power  
VDAC2  
GDAC2  
VDAC1  
GDAC1  
VDAC0  
GDAC0  
AVDD  
AGND  
V3V  
DAC Supply Voltage (3.3V)  
DAC Ground  
DAC Supply Voltage (3.3V)  
DAC Ground  
DAC Supply Voltage (3.3V)  
DAC Ground  
Analog Supply Voltage (2.5V)  
Analog Ground  
52,58,64 Power  
49,55,61 Power  
33  
Power  
3.3V Supply Voltage (3.3V)  
201-0000-087  
Rev. 1.2, 12/2/2008  
7
CHRONTEL  
CH7317A  
2.0 Functional Description  
2.1 Input Interface  
2.1.1 Overview  
One pair of differential clock signal and three differential pairs of data signals (R/G/B) form one channel data. The  
input data are 10-bit serialized data. Input data run at 1Gbits/s~2Gbits/s, being a 10x multiple of the clock rate  
(SDVO_CLK+/-). The CH7317A de-serializes the input into 10-bit parallel data with synchronization and  
alignment. Then the 10-bit characters are mapped into 8-bit color data or control data (Hsync, Vsync, DE).  
2.1.2 Interface Voltage Levels  
All differential SDVO pairs are AC coupled differential signals. Therefore, there is not a specified DC signal level  
for the signals to operate at. The differential p-p input voltage has a min of 175mV, and a max of 1.2V. The  
differential p-p output voltage has a min of 0.8V, with a max of 1.2V.  
2.1.3 Input Clock and Data Timing  
A data character is transmitted least significant bit first. The beginning of a character is noted by the falling edge of  
the SDVO_CLK+ edge. The skew among input lanes is required to be no larger than 2ns.  
The clock rate runs at 100MHz~200MHz. The pixel rate can be 25MP/s~165MP/s. The pixel rate and the clock rate  
do not always equal. The clock rate can be a multiple of the pixel rate (1x, 2x or 4x depending on the pixel rate) so  
that the clock rate will be stay in the 100MHz~200MHz range. In the condition that the clock rate is running at a  
multiple of the pixel rate, there isn’t enough pixel data to fill the data channels. Dummy fill characters  
(‘0001111010’) are used to stuff the data stream. The CH7317A supports the following clock rate multipliers and  
fill patterns shown in Table 2.  
Table 2: CH7317A supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns  
Pixel Rate  
25~50 MP/s  
50~100 MP/s  
Clock Rate – Multiplier  
100~200 MHz – 4xPixel Rate  
100~200 MHz – 2xPixel Rate  
Stuffing Format  
Data, Fill, Fill, Fill  
Data, Fill  
Data Transfer Rate - Multiplier  
1.00~2.00 Gbits/s – 10xClock Rate  
1.00~2.00 Gbits/s – 10xClock Rate  
1.00~2.00 Gbits/s – 10xClock Rate  
100~200 MP/s 100~200 MHz – 1xPixel Rate  
Data  
2.1.4 Synchronization  
Synchronization and channel-to-channel de-skewing is facilitated by the transmission of special characters during  
the blank period. The CH7317A synchronizes during the initialization period and subsequently uses the blank  
periods to re-synch to the data stream.  
2.2 CRT Bypass Operation  
The CH7317A operates in CRT RGB Bypass mode. In CRT Bypass mode, data from the graphics device, after  
proper decoding, are bypassed directly to the video DACs to implement a second CRT DAC function. Sync signals,  
after proper decoding, are buffered internally, and can be output to drive the CRT. The CH7317A can support a  
pixel rate of 200MHz. This operating mode uses 8-bits of the DAC’s 10-bit range, and provides a nominal signal  
swing of 0.661V (or 0.7V depending on DAC Gain setting in control registers) when driving a 75Ω doubly  
terminated load. No scaling, scan conversion or flicker filtering is applied in CRT Bypass modes.  
8
201-0000-087  
Rev. 1.2,  
12/2/2008  
 
CHRONTEL  
CH7317A  
2.2.1 Video DAC Outputs  
Table 3 below lists the DAC output configurations of the CH7317A.  
Table 3: Video DAC Configurations for CH7317A  
Output Type  
DACA[0]  
DACA[1]  
DACA[2]  
CRT RGB  
B
G
R
2.3 Command Interface  
Communication is through two-wire path, control clock (SPC) and data (SPD). The CH7317A accepts incoming  
control clock and data from graphics controller, and is capable of redirecting that stream to an ADD2 card PROM,  
DDC, or CH7317A internal registers. The control bus is able to run up to 1MHz when communicating with internal  
registers, up to 400kHz for the PROM and up to 100kHz for the DDC.  
Internal  
Device  
Registers  
control  
the  
observer  
switch  
on/off  
SPC,SPD  
DDC  
default  
position  
PROM  
Figure 4: Control Bus Switch  
Upon reset, the default state of the directional switch is to redirect the control bus to the ADD2 PROM. At this  
stage, the CH7317A observes the control bus traffic. If the observing logic sees a control bus transaction destined  
for the internal registers (device address 70h or 72h), it disables the PROM output pairs, and switches to internal  
registers. In the condition that traffic is to the internal registers, an op-code command is used to set the redirection  
circuitry to the appropriate destination (ADD2 PROM or DDC). Redirecting the traffic to internal registers while at  
the stage of traffic to DDC occurs on observing a STOP after a START on the control bus.  
2.4 Boundary scan Test  
CH7317A provides a called “NAND TREE Testing” to verify IO cell function at the PC board level. This test will  
check the interconnection between chip I/O and the printed circuit board for faults (soldering, bend leads, open  
printed circuit board traces, etc.). NAND tree test is a simple serial logic which turns all IO cell signals to input  
mode, connects all inputs with NAND gates as shown in the figure below and switches each signal to high or low  
according to the sequence in Table 4. The test results then pass out at pin 51 (NC).  
201-0000-087  
Rev. 1.2, 12/2/2008  
9
 
CHRONTEL  
CH7317A  
Figure 5: NAND Tree Connection  
Testing Sequence  
Set BSCAN =1; (internal weak pull low)  
Set all signals listed in Table 4 to 1.  
Set all signals listed in Table 4 to 0, toggle one by one with certain time period suggested 100ns. Pin 51 (NC) will  
change its value each time an input value changed.  
Table 4: Signal Order in the NAND Tree Testing  
Order Pin Name  
LQFP Pin  
2
3
4
5
1
SD_DDC  
SC_DDC  
SD_PROM  
SC_ PROM  
RESETB  
AS  
2
3
4
5
7
8
6
7
8
9
SPD  
SPC  
NC  
DACA[2]  
NC  
NC  
DACA[1]  
NC  
NC  
DACA[0]  
NC  
NC  
ISET  
CHSYNC  
VSYNC  
XI/FIN  
XO  
NC  
NC  
NC  
NC  
11  
12  
18  
20  
21  
22  
24  
25  
26  
28  
29  
30  
32  
34  
36  
39  
40  
43  
44  
46  
47  
48  
51  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
NC  
NC  
10  
201-0000-087  
Rev. 1.2,  
12/2/2008  
 
CHRONTEL  
CH7317A  
Table 5: Signals not be tested in NAND Test besides power pins  
Pin Name  
SDVO_R+  
SDVO_R-  
SDVO_G+  
SDVO_G-  
SDVO_B+  
SDVO_B-  
SDVO_CLK+  
SDVO_CLK-  
BSCAN  
LQFP Pin  
53  
54  
56  
57  
59  
60  
62  
63  
14  
15  
1
NC  
NC  
201-0000-087  
Rev. 1.2, 12/2/2008  
11  
 
CHRONTEL  
CH7317A  
3.0 Register Control  
The CH7317A is controlled via a serial control port. The serial bus uses only the SC clock to latch data into  
registers, and does not use any internally generated clocks so that the device can be written to in all power down  
modes. The device will retain all register values during power down modes.  
Registers 00h to 11h are reserved for op-code use. All registers except bytes 00h to 11h are reserved for internal  
factory use. For details regarding Intel® SDVO op-codes, please contact Intel®.  
12  
201-0000-087  
Rev. 1.2,  
12/2/2008  
 
CHRONTEL  
CH7317A  
4.0 Electrical Specifications  
4.1 Absolute Maximum Ratings  
Symbol  
Description  
Min  
Typ  
Max  
Units  
All 2.5V power supplies relative to GND  
All 3.3V power supplies relative to GND  
-0.5  
-0.5  
3.0  
5.0  
V
T
Analog output short circuit duration  
Ambient operating temperature  
Storage temperature  
Indefinite  
Sec  
°C  
SC  
T
AMB  
-20  
-65  
85  
T
STOR  
150  
150  
°C  
T
J
Junction temperature  
°C  
Vapor phase soldering (5 second)  
Vapor phase soldering (11 second)  
Vapor phase soldering (1 minute)  
260  
245  
225  
T
VPS  
°C  
Note:  
1) Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device.  
These are stress ratings only. Functional operation of the device at these or any other conditions above those  
indicated under the normal operating condition of this specification is not recommended. Exposure to absolute  
maximum rating conditions for extended periods may affect reliability. The temperature requirements of vapor  
phase soldering apply to all standard and lead free parts.  
2) The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive  
device. Voltage on any signal pin that exceeds the power supply voltages by more than ± 0.5V can induce  
destructive latch-up.  
4.2 Recommended Operating Conditions  
Symbol  
Description  
Min  
2.375  
2.375  
3.100  
3.100  
2.375  
3.100  
1188  
-20  
Typ  
2.5  
Max  
2.625  
2.625  
3.500  
3.500  
2.625  
3.500  
1212  
70  
Units  
AVDD  
Analog Power Supply Voltage  
Digital Power Supply Voltage  
DAC Power Supply  
V
DVDD  
VDAC  
VDD33  
VDD25  
V3V  
2.5  
V
3.3  
V
Generic for all 3.3V supplies  
Generic for all 2.5V supplies  
3.3V Power Supply  
3.3  
V
2.5  
V
3.3  
V
RSET  
Resistor on ISET pin (32)  
Ambient operating temperature  
1200  
Ω
°C  
201-0000-087  
Rev. 1.2, 12/2/2008  
13  
 
CHRONTEL  
CH7317A  
4.3 Electrical Characteristics  
(Operating Conditions: TA = -20°C – 70°C, VDD25 =2.5V ± 5%, VDD33 = 3. 3V ± 5%,)  
Symbol  
Description  
Min  
Typ  
10  
Max  
Units  
bits  
Video D/A Resolution  
Full scale output current  
Video level error  
10  
10  
35. 3  
mA  
10  
%
I
VDD25  
Total VDD25 supply current (2.5V supplies) with 1600x1200,  
32bit, 60H  
131  
105  
mA  
mA  
(162 MHz  
pixel clock)  
I
VDD33  
Total VDD33 supply current (3.3V supplies) with 1600x1200,  
32bit, 60H  
(162 MHz  
pixel clock)  
I
Total V3V current (3.3V supply)  
Total Power Down Current  
0
mA  
mA  
VDDV  
I
0.1  
PD  
4.4 DC Specifications  
Symbol  
Description  
Test Condition  
Min  
Typ  
Max  
Unit  
SDVO Receiver Differential  
Input Peak to Peak Voltage  
0.175  
1.200  
V
VRX-DIFFp-p  
VRX-DIFFp-p = 2 * ⏐VRX-D+  
- VRX-D-  
⏐
SDVO Receiver DC Differential  
Input Impedance  
80  
40  
5
100  
50  
120  
60  
Ω
Ω
Ω
ZRX-DIFF-DC  
SDVO Receiver DC Common  
Mode Input Impedance  
ZRX-COM-DC  
SDVO Receiver Initial DC  
Common Mode Input  
Impedance  
Impedance allowed when  
receiver terminations are  
first turned on  
50  
60  
ZRX-COM-INITIAL-  
DC  
SDVO Receiver Powered  
Down DC Common Mode  
Input Impedance  
Impedance allowed when  
receiver terminations are not  
powered  
20k  
0.8  
200k  
Ω
ZRX-COM-High-  
IMP-DC  
POCLK Differential Pk – Pk  
Output Voltage  
1.2  
0.4  
V
V
V
V
VPP_POCLK  
1
SPD (serial port data) Output  
Low Voltage  
VSDOL  
I
OL  
= 2.0 mA  
2
Serial Port (SPC, SPD) Input  
High Voltage  
2.0  
GND-0.5  
0.25  
+5V  
+0.5  
VSPIH  
2
Serial Port (SPC, SPD) Input  
Low Voltage  
0.4  
VSPIL  
Hysteresis of Serial Port Inputs  
V
V
VHYS  
VDDCIH  
DDC Serial Port  
+5V  
+0.5  
Input High Voltage  
4.0  
VDDCIL  
DDC Serial Port  
V
V
Input Low Voltage  
GND-0.5  
4.0  
0.4  
VPROMIH  
PROM Serial Port  
Input High Voltage  
+5V  
+0.5  
14  
201-0000-087  
Rev. 1.2,  
12/2/2008  
 
CHRONTEL  
CH7317A  
Symbol  
Description  
Test Condition  
Min  
Typ  
Max  
Unit  
VPROMIL  
PROM Serial Port  
Input Low Voltage  
V
GND-0.5  
0.4  
3
Input is VINL at SD_DDC or  
SD_EPROM.  
SPD (serial port data) Output  
Low Voltage from SD_DDC (or  
SD_EPROM)  
0.9*VINL  
0.25  
+
V
V
V
VSD_DDCOL  
4.0kΩ pullup to 2.5V.  
4
Input is VINL at SPC and  
SPD.  
SC_DDC and SD_DDC Output  
Low Voltage  
0.933*VINL  
+ 0.35  
VDDCOL  
5.6kΩ pullup to 5.0V.  
5
Input is VINL at SPC and  
SPD.  
SC_EPROM and SD_EPROM  
Output Low Voltage  
0.933*VINL  
+ 0.35  
VEPROMOL  
5.6kΩ pullup to 5.0V.  
6
RESET*  
Input High Voltage  
2.7  
GND-0.5  
2.0  
VDD33 +  
0.5  
V
V
VMISC1IH  
VMISC1IL  
VMISC2IH  
6
7
RESET*  
0.5  
Input Low Voltage  
AS, BSCAN  
Input High Voltage  
VDD25 +  
0.5  
V
7
AS, BSCAN  
Input Low Voltage  
DVDD=2.5V  
VIN = 0V  
GND-0.5  
10  
0.5  
V
VMISC2IL  
IPU  
AS, RESET*  
Pull Up Current  
30  
μA  
BSCAN  
IPD  
V
I
IN = 2.5V  
10  
30  
μA  
Pull Down Current  
8
VSYNCOH  
CHSYNC, VSYNC  
Output High Voltage  
= -0.4mA  
2.0  
V
OH  
8
VSYNCOL  
CHSYNC, VSYNC  
Output Low Voltage  
IOL = 3.2mA  
DC  
0.4  
13  
V
ZDL  
DL[3:1]  
7
10  
kΩ  
Output Impedance  
Notes:  
1. VSDOL is the SPD output low voltage when transmitting from internal registers, not from DDC or EEPROM.  
2.  
V
SPIH and VSPIL are the serial port (SPC and SPD) input low voltage when transmitting to internal registers. Separate  
requirements may exist for transmission to the DDC and EEPROM.  
3.  
V
SD_DDCOL is the output low voltage at the SPD pin when the voltage at SD_DDC or SD_EPROM is VINL. Maximum output  
voltage has been calculated with a worst case pull-up of 4.0kΩ to 2.5V on SPD.  
4. VDDCOL is the output low voltage at the SC_DDC and SD_DDC pins when the voltage at SPC and SPD is VINL. Maximum output  
voltage has been calculated with 5.6k pull-up to 5V on SC_DDC and SD_DDC.  
5.  
V
EPROMOL is the output low voltage at the SC_EPROM and SD_EPROM pins when the voltage at SPC and SPD is VINL  
.
Maximum output voltage has been calculated with 5.6kΩ pull-up to 5V on SC_EPROM and SD_EPROM.  
6. VMISC1 - refers to RESET* input which is 3.3V compliant.  
7. VMISC2 - refers to AS, BSCAN which are 2.5V compliant  
8. VSYNC – refers to CHSYNC and VSYNC outputs.  
201-0000-087  
Rev. 1.2, 12/2/2008  
15  
CHRONTEL  
CH7317A  
4.5 AC Specifications  
Symbol  
Description  
Test Condition  
Min  
Typ  
Max  
Unit  
UIDATA  
SDVO Receiver Unit Interval  
for Data Channels  
Typ. –  
1/[Data  
Transfer  
Rate]  
Typ. +  
ps  
300ppm  
300ppm  
fSDVO_CLK  
fPIXEL  
SDVO CLK Input Frequency  
100  
25  
200  
165  
MHz  
MHz  
SDVO Receiver Pixel  
frequency  
fSYMBOL  
tRX-EYE  
SDVO Receiver Symbol  
frequency  
1
2
GHz  
UI  
SDVO Receiver Minimum Eye  
Width  
0.4  
tRX-EYE-JITTER  
SDVO Receiver Max. time  
between jitter median and  
max. deviation from median  
0.3  
UI  
VRX-CM-ACp  
SDVO Receiver AC Peak  
150  
mV  
Common Mode Input Voltage  
RLRX-DIFF  
RLRX-CM  
TSPR  
Differential Return Loss  
50MHz – 1.25GHz  
50MHz – 1.25GHz  
15  
6
dB  
dB  
Common Mode Return Loss  
SPC, SPD Rise Time  
(20% - 80%)  
Standard mode 100k  
Fast mode 400k  
1000  
300  
ns  
ns  
ns  
1M running speed  
150  
TSPF  
SPC, SPD Fall Time  
(20% - 80%)  
Standard mode 100k  
Fast mode 400k  
300  
300  
150  
300  
ns  
ns  
ns  
ns  
1M running speed  
Fast mode 400K  
TPROMR  
TPROMF  
TDDCR  
TDDCF  
SC_PROM, SD_PROM Rise  
Time (20% - 80%)  
SC_PROM, SD_PROM Rise  
Time (20% - 80%)  
Fast mode 400K  
300  
1000  
300  
ns  
ns  
ns  
SC_DDC, SD_DDC Rise  
Time (20% - 80%)  
Standard mode 100k  
Standard mode 100k  
SC_DDC, SD_DDC Fall  
Time (20% - 80%)  
1
TDDCR-DELAY  
SC_DDC, SD_DDC Rise  
Time Delay (50%)  
Standard mode 100k  
Standard mode 100k  
0
3
ns  
ns  
1
TDDCF-DELAY  
SC_DDC, SD_DDC Fall  
Time Delay (50%)  
tSKEW  
tR  
SDVO Receiver Total Lane to  
Lane Skew of Inputs  
Across all lanes  
2
ns  
ns  
CHSYNC and VSYNC (when  
configured as outputs)  
15pF load  
1.50  
DVDD = 2.5V  
Output Rise Time  
(20% - 80%)  
16  
201-0000-087  
Rev. 1.2,  
12/2/2008  
 
CHRONTEL  
CH7317A  
tF  
H and V (when configured as  
15pF load  
1.50  
ns  
outputs)  
DVDD = 2.5V  
Output Fall Time  
(20% - 80%)  
Notes:  
1.  
Refers to the figure below, the delay refers to the time pass through the internal switches.  
3.3V typ.  
2.5V typ.  
R=5K  
To SPC/SPD pin  
To DDC pin  
201-0000-087  
Rev. 1.2, 12/2/2008  
17  
CHRONTEL  
CH7317A  
5.0 Package Dimensions  
A
B
I
1
A
B
H
D
C
J
LEAD  
CO-PLANARITY  
.004  
“
E
F
G
Figure 6: 64 Pin LQFP Package  
SYMBOL  
Table of Dimensions  
No. of Leads  
64 (10 X 10 mm)  
A
B
C
D
E
F
G
H
I
J
Milli-  
meters  
MIN  
MAX  
0.17  
0.27  
1.35  
1.45  
0.05  
0.15  
0.45  
0.75  
0.09  
0.20  
0°  
7°  
12  
10  
0.50  
1.00  
Notes:  
1. Conforms to JEDEC standard JESD-30 MS-026D.  
2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm.  
3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side.  
18  
201-0000-087  
Rev. 1.2,  
12/2/2008  
 
CHRONTEL  
CH7317A  
TOP VIEW  
BOTTOM VIEW  
B
A
B/2  
16  
1
1
16  
17  
17  
64  
64  
Pin 1  
A
C
C/2  
32  
49  
49  
32  
F
48  
33  
E
33  
48  
D
I
G
H
Figure 7: 64 Pin QFN Package (8 x 8 x 0.8mm)  
SYMBOL  
Table of Dimensions  
No. of Leads  
64 (8 X 8 mm)  
A
8
B
C
D
E
F
G
H
I
Milli-  
MIN  
6.1  
6.3  
6.1  
6.3  
0.15  
0.25  
0.35  
0.45  
0.7  
0.8  
0
0.05  
0.4  
0.203  
meters  
MAX  
Notes:  
1. Conforms to JEDEC standard JESD-30 MO-220.  
201-0000-087  
Rev. 1.2, 12/2/2008  
19  
 
CHRONTEL  
CH7317A  
6.0 Revision History  
Table 6: Revisions  
Rev. # Date  
Section  
Description  
1.0  
1.1  
1.11  
1.2  
12/19/06 All  
Initial official release.  
Add 64-QFN package.  
Change VDD5+ to +5V  
Update operating temperature.  
9/13/07  
1.1, 5.0  
10/26/07 4.4  
12/2/08 4.2, 4.3  
20  
201-0000-087  
Rev. 1.2,  
12/2/2008  
 
CHRONTEL  
CH7317A  
Disclaimer  
This document provides technical information for the user. Chrontel reserves the right to make changes at any time  
without notice to improve and supply the best possible product and is not responsible and does not assume any  
liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use  
of our products and assume no liability for errors contained in this document. The customer should make sure that  
they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the  
products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not  
infringe upon or assist others to infringe upon such rights.  
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT  
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF  
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used  
as directed can reasonably expect to result in personal injury or death.  
ORDERING INFORMATION  
Number of  
Part Number  
CH7317A-TF  
Package Type  
Voltage Supply  
2.5V & 3.3V  
2.5V & 3.3V  
2.5V & 3.3V  
2.5V & 3.3V  
Pins  
Lead Free LQFP  
64  
Lead Free LQFP  
in Tape & Reel  
CH7317A-TF-TR  
CH7317A-BF  
64  
64  
64  
Lead Free QFN  
Lead Free QFN  
in Tape & Reel  
CH7317A-BF-TR  
Chrontel  
2210 O’Toole Avenue, Suite 100,  
San Jose, CA 95131-1326  
Tel: (408) 383-9328  
Fax: (408) 383-9338  
www.chrontel.com  
E-mail: sales@chrontel.com  
©2008 Chrontel, Inc. All Rights Reserved.  
Printed in the U.S.A.  
201-0000-087  
Rev. 1.2, 12/2/2008  
21  

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