CS4335-DSZ [CIRRUS]
8-Pin, 24-Bit, 96 kHz Stereo D/A Converter; 8引脚，24位， 96千赫立体声D / A转换器
| 型号： | CS4335-DSZ |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | 8-Pin, 24-Bit, 96 kHz Stereo D/A Converter |
| 文件： | 总24页 (文件大小：787K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Confidential Draft
3/11/08
CS4334/5/8/9
8-Pin, 24-Bit, 96 kHz Stereo D/A Converter
Features
Description
Complete Stereo DAC System: Interpolation,
The CS4334 family members are complete, stereo dig-
ital-to-analog output systems including interpolation,
1-bit D/A conversion and output analog filtering in an
8-pin package. The CS4334/5/8/9 support all major au-
dio data interface formats, and the individual devices
differ only in the supported interface format.
D/A, Output Analog Filtering
24-Bit Conversion
96 dB Dynamic Range
The CS4334 family is based on Delta-Sigma modula-
tion, where the modulator output controls the reference
voltage input to an ultra-linear analog low-pass filter.
This architecture allows for infinite adjustment of sam-
ple rate between 2 kHz and 100 kHz simply by
changing the master clock frequency.
-88 dB THD+N
Low Clock-Jitter Sensitivity
Single +5 V Power Supply
Filtered Line-Level Outputs
On-Chip Digital De-emphasis
Popguard® Technology
Functionally Compatible with CS4330/31/33
The CS4334 family contains on-chip digital de-empha-
sis, operates from a single +5V power supply, and
requires minimal support circuitry. These features are
ideal for set-top boxes, DVD players, SVCD players,
and A/V receivers.
ORDERING INFORMATION
See “Ordering Information” on page 24
DEM/SCLK
2
AGND
6
VA
7
3
LRCK
Serial Input
De-emphasis
Interface
Voltage Reference
1
SDATA
Analog
Low-Pass
Filter
∆Σ
Interpolator
AOUTL
AOUTR
DAC
DAC
Modulator
8
5
Analog
Low-Pass
Filter
∆Σ
Interpolator
Modulator
4
MCLK
March '08
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Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
http://www.cirrus.com
Confidential Draft
3/11/08
CS4334/5/8/9
TABLE OF CONTENTS
1. TYPICAL CONNECTION DIAGRAM .................................................................................................... 4
2. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 5
SPECIFIED OPERATING CONDITIONS.............................................................................................. 5
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 5
ANALOG CHARACTERISTICS............................................................................................................. 6
POWER AND THERMAL CHARACTERISTICS ................................................................................... 8
DIGITAL INPUT CHARACTERISTICS.................................................................................................. 9
SWITCHING CHARACTERISTICS ..................................................................................................... 10
3. GENERAL DESCRIPTION ................................................................................................................. 12
3.1 Digital Interpolation Filter .............................................................................................................. 12
3.2 Delta-Sigma Modulator ................................................................................................................. 12
3.3 Switched-Capacitor DAC .............................................................................................................. 12
3.4 Analog Low-Pass Filter ................................................................................................................. 12
4. SYSTEM DESIGN ............................................................................................................................... 13
4.1 Master Clock ................................................................................................................................. 13
4.2 Serial Clock .................................................................................................................................. 13
4.2.1 External Serial Clock Mode ................................................................................................. 13
4.2.2 Internal Serial Clock Mode .................................................................................................. 13
4.3 De-Emphasis ................................................................................................................................ 14
4.4 Initialization and Power-Down ...................................................................................................... 14
4.5 Output Transient Control .............................................................................................................. 14
4.6 Grounding and Power Supply Decoupling .................................................................................... 15
4.7 Analog Output and Filtering .......................................................................................................... 15
4.8 Overall Base-Rate Frequency Response ..................................................................................... 18
4.9 Overall High-Rate Frequency Response ...................................................................................... 19
4.10 Base Rate Mode Performance Plots .......................................................................................... 20
4.11 High Rate Mode Performance Plots ........................................................................................... 21
5. PARAMETER DEFINITIONS ............................................................................................................... 22
6. REFERENCES ..................................................................................................................................... 22
7. PACKAGE DIMENSIONS ................................................................................................................... 23
8. ORDERING INFORMATION ............................................................................................................... 24
9. FUNCTIONAL COMPATIBILITY ......................................................................................................... 24
10. REVISION HISTORY ......................................................................................................................... 24
LIST OF FIGURES
Figure 1. Recommended Connection Diagram......................................................................................... 4
Figure 2. Output Test Load ....................................................................................................................... 8
Figure 3. Maximum Loading...................................................................................................................... 9
Figure 4. Power vs. Sample Rate ............................................................................................................. 9
Figure 5. External Serial Mode Input Timing........................................................................................... 11
Figure 6. Internal Serial Mode Input Timing............................................................................................ 11
Figure 7. Internal Serial Clock Generation............................................................................................. 11
Figure 8. System Block Diagram............................................................................................................. 12
Figure 9. De-Emphasis Curve (Fs = 44.1kHz) ........................................................................................ 14
Figure 10. CS4334 Data Format (I²S)....................................................................................................... 15
Figure 11. CS4335 Data Format............................................................................................................... 15
Figure 12. CS4338 Data Format............................................................................................................... 16
Figure 13. CS4339 Data Format............................................................................................................... 16
Figure 14. CS4334/5/8/9 Initialization and Power-Down Sequence ......................................................... 17
Figure 15. Stopband Rejection.................................................................................................................. 18
Figure 16. Transition Band........................................................................................................................ 18
Figure 17. Transition Band........................................................................................................................ 18
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Figure 18. Passband Ripple...................................................................................................................... 18
Figure 19. Stopband Rejection.................................................................................................................. 19
Figure 20. Transition Band........................................................................................................................ 19
Figure 21. Transition Band........................................................................................................................ 19
Figure 22. Passband Ripple...................................................................................................................... 19
Figure 23. 0 dBFS FFT (BRM).................................................................................................................. 20
Figure 24. -60 dBFS FFT (BRM).............................................................................................................. 20
Figure 25. Idle Channel Noise FFT (BRM)................................................................................................ 20
Figure 26. Twin Tone IMD FFT (BRM)...................................................................................................... 20
Figure 27. THD+N vs. Amplitude (BRM)................................................................................................... 20
Figure 28. THD+N vs. Frequency (BRM).................................................................................................. 20
Figure 29. 0 dBFS FFT (HRM).................................................................................................................. 21
Figure 30. -60 dBFS FFT (HRM).............................................................................................................. 21
Figure 31. Idle Channel Noise FFT (HRM) ............................................................................................... 21
Figure 32. Twin Tone IMD FFT (HRM) ..................................................................................................... 21
Figure 33. THD+N vs. Amplitude (HRM)................................................................................................... 21
Figure 34. THD+N vs. Frequency (HRM)................................................................................................. 21
LIST OF TABLES
Table 1. Common Clock Frequencies ...................................................................................................... 13
PIN DESCRIPTIONS
1
2
3
4
8
7
6
5
SERIAL DATA INPUT
DE-EMPHASIS / SCLK
LEFT / RIGHT CLOCK
MASTER CLOCK
SDATA
DEM/SCLK
LRCK
AOUTL
VA
ANALOG LEFT CHANNEL OUTPUT
ANALOG POWER
AGND
AOUTR
ANALOG GROUND
MCLK
ANALOG RIGHT CHANNEL OUTPUT
No. Pin Name I/O
Pin Function and Description
Serial Audio Data Input - Two’s complement MSB-first serial data is input on this pin. The data is
clocked into the CS4334/5/8/9 via internal or external SCLK, and the channel is determined by
LRCK.
1
SDATA
I
De-Emphasis/External Serial Clock Input - Used for de-emphasis filter control or external serial
clock input.
Left/Right Clock - Determines which channel is currently being input on the Audio Serial Data
Input pin, SDATA.
Master Clock - Frequency must be 256x, 384x, or 512x the input sample rate in BRM and either
128x or 192x the input sample rate in HRM.
2
3
4
DEM/SCLK
LRCK
I
I
I
MCLK
5
6
7
8
AOUTR
AGND
VA
O
I
I
Analog Right Channel Output - Typically 3.5 Vp-p for a full-scale input signal.
Analog Ground - Analog ground reference is 0V.
Analog Power - Analog power supply is nominally +5 V.
AOUTL
O
Analog Left Channel Output - Typically 3.5 Vp-p for a full-scale input signal.
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1. TYPICAL CONNECTION DIAGRAM
+5V
+
0.1 µF
1 µF
7
VA
1
2
3
SDATA
DEM/SCLK
LRCK
3.3 µF
Ω
560
Audio
Data
Processor
8
Left Audio
Output
AOUTL
+
267 k
Ω
C
R
L
10 kΩ
CS4334
CS4335
CS4338
CS4339
3.3 µF
+
Ω
560
5
AOUTR
Right Audio
Output
4
External Clock
MCLK
C
R
L
267 k
Ω
10 k
Ω
R
+ 560
L
C =
AGND
6
π
4 Fs(R 560)
L
Figure 1. Recommended Connection Diagram
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2. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltages
and T = 25°C.)
A
SPECIFIED OPERATING CONDITIONS
(AGND = 0V; all voltages with respect to ground.)
Parameters
Symbol
VA
Min
4.75
Nom
5.0
Max
5.5
Units
V
DC Power Supply
Ambient Operating Temperature (Power Applied)
-KSZ
-DSZ
TA
-10
-40
-
-
+70
+85
°C
°C
ABSOLUTE MAXIMUM RATINGS
(AGND = 0V; all voltages with respect to ground.)
Parameters
DC Power Supply
Symbol
VA
Min
-0.3
-
Max
6.0
Units
V
Input Current, Any Pin Except Supplies
Digital Input Voltage
Iin
±10
mA
V
VIND
TA
-0.3
-55
-65
VA+0.4
125
Ambient Operating Temperature (power applied)
Storage Temperature
°C
Tstg
150
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
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ANALOG CHARACTERISTICS
(Full-Scale Output Sine Wave, 997 Hz; Test load R = 10 kΩ, C = 10 pF (see Figure 2). Fs for Base-Rate Mode =
L
L
48 kHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz,
Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise specified.)
Base-Rate Mode
High-Rate Mode
Parameter
Symbol Min
Typ
Max Min
Typ
Max Unit
Dynamic Performance for CS4334/5/8/9-KSZ
Dynamic Range
(Note 1)
18 to 24-Bit
88
91
86
89
93
96
91
94
-
-
-
-
-
91
-
90
96
88
94
-
-
-
-
dB
dB
dB
dB
unweighted
A-Weighted
unweighted
A-Weighted
16-Bit
89
Total Harmonic Distortion + Noise
18 to 24-Bit
(Note 1) THD+N
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-88
-73
-33
-86
-71
-31
-83
-68
-28
-81
-66
-26
-
-
-
-
-
-
-88
-70
-30
-86
-68
-28
-83
-65
-25
-81
-63
-23
dB
dB
dB
dB
dB
dB
16-Bit
Interchannel Isolation
(1 kHz)
-
94
-
-
95
-
dB
Dynamic Performance for CS4334/5/8/9-DSZ
Dynamic Range (Note 1)
18 to 24-Bit
85
88
83
86
93
96
91
94
-
-
-
-
-
88
-
90
96
88
94
-
-
-
-
dB
dB
dB
dB
unweighted
A-Weighted
unweighted
A-Weighted
16-Bit
86
Total Harmonic Distortion + Noise
18 to 24-Bit
(Note 1) THD+N
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-88
-73
-33
-86
-71
-31
-82
-65
-25
-70
-63
-23
-
-
-
-
-
-
-88
-70
-30
-86
-68
-28
-82
-62
-22
-80
-60
-20
dB
dB
dB
dB
dB
dB
16-Bit
Interchannel Isolation
(1 kHz)
-
94
-
-
95
-
dB
Notes:
1. One-half LSB of triangular PDF dither added to data.
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ANALOG CHARACTERISTICS (Continued)
Base-Rate Mode
High-Rate Mode
Min Typ Max Unit
Parameter
Symbol Min
Typ
Max
Combined Digital and On-chip Analog Filter Response (Note 2)
Passband
(Note 3)
to -0.05 dB corner
to -0.1 dB corner
to -3 dB corner
0
-
0
-
-
-
.4780
-
.4996
-
0
0
-
-
-
-
Fs
.4650 Fs
.4982 Fs
Frequency Response 10 Hz to 20 kHz
Passband Ripple
-.01
-
+.08
-.05
-
+.2
dB
dB
Fs
dB
s
-
-
±.08
-
.5770
55
-
±.2
StopBand
.5465
-
-
-
-
-
-
-
-
-
-
-
StopBand Attenuation
Group Delay
(Note 4)
50
-
tgd
9/Fs
±0.36/Fs
-
4/Fs
Passband Group Delay Deviation
0 - 40 kHz
0 - 20 kHz
-
-
-
±1.39/Fs
±0.23/Fs
-
-
s
s
De-emphasis Error
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
+1.5/+0
+.05/-.25
-.2/-.4
dB
dB
dB
(Note 5)
Parameters
Symbol
Min
Typ
Max
Units
DC Accuracy
Interchannel Gain Mismatch
Gain Error
-
-
-
0.1
±5
0.4
dB
%
-
-
Gain Drift
100
ppm/°C
Analog Output
Full Scale Output Voltage
Quiescent Voltage
Max AC-Load Resistance
Max Load Capacitance
3.25
3.5
2.2
3
3.75
Vpp
VDC
kΩ
VQ
RL
CL
-
-
-
-
-
-
(Note 6)
(Note 6)
100
pF
Notes:
2. Filter response is not tested but is guaranteed by design.
3. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 15-22) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
4. For Base-Rate Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For High-Rate Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
5. De-emphasis is not available in High-Rate Mode.
6. Refer to Figure 3.
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POWER AND THERMAL CHARACTERISTICS
Parameters
Symbol
Min
Typ
Max
Units
Power Supplies
Power Supply Current
normal operation
power-down state
IA
IA
-
-
15
40
19
-
mA
µA
Power Dissipation
(Note 7)
normal operation
power-down
-
-
75
0.2
104
-
mW
mW
Package Thermal Resistance
Power Supply Rejection Ratio
θJA
PSRR
-
-
110
79
-
-
°C/Watt
dB
(1 kHz)
Notes:
7. Refer to Figure 4. Max Power Dissipation is measured at VA=5.5V.
10 µF
V
AOUTx
out
R
C
L
L
AGND
Figure 2. Output Test Load
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125
100
75
70
65
60
55
75
50
M
R
H
Safe Operating
Region
25
50
20
2.5
5
10
15
30
40
50
60
70
80
90
100
3
Ω
Resistive Load -- R (k )
L
Sample Rate (kHz)
Figure 3. Maximum Loading
Figure 4. Power vs. Sample Rate
DIGITAL INPUT CHARACTERISTICS
Parameters
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Symbol
VIH
Min
2.0
Typ
-
-
Max
-
Units
V
V
VIL
-
-
-
0.8
±10
-
(Note 8)
Iin
-
µA
pF
Input Capacitance
8
Notes:
8. I for CS433X LRCK is ±20µA max.
in
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SWITCHING CHARACTERISTICS
Parameters
Symbol
Min
2
Typ
Max
100
Units
kHz
ns
Input Sample Rate
Fs
-
-
-
-
-
-
-
MCLK Pulse Width High
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Pulse Width Low
MCLK Pulse Width High
MCLK Pulse Width Low
External SCLK Mode
MCLK/LRCK = 512
MCLK/LRCK = 512
10
10
21
21
31
31
1000
1000
1000
1000
1000
1000
ns
MCLK / LRCK = 384 or 192
MCLK / LRCK = 384 or 192
MCLK / LRCK = 256 or 128
MCLK / LRCK = 256 or 128
ns
ns
ns
ns
LRCK Duty Cycle (External SCLK only)
SCLK Pulse Width Low
40
20
20
50
-
60
-
%
ns
ns
ns
tsclkl
tsclkh
tsclkw
SCLK Pulse Width High
-
-
1
SCLK Period
MCLK / LRCK = 512, 256 or 384
Base-Rate Mode
High-Rate Mode
-
-
---------------------
(128)Fs
1
SCLK Period
MCLK / LRCK = 128 or 192
tsclkw
-
-
ns
------------------
(64)Fs
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
Internal SCLK Mode
tslrd
tslrs
tsdlrs
tsdh
20
20
20
20
-
-
-
-
-
-
-
-
ns
ns
ns
ns
LRCK Duty Cycle (Internal SCLK only)
(Note 9)
-
50
-
-
-
%
tsclkw
tsclkr
ns
1
SCLK Period
(Note 10)
----------------
SCLK
-
-
µs
SCLK rising to LRCK edge
tsclkw
------------------
2
tsdlrs
-
-
-
ns
ns
1
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
--------------------- + 10
(512)Fs
tsdh
-
-
1
--------------------- + 15
MCLK / LRCK = 512, 256 or 128
(512)Fs
tsdh
-
ns
SCLK rising to SDATA hold time
1
--------------------- + 15
MCLK / LRCK = 384 or 192
(384)Fs
Notes:
9. In Internal SCLK Mode, the Duty Cycle must be 50% +/− 1/2 MCLK Period.
10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK
ratio. (See figures Figures 10-13)
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LRCK
t
t
sclkh
slrs
t
slrd
t
sclkl
SCLK
t
t
sdh
sdlrs
SDATA
Figure 5. External Serial Mode Input Timing
LRCK
t
sclkr
SDATA
t
sclkw
t
t
sdh
sdlrs
*INTERNAL SCLK
Figure 6. Internal Serial Mode Input Timing
The SCLK pulses shown are internal to the CS4334/5/8/9.
LRCK
MCLK
N
2
N
1
*INTERNAL SCLK
SDATA
Figure 7. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4334/5/8/9.
N equals MCLK divided by SCLK
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3. GENERAL DESCRIPTION
The CS4334 family of devices offers a complete stereo digital-to-analog system including digital interpolation,
fourth-order delta-sigma digital-to-analog conversion, digital de-emphasis and analog filtering, as shown in
Figure 8. This architecture provides a high tolerance to clock jitter.
The primary purpose of using delta-sigma modulation techniques is to avoid the limitations of resistive laser trimmed
digital-to-analog converter architectures by using an inherently linear 1-bit digital-to-analog converter. The advan-
tages of a 1-bit digital-to-analog converter include: ideal differential linearity, no distortion mechanisms due to resis-
tor matching errors and no linearity drift over time and temperature due to variations in resistor values.
The CS4334 family of devices supports two modes of operation. The devices operate in Base Rate Mode (BRM)
when MCLK/LRCK is 256, 384 or 512 and in High Rate Mode (HRM) when MCLK/LRCK is 128 or 192. High Rate
Mode allows input sample rates up to 100 kHz.
3.1
Digital Interpolation Filter
The digital interpolation filter increases the sample rate, Fs, by a factor of 4 and is followed by a 32× digital
sample-and-hold (16× in HRM). This filter eliminates images of the baseband audio signal which exist at
multiples of the input sample rate. The resulting frequency spectrum has images of the input signal at mul-
tiples of 4 Fs. These images are easily removed by the on-chip analog low-pass filter and a simple external
analog filter (see Figure 1).
3.2
3.3
Delta-Sigma Modulator
The interpolation filter is followed by a fourth order delta-sigma modulator which converts the interpolation
filter output into 1-bit data at a rate of 128 Fs in BRM (or 64 Fs in HRM).
Switched-Capacitor DAC
The delta-sigma modulator is followed by a digital-to-analog converter which translates the 1-bit data into a
series of charge packets. The magnitude of the charge in each packet is determined by sampling of a volt-
age reference onto a switched capacitor, where the polarity of each packet is controlled by the 1-bit data.
This technique greatly reduces the sensitivity to clock jitter and provides low-pass filtering of the output.
3.4
Analog Low-Pass Filter
The final signal stage consists of a continuous-time low-pass filter which serves to smooth the output and
attenuate out-of-band noise.
Analog
Low-Pass
Filter
Digital
Input
Analog
Output
Delta-Sigma
Modulator
Interpolator
DAC
Figure 8. System Block Diagram
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4. SYSTEM DESIGN
The CS4334 family accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in BRM and 96, 88.2
and 64 kHz in HRM. Audio data is input via the serial data input pin (SDATA). The Left/Right Clock (LRCK) defines
the channel and delineation of data, and the Serial Clock (SCLK) clocks audio data into the input data buffer. The
CS4334/5/8/9 differ in serial data formats as shown in Figures 10-13.
4.1
Master Clock
MCLK must be either 256x, 384x or 512x the desired input sample rate in BRM and either 128x or 192x the
desired input sample rate in HRM. The LRCK frequency is equal to Fs, the frequency at which words for
each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected automatically during
the initialization sequence by counting the number of MCLK transitions during a single LRCK period. Internal
dividers are set to generate the proper clocks. Table 1 illustrates several standard audio sample rates and
the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK,
LRCK and SCLK must be synchronous.
MCLK (MHz)
LRCK
(kHz)
HRM
128x 192x
BRM
384x
256x
512x
32
4.0960 6.1440 8.1920 12.2880 16.3840
44.1 5.6448 8.4672 11.2896 16.9344 22.5792
48
64
6.1440 9.2160 12.2880 18.4320 24.5760
8.1920 12.2880
-
-
-
-
-
-
-
-
-
88.2 11.2896 16.9344
96 12.2880 18.4320
Table 1. Common Clock Frequencies
4.2
Serial Clock
The serial clock controls the shifting of data into the input data buffers. The CS4334 family supports both
external and internal serial clock generation modes. Refer to Figures 10-13 for data formats.
4.2.1
External Serial Clock Mode
The CS4334 family will enter the External Serial Clock Mode when 16 low to high transitions are detected
on the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Se-
rial Clock Mode and de-emphasis filter cannot be accessed. The CS4334 family will switch to Internal Se-
rial Clock Mode if no low to high transitions are detected on the DEM/SCLK pin for 2 consecutive frames
of LRCK. Refer to Figure 14.
4.2.2
Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and
LRCK. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending upon data format. Operation in
this mode is identical to operation with an external serial clock synchronized with LRCK. This mode allows
access to the digital de-emphasis function. Refer to Figures 10 - 14 for details.
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4.3
De-Emphasis
The CS4334 family includes on-chip digital de-emphasis. Figure 9 shows the de-emphasis curve for Fs
equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes
in sample rate, Fs.
The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for 5 consecutive falling edges
of LRCK. This function is available only in the internal serial clock mode.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
F2
Frequency
3.183 kHz
10.61 kHz
Figure 9. De-Emphasis Curve (Fs = 44.1kHz)
4.4
Initialization and Power-Down
The Initialization and Power-Down sequence flow chart is shown in Figure 14. The CS4334 family enters
the Power-Down State upon initial power-up. The interpolation filters and delta-sigma modulators are reset,
and the internal voltage reference, one-bit digital-to-analog converters and switched-capacitor low-pass fil-
ters are powered down. The device will remain in the Power-Down mode until MCLK and LRCK are present.
Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period to determine
the MCLK/LRCK frequency ratio. Power is then applied to the internal voltage reference. Finally, power is
applied to the D/A converters and switched-capacitor filters, and the analog outputs will ramp to the quiescent
voltage, V .
Q
4.5
Output Transient Control
The CS4334 family uses Popguard® technology to minimize the effects of output transients during power-
up and power-down. This technique eliminates the audio transients commonly produced by single-ended
single-supply converters when it is implemented with external DC-blocking capacitors connected in series
with the audio outputs. To make best use of this feature, it is necessary to understand its operation.
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Af-
ter a short delay of approximately 1000 sample periods, each output begins to ramp towards its quiescent
voltage, V . Approximately 10,000 sample cycles later, the outputs reach V and audio output begins. This
Q
Q
gradual voltage ramping allows time for the external DC-blocking capacitor to charge to V , effectively
Q
blocking the quiescent DC voltage.
To prevent transients at power-down, the device must first enter its power-down state. This is accomplished
by removing MCLK or LRCK. When this occurs, audio output ceases and the internal output buffers are dis-
connected from AOUTL and AOUTR. A soft-start current sink is substituted in place of AOUTL and AOUTR
which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to
the device may be turned off, and the system is ready for the next power-on.
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before
turning off the power or exiting the power-down state. If full discharge does not occur, a transient will occur
when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-
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down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 µF capacitor, the
time that the device must remain in the power-down state will be approximately 0.4 seconds.
4.6
4.7
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4334 family requires careful attention to power supply and
grounding arrangements to optimize performance. Figure 1 shows the recommended power arrangement
with VA connected to a clean +5V supply. For best performance, decoupling capacitors should be located
as close to the device package as possible with the smallest capacitor closest.
Analog Output and Filtering
The analog filter present in the CS4334 family is a switched-capacitor filter followed by a continuous time
lowpassfilter.Itsresponse, combinedwiththatofthedigitalinterpolator, isgiveninFigures 15-22.
Left Channel
Right Channel
LRCK
SCLK
SDATA
+5 +4 +3 +2 +1 LSB
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4 -5
M SB -1 -2 -3 -4
Internal SCLK Mode
External SCLK Mode
I²S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
I²S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128
I²S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Figure 10. CS4334 Data Format (I²S)
Left Channel
Right Channel
LRCK
SCLK
SDATA
M SB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LS B
M SB -1 -2 -3 -4
+5 +4 +3 +2 +1 LS B
Internal SCLK Mode
External SCLK Mode
Left Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Left Justified, up to 24-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Figure 11. CS4335 Data Format
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Right Channel
LRCK
SCLK
Left Channel
SDATA
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
32 clocks
15 14 13 12 11 10
Internal SCLK Mode
Right Justified, 16-Bit Data
External SCLK Mode
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 12. CS4338 Data Format
Right Channel
LRCK
SCLK
Left Channel
SDATA
1
0
17 16
9
8
7
6
5
4
3
2
1
0
17 16
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
32 clocks
15 14 13 12 11 10
Internal SCLK Mode
Right Justified, 18-Bit Data
External SCLK Mode
Right Justified, 18-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 36 Cycles per LRCK Period
Figure 13. CS4339 Data Format
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Figure 14. CS4334/5/8/9 Initialization and Power-Down Sequence
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4.8
Overall Base-Rate Frequency Response
Figure 15. Stopband Rejection
Figure 16. Transition Band
Figure 17. Transition Band
Figure 18. Passband Ripple
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4.9
Overall High-Rate Frequency Response
Figure 19. Stopband Rejection
Figure 20. Transition Band
Figure 21. Transition Band
Figure 22. Passband Ripple
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4.10 Base Rate Mode Performance Plots
+
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-100
-110
-110
-120
-120
-130
-130
-140
-140
4k
2k
6k
8k
10k
12k
14k
16k
18k 20k
18k
2k
4k
6k
8k
10k
12k
14k
16k
20k
Hz
Hz
(16k FFT of a 1 kHz input signal)
(16k FFT of a 1 kHz input signal)
Figure 23. 0 dBFS FFT (BRM)
Figure 24. -60 dBFS FFT (BRM)
0
0
+0
+
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-100
-110
-110
-120
-120
-130
-130
-140
2
k
4k
6k
8k
10k
12k
14k
16k
18k
-140
20k
k
k
k
k
0k
k
k
6k
16k
k
18k
k
20k
20k
k
k
1k
4
2k
4k
6k
8k
10k
12k
14k
Hz
Hz
(16k FFT with no input signal)
(16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals)
Figure 25. Idle Channel Noise FFT (BRM)
Figure 26. Twin Tone IMD FFT (BRM)
-60
+0
-10
-70
-20
-30
-40
-80
-50
-60
-90
-70
-80
-100
-90
-100
-110
-
6
0
-
5
0
-
4
0
-
3
0
-
2
0
-
1
0
+0
-110
50
200
1k
2k
5k
20
500
10k 20k
100
dBFS
Hz
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
Figure 27. THD+N vs. Amplitude (BRM)
Figure 28. THD+N vs. Frequency (BRM)
All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain
System Two Cascade.
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4.11 High Rate Mode Performance Plots
+0
+0
+0
-10
-10
-20
-2
0
-30
-3
0
-40
-40
-50
-5
0
-60
-60
-70
-70
-80
-80
-90
-9
0
-100
-100
-110
-110
-120
-120
-130
-130
-140
-140
4k
6k
8k
10k
12k
14k
16k
2k
18k 20k
4k
2
k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Hz
(16k FFT of a 1 kHz input signal)
(16k FFT of a 1 kHz input signal)
Figure 29. 0 dBFS FFT (HRM)
Figure 30. -60 dBFS FFT (HRM)
Audio Precision
D-A CCIF IMD vs AMPLITUDE
08/05/99 11:11:36
+0
+0
+0
+0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-6
0
-60
-7
0
-70
-8
-9
-80
0
-90
0
-100
-100
-110
-1
1
0
-120
-120
-130
-1
3
0
-140
2
k
4k
6k
8k
10k
12k
14k
16k
-14
0
18k 20k
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
Hz
Hz
(16k FFT with no input signal)
(16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals)
Figure 31. Idle Channel Noise FFT (HRM)
Figure 32. Twin Tone IMD FFT (HRM)
-60
+0
-10
-20
-70
-30
-40
-80
-50
-60
-90
-70
-80
-100
-90
-100
-60
-110
-110
-50
-40
-20
-10
+0
-30
0
50
100
200
500
1k
2k
5k
10k 20k
10k 20k
20
50
200
5001k
2k
5k
100
dBFS
Hz
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
Figure 33. THD+N vs. Amplitude (HRM)
Figure 34. THD+N vs. Frequency (HRM)
All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain
System Two Cascade.
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5. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full
scale. This technique ensures that the distortion components are below the noise level and do not effect the
measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-
1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in deci-
bels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
6. REFERENCES
1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper
presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2. CDB4334/5/8/9 Evaluation Board Datasheet
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7. PACKAGE DIMENSIONS
8L SOIC (150 MIL BODY) PACKAGE DRAWING
E
H
1
b
c
D
SEATING
PLANE
∝
A
L
e
A1
INCHES
MILLIMETERS
DIM
MIN
MAX
MIN
MAX
A
A1
b
0.053
0.004
0.013
0.007
0.189
0.150
0.040
0.228
0.016
0°
0.069
0.010
0.020
0.010
0.197
0.157
0.060
0.244
0.050
8°
1.35
0.10
0.33
0.19
4.80
3.80
1.02
5.80
0.40
0°
1.75
0.25
0.51
0.25
5.00
4.00
1.52
6.20
1.27
8°
c
D
E
e
H
L
∝
JEDEC # : MS-012
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8. ORDERING INFORMATION
Model
CS4334-KSZ
CS4335-KSZ
CS4338-KSZ
CS4339-KSZ
Temperature
-10 to +70 °C
-10 to +70 °C
-10 to +70 °C
-10 to +70 °C
Package
8-pin Plastic SOIC, lead free
8-pin Plastic SOIC, lead free
8-pin Plastic SOIC, lead free
8-pin Plastic SOIC, lead free
Serial Interface
16 to 24-bit, I²S
16 to 24-bit, left justified
16-bit, right justified
18-bit, right justified, 32 Fs Internal SCLK mode
CS4334-DSZ
CS4335-DSZ
CS4338-DSZ
CS4339-DSZ
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
8-pin Plastic SOIC, lead free
8-pin Plastic SOIC, lead free
8-pin Plastic SOIC, lead free
8-pin Plastic SOIC, lead free
16 to 24-bit, I²S
16 to 24-bit, left justified
16-bit, right justified
18-bit, right justified, 32 Fs Internal SCLK mode
9. FUNCTIONAL COMPATIBILITY
CS4330-KS ⇒ CS4339-KSZ
CS4331-KS ⇒ CS4334-KSZ
CS4333-KS ⇒ CS4338-KSZ
CS4330-BS ⇒ CS4339-DSZ
CS4331-BS ⇒ CS4334-DSZ
CS4333-BS ⇒ CS4338-DSZ
10.REVISION HISTORY
Revision
Changes
F3
Removed CS4335-BS and CS4339-BS from the Ordering Information section.
Removed CS4334-BS & CS4349-BS and updated all other packages to lead-free. Functional compatibility
was updated to reflect that of the new lead-free packages.
F4
Corrected “B” to “b” and “C” to “c” to match drawing in “Package Dimensions” on page 23
Updated legal text
F5
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
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sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT-
ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND
CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR
CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO
FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUD-
ING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
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