CS4362A-DQZR [CIRRUS]
114 dB, 192 kHz 6-Channel D/A Converter; 114分贝192千赫6声道D / A转换器
| 型号： | CS4362A-DQZR |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | 114 dB, 192 kHz 6-Channel D/A Converter |
| 文件： | 总50页 (文件大小：973K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS4362A
114 dB, 192 kHz 6-Channel D/A Converter
Features
Description
The CS4362A is a complete 6-channel digital-to-analog
system. This D/A system includes digital de-emphasis,
1 dB step size volume control, ATAPI channel mixing,
selectable fast and slow digital interpolation filters fol-
lowed by an oversampled, multi-bit delta-sigma
modulator which includes mismatch shaping technolo-
gy that eliminates distortion due to capacitor mismatch.
Following this stage is a multi-element switched capac-
itor stage and low-pass filter with differential analog
outputs.
Advanced Multi-bit Delta Sigma Architecture
24-bit Conversion
Up to 192 kHz Sample Rates
114 dB Dynamic Range
-100 dB THD+N
Direct Stream Digital® (DSD™) Mode
On-chip 50 kHz Filter
The CS4362A also has a proprietary DSD processor
which allows for 50 kHz on-chip filtering without an in-
termediate decimation stage. The CS4362A is available
in a 48-pin LQFP package in both Commercial (-40°C to
+85°C) and Automotive grades (-40°C to +105°C). The
CDB4362A Customer Demonstration board is also
available for device evaluation and implementation sug-
gestions. Please see “Ordering Information” on page 48
for complete details.
Matched PCM and DSD Analog Output Levels
Selectable Digital Filters
Volume Control with 1 dB Step Size and Soft
Ramp
The CS4362A accepts PCM data at sample rates from
4 kHz to 216 kHz, DSD audio data, and delivers excel-
lent sound quality. These features are ideal for multi-
channel audio systems including SACD players, A/V re-
ceivers, digital TV’s, mixing consoles, effects
processors, sound cards, and automotive audio
systems.
Low Clock-jitter Sensitivity
+5 V Analog Supply, +2.5 V Digital Supply
Separate 1.8 to 5 V Logic Supplies for the
Control & Serial Ports
Control Port Supply = 1.8 V to 5 V
Digital Supply = 2.5 V
Analog Supply = 5 V
Hardware Mode or
I2C/SPI Software Mode
Control Data
Internal Voltage
Reference
Register/Hardware
Configuration
Reset
Serial Audio Port
Supply = 1.8 V to 5 V
Six Channels of
Differential
Outputs
Switch-Cap
DAC and
Analog Filters
6
6
Volume
Controls
Digital
Filters
Multi-bit ∆Σ
Modulators
PCM Serial
Audio Input
6
External Mute
Control
Mute Signals
DSD Processor
-50 kHz filter
DSD Audio
Input
6
Copyright © Cirrus Logic, Inc. 2009
JAN '09
DS617F2
(All Rights Reserved)
http://www.cirrus.com
CS4362A
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 6
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8
RECOMMENDED OPERATING CONDITIONS .................................................................................... 8
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 8
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) ............................................................. 9
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) ........................................................... 10
POWER AND THERMAL CHARACTERISTICS .................................................................................. 11
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ...................................... 12
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ...................................... 13
DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE ............................................ 13
DIGITAL CHARACTERISTICS ............................................................................................................ 14
SWITCHING CHARACTERISTICS - PCM .......................................................................................... 15
SWITCHING CHARACTERISTICS - DSD ........................................................................................... 16
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................. 17
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................................ 18
3. TYPICAL CONNECTION DIAGRAM .................................................................................................. 19
4. APPLICATIONS ................................................................................................................................... 21
4.1 Master Clock .................................................................................................................................. 21
4.2 Mode Select ................................................................................................................................... 21
4.3 Digital Interface Formats ................................................................................................................ 23
4.4 Oversampling Modes ..................................................................................................................... 24
4.5 Interpolation Filter .......................................................................................................................... 24
4.6 De-emphasis .................................................................................................................................. 24
4.7 ATAPI Specification ....................................................................................................................... 25
4.8 Direct Stream Digital (DSD) Mode ................................................................................................. 26
4.9 Grounding and Power Supply Arrangements ................................................................................ 26
4.9.1 Capacitor Placement ............................................................................................................. 26
4.10 Analog Output and Filtering ......................................................................................................... 26
4.11 Mute Control ................................................................................................................................ 27
4.12 Recommended Power-Up Sequence .......................................................................................... 28
4.12.1 Hardware Mode ................................................................................................................... 28
4.12.2 Software Mode .................................................................................................................... 28
4.13 Recommended Procedure for Switching Operational Modes ...................................................... 29
4.14 Control Port Interface ................................................................................................................... 29
4.14.1 MAP Auto Increment ........................................................................................................... 29
4.14.2 I²C Mode .............................................................................................................................. 29
4.14.2.1 I²C Write ................................................................................................................... 29
4.14.2.2 I²C Read .................................................................................................................. 30
4.14.3 SPI Mode ............................................................................................................................. 30
4.14.3.1 SPI Write .................................................................................................................. 30
4.15 Memory Address Pointer (MAP) ................................................................................................. 31
4.16 INCR (Auto Map Increment Enable) ............................................................................................ 31
4.16.1 MAP4-0 (Memory Address Pointer) .................................................................................... 31
5. REGISTER QUICK REFERENCE ........................................................................................................ 32
6. REGISTER DESCRIPTION .................................................................................................................. 33
6.1 Mode Control 1 (Address 01h) ....................................................................................................... 33
6.1.1 Control Port Enable (CPEN) .................................................................................................. 33
6.1.2 Freeze Controls (FREEZE) ................................................................................................... 33
6.1.3 Master Clock Divide Enable (MCLKDIV) ............................................................................... 33
6.1.4 DAC Pair Disable (DACx_DIS) .............................................................................................. 33
6.1.5 Power Down (PDN) ............................................................................................................... 34
6.2 Mode Control 2 (Address 02h) ....................................................................................................... 34
2
DS617F2
CS4362A
6.2.1 Digital Interface Format (DIF) ................................................................................................ 34
6.3 Mode Control 3 (Address 03h) ....................................................................................................... 35
6.3.1 Soft Ramp and Zero Cross Control (SZC) ............................................................................ 35
6.3.2 Single Volume Control (SNGLVOL) ...................................................................................... 36
6.3.3 Soft Volume Ramp-Up After Error (RMP_UP) ...................................................................... 36
6.3.4 Mutec Polarity (MUTEC+/-) ................................................................................................... 36
6.3.5 Auto-Mute (AMUTE) .............................................................................................................. 36
6.3.6 Mute Pin Control (MUTEC1, MUTEC0) ................................................................................. 37
6.4 Filter Control (Address 04h) ........................................................................................................... 37
6.4.1 Interpolation Filter Select (FILT_SEL) ................................................................................... 37
6.4.2 De-Emphasis Control (DEM) ................................................................................................. 37
6.4.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) .................................................... 37
6.5 Invert Control (Address 05h) .......................................................................................................... 38
6.5.1 Invert Signal Polarity (Inv_Xx) ............................................................................................... 38
6.6 Mixing Control Pair 1 (Channels A1 & B1)(Address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(Address 09h)
Mixing Control Pair 3 (Channels A3 & B3)(Address 0Ch) .................................................................... 38
6.6.1 Channel A Volume = Channel B Volume (A=B) .................................................................... 38
6.6.2 ATAPI Channel Mixing and Muting (ATAPI) .......................................................................... 39
6.6.3 Functional Mode (FM) ........................................................................................................... 40
6.7 Volume Control (Addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh) ........................................................ 40
6.7.1 Mute (MUTE) ......................................................................................................................... 40
6.7.2 Volume Control (XX_VOL) .................................................................................................... 41
6.8 Chip Revision (Address 12h) ......................................................................................................... 41
6.8.1 Part Number ID (PART) [Read Only] .................................................................................... 41
6.8.2 Revision ID (REV) [Read Only] ............................................................................................. 41
7. FILTER PLOTS ..................................................................................................................................... 42
8. PARAMETER DEFINITIONS ................................................................................................................ 46
9. PACKAGE DIMENSIONS .................................................................................................................... 47
10. ORDERING INFORMATION .............................................................................................................. 48
11. REFERENCES .................................................................................................................................... 48
12. REVISION HISTORY .......................................................................................................................... 49
DS617F2
3
CS4362A
LIST OF FIGURES
Figure 1.Serial Audio Interface Timing ...................................................................................................... 15
Figure 2.Direct Stream Digital - Serial Audio Input Timing ........................................................................ 16
Figure 3.Control Port Timing - I²C Format ................................................................................................. 17
Figure 4.Control Port Timing - SPI Format ................................................................................................ 18
Figure 5.Typical Connection Diagram, Software Mode ............................................................................. 19
Figure 6.Typical Connection Diagram, Hardware Mode ........................................................................... 20
Figure 7.Format 0 - Left-Justified up to 24-bit Data .................................................................................. 23
Figure 8.Format 1 - I²S up to 24-bit Data .................................................................................................. 23
Figure 9.Format 2 - Right-Justified 16-bit Data ......................................................................................... 23
Figure 10.Format 3 - Right-Justified 24-bit Data ....................................................................................... 23
Figure 11.Format 4 - Right-Justified 20-bit Data ....................................................................................... 24
Figure 12.Format 5 - Right-Justified 18-bit Data ....................................................................................... 24
Figure 13.De-Emphasis Curve .................................................................................................................. 25
Figure 14.ATAPI Block Diagram (x = channel pair 1, 2, or 3) ................................................................... 25
Figure 15.Full-Scale Output ...................................................................................................................... 27
Figure 16.Recommended Output Filter ..................................................................................................... 27
Figure 17.Recommended Mute Circuitry .................................................................................................. 28
Figure 18.Control Port Timing, I²C Mode .................................................................................................. 30
Figure 19.Control Port Timing, SPI Mode ................................................................................................. 31
Figure 20.Single-Speed (fast) Stopband Rejection ................................................................................... 42
Figure 21.Single-Speed (fast) Transition Band ......................................................................................... 42
Figure 22.Single-Speed (fast) Transition Band (detail) ............................................................................. 42
Figure 23.Single-Speed (fast) Passband Ripple ....................................................................................... 42
Figure 24.Single-Speed (slow) Stopband Rejection ................................................................................. 42
Figure 25.Single-Speed (slow) Transition Band ........................................................................................ 42
Figure 26.Single-Speed (slow) Transition Band (detail) ............................................................................ 43
Figure 27.Single-Speed (slow) Passband Ripple ...................................................................................... 43
Figure 28.Double-Speed (fast) Stopband Rejection ................................................................................. 43
Figure 29.Double-Speed (fast) Transition Band ........................................................................................ 43
Figure 30.Double-Speed (fast) Transition Band (detail) ............................................................................ 43
Figure 31.Double-Speed (fast) Passband Ripple ...................................................................................... 43
Figure 32.Double-Speed (slow) Stopband Rejection ................................................................................ 44
Figure 33.Double-Speed (slow) Transition Band ...................................................................................... 44
Figure 34.Double-Speed (slow) Transition Band (detail) .......................................................................... 44
Figure 35.Double-Speed (slow) Passband Ripple .................................................................................... 44
Figure 36.Quad-Speed (fast) Stopband Rejection .................................................................................... 44
Figure 37.Quad-Speed (fast) Transition Band .......................................................................................... 44
Figure 38.Quad-Speed (fast) Transition Band (detail) .............................................................................. 45
Figure 39.Quad-Speed (fast) Passband Ripple ........................................................................................ 45
Figure 40.Quad-Speed (slow) Stopband Rejection ................................................................................... 45
Figure 41.Quad-Speed (slow) Transition Band ......................................................................................... 45
Figure 42.Quad-Speed (slow) Transition Band (detail) ............................................................................. 45
Figure 43.Quad-Speed (slow) Passband Ripple ....................................................................................... 45
4
DS617F2
CS4362A
LIST OF TABLES
Table 1. Common Clock Frequencies ....................................................................................................... 21
Table 2. Digital Interface Format, Stand-Alone Mode Options .................................................................. 22
Table 3. Mode Selection, Stand-Alone Mode Options .............................................................................. 22
Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options ........................................................... 22
Table 5. Digital Interface Formats - PCM Mode ........................................................................................ 34
Table 6. Digital Interface Formats - DSD Mode ........................................................................................ 35
Table 7. ATAPI Decode ............................................................................................................................ 39
Table 8. Example Digital Volume Settings ................................................................................................ 41
DS617F2
5
CS4362A
1. PIN DESCRIPTION
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
AOUTA2-
AOUTA2+
AOUTB2+
AOUTB2-
DSDA2
DSDB1
DSDA1
VD
1
2
3
4
GND
5
VA
6
GND
MCLK
CS4362A
LRCK(DSD_EN)
SDIN1
7
AOUTA3-
AOUTA3+
AOUTB3+
AOUTB3-
MUTEC2
MUTEC3
8
SCLK
9
10
TST
SDIN2 11
TST
2
1
13 14 15 16 17 18 19 20 21 22 23 24
Pin Name
#
Pin Description
Digital Power (Input) - Positive power supply for the digital section. Refer to the Recom-
mended Operating Conditions for appropriate voltages.
VD
4
GND
5,31 Ground (Input) - Ground reference. Should be connected to analog ground.
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Table 1
illustrates several standard audio sample rates and the required master clock frequencies.
MCLK
LRCK
6
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the
serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
7
SDIN1
SDIN2
SDIN3
8
11 Serial Data Input (Input) - Input for two’s complement serial audio data.
13
SCLK
9
Serial Clock (Input) - Serial clocks for the serial audio interface.
10,12
TST
14,44 Test - These pins need to be tied to analog ground.
45
Reset (Input) - The device enters a low power mode and all internal registers are reset to their
default settings when low.
RST
VA
19
Analog Power (Input) - Positive power supply for the analog section. Refer to the Recom-
mended Operating Conditions for appropriate voltages.
32
Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio
interface. Refer to the Recommended Operating Conditions for appropriate voltages.
VLS
43
Control Port Power (Input) - Determines the required signal level for the control port and hard-
18 ware mode configuration pins. Refer to the Recommended Operating Conditions for appropri-
ate voltages.
VLC
6
DS617F2
CS4362A
Pin Name
#
Pin Description
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be
capacitively coupled to analog ground, as shown in the Typical Connection Diagram. The nom-
inal voltage level is specified in the Analog Characteristics and Specifications section. VQ pre-
VQ
21 sents an appreciable source impedance and any current drawn from this pin will alter device
performance. However, VQ can be used to bias the analog circuitry assuming there is no AC
signal component and the DC current is less then the maximum specified in the Analog Charac-
teristics and Specifications section.
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-
20 cuits. Requires the capacitive decoupling to analog ground as shown in the Typical Connection
Diagram.
FILT+
AOUTA1 +,-
AOUTB1 +,-
AOUTA2 +,-
AOUTB2 +,-
AOUTA3 +,-
AOUTB3 +,-
39,40
38,37
35,36 Differential Analog Output (Output) - The full-scale differential analog output level is specified
34,33 in the Analog Characteristics specification table.
29,30
28,27
MUTEC1
MUTEC2
MUTEC3
MUTEC4
MUTEC5
MUTEC6
41
26 Mute Control (Output) - These pins are intended to be used as a control for external mute cir-
25 cuits on the line outputs to prevent the clicks and pops that can occur in any single supply sys-
24 tem. Use of Mute Control is not mandatory but recommended for designs requiring the absolute
23 minimum in extraneous clicks and pops.
22
Hardware Mode Definitions
17
M0
16 Mode Selection (Input) - Determines the operational mode of the device as detailed in Table 6
15 and Table 7.
42
M2
M3
Software Mode Definitions
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external
pull-up resistor to the logic interface voltage in I²C® Mode as shown in the Typical Connection
Diagram.
SCL/CCLK
SDA/CDIN
15
Serial Control Port Data (Input/Output) - SDA is a data I/O line in I²C Mode and is open drain,
16 requiring an external pull-up resistor to the logic interface voltage, as shown in the Typical Con-
nection Diagram; CDIN is the input data line for the control port interface in SPI™ mode.
Address Bit 0 (C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C
Mode; CS is the chip select signal for SPI mode.
AD0/CS
17
DSD Definitions
DSDA1
DSDB1
DSDA2
DSDB2
DSDA3
DSDB3
3
2
1
48
47
46
Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.
DSD_SCLK
42 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital serial audio interface.
DSD Enable (Input) - When held at logic ‘1’, the device will enter DSD Mode (Stand-Alone Mode
only).
DSD_EN
7
DS617F2
7
CS4362A
2. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to ground.)
Parameters
Symbol
Min
Typ
Max
Units
DC Power Supply
Analog Power
Digital Internal Power
Serial Data Port Interface Power
Control Port Interface Power
VA
VD
VLS
VLC
4.75
2.37
1.71
1.71
5.0
2.5
5.0
5.0
5.25
2.63
5.25
5.25
V
V
V
V
Ambient Operating Temperature (power applied)
Commercial Grade (-CQZ)
Automotive Grade (-DQZ)
-40
-40
-
-
+85
+105
TA
°C
°C
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to ground.)
Parameters
Symbol
Min
Max
Units
DC Power Supply
Analog Power
VA
VD
VLS
VLC
-0.3
-0.3
-0.3
-0.3
6.0
3.2
6.0
6.0
V
V
V
V
Digital Internal Power
Serial Data Port Interface Power
Control Port Interface Power
Input Current
Any Pin Except Supplies
Iin
-
±10
mA
Digital Input Voltage
Serial Data Port Interface
Control Port Interface
VIND-S
VIND-C
-0.3
-0.3
VLS+ 0.4
VLC+ 0.4
V
V
Ambient Operating Temperature (power applied)
Storage Temperature
Top
-55
-65
125
150
°C
°C
Tstg
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
8
DS617F2
CS4362A
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ)
Test Conditions (unless otherwise specified): VA = VLS = VLC = 5 V; VD = 2.5 V; T = 25°C; Full-Scale 997 Hz
A
input sine wave (Note 1); Tested under max ac-load resistance; Valid with FILT+ and VQ capacitors as shown in
“Typical Connection Diagram” on page 19; Measurement Bandwidth 10 Hz to 20 kHz.
Parameters
Symbol
Min
Typ
Max
Unit
FS = 48 kHz, 96 kHz, 192 kHz and DSD
Dynamic Range
24-bit A-weighted
108
105
-
-
114
111
97
-
-
-
-
dB
dB
dB
dB
Unweighted
16-bit A-weighted
(Note 2) Unweighted
94
Total Harmonic Distortion + Noise
24-bit
0 dB
-
-
-
-
-
-
-100
-91
-51
-94
-74
-34
-94
-
-45
-
-
-
dB
dB
dB
dB
dB
dB
-20 dB
-60 dB THD+N
0 dB
-20 dB
-60 dB
(Note 2) 16-bit
Idle Channel Noise / Signal-to-noise Ratio
Interchannel Isolation
-
-
114
110
-
-
dB
dB
(1 kHz)
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
-
-
0.1
-
-
dB
100
ppm/°C
Analog Output
Full-scale Differential Output Voltage
Output Impedance
VFS
128%•VA
132%•VA
130
136%•VA
Vpp
Ω
(Note 3) ZOUT
-
-
-
-
-
-
-
-
-
-
-
-
Max DC Current Draw From an AOUT Pin
Min AC-load Resistance
Max Load Capacitance
Quiescent Voltage
IOUTmax
RL
1.0
mA
kΩ
3
CL
100
pF
VQ
50%•VA
10
VDC
µA
Max Current draw from VQ
IQMAX
Notes:
1. One-half LSB of triangular PDF dither is added to data.
2. Performance limited by 16-bit quantization noise.
3.
V
is tested under load R and includes attenuation due to Z
FS L OUT
DS617F2
9
CS4362A
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ)
Test Conditions (unless otherwise specified): VA = 4.75 to 5.25 V; VLS = 1.71 to 5.25 V; VLC = 1.71 to 5.25 V; VD
= 2.37 to 2.63 V; T = -40°C to 85°C; Full-Scale 997 Hz input sine wave (Note 1); Tested under max ac-load resis-
A
tance; Valid with FILT+ and VQ capacitors as shown in “Typical Connection Diagram” on page 19; Measurement
Bandwidth 10 Hz to 20 kHz.
Parameters
Symbol
Min
Typ
Max
Unit
FS = 48 kHz, 96 kHz, 192 kHz and DSD
Dynamic Range
24-bit A-weighted
105
102
-
-
114
111
97
-
-
-
-
dB
dB
dB
dB
Unweighted
16-bit A-weighted
(Note 2) Unweighted
94
Total Harmonic Distortion + Noise
24-bit
0 dB
-
-
-
-
-
-
-100
-91
-51
-94
-74
-34
-91
-
-42
-
-
-
dB
dB
dB
dB
dB
dB
-20 dB
-60 dB THD+N
0 dB
-20 dB
-60 dB
(Note 2) 16-bit
Idle Channel Noise / Signal-to-noise Ratio
Interchannel Isolation
-
-
114
110
-
-
dB
dB
(1 kHz)
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
-
-
0.1
-
-
dB
100
ppm/°C
Analog Output
Full-scale Differential Output Voltage
Output Impedance
VFS
128%•VA
132%•VA
130
136%•VA
Vpp
Ω
(Note 3) ZOUT
-
-
-
-
-
-
-
-
-
-
-
-
Max DC Current Draw From an AOUT Pin
Min AC-load Resistance
Max Load Capacitance
Quiescent Voltage
IOUTmax
RL
1.0
mA
kΩ
3
CL
100
pF
VQ
50%•VA
10
VDC
µA
Max Current draw from VQ
IQMAX
10
DS617F2
CS4362A
POWER AND THERMAL CHARACTERISTICS
Parameters
Symbol
Min
Typ
Max
Units
Power Supplies
Power Supply Current
(Note 4)
Normal Operation, VA= 5 V
VD= 2.5 V
(Note 5) Interface Current, VLC=5 V
VLS=5 V
IA
ID
ILC
ILS
Ipd
-
-
-
-
-
60
16
2
84
200
65
22
-
-
-
mA
mA
µA
µA
µA
(Note 6) Power-down State (all supplies)
Power Dissipation (Note 4)
VA = 5 V, VD = 2.5 V
Normal Operation
-
-
340
1
390
-
mW
mW
(Note 6) Power-down
Package Thermal Resistance
Multi-layer
Two-layer
θJA
θJA
θJC
-
-
-
48
65
15
-
-
-
°C/Watt
°C/Watt
°C/Watt
Power Supply Rejection Ratio (Note 7)
(1 kHz)
(60 Hz)
-
-
60
40
-
-
dB
dB
PSRR
Notes:
4. Current consumption increases with increasing FS within a given speed mode and is signal-dependent.
Max values are based on highest FS and highest MCLK.
5.
I
measured with no external loading on the SDA pin.
LC
6. Power-down Mode is defined as RST pin = Low with all clock and data lines held static.
7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 5 and Figure 6.
DS617F2
11
CS4362A
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam-
ple rate by multiplying the given characteristic by Fs.
See Note 12.
Fast Roll-Off
Parameter
Min
Typ
Max
Unit
Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
.454
.499
+0.01
-
-
-
±0.23
±0.14
±0.09
Fs
Fs
dB
Fs
dB
s
dB
dB
dB
Frequency Response
Stop Band
Stop-band Attenuation
Group Delay
De-emphasis Error (Note 11)
(Relative to 1 kHz)
-0.01
0.547
102
-
-
-
-
(Note 10)
-
10.4/Fs
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
.430
.499
+0.01
-
-
-
Fs
Fs
dB
Fs
dB
s
Frequency Response
Stop Band
Stop-band Attenuation
Group Delay
-0.01
.583
80
(Note 10)
-
-
6.15/Fs
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
-
.105
.490
+0.01
-
-
-
Fs
Fs
dB
Fs
dB
s
Frequency Response
Stop Band
Stop-band Attenuation
Group Delay
-0.01
.635
90
(Note 10)
-
7.1/Fs
Notes:
8. Slow roll-off interpolation filter is only available in Software Mode.
9. Response is clock-dependent and will scale with Fs.
10. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.
11. De-emphasis is available only in Single-Speed Mode; only 44.1 kHz De-emphasis is available in Hard-
ware Mode.
12. Amplitude vs. Frequency plots of this data are available in Section 7. “Filter Plots” on page 42.
12
DS617F2
CS4362A
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(CONTINUED)
Slow Roll-Off (Note 8)
Parameter
Min
Typ
Max
Unit
Single-Speed Mode - 48 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
0.417
0.499
+0.01
-
-
-
Fs
Fs
dB
Fs
dB
s
Frequency Response
Stop Band
Stop-band Attenuation
Group Delay
-0.01
.583
64
-
(Note 10)
-
7.8/Fs
De-emphasis Error (Note 11)
(Relative to 1 kHz)
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
±0.36
±0.21
±0.14
dB
dB
dB
Double-Speed Mode - 96 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
-
.296
.499
+0.01
-
-
-
Fs
Fs
dB
Fs
dB
s
Frequency Response
Stop Band
Stop-band Attenuation
Group Delay
-0.01
.792
70
(Note 10)
-
5.4/Fs
Quad-Speed Mode - 192 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
-
.104
.481
+0.01
-
-
-
Fs
Fs
dB
Fs
dB
s
Frequency Response
Stop Band
Stop-band Attenuation
Group Delay
-0.01
.868
75
(Note 10)
-
6.6/Fs
DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE
Parameter
Min
Typ
Max
Unit
DSD Processor mode
Passband (Note 9)
Frequency Response
Roll-off
to -3 dB corner
10 Hz to 20 kHz
0
-
-
-
50
+0.05
-
kHz
dB
dB/Oct
-0.05
27
DS617F2
13
CS4362A
DIGITAL CHARACTERISTICS
Parameters
Input Leakage Current
Symbol
Min
-
-
Typ
-
Max
±10
-
Units
µA
pF
(Note 13)
Iin
Input Capacitance
8
High-level Input Voltage
Serial I/O
Control I/O
VIH
VIH
70%
70%
-
-
-
-
VLS
VLC
Low-level Input Voltage
Serial I/O
Control I/O
VIL
VIL
-
-
-
-
30%
30%
VLS
VLC
Low-level Output Voltage (IOL = -1.2 mA)
Control I/O = 3.3 V, 5 V
Control I/O = 1.8 V, 2.5 V
VOL
VOL
-
-
-
-
20%
25%
VLC
VLC
Maximum MUTEC Drive Current
MUTEC High-level Output Voltage
MUTEC Low-level Output Voltage
Imax
VOH
VOL
-
-
-
3
VA
0
-
-
-
mA
V
V
13. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch-
up.
14
DS617F2
CS4362A
SWITCHING CHARACTERISTICS - PCM
(Inputs: Logic 0 = GND, Logic 1 = VLS, C = 30 pF)
L
Parameters
Symbol
Min
Max
Units
RST pin Low Pulse Width
(Note 14)
(Note 15)
1
-
ms
MCLK Frequency
1.024
45
55.2
55
MHz
%
MCLK Duty Cycle
Input Sample Rate - LRCK
Single-speed Mode
Double-speed Mode
Quad-speed Mode
Fs
Fs
Fs
4
50
100
54
108
216
kHz
kHz
kHz
LRCK Duty Cycle
45
45
8
55
55
-
%
%
SCLK Duty Cycle
SCLK High Time
tsckh
tsckl
tlcks
tds
ns
ns
ns
ns
ns
SCLK Low Time
8
-
LRCK Edge to SCLK rising edge
SDIN Setup Time before SCLK rising edge
SDIN Hold Time after SCLK rising edge
5
-
3
-
tdh
5
-
Notes:
14. After powering up, RST should be held low until after the power supplies and clocks are settled.
15. See Table 1 on page 21 for suggested MCLK frequencies.
LRCK
tlcks
tsckh
tsckl
SCLK
tds
tdh
MSB
SDINx
MSB-1
Figure 1. Serial Audio Interface Timing
DS617F2
15
CS4362A
SWITCHING CHARACTERISTICS - DSD
(Logic 0 = AGND = DGND; Logic 1 = VLS; CL = 20 pF)
Parameter
MCLK Duty Cycle
Symbol
Min
40
Typ
Max
60
-
Unit
%
-
-
-
DSD_SCLK Pulse Width Low
DSD_SCLK Pulse Width High
tsclkl
160
160
ns
tsclkh
-
ns
DSD_SCLK Frequency
(64x Oversampled)
(128x Oversampled)
1.024
2.048
-
-
3.2
6.4
MHz
MHz
DSD_A / _B valid to DSD_SCLK rising setup time
DSD_SCLK rising to DSD_A or DSD_B hold time
tsdlrs
tsdh
20
20
-
-
-
-
ns
ns
t
sclkh
t
sclkl
DSD_SCLK
DSDxx
t
t
sdlrs
sdh
Figure 2. Direct Stream Digital - Serial Audio Input Timing
16
DS617F2
CS4362A
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol
fscl
Min
-
Max
Unit
kHz
ns
SCL Clock Frequency
100
RST Rising Edge to Start
tirs
500
4.7
4.0
4.7
4.0
4.7
0
-
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
tbuf
-
µs
thdst
tlow
-
µs
-
µs
Clock High Time
thigh
tsust
thdd
-
µs
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
-
µs
(Note 16)
-
µs
tsud
250
-
-
1
ns
trc, trc
tfc, tfc
tsusp
tack
µs
Fall Time SCL and SDA
-
300
-
ns
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
4.7
300
µs
1000
ns
Notes:
16. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t
irs
Repeated
Start
Stop
Start
Stop
SDA
SC L
t
t
t
t
t
buf
t
high
hdst
f
susp
hdst
t
t
t
t
t
sust
sud
r
low
hdd
Figure 3. Control Port Timing - I²C Format
DS617F2
17
CS4362A
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol
fsclk
tsrs
Min
-
Max
Unit
MHz
ns
CCLK Clock Frequency
6
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
500
500
1.0
20
66
66
40
15
-
-
(Note 17)
tspi
-
ns
tcsh
tcss
tscl
-
µs
-
ns
-
ns
CCLK High Time
tsch
tdsu
tdh
-
-
ns
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
ns
(Note 18)
(Note 19)
(Note 19)
-
ns
tr2
100
100
ns
tf2
-
ns
Notes:
17. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
18. Data must be held for sufficient time to bridge the transition time of CCLK.
19. For FSCK < 1 MHz.
RST
CS
t
srs
spi
t
t
t
t
css
scl
sch
t
csh
CCLK
t
t
r2
f2
C DIN
t
t
dsu
dh
Figure 4. Control Port Timing - SPI Format
18
DS617F2
CS4362A
3. TYPICAL CONNECTION DIAGRAM
+2.5 V
+5 V
+
+
1 µF
0.1 µF
0.1 µF
1 µF
4
32
VA
VD
220 Ω
6
7
9
MCLK
39
40
AOUTA1+
AOUTA1-
Analog Conditioning
and Muting
LRCK
SCLK
PCM
Digital
Audio
Source
8
11
13
SDIN1
SDIN2
SDIN3
38
37
AOUTB1+
AOUTB1-
Analog Conditioning
and Muting
470 Ω
470 Ω
35
36
AOUTA2+
AOUTA2-
Analog Conditioning
and Muting
43
+1.8 V to +5 V
VLS
CS4362A
34
33
AOUTB2+
0.1 µF
Analog Conditioning
and Muting
AOUTB2-
3
2
29
30
DSDA1
DSDB1
DSDA2
AOUTA3+
AOUTA3-
Analog Conditioning
and Muting
1
DSD
Audio
Source
48
28
27
AOUTB3+
AOUTB3-
DSDB2
Analog Conditioning
and Muting
47
DSDA3
DSDB3
46
42
41
26
25
24
23
22
DSD_SCLK
MUTEC1
MUTEC2
MUTEC3
MUTEC4
Mute
Drive
19
RST
MUTEC5
MUTEC6
15
16
Micro-
Controller
SCL/CCLK
SDA/CDIN
17
ADO/CS
Note*
20
21
FILT+
18
+1.8 V to +5 V
VLC
+
CMOUT
0.1 µF
F
47 µF
0.1 µ
F
1 µF
0.1 µ
+
GND
5
TST
GND
31
10, 12,
14, 44, 45
Note*: Necessary for I2C
control port operation
Figure 5. Typical Connection Diagram, Software Mode
DS617F2
19
CS4362A
+2.5 V
+5 V
+
+
1 µF
0.1 µF
0.1 µF
1 µF
4
VD
32
VA
47 K
Ω
NoteDSD
VLS
220 Ω
6
MCLK
39
40
41
AOUTA1+
AOUTA1-
MUTEC1
7
9
8
LRCK
SCLK
SDIN1
SDIN2
Analog Conditioning
and Muting
PCM
Digital
Audio
Source
11
13
38
37
26
AOUTB1+
AOUTB1-
MUTEC2
SDIN3
Analog Conditioning
and Muting
470 Ω
470 Ω
43
+1.8 V to +5 V
VLS
CS4362A
0.1 µF
35
36
25
AOUTA2+
AOUTA2-
MUTEC3
Analog Conditioning
and Muting
3
2
DSDA1
DSDB1
DSDA2
1
34
DSD
Audio
Source
AOUTB2+
AOUTB2-
MUTEC4
48
Analog Conditioning
and Muting
33
24
DSDB2
47
46
DSDA3
DSDB3
29
30
23
AOUTA3+
AOUTA3-
MUTEC5
Analog Conditioning
and Muting
NoteDSD
Optional
47 KΩ
42
M3(DSD_SCLK)
28
27
22
AOUTB3+
AOUTB3-
MUTEC6
15
16
Analog Conditioning
and Muting
M2
M1
Stand-Alone
Mode
Configuration
17
19
M0
RST
20
21
FILT+
+
CMOUT
F
47 µF
0.1 µ
18
F
0.1 µ
1 µF
+1.8 V to +5 V
VLC
+
0.1 µF
NoteDSD: For DSD operation:
1) LRCK must be tied to VLS and
remain static high.
GND
5
TST
GND
31
10, 12,
14, 44, 45
2) M3 PCM stand-alone configuration
pin becomes DSD_SCLK
Figure 6. Typical Connection Diagram, Hardware Mode
20
DS617F2
CS4362A
4. APPLICATIONS
The CS4362A serially accepts two’s-complement formatted PCM data at standard audio sample rates including 48,
44.1, and 32 kHz in SSM, 96, 88.2, and 64 kHz in DSM, and 192, 176.4, and 128 kHz in QSM. Audio data is input
via the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input
on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer.
The CS4362A can be configured in Hardware Mode by the M0, M1, M2, M3, and DSD_EN pins and in Software
Mode through I²C or SPI.
4.1
Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequen-
cy at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected
automatically during the initialization sequence by counting the number of MCLK transitions during a single
LRCK period. Internal dividers are then set to generate the proper internal clocks. Table 1 illustrates several
standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no re-
quired phase relationship, but MCLK, LRCK, and SCLK must be synchronous.
Sample
Rate
(kHz)
Speed Mode
(sample-rate range)
Software
Mode Only
MCLK (MHz)
MCLK Ratio
256x
8.1920
11.2896
12.2880
128x
384x
512x
768x
1024x*
32.7680
45.1584
49.1520
512x*
32
44.1
48
12.2880
16.9344
18.4320
192x
16.3840
22.5792
24.5760
256x
24.5760
33.8688
36.8640
384x
Single-Speed
(4 to 50 kHz)
MCLK Ratio
64
88.2
96
8.1920
11.2896
12.2880
64x
12.2880
16.9344
18.4320
96x
16.3840
22.5792
24.5760
128x
24.5760
33.8688
36.8640
192x
32.7680
45.1584
49.1520
256x*
Double-Speed
(50 to 100 kHz)
MCLK Ratio
176.4
192
11.2896
12.2880
16.9344
18.4320
22.5792
24.5760
33.8688
36.8640
45.1584
49.1520
Quad-Speed
(100 to 200 kHz)
Note: These modes are only available in Software Mode by setting the MCLKDIV bit = 1.
Table 1. Common Clock Frequencies
4.2
Mode Select
In Hardware Mode, operation is determined by the Mode Select pins. The states of these pins are continu-
ally scanned for any changes; however, the mode should only be changed while the device is in reset
(RST pin low) to ensure proper switching from one mode to another. These pins require connection to sup-
ply or ground as outlined in Figure 6. VLC supplies M0, M1, and M2. VLS supplies M3 and DSD_EN.
Tables 2 - 4 show the decode of these pins.
In Software Mode, the operational mode and data format are set in the FM and DIF registers. See “Digital
Interface Format (DIF)” on page 34 and “Functional Mode (FM)” on page 40.
DS617F2
21
CS4362A
M1
(DIF1)
M0
(DIF0)
DESCRIPTION
Left-justified, up to 24-bit data
I²S, up to 24-bit data
Right-justified, 16-bit Data
Right-justified, 24-bit Data
FORMAT
FIGURE
0
0
1
1
0
1
0
1
0
1
2
3
Figure 7
Figure 8
Figure 9
Figure 10
Table 2. Digital Interface Format, Stand-Alone Mode Options
M3
M2
DESCRIPTION
(DEM)
Single-speed without De-emphasis (4 to 50 kHz sample rates)
Single-speed with 44.1 kHz De-Emphasis; see Figure 13
Double-speed (50 to 100 kHz sample rates)
0
0
1
1
0
1
0
1
Quad-speed (100 to 200 kHz sample rates)
Table 3. Mode Selection, Stand-Alone Mode Options
DSD_EN
(LRCK)
M2
M1
M0
DESCRIPTION
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options
22
DS617F2
CS4362A
4.3
Digital Interface Formats
The serial port operates as a slave and supports the I²S, Left-justified, and Right-justified digital interface
formats with varying bit depths from 16 to 24 as shown in Figures 7-12. Data is clocked into the DAC on the
rising edge.
Left Channel
Right Channel
LRCK
SCLK
SDINx
MSB
LSB
MSB
LSB
+5 +4 +3 +2 +1
+5 +4 +3 +2 +1
-1 -2 -3 -4 -5
-1 -2 -3 -4
Figure 7. Format 0 - Left-Justified up to 24-bit Data
Left Channel
Right Channel
LRCK
SCLK
SDINx
MSB
+5 +4 +3 +2 +1
LSB
MSB
LSB
+5 +4 +3 +2 +1
-1 -2 -3 -4 -5
-1 -2 -3 -4
Figure 8. Format 1 - I²S up to 24-bit Data
Right Channel
LRCK
SCLK
Left Channel
SDINx
9
8
7
6
5
4
3
2
1
0
9
15 14 13 12 11 10
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
32 clocks
Figure 9. Format 2 - Right-Justified 16-bit Data
Right Channel
LRCK
SCLK
Left Channel
SDINx
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
23 22 21 20 19 18
32 clocks
23 22 21 20 19 18
Figure 10. Format 3 - Right-Justified 24-bit Data
DS617F2
23
CS4362A
Right Channel
LRCK
SCLK
Left Channel
SDINx
1
0
19 18 17 16
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
32 clocks
15 14 13 12 11 10
19 18 17 16 9
Figure 11. Format 4 - Right-Justified 20-bit Data
Right Channel
LRCK
SCLK
Left Channel
SDINx
1
0
17 16
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1 0
15 14 13 12 11 10
32 clocks
15 14 13 12 11 10
17 16 9
Figure 12. Format 5 - Right-Justified 18-bit Data
4.4
Oversampling Modes
The CS4362A operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the DSD_EN, M3, and M2 pins in Hardware Mode or the FM bits in Software Mode. Single-
speed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-speed
Mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-speed Mode
supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
4.5
Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS4362A incorpo-
rates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available
in each of Single, Double, and Quad-Speed modes. These filters have been designed to accommodate a
variety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the “Filter
Plots” on page 42 for more details).
When in Hardware Mode, only the “fast” roll-off filter is available.
Filter specifications can be found in Section 2, and filter response plots can be found in Figures 20 to 43.
4.6
De-emphasis
The CS4362A includes on-chip digital de-emphasis filters. The de-emphasis feature is included to accom-
modate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction.
Figure 13 shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale pro-
portionally with changes in sample rate (Fs) if the input sample rate does not match the coefficient which
has been selected.
24
DS617F2
CS4362A
In Software Mode, the required de-emphasis filter coefficients for 32 kHz, 44.1 kHz, or 48 kHz are selected
via the de-emphasis control bits.
In Hardware Mode, only the 44.1 kHz coefficient is available (enabled through the M2 pin). If the input sam-
ple rate is not 44.1 kHz and de-emphasis has been selected, the corner frequencies of the de-emphasis
filter will be scaled by a factor of the actual Fs over 44,100.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
F2
Frequency
3.183 kHz
10.61 kHz
Figure 13. De-Emphasis Curve
4.7
ATAPI Specification
The CS4362A implements the channel mixing functions of the ATAPI CD-ROM specification. The
ATAPI functions are applied per A-B pair. Refer to Table 8 on page 41 and Figure 14 for additional informa-
tion.
A Channel
Volume
Control
Left Channel
Audio Data
MUTE
AoutAx
Σ
Σ
SDINx
B Channel
Volume
Control
Right Channel
Audio Data
MUTE
AoutBx
Figure 14. ATAPI Block Diagram (x = channel pair 1, 2, or 3)
DS617F2
25
CS4362A
4.8
Direct Stream Digital (DSD) Mode
In Stand-alone Mode, DSD operation is selected by holding DSD_EN(LRCK) high and applying the DSD
data and clocks to the appropriate pins. The M[2:0] pins set the expected DSD rate and MCLK ratio.
In Control Port Mode, the FM bits set the device into DSD Mode (DSD_EN pin is not required to be held
high). The DIF register then controls the expected DSD rate and MCLK ratio.
During DSD operation, the PCM related pins should either be tied low or remain active with clocks (except
LRCK in Stand-alone Mode). When the DSD related pins are not being used, they should either be tied static
low or remain active with clocks (except M3 in Stand-alone Mode).
4.9
Grounding and Power Supply Arrangements
As with any high-resolution converter, the CS4362A requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. The Typical Connection Diagram shows the
recommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground
planes are split between digital ground and analog ground, the GND pins of the CS4362A should be con-
nected to the analog ground plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the DAC.
4.9.1
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low-value ceramic ca-
pacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins with similar voltage ratings may be connected to the same
supply, but a decoupling capacitor should still be placed on each supply pin.
Notes: All decoupling capacitors should be referenced to analog ground.
The CDB4362A evaluation board demonstrates the optimum layout and power supply arrangements.
4.10 Analog Output and Filtering
The application note “Design Notes for a 2-pole Filter with Differential Input” discusses the second-order
Butterworth filter and differential-to-single-ended converter which was implemented on the CS4362A eval-
uation board, CDB4362A, as seen in Figure 16. The CS4362A does not include phase or amplitude com-
pensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent
on the external analog circuitry. The off-chip filter has been designed to attenuate the typical full-scale out-
put level to below 2 Vrms.
Figure 15 shows how the full-scale differential analog output level specification is derived.
26
DS617F2
CS4362A
3.85 V
2.5 V
AOUT+
AOUT-
1.15 V
3.85 V
2.5 V
1.15 V
Full-Scale Output Level= (AOUT+) - (AOUT-)= 6.7 Vpp
Figure 15. Full-Scale Output
Figure 16. Recommended Output Filter
4.11 Mute Control
The Mute Control pins go active during power-up initialization, muting, or if the MCLK-to-LRCK ratio is in-
correct. These pins are intended to be used as control for external mute circuits to prevent the clicks and
pops that can occur in any single-ended, single-supply system. The MUTEC output pins are high impedance
at the time of reset. The external mute circuitry needs to be self biased into an active state in order to be
muted during reset. Once reset has been released, the MUTEC pins are active high in hardware mode and
the active state is set by the MUTEC+/- register in software mode (see Section 6.3.4).
Figure 17 shows a single example of both an active high and an active low mute drive circuit. In these de-
signs, the pull-up and pull-down resistors have been especially chosen to meet the input high/low threshold
when used with the MMUN2111 and MMUN2211 internal bias resistances of 10 kΩ.
DS617F2
27
CS4362A
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute min-
imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer
to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
Figure 17. Recommended Mute Circuitry
4.12 Recommended Power-Up Sequence
4.12.1 Hardware Mode
1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the
registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2.
If RST can not be held low long enough the SDINx pins should remain static low until all other clocks
are stable, and if possible the RST should be toggled low again once the system is stable.
2. Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the
Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024
LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.12.2 Software Mode
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default
settings; FILT+ will remain low, and VQ will be connected to VA/2.
2. Bring RST high. The device will remain in a low-power state with FILT+ low for 512 LRCK cycles in
Single-speed Mode (1024 LRCK cycles in Double-speed Mode, and 2048 LRCK cycles in Quad-
speed Mode).
3. In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the
completion of approximately 512 LRCK cycles in Single-speed Mode (1024 LRCK cycles in Double-
speed Mode, and 2048 LRCK cycles in Quad-speed Mode). The desired register settings can be
loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1; then set the
format and mode control bits to the desired settings.
If more than the stated number of LRCK cycles passes before CPEN bit is written, the chip will enter
Hardware Mode and begin to operate with the M0-M3 as the mode settings. CPEN bit may be written
at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit cannot be
set in time, the SDINx pins should remain static low (this way, no audio data can be converted
incorrectly by the Hardware Mode settings).
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs.
28
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CS4362A
4.13 Recommended Procedure for Switching Operational Modes
For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE
bits are set prior to changing significant DAC functions (such as changing sample rates or clock sources).
The mute bits may then be released after clocks have settled and the proper modes have been set.
It is required to have the device held in reset if the minimum high/low time specs of MCLK cannot be met
during clock source changes.
4.14 Control Port Interface
The Control Port is used to load all the internal register settings in order to operate in Software Mode (see
the “Filter Plots” on page 42). The operation of the Control Port may be completely asynchronous with the
audio sample rate. However, to avoid potential interference problems, the Control Port pins should remain
static if no operation is required.
The Control Port operates in one of two modes: I²C or SPI.
4.14.1 MAP Auto Increment
The device has MAP (memory address pointer) auto-increment capability enabled by the INCR bit (also
the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and
SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or
writes of successive registers.
4.14.2 I²C Mode
In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
Control Port clock, SCL (see Figure 18 for the clock to data relationship). There is no CS pin. Pin AD0
enables the user to alter the chip address (001100[AD0][R/W]) and should be tied to VLC or GND, as re-
quired, before powering up the device. If the device ever detects a high-to-low transition on the AD0/CS
pin after power-up, SPI Mode will be selected.
4.14.2.1 I²C Write
To write to the device, follow the procedure below while adhering to the Control Port Switching Specifica-
tions in Section 2.
1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth
bit of the address byte is the R/W bit.
2. Wait for an acknowledge (ACK) from the part; then write to the memory address pointer, MAP. This
byte points to the register to be written.
3. Wait for an acknowledge (ACK) from the part; then write the desired data to the register pointed to by
the MAP.
4. If the INCR bit (see Section 4.14.1) is set to 1, repeat the previous step until all the desired registers
are written, then initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to initiate
a repeated START condition and follow the procedure detailed from step 1. If no further writes to other
registers are desired, initiate a STOP condition to the bus.
DS617F2
29
CS4362A
4.14.2.2 I²C Read
To read from the device, follow the procedure below while adhering to the Control Port Switching Speci-
fications.
1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth
bit of the address byte is the R/W bit.
2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register
pointed to by the MAP. The MAP register will contain the address of the last register written to the
MAP, or the default address (see Section 4.14.1) if an I²C read is the first operation performed on the
device.
3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Con-
tinue providing a clock and issue an ACK after each byte until all the desired registers are read; then
initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to initiate
a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I²C Write
instructions followed by step 1 of the I²C Read section. If no further reads from other registers are de-
sired, initiate a STOP condition to the bus.
Note 1
ADDR
AD0
DATA
1-8
DATA
1-8
001100
R/W
ACK
ACK
ACK
SDA
SCL
Start
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 18. Control Port Timing, I²C Mode
4.14.3 SPI Mode
In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial Control Port clock, CCLK
(see Figure 19 for the clock-to-data relationship). There is no AD0 pin. Pin CS is the chip select signal and
is used to control SPI writes to the Control Port. When the device detects a high-to-low transition on the
AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
4.14.3.1 SPI Write
To write to the device, follow the procedure below while adhering to the Control Port Switching Specifica-
tions in Section 2.
1. Bring CS low.
2. The address byte on the CDIN pin must then be 00110000.
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see Section 4.14.1) is set to 1, repeat the previous step until all the desired registers
are written, then bring CS high.
30
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CS4362A
6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring
CS high, and follow the procedure detailed from step 1. If no further writes to other registers are de-
sired, bring CS high.
CS
CCLK
CHIP
ADDRESS
MAP
DATA
0011000
LSB
CDIN
MSB
R/W
byte 1
byte n
MAP = Memory Address Pointer
Figure 19. Control Port Timing, SPI Mode
4.15 Memory Address Pointer (MAP)
7
INCR
0
6
Reserved
0
5
Reserved
0
4
MAP4
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
4.16 INCR (Auto Map Increment Enable)
Default = ‘0’
0 - Disabled
1 - Enabled
4.16.1 MAP4-0 (Memory Address Pointer)
Default = ‘00000’
DS617F2
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CS4362A
5. REGISTER QUICK REFERENCE
Addr
Function
7
6
5
4
3
2
1
0
01h Mode Control 1
CPEN
FREEZE MCLKDIV Reserved DAC3_DIS DAC2_DIS DAC1_DIS
PDN
1
0
0
DIF2
0
0
DIF0
0
0
0
0
default
0
DIF1
0
02h Mode Control 2
default
03h Mode Control 3
default
Reserved
Reserved Reserved Reserved Reserved
0
SZC1
1
0
0
0
MUTEC1
0
0
SZC0
0
SNGLVOL RMP_UP MUTEC+/-
AMUTE
MUTEC0
0
0
0
1
DEM1
0
0
RMP_DN
0
04h Filter Control
default
Reserved Reserved Reserved FILT_SEL Reserved
DEM0
0
0
0
0
INV_B3
0
0
INV_A3
0
0
INV_B2
0
05h Invert Control
Reserved Reserved
INV_A2
0
INV_B1
0
INV_A1
0
0
0
default
06h Mixing Control
Pair 1 (AOUTx1)
P1_A=B P1ATAPI4 P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0
FM1
FM0
0
0
1
0
0
1
0
0
default
07h Vol. Control A1
default
A1_MUTE A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0
0
0
0
0
0
0
0
0
08h Vol. Control B1
default
B1_MUTE B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0
0
0
0
0
0
0
0
0
09h Mixing Control
Pair 2 (AOUTx2)
P2_A=B P2ATAPI4 P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0 Reserved Reserved
0
0
1
0
0
1
0
0
default
0Ah Vol. Control A2
default
A2_MUTE A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0
0
0
0
0
0
0
0
0
0Bh Vol. Control B2
B2_MUTE B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0
0
0
0
0
0
0
0
0
default
0Ch Mixing Control
Pair 3 (AOUTx3)
P3_A=B P3ATAPI4 P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0 Reserved Reserved
0
0
1
0
0
1
0
0
default
0Dh Vol. Control A3
default
A3_MUTE A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0
0
0
0
0
0
0
0
0
0Eh Vol. Control B3
default
12h Chip Revision
default
B3_MUTE B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0
0
PART4
0
0
PART3
1
0
PART2
0
0
PART1
1
0
PART0
0
0
REV2
x
0
REV1
x
0
REV0
x
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CS4362A
6. REGISTER DESCRIPTION
Note: All registers are read/write in I²C Mode and write only in SPI, unless otherwise noted.
6.1
Mode Control 1 (Address 01h)
7
CPEN
0
6
FREEZE
0
5
MCLKDIV
0
4
Reserved
0
3
DAC3_DIS
0
2
DAC2_DIS
0
1
0
PDN
1
DAC1_DIS
0
6.1.1
Control Port Enable (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can
be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg-
isters and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user
should write this bit within 10 ms following the release of Reset.
6.1.2
Freeze Controls (FREEZE)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until the
FREEZE is disabled. To make multiple changes in the Control Port registers take effect simultaneously,
enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
6.1.3
Master Clock Divide Enable (MCLKDIV)
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry.
6.1.4
DAC Pair Disable (DACx_DIS)
Default = 0
0 - DAC Pair x Enabled
1 - DAC Pair x Disabled
Function:
When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state.
It is advised that changes to these bits be made while the power-down (PDN) bit is enabled to eliminate
the possibility of audible artifacts.
DS617F2
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CS4362A
6.1.5
Power Down (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be
disabled before normal operation in Control Port Mode can occur.
6.2
Mode Control 2 (Address 02h)
7
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
Reserved
0
2
Reserved
0
1
Reserved
0
0
Reserved
0
Reserved
0
6.2.1
Digital Interface Format (DIF)
Default = 000 - Format 0 (Left-Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The Functional Mode bits determine
whether PCM or DSD Mode is selected.
PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined
by the Digital Interface Format and the options are detailed in Figures 7-12.
Note: While in PCM Mode, the DIF bits should only be changed when the power-down (PDN) bit is set
to ensure proper switching from one mode to another.
DIF2
DIF1
DIF0
DESCRIPTION
Left-Justified, up to 24-bit data
Format
FIGURE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
-
7
8
9
10
11
12
I²S, up to 24-bit data
Right-Justified, 16-bit data
Right-Justified, 24-bit data
Right-Justified, 20-bit data
Right-Justified, 18-bit data
Reserved
Reserved
-
Table 5. Digital Interface Formats - PCM Mode
34
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CS4362A
DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required
master clock-to-DSD-data-rate is defined by the Digital Interface Format pins.
DIF2
DIF1
DIFO
DESCRIPTION
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 6. Digital Interface Formats - DSD Mode
6.3
Mode Control 3 (Address 03h)
7
SZC1
1
6
SZC0
0
5
SNGLVOL
0
4
RMP_UP
0
3
MUTEC+/-
0
2
AMUTE
1
1
MUTEC1
0
0
MUTEC0
0
6.3.1
Soft Ramp and Zero Cross Control (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected, all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel.
Soft Ramp
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or
muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change
will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz
sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently
monitored and implemented for each channel.
DS617F2
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CS4362A
6.3.2
Single Volume Control (SNGLVOL)
Default = 0
0 - Disabled
1 - Enabled
Function:
The individual channel volume levels are independently controlled by their respective Volume Control
Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel Volume
Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.
6.3.3
Soft Volume Ramp-Up After Error (RMP_UP)
Default = 0
0 - Disabled
1 - Enabled
Function:
An un-mute will be performed after a LRCK/MCLK ratio change or error, and after changing the Functional
Mode. When this feature is enabled, this un-mute is affected, similar to attenuation changes, by the Soft
and Zero Cross bits in the Mode Control 3 register. When disabled, an immediate un-mute is performed
in these instances.
Notes: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
6.3.4
Mutec Polarity (MUTEC+/-)
Default = 0
0 - Active High
1 - Active Low
Function:
The active polarity of the MUTEC pin(s) is determined by this register. When set to 0 (default), the MUTEC
pins are high when active. When set to 1 the MUTEC pin(s) are low when active.
Note: During reset the MUTEC output pins are high impedance and the external mute circuitry will need
to be self biased into an active state, see Section 4.11. Once reset has been released, the MUTEC out-
puts’ active polarity will be set by this bit.
6.3.5
Auto-Mute (AMUTE)
Default = 1
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio sam-
ples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is
done independently for each channel. The quiescent voltage on the output will be retained, and the Mute
Control pin will go active during the mute period. The muting function is affected, similar to volume control
changes, by the Soft and Zero Cross bits in the Mode Control 3 register.
36
DS617F2
CS4362A
6.3.6
Mute Pin Control (MUTEC1, MUTEC0)
Default = 00
00 - Six mute control signals
01, 10 - One mute control signal
11 - Three mute control signals
Function:
Selects how the internal mute control signals are routed to the MUTEC1 through MUTEC6 pins. When
set to ‘00’, there is one mute control signal for each channel: AOUT1A on MUTEC1, AOUT1B on
MUTEC2, etc. When set to ‘01’ or ‘10’, there is a single mute control signal on the MUTEC1 pin. When
set to ‘11’, there are three mute control signals, one for each stereo pair: AOUT1A and AOUT1B on
MUTEC1, AOUT2A and AOUT2B on MUTEC2, and AOUT3A and AOUT3B on MUTEC3.
6.4
Filter Control (Address 04h)
7
6
Reserved
0
5
Reserved
0
4
FILT_SEL
0
3
Reserved
0
2
DEM1
0
1
DEM0
0
0
RMP_DN
0
Reserved
0
6.4.1
Interpolation Filter Select (FILT_SEL)
Default = 0
0 - Fast roll-off
1 - Slow roll-off
Function:
This function allows the user to select whether the interpolation filter has a fast or slow roll off. For filter
characteristics, please see Section 2.
6.4.2
De-Emphasis Control (DEM)
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re-
sponse at 32, 44.1 or 48 kHz sample rates. (see Figure 13)
De-emphasis is only available in Single-Speed Mode.
6.4.3
Soft Ramp-Down Before Filter Mode Change (RMP_DN)
Default = 0
0 - Disabled
1 - Enabled
Function:
If either the FILT_SEL or DEM bits are changed, the DAC will stop conversion for a period of time to
change filter values. This bit selects how the data is effected prior to and after the change of the filter val-
DS617F2
37
CS4362A
ues. When this bit is enabled, the DAC will ramp down the volume prior to a filter-mode change and ramp
from mute to the original volume value after a filter-mode change according to the settings of the Soft and
Zero Cross bits in the Mode Control 3 register. When disabled, an immediate mute and unmute is per-
formed.
Loss of clocks or a change in the FM bits will always cause an immediate mute; unmute in these condi-
tions is affected by the RMP_UP bit.
Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
6.5
Invert Control (Address 05h)
7
6
Reserved
0
5
INV_B3
0
4
INV_A3
0
3
INV_B2
0
2
INV_A2
0
1
INV_B1
0
0
INV_A1
0
Reserved
0
6.5.1
Invert Signal Polarity (Inv_Xx)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
6.6
Mixing Control Pair 1 (Channels A1 & B1)(Address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(Address 09h)
Mixing Control Pair 3 (Channels A3 & B3)(Address 0Ch)
7
6
PxATAPI4
0
5
PxATAPI3
1
4
PxATAPI2
0
3
PxATAPI1
0
2
PxATAPI0
1
1
PxFM1
0
0
PxFM0
0
Px_A=B
0
6.6.1
Channel A Volume = Channel B Volume (A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Vol-
ume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are deter-
mined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes
are ignored when this function is enabled.
38
DS617F2
CS4362A
6.6.2
ATAPI Channel Mixing and Muting (ATAPI)
Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo)
Function:
The CS4362A implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI
functions are applied per A-B pair. Refer to Table 7 and Figure 14 for additional information.
ATAPI4
ATAPI3
ATAPI2
ATAPI1
ATAPI0
AOUTAx
MUTE
MUTE
MUTE
MUTE
aR
AOUTBx
MUTE
bR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
bL
b[(L+R)/2]
MUTE
bR
aR
aR
aR
aL
aL
aL
aL
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
MUTE
MUTE
MUTE
MUTE
aR
bL
b[(L+R)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
aR
aR
aR
aL
aL
aL
aL
bL
[(bL+aR)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
[(aL+bR)/2]
[(aL+bR)/2]
[(bL+aR)/2]
[(aL+bR)/2]
bL
[(aL+bR)/2]
Table 7. ATAPI Decode
DS617F2
39
CS4362A
6.6.3
Functional Mode (FM)
Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
11 - Direct Stream Digital Mode
Function:
Selects the required range of input sample rates or DSD Mode. All DAC pairs are required to be set to the
same functional mode setting before a speed-mode change is accepted. When DSD Mode is selected for
any channel pair, all pairs switch to DSD Mode.
6.7
Volume Control (Addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh)
7
6
xx_VOL6
0
5
xx_VOL5
0
4
xx_VOL4
0
3
xx_VOL3
0
2
xx_VOL2
0
1
xx_VOL1
0
0
xx_VOL0
0
xx_MUTE
0
Note: These six registers provide individual volume and mute control for each of the six channels.
The values for “xx” in the bit fields above are as follows:
Register address 07h - xx = A1
Register address 08h - xx = B1
Register address 0Ah - xx = A2
Register address 0Bh - xx = B2
Register address 0Dh - xx = A3
Register address 0Eh - xx = B3
6.7.1
Mute (MUTE)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will
be retained. The muting function is affected, similarly to attenuation changes, by the Soft and Zero Cross
bits. The MUTE pins will go active during the mute period according to the MUTEC bits.
40
DS617F2
CS4362A
6.7.2
Volume Control (XX_VOL)
Default = 0 (No attenuation)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments
from 0 to -127 dB. Volume settings are decoded as shown in Table 8. The volume changes are imple-
mented as dictated by the Soft and Zero Cross bits. All volume settings less than -127 dB are equivalent
to enabling the MUTE bit.
Binary Code
0 0 0 0 0 0 0
0 0 1 0 1 0 0
0 1 0 1 0 0 0
0 1 1 1 1 0 0
1 0 1 1 0 1 0
Decimal Value
Volume Setting
0 dB
0
20
40
60
90
-20 dB
-40 dB
-60 dB
-90 dB
Table 8. Example Digital Volume Settings
6.8
Chip Revision (Address 12h)
7
6
PART3
1
5
PART2
0
4
PART1
1
3
PART0
0
2
REV2
-
1
REV1
-
0
REV0
-
PART4
0
6.8.1
Part Number ID (PART) [Read Only]
01010 - CS4362A
6.8.2
Revision ID (REV) [Read Only]
000 - Revision A
001 - Revision B
Function:
This read-only register can be used to identify the model and revision number of the device.
DS617F2
41
CS4362A
7. FILTER PLOTS
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−100
−120
−120
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 20. Single-Speed (fast) Stopband Rejection
Figure 21. Single-Speed (fast) Transition Band
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.02
0.015
0.01
0.005
0
−0.005
−0.01
−0.015
−0.02
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 22. Single-Speed (fast) Transition Band (detail)
Figure 23. Single-Speed (fast) Passband Ripple
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0.4
0.5
0.6
0.7
0.8
0.9
1
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 24. Single-Speed (slow) Stopband Rejection
Figure 25. Single-Speed (slow) Transition Band
42
DS617F2
CS4362A
0.02
0.015
0.01
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.005
0
−0.005
−0.01
−0.015
−0.02
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 26. Single-Speed (slow) Transition Band (detail)
Figure 27. Single-Speed (slow) Passband Ripple
0
0
20
20
40
40
60
60
80
80
100
120
100
120
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 28. Double-Speed (fast) Stopband Rejection
Figure 29. Double-Speed (fast) Transition Band
0
1
0.02
0.015
0.01
2
3
0.005
0
4
5
6
0.005
0.01
7
8
0.015
0.02
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 30. Double-Speed (fast) Transition Band (detail)
Figure 31. Double-Speed (fast) Passband Ripple
DS617F2
43
CS4362A
0
0
20
40
20
40
60
60
80
80
100
120
100
120
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 32. Double-Speed (slow) Stopband Rejection
Figure 33. Double-Speed (slow) Transition Band
0
1
0.02
0.015
0.01
2
3
0.005
0
4
5
6
0.005
0.01
7
8
0.015
0.02
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 34. Double-Speed (slow) Transition Band (detail)
Figure 35. Double-Speed (slow) Passband Ripple
0
0
20
20
40
40
60
60
80
80
100
120
100
120
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 36. Quad-Speed (fast) Stopband Rejection
Figure 37. Quad-Speed (fast) Transition Band
44
DS617F2
CS4362A
0
0.2
0.15
0.1
1
2
3
0.05
0
4
5
6
0.05
7
0.1
0.15
0.2
8
9
10
0
0.05
0.1
0.15
0.2
0.25
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 38. Quad-Speed (fast) Transition Band (detail)
Figure 39. Quad-Speed (fast) Passband Ripple
0
0
20
40
20
40
60
60
80
80
100
120
100
120
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 40. Quad-Speed (slow) Stopband Rejection
Figure 41. Quad-Speed (slow) Transition Band
0
1
0.02
0.015
0.01
0.005
0
2
3
4
5
6
0.005
0.01
0.015
0.02
7
8
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.02
0.04
0.06
0.08
0.1
0.12
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 42. Quad-Speed (slow) Transition Band (detail)
Figure 43. Quad-Speed (slow) Passband Ripple
DS617F2
45
CS4362A
8. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measure-
ment to full scale. This technique ensures that the distortion components are below the noise level and
do not affect the measurement. This measurement technique has been accepted by the Audio Engineer-
ing Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
46
DS617F2
CS4362A
9. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E
E1
D1
D
1
e
B
∝
A
A1
L
INCHES
MILLIMETERS
DIM
A
A1
B
D
D1
E
E1
e*
L
MIN
---
NOM
0.055
0.004
0.009
0.354
0.28
0.354
0.28
0.020
0.24
MAX
MIN
---
NOM
1.40
0.10
MAX
1.60
0.15
0.27
9.30
7.10
9.30
7.10
0.60
0.75
7.00°
0.063
0.006
0.011
0.366
0.280
0.366
0.280
0.024
0.030
7.000°
0.002
0.007
0.343
0.272
0.343
0.272
0.016
0.018
0.000°
0.05
0.17
8.70
6.90
8.70
6.90
0.40
0.45
0.00°
0.22
9.0 BSC
7.0 BSC
9.0 BSC
7.0 BSC
0.50 BSC
0.60
µ
4°
4°
* Nominal pin pitch is 0.50 mm
Controlling dimension is mm.
JEDEC Designation: MS022
DS617F2
47
CS4362A
10.ORDERING INFORMATION
Product
Description
Package Pb-Free
Grade
Temp Range Container
Order #
CS4362A-CQZ
Tray
Commercial -40°C to +85°C
Tape & Reel CS4362A-CQZR
114 dB, 192 kHz 6-
channel D/A Converter
48-pin
YES
CS4362A
LQFP
Tray
Tape & Reel CS4362A-DQZR
CDB4362A
CS4362A-DQZ
Automotive -40°C to +105°C
CDB4362A CS4362A Evaluation Board
-
-
-
-
11.REFERENCES
1. How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters, by Steven Harris. Paper
presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2. CDB4362A data sheet, available at http://www.cirrus.com.
3. Design Notes for a 2-Pole Filter with Differential Input, by Steven Green. Cirrus Logic Application Note
AN48.
4. The I²C Bus Specification: Version 2.0, Philips Semiconductors, December 1998
http://www.semiconductors.philips.com.
48
DS617F2
CS4362A
12.REVISION HISTORY
Release
Changes
Updated output impedance spec in “DAC Analog Characteristics - Automotive (-DQZ)” on page 10.
Improved interchannel isolation spec in “DAC Analog Characteristics - Automotive (-DQZ)” on page 10.
Corrected package type.
PP1
PP2
Corrected register description in “DAC Pair Disable (DACx_DIS)” on page 33.
Added note to “Digital Interface Format (DIF)” on page 34.
Added PCM mode format changeable in reset only to “Mode Select” on page 21.
Updated ambient operating temperature range for Commercial and Automotive grade.
Updated “DAC Analog Characteristics - Commercial (-CQZ)” on page 9.
Updated “DAC Analog Characteristics - Automotive (-DQZ)” on page 10.
Updated “Power and Thermal Characteristics” on page 11.
F1
F2
Updated “Digital Characteristics” on page 14.
Updated Legal Information under “IMPORTANT NOTICE” on page 50
Updated MUTEC pin description in “Pin Description” on page 6.
Updated “Mute Control” on page 27.
Updated “Mutec Polarity (MUTEC+/-)” on page 36.
DS617F2
49
CS4362A
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-
sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT-
ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIR-
RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM-
ER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY
INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT-
TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
Direct Stream Digital is a registered trademark of Sony Kabushiki Kaisha TA Sony Corporation.
DSD is a trademark of Sony Kabushiki Kaisha TA Sony Corporation
50
DS617F2
相关型号：
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