CS4373A_技术文档

CS4373A

Low-power, High-performance ∆Σ Test DAC

Features

Description

The CS4373A is a high-performance, differential output

digital-to-analog converter (DAC) with programmable at-

tenuation and multiple operational modes. AC test

modes measure system dynamic performance through

THD and CMRR tests while DC test modes are for gain

calibration and pulse tests.

z Digital ∆Σ Input from CS5376A Digital Filter

z Selectable Differential Analog Outputs

• Precision output (OUT±) for electronics tests

• Buffered output (BUF±) for sensor tests

z Multiple AC and DC Operational Modes

• Signal bandwidth: DC to 100 Hz

• Max AC amplitude: 5 V_PPdifferential

• Max DC amplitude: + 2.5 V_dcdifferential

z Selectable Attenuation for CS3301A / CS3302A

• 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64

The CS4373A is driven by a ∆Σ digital bit stream from the

CS5376A digital filter test bit stream (TBS) generator. It

has two sets of differential analog outputs, OUT and

BUF, to simplify system design as dedicated outputs for

testing the electronics channel and for in-circuit sensor

tests. Analog output attenuation is selected by simple pin

settings

and

matches

the

gain

of

the

z Outstanding Performance

CS3301A / CS3302A differential amplifiers for full-scale

testing at all gain ranges.

• AC (OUT): -116 dB THD typical, -112 dB max

• AC (BUF): -108 dB THD typical, -90 dB max

• DC absolute accuracy: 0.4% typical, 1% max

z Low Power Consumption

The CS4373A test DAC provides self-test and precision

calibration capability for high-resolution, low-frequency

multi-channel measurement systems designed from

• AC modes / DC modes: 40 mW / 20 mW

• Sleep mode / Power Down: 1 mW / 10 µW

z Extremely Small Footprint

CS3301A / CS3302A

CS5371A / CS5372A ∆Σ modulators and the CS5376A

digital filter.

differential

amplifiers,

• 28-pin SSOP package, 8 mm x 10 mm

z Bipolar Power Supply Configuration

• VA+ = +2.5 V;VA- = -2.5 V;VD = +3.3 V

ORDERING INFORMATION

See page 34.

VA+

MODE(0, 1, 2)

ATT(0, 1, 2)

Attenuator

VD

TDATA

OUT+

OUT-

BUF+

BUF-

24-Bit ∆Σ

DAC

VREF+

VREF-

MCLK

Clock

Generator

MSYNC

VA-

CAP+ CAP-

GND

DEC ‘06

DS699F2

http://www.cirrus.com

CS4373A

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4

2. GENERAL DESCRIPTION ..................................................................................................... 16

2.1 Digital Inputs .................................................................................................................... 16

2.2 Analog Outputs ................................................................................................................ 16

2.3 Multiple Operational Modes ............................................................................................. 16

2.4 Low Power ....................................................................................................................... 16

3. SYSTEM DIAGRAMS .......................................................................................................... 17

4. POWER MODES ..................................................................................................................... 18

4.1 Power Down ..................................................................................................................... 18

4.2 Sleep Modes .................................................................................................................... 18

4.3 AC Test Modes ................................................................................................................ 18

4.4 DC Test Modes ................................................................................................................ 18

5. OPERATIONAL MODES ........................................................................................................ 19

5.1 Sleep Modes .................................................................................................................... 19

5.2 AC Test Modes ................................................................................................................ 19

5.2.1 AC Differential ..................................................................................................... 19

5.2.2 AC Common Mode .............................................................................................. 20

5.2.3 AC Stability .......................................................................................................... 20

5.3 DC Test Modes ................................................................................................................ 20

5.3.1 DC Common Mode ............................................................................................. 20

5.3.2 DC Differential ..................................................................................................... 20

6. DIGITAL INPUTS .................................................................................................................... 22

6.1 TDATA Connection .......................................................................................................... 22

6.2 MCLK Connection ............................................................................................................ 22

6.3 MSYNC Connection ......................................................................................................... 22

6.4 GPIO Connections ........................................................................................................... 23

7. ANALOG OUTPUTS ............................................................................................................... 24

7.1 Differential Signals ........................................................................................................... 24

7.2 Analog Output Attenuation ............................................................................................... 24

7.3 OUT± Precision Output .................................................................................................... 25

7.4 BUF± Buffered Output ..................................................................................................... 25

7.5 CAP± Analog Output ........................................................................................................ 25

8. VOLTAGE REFERENCE ........................................................................................................ 26

8.1 VREF Power Supply ........................................................................................................ 26

8.2 VREF RC Filter ................................................................................................................ 26

8.3 VREF PCB Routing .......................................................................................................... 26

8.4 VREF Input Impedance .................................................................................................... 27

8.5 VREF Accuracy ................................................................................................................ 27

8.6 VREF Independence ....................................................................................................... 27

9. POWER SUPPLIES ................................................................................................................ 28

9.1 Power Supply Bypassing ................................................................................................. 28

9.2 PCB Layers and Routing ................................................................................................. 28

9.3 Power Supply Rejection ................................................................................................... 28

9.4 SCR Latch-up .................................................................................................................. 29

9.5 DC-DC Converters .......................................................................................................... 29

10. TERMINOLOGY .................................................................................................................... 30

11. PIN DESCRIPTION ............................................................................................................... 31

12. PACKAGE DIMENSIONS ..................................................................................................... 33

13. ORDERING INFORMATION ................................................................................................ 34

14. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .......................... 34

15. REVISION HISTORY ........................................................................................................... 34

2

DS699F2

CS4373A

LIST OF FIGURES

Figure 1. Digital Input Rise and Fall Times ................................................................................... 12

Figure 2. System Timing Diagram................................................................................................. 14

Figure 3. MCLK / MSYNC Timing Detail....................................................................................... 14

Figure 4. CS4373A Block Diagram ............................................................................................... 16

Figure 6. Connection Diagram ...................................................................................................... 17

Figure 5. System Diagram ............................................................................................................ 17

Figure 7. Power Mode Diagram .................................................................................................... 18

Figure 8. AC Differential Modes.................................................................................................... 19

Figure 9. AC Common Mode ........................................................................................................ 20

Figure 10. DC Test Modes............................................................................................................ 21

Figure 11. Digital Inputs ................................................................................................................ 22

Figure 12. Analog Outputs ............................................................................................................ 24

Figure 13. Voltage Reference Circuit............................................................................................ 26

Figure 14. Power Supply Diagram ................................................................................................ 28

LIST OF TABLES

Table 1. Selections for Operational Mode and Attenuation............................................................. 4

Table 2. Operational Modes.......................................................................................................... 19

Table 3. Output Attenuation Settings ............................................................................................ 24

DS699F2

3

CS4373A

1. CHARACTERISTICS AND SPECIFICATIONS

•

Min / Max characteristics and specifications are guaranteed over the Specified Operating Conditions.

Typical performance characteristics and specifications are measured at nominal supply voltages and T = 25°C.

GND = 0 V. Single-ended voltages with respect to GND, differential voltages with respect to opposite half.

Device is connected as shown in Figure 6 on page 17, unless otherwise noted.

A

SPECIFIED OPERATING CONDITIONS

Parameter

Symbol

Min

Nom

Max

Unit

Bipolar Power Supplies

Positive Analog

± 2%

(Note 1) ± 2%

± 3%

VA+

VA-

VD

2.45

-2.45

3.20

2.50

-2.50

3.30

2.55

-2.55

3.40

V

Negative Analog

Positive Digital

Voltage Reference Input

{VREF+} - {VREF-}

VREF-

(Note 2, 3)

VREF

-

2.500

VA -

-

V

(Note 4) VREF-

Thermal

Ambient Operating Temperature

Industrial (-IS, -ISZ)

T

-40

25

85

°C

A

Notes: 1. VA- must always be the most-negative input voltage to avoid potential SCR latch-up conditions.

2. By design, a 2.500 V voltage reference input results in the best signal-to-noise performance.

3. Full-scale accuracy is directly proportional to the voltage reference absolute accuracy.

4. VREF inputs must satisfy: VA- < VREF- < VREF+ < VA+.

Modes of Operation

Selection MODE[2:0] Mode Description

Sleep mode.

Attenuation

Selection ATT[2:0] Attenuation

dB

0 dB

0

1

2

3

4

5

6

7

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0

1

2

3

4

5

6

7

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1/1

1/2

AC OUT and BUF outputs.

AC OUT only, BUF high-z.

AC BUF only, OUT high-z.

DC common mode output.

DC differential output.

AC common mode output.

Sleep mode.

-6.02 dB

1/4

-12.04 dB

-18.06 dB

-24.08 dB

-30.10 dB

-36.12 dB

reserved

1/8

1/16

1/32

1/64

reserved

Table 1. Selections for Operational Mode and Attenuation

4

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CS4373A

TEMPERATURE CONDITIONS

Parameter

Ambient Operating Temperature

Symbol

Min

-40

-65

-

Typ

Max

+85

150

125

-

Unit

ºC

T

-

A

Storage Temperature Range

T

ºC

STG

Allowable Junction Temperature

T

-

ºC

JCT

-

Junction to Ambient Thermal Impedance (4-layer PCB)

Θ

65

ºC / W

JA

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Min

Max

Parameter

DC Power Supplies

Positive Analog

Negative Analog

Digital

VA+

VA-

VD

-0.5

-6.8

-0.5

6.8

0.5

6.8

V

Analog Supply Differential

Digital Supply Differential

Input Current, Power Supplies

Input Current, Any Pin Except Supplies

Output Current

(VA+) - (VA-)

(VD) - (VA-)

(Note 5)

VA

-

6.8

7.6

V

DIFF

IN

VD

-

I

-

±50

±10

±25

500

mA

mW

V

(Note 5)

-

IN

(Note 5)

I

-

OUT

Power Dissipation

PDN

-

Analog Input Voltages

V

(VA-) - 0.5

-0.5

(VA+) + 0.5

(VD) + 0.5

INA

IND

Digital Input Voltages

V

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Notes: 5. Transient currents up to ±100 mA will not cause SCR latch-up.

DS699F2

5

CS4373A

ANALOG CHARACTERISTICS

Parameter

VREF Input

Symbol

Min

Typ

Max

Unit

{VREF+} - {VREF-}

(Note 2, 3)

(Note 4)

VREF

-

2.500

VA -

80

-

V

VREF-

VREF Input Current, AC modes

VREF Input Current, DC modes

VREF Input Noise

VREF

-

µA

IAC

IDC

40

-

(Note 6) VREF

-

1

µV

rms

IN

Analog OUT± Output

R

C

50

-

50

MΩ

pF

Analog External Load at OUT±

(Note 7, 8)

Load Resistance

Load Capacitance

LOUT

Differential Output Impedance

1/1 ZDIF

-

1.4

10.1

7.9

5.1

3.3

2.3

1.7

-

kΩ

OUT

1/2

1/4

1/8

1/16

1/32

1/64

Single-ended Output Impedance

1/1 ZSE

1/2

1/4

-

0.7

7.4

9.0

9.4

9.5

9.4

-

kΩ

OUT

1/8

1/16

1/32

1/64

High-Z Impedance

(Note 8)

HZ

XT

-

3

-

MΩ

dB

OUT

-120

Crosstalk to BUF± High-Z Output

Analog BUF± Output

OUT

R

1

-

2

kΩ

nF

Analog External Load at BUF±

(Note 8)

Load Resistance

Load Capacitance

LBUF

C

Differential Output Impedance

Single-ended Output Impedance

1/1 - 1/64 ZDIF

1/1 - 1/32 ZSE

(Note 9) (BUF-) 1/64

(Note 9) (BUF+) 1/64

-

6

-

Ω

BUF

-

3

50

-

BUF

High-Z Impedance

(Note 8)

HZ

XT

-

4.5

-

MΩ

dB

BUF

-120

Crosstalk to OUT± High-Z Output

BUF

Notes: 6. Maximum integrated noise over the measurement bandwidth for the voltage reference device attached

to the VREF± inputs.

7. Load on the precision OUT± outputs is normally from the CS3301A / CS3302A amplifiers, which have

1 GΩ/1 TΩ typical input impedance and 18 pF typical input capacitance.

8. Guaranteed by design and/or characterization.

9. Single-ended output impedance at 1/64 is different for BUF+ and BUF- due to the output attenuator

architecture.

6

DS699F2

CS4373A

AC DIFFERENTIAL MODES 1, 2, 3

Parameter

AC Differential Characteristics

Full-scale Differential AC Output

Symbol

Min

Typ

Max

Unit

1/1

1/2

1/4

VAC

-

5

2.5

1.25

625

312.5

156.25

78.125

-

V

FS

pp

1/8

mV

pp

1/16

1/32

1/64

Full-scale Bandwidth

Impulse Amplitude

(Note 8) VAC

-

100

-20

Hz

BW

(Note 8, 10) VAC

dBfs

IMP

AC Differential Accuracy

Full-scale Accuracy

(Note 3, 11)

1/1 VAC

1/2 VAC

1/4

1/8

1/16

1/32

1/64

- 0.5

- 0.2

0.2

%FS

ABS

- 0.2

± 0.1

- 0.1 ± 0.2

- 0.2 ± 0.3

- 0.5 ± 0.5

0.2

%

Relative Accuracy

(Note 12)

REL

-

Full-scale Drift

(Note 14)

VAC

-

25

-

µV/°C

TC

DC Common Mode Characteristics

Common Mode

(Note 13) VAC

-

(VA-)+2.35

-

V

CM

Common Mode Drift

(Note 13, 14) VAC

300

µV/°C

CMTC

Notes: 10. Maximum amplitude for operation above 100 Hz. A reduced amplitude for higher frequencies is required

to guarantee stability of the low-power delta-sigma architecture.

11. Full-scale accuracy compares the defined full-scale 1/1 amplitude to the measured 1/1 amplitude.

Specification is for unloaded outputs. Applying a differential load lowers the output amplitude ratiometric

to the differential output impedance.

12. Relative accuracy compares the measured 1/2,1/4,1/8,1/16,1/32,1/64 amplitude to the measured 1/1

amplitude.

13. Common mode voltage is defined as [(SIG+) + (SIG-)] / 2.

14. Specification is for the parameter over the specified temperature range and is for the device only. It does

not include the effects of external components.

DS699F2

7

CS4373A

AC DIFFERENTIAL MODES 1, 2, 3 (CONT.)

Parameter

Symbol

Min

Typ

Max

Unit

Signal to Noise

(OUT± Unloaded)

(Note 15)

1/1 -> 1x SNR

1/2 -> 2x

1/4 -> 4x

-

114

113

111

108

103

-

dB

OUT

1/8 -> 8x

1/16 -> 16x

1/32 -> 32x

1/64 -> 64x

Signal to Noise

(BUF± Unloaded, 1 kΩ Load)

(Note 15, 16)

1/1 -> 1x SNR

1/2 -> 2x

1/4 -> 4x

-

110

106

101

95

89

83

-

dB

BUF

1/8 -> 8x

1/16 -> 16x

1/32 -> 32x

1/64 -> 64x

77

Total Harmonic Distortion

(OUT± Unloaded)

(Note 17, 18)

1/1 -> 1x THD

1/2 -> 2x

1/4 -> 4x

-

- 116

- 115

- 114

- 112

- 111

- 110

- 106

- 112

dB

OUT

-

1/8 -> 8x

1/16 -> 16x

1/32 -> 32x

1/64 -> 64x

Total Harmonic Distortion

(BUF± Unloaded)

(Note 16, 17, 18)

1/1 -> 1x THD

1/2 -> 2x

1/4 -> 4x

-

- 108

- 105

- 100

- 94

- 88

- 82

- 90

dB

BUF

-

1/8 -> 8x

1/16 -> 16x

1/32 -> 32x

1/64 -> 64x

- 76

Total Harmonic Distortion

(BUF± 1 kΩ Load)

(Note 16, 17, 18)

1/1 -> 1x THD

1/2 -> 2x

1/4 -> 4x

-

- 102

- 101

- 97

- 92

- 87

- 82

- 76

- 80

dB

BUFL

-

1/8 -> 8x

1/16 -> 16x

1/32 -> 32x

1/64 -> 64x

Notes: 15. Specification measured using CS3301A amplifier at corresponding gain with the CS5371A / CS5372A

modulator measuring a 430 Hz bandwidth. Amplified noise dominates for x16, x32, x64 amplifier gains.

16. Buffered outputs (BUF±) include 1/f noise not present on the precision outputs (OUT±).

17. Tested with a 31.25 Hz sine wave at -1 dB amplitude.

18. Specification measured using CS3301A amplifier at corresponding gain using the CS5371A / CS5372A

modulator measuring a 430 Hz bandwidth. Amplified noise in the harmonic bins dominates THD

measurements for x16, x32, x64 amplifier gains.

8

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CS4373A

DC COMMON MODE 4

Parameter

DC Common Mode Characteristics

Common Mode Output

Common Mode Drift

Symbol

VDC

Min

Typ

Max

Unit

-

(VA-)+2.35

-

V

CM

(Note 14) VDC

300

µV/°C

CMTC

DC Common Mode Accuracy

Common Mode Match

1/1 VDC

- 5

± 1

5

mV

CMM

Noise

N

-

6

7

-

µV

Noise (OUT± Unloaded)

(Note 15)

1/1 -> 1x

1/2 -> 2x

1/4 -> 4x

1/8 -> 8x

1/16 -> 16x

1/32 -> 32x

1/64 -> 64x

OUT

rms

µV

rms

µV

rms

µV

rms

µV

rms

µV

9

14

rms

µV

rms

N

-

7

10

17

33

64

130

257

-

µV

Noise (BUF± Unloaded, 1 kΩ Load)

(Note 15, 16)

1/1 -> 1x

1/2 -> 2x

1/4 -> 4x

1/8 -> 8x

1/16 -> 16x

1/32 -> 32x

1/64 -> 64x

BUF

rms

µV

rms

µV

rms

µV

rms

µV

rms

µV

rms

µV

rms

DS699F2

9

CS4373A

DC DIFFERENTIAL MODE 5

Parameter

Symbol

Min

Typ

Max

Unit

DC Differential Mode Characteristics

Full-scale Differential DC Output

(Note 19)

1/1

1/2

1/4

VDC

-

2.5

1.25

625

312.5

156.25

78.125

39.0625

-

V

FS

mV

1/8

1/16

1/32

1/64

DC Differential Accuracy

Full-scale Accuracy

(Note 3, 11)

1/1 VDC

1/2 VDC

1/4

1/8

1/16

1/32

1/64

- 1.0

- 0.4

0.2

%FS

ABS

- 0.2

± 0.1

-0.1 ± 0.4

-0.2 ± 0.9

-0.5 ± 1.7

-1.0 ± 3.6

0.2

%

Relative Accuracy

(Note 12)

REL

-

Full-scale Drift

(Note 14) VDC

-

25

-

µV/°C

TC

DC Common Mode Characteristics

Common Mode

(Note 13) VDC

-

(VA-)+2.35

-

V

CM

Common Mode Drift

Noise

(Note 13, 14) VDC

300

µV/°C

CMTC

N

-

9

-

µV

Noise (OUT± Unloaded)

(Note 15, 19)

1/1 -> 1x

1/2 -> 2x

1/4 -> 4x

1/8 -> 8x

1/16 -> 16x

1/32 -> 32x

1/64 -> 64x

OUT

rms

µV

rms

µV

rms

µV

9

rms

10

11

15

µV

rms

µV

rms

µV

rms

N

-

10

12

18

32

67

-

µV

Noise (BUF± Unloaded, 1 kΩ Load)

(Note 15, 16, 19)

1/1 -> 1x

1/2 -> 2x

1/4 -> 4x

1/8 -> 8x

1/16 -> 16x

1/32 -> 32x

1/64 -> 64x

BUF

rms

µV

rms

µV

rms

µV

rms

µV

rms

µV

122

265

rms

µV

rms

Notes: 19. DC differential output is chopper stabilized and includes low-level 32 kHz out-of-band noise which is

rejected by the digital filter during acquisition.

10

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CS4373A

AC COMMON MODE 6

Parameter

Symbol

Min

Typ

Max

Unit

AC Common Mode Characteristics

Full-scale Common Mode AC Output

(Note 20)

1/1 VCM

1/2

1/4

1/8

1/16

1/32

-

2.5

1.25

625

312.5

156.25

78.125

-

V

mV

FS

pp

Full-scale Bandwidth

(Note 8) VCM

-

100

-20

Hz

BW

Impulse Amplitude

(Note 8, 10) VCM

dBfs

IMP

AC Common Mode Accuracy

VCM

-

-115

-95

-105

-85

-

dB

Common Mode Match (OUT± Unloaded)

(Note 17, 20)

CMM

VCM

Common Mode Match (BUF± Unloaded, 1 kΩ Load)

(Note 16, 17, 20)

Full-scale Accuracy

(Note 3, 11)

1/1 VAC

- 0.3

%FS

ABS

REL

Relative Accuracy

(Note 12, 20)

1/2 VAC

1/4

-

- 0.1

- 0.5

- 1.0

-2.0

-5.0

-

%

1/8

1/16

1/32

(Note 14) VCM

Full-scale Drift

-

25

-

µV/°C

TC

DC Common Mode Characteristics

Common Mode Mean

(Note 21) VCM

-

(VA-)+2.35

-

V

CM

Common Mode Mean Drift

(Note 14, 21) VCM

300

µV/°C

CMTC

Notes: 20. No AC common mode signal is output at 1/64 attenuation due to the attenuator architecture.

21. Common mode mean is defined as [(SIG ) + (SIG )] / 2.

max

min

DS699F2

11

CS4373A

DIGITAL CHARACTERISTICS

Parameter

Digital Inputs

Symbol

Min

Typ

Max

Unit

High-level Input Drive Voltage

Low-level Input Drive Voltage

Input Leakage Current

(Note 22)

V

0.6*VD

-

VD

0.8

+10

-

V

IH

V

I

0.0

IL

-

+1

9

-

µA

pF

ns

IN

Digital Input Capacitance

Rise Times Except MCLK

Fall Times Except MCLK

TDATA Input

(Note 8)

C

IN

t

100

RISE

FALL

-

TDATA Input Bit Rate

(Note 23)

(Note 8)

f

-

25

-

256

-

75

-

kbits/s

%

tdata

TDATA Input One’s Density Range

TBSGAIN Full-scale Code

TBSGAIN -20 dB Code

INR

-

OD

0x04B8F2

(Note 24)

TBS

FS

0x0078E5

(Note 24) TBS

-

-20dB

Notes: 22. Device is intended to be driven with CMOS logic levels.

23. TDATA is generated by the test bit stream generator in the CS5376A digital filter.

24. TBSGAIN register value in the CS5376A digital filter.

t

fall

rise

0.9 * VD

0.1 * VD

Figure 1. Digital Input Rise and Fall Times

12

DS699F2

CS4373A

DIGITAL CHARACTERISTICS (CONT.)

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock

MCLK Frequency

(Note 25)

f

-

2.048

-

MHz

ns

CLK

MCLK Period

t

488

mclk

MCLK Duty Cycle

(Note 8) MCLK

40

-

60

50

300

1

%

DC

RISE

FALL

MCLK Rise Time

(Note 8)

t

ns

MCLK Fall Time

-

ns

MCLK Jitter (In-band or aliased in-band)

MCLK Jitter (Out-of-band)

Master Sync

(Note 8) MCLK

-

ps

IBJ

(Note 8) MCLK

-

ns

OBJ

MSYNC Setup Time to MCLK rising

MSYNC Period

(Note 8, 26)

(Note 8, 27)

t

20

40

20

-

122

976

-

ns

mss

t

msync

MSYNC Hold Time after MCLK falling

MSYNC Instant to TDATA Start

t

122

msh

t

1220

tdata

Notes: 25. MCLK is generated by the CS5376A digital filter. If MCLK is disabled, the device automatically enters

a power-down state.

26. MSYNC is generated by the CS5376A digital filter and is latched on MCLK rising edge, synchronization

instant (t ) on next MCLK rising edge.

0

27. TDATA can be delayed from 0 to 63 full bit periods by the CS5376A test bit stream generator. The timing

diagram shows no TBSDATA delay.

DS699F2

13

CS4373A

DIGITAL CHARACTERISTICS (CONT.)

SYNC

MCLK

(2.048 MHz)

MSYNC

t

0

TDATA

(256 kHz)

Figure 2. System Timing Diagram

MCLK

(2.048 MHz)

t_mss

t_msh

t_mclk

t

MSYNC

0

t_msync

TDATA

(256 kHz)

t_tdata

Figure 3. MCLK / MSYNC Timing Detail

14

DS699F2

CS4373A

POWER SUPPLY CHARACTERISTICS

Parameter

Symbol

Min

Typ

Max

Unit

AC Mode Supply Current (MODE = 1, 2, 3, 6)

Analog Power Supply Current

(Note 28)

I

-

8

10

-

mA

A

Digital Power Supply Current

20

µA

D

DC Mode Supply Current (MODE = 4)

Analog Power Supply Current

(Note 28)

I

-

2.7

20

-

mA

A

Digital Power Supply Current

I

µA

D

DC Mode Supply Current (MODE = 5)

Analog Power Supply Current

(Note 28)

I

-

4.2

20

-

mA

A

Digital Power Supply Current

µA

D

Sleep Mode Supply Current (MODE = 0, 7)

Analog Power Supply Current

(Note 28)

I

-

200

260

-

µA

A

Digital Power Supply Current

I

D

Power Down Supply Current (MCLK = 0)

Analog Power Supply Current

(Note 28)

(Note 8)

I

-

1

-

µA

µS

A

Digital Power Supply Current

20

40

D

Time to Enter Power Down (MCLK disabled)

Power Supply Rejection

PD

TC

Power Supply Rejection Ratio

(Note 29)

PSRR

-

90

-

dB

Notes: 28. All outputs unloaded. Digital inputs forced to VD or DGND respectively.

29. Power supply rejection is characterized by applying a 100 mVp-p 50-Hz sine wave to each supply.

DS699F2

15

CS4373A

VA+

MODE(0, 1, 2)

ATT(0, 1, 2)

Attenuator

VD

TDATA

OUT+

OUT-

BUF+

BUF-

24-Bit ∆Σ

DAC

VREF+

VREF-

MCLK

Clock

Generator

MSYNC

VA-

CAP+ CAP-

GND

Figure 4. CS4373A Block Diagram

2. GENERAL DESCRIPTION

The CS4373A is a differential output digital-to-

For maximum performance, the precision out-

analog converter with multiple operational puts (OUT±) must drive only high-impedance

modes and programmable output attenuation.

It provides self-test and precision calibration

capability for high-resolution, low-frequency

measurement systems designed from

CS3301A / CS3302A differential amplifiers,

CS5371A / CS5372A ∆Σ modulators, and the

CS5376A digital filter.

loads such as the CS3301A / CS3302A ampli-

fier inputs. The buffered outputs (BUF±) can

drive lower-impedance loads, down to 1 kΩ,

but with reduced performance compared to

the precision outputs.

2.3 Multiple Operational Modes

The CS4373A operates in either AC or DC test

modes. AC test modes (MODE 1, 2, 3, 6) are

used to measure system THD and CMRR per-

2.1 Digital Inputs

The CS4373A is driven by a ∆Σ digital bit

stream from the CS5376A digital filter test bit formance. DC test modes (MODE 4, 5) are for

stream (TBS) generator. The digital filter also

provides clock and sync signals as well as

GPIO control signals to set the operational

mode and attenuation.

gain calibration and pulse tests.

2.4 Low Power

The CS4373A is optimized for low-power op-

eration and has a restricted operational band-

width in the AC modes. For stable operation,

2.2 Analog Outputs

Two sets of differential analog outputs, OUT full-scale AC test signals must not contain fre-

and BUF, simplify system design as dedicated

outputs for testing the electronics channel and

for in-circuit sensor tests. Output attenuator

settings are binary weighted (1, 1/2, 1/4, 1/8,

quencies above 100 Hz. AC test signals above

100 Hz (TBS impulse mode, for example)

must have a -20 dB reduced amplitude to en-

sure stability of the CS4373A low-power ∆Σ ar-

chitecture.

1/16,

1/32,

1/64)

and

match

the

CS3301A / CS3302A amplifier input levels for

full-scale testing at all gain ranges.

16

DS699F2

CS4373A

3. SYSTEM DIAGRAMS

Geophone

or

Hydrophone

Sensor

CS3301A

CS3302A

M

U

X

CS5371A

CS5372A

AMP

System Telemetry

∆Σ

Modulator

Geophone

or

Hydrophone

Sensor

CS3301A

CS3302A

µController

or

M

U

X

Configuration

EEPROM

CS5376A

Digital Filter

Geophone

or

Hydrophone

Sensor

CS3301A

CS3302A

M

U

X

CS5371A

CS5372A

AMP

Communication

Interface

∆Σ

Geophone

or

Hydrophone

Sensor

Modulator

CS3301A

CS3302A

M

U

X

CS4373A

Test

DAC

Switch

MUX

Figure 5. System Diagram

VA+

VD

0.1µF

SWITCH

CONTROL

VA-

VD

10nF

C0G

MCLK

MSYNC

CAP+

CAP-

MCLK

SENSOR

MSYNC

TDATA

CH1 BUF

CH2 BUF

CH3 BUF

CH4 BUF

Route BUF as diff pair BUF+

BUF-

Analog

Switches

TBSDATA

CS4373A

GPIO

ELECTRONICS

MODE0

MODE1

MODE2

Route OUT as diff pair

Route VREF as diff pair

OUT+

OUT-

CH1,2,3,4 OUT

VA+

10 Ω

GPIO

VREF+

VREF-

ATT0

ATT1

ATT2

2.5 V

VREF

100µF

+

VA-

DGND

CS5376A

SIGNALS

VA-

0.1µF

Figure 6. Connection Diagram

DS699F2

17

CS4373A

POWER DOWN

MCLK = OFF

MODE = XXX

SLEEP MODES

MCLK = ON

MODE = 0, 7

AC TEST MODES

MCLK = ON

DC TEST MODES

MCLK = ON

MODE = 1, 2, 3, 6

MODE = 4, 5

Figure 7. Power Mode Diagram

4. POWER MODES

The CS4373A has four power modes. AC test

modes and DC test modes are operational

sleep mode for normal data acquisition. In

sleep mode the AC and DC test circuitry is in-

modes, while the power down and sleep active and the analog outputs are high imped-

modes are non-operational, standby modes.

ance.

4.1 Power Down

4.3 AC Test Modes

If MCLK is stopped, an internal loss-of-clock

detection circuit automatically places the

With MCLK and TDATA active, selecting an

AC test mode (MODE 1, 2, 3, 6) causes the

CS4373A into power down. Power down is in- CS4373A to output AC waveforms on the en-

dependent of the MODE and ATT pin settings,

and is automatically invoked after approxi-

mately 40 µs without an incoming MCLK edge.

abled analog outputs. AC test modes use the

low-power ∆Σ circuitry in the CS4373A to cre-

ate precision differential or common mode an-

alog AC output signals from the encoded

digital test bit stream (TBS) input.

In power down the AC and DC test circuitry is

inactive and the analog outputs are high im-

pedance. When used with the CS5376A digital

filter, the CS4373A is powered down immedi-

ately after reset since MCLK is disabled by de-

fault.

4.4 DC Test Modes

With MCLK active, selecting a DC test mode

(MODE 4, 5) causes the CS4373A to generate

precision DC voltages on the analog outputs.

DC test modes use switch-capacitor level-

shifting buffer circuitry in the CS4373A to cre-

ate differential or common mode DC analog

output voltages from the voltage reference in-

put.

4.2 Sleep Modes

With MCLK enabled, selecting either of the

sleep modes (MODE 0, 7) places the

CS4373A into a micropower sleep state. Fol-

lowing completion of the AC and DC system

self-tests, the CS4373A is typically set into

18

DS699F2

CS4373A

only the BUF analog output is enabled, and

OUT is high impedance.

5. OPERATIONAL MODES

The CS4373A has six operational modes and

two sleep modes selected by the MODE2,

MODE1, and MODE0 pins.

OUT+

Maximum

5 Vpp

Differential

OUT-

Selection MODE[2:0]

Mode Description

Sleep mode.

CS4373A

MODE 1

0

1

2

3

4

5

6

7

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

AC OUT and BUF outputs.

AC OUT only, BUF high-z.

AC BUF only, OUT high-z.

DC common mode output.

DC differential output.

AC common mode output.

Sleep mode.

BUF+

Maximum

5 Vpp

Differential

BUF-

OUT+

Maximum

5 Vpp

Differential

OUT-

CS4373A

MODE 2

Table 2. Operational Modes

BUF+

High

Impedance

BUF-

5.1 Sleep Modes

Sleep modes (MODE 0, 7) save power during

normal acquisition by turning off the AC and

DC test circuitry after system self-tests are

complete. In sleep mode the OUT and BUF

analog outputs are high impedance.

OUT+

OUT-

High

Impedance

CS4373A

MODE 3

5.2 AC Test Modes

BUF+

Maximum

5 Vpp

Differential

AC test modes use the digital test bit stream

(TBS) input from the CS5376A digital filter to

construct analog AC waveforms. The digital bit

stream input to the TDATA pin encodes the

analog waveform as over-sampled one bit ∆Σ

data, which is then converted into precision

differential or common mode analog AC sig-

nals by the CS4373A.

BUF-

Figure 8. AC Differential Modes

Differential AC signals out of the CS4373A

consist of two halves with equal but opposite

magnitude, varying about a common mode

5.2.1

AC Differential

The first three AC test modes (MODE 1, 2, 3)

create precision differential analog signals for

THD and impulse testing of the measurement

channel. In mode 1, both sets of differential an-

alog outputs (OUT and BUF) are enabled. In

mode 2 only the OUT analog output is en-

abled, and BUF is high impedance. In mode 3

voltage. A full-scale 5 V differential AC sig-

nal centered on a -0.15 V common mode volt-

age will have:

PP

SIG+ = -0.15 V + 1.25 V = +1.1 V

SIG- = -0.15 V - 1.25 V = -1.4 V

SIG+ is +2.5 V relative to SIG-

DS699F2

19

CS4373A

For the opposite case:

verted to a measurable differential signal at

the fundamental frequency.

SIG+ = -0.15 V - 1.25 V = -1.4 V

SIG- = -0.15 V + 1.25 V = +1.1 V

SIG+ is -2.5 V relative to SIG-

So the total swing for SIG+ relative to SIG- is

(+2.5 V) - (-2.5 V) = 5 V differential. A similar

calculation can be done for SIG- relative to

5.2.3

AC Stability

For the CS4373A low-power ∆Σ architecture to

remain stable, the TDATA input bit stream

should only encode 100 Hz or lower band-

width analog signals. For TDATA bit stream

frequencies above 100 Hz (for example, TBS

impulse mode), the encoded amplitude must

be reduced -20 dB below full scale to guaran-

tee stability.

pp

SIG+. It’s important to note that a 5 V differ-

pp

ential signal centered on a -0.15 V common

mode voltage never exceeds +1.1 V with re-

spect to ground and never drops below -1.4 V

with respect to ground on either half. By defini-

tion, differential voltages are measured with

respect to the opposite half, not relative to

ground. A voltmeter differentially measuring

between SIG+ and SIG- in the above example

If the CS4373A low-power ∆Σ architecture be-

comes unstable, persistent elevated noise will

be present on the analog outputs and AC lin-

earity will be poor. To recover stability, place

the CS4373A into power down or sleep mode

and restart the CS5376A test bit stream gener-

ator before placing the CS4373A back into an

AC test mode.

would read 1.767 V , or 5 V .

rms

pp

5.2.2

AC Common Mode

The final AC test mode (MODE 6) creates a

matched AC common mode analog signal for

CMRR testing of the measurement channel. In 5.3 DC Test Modes

mode 6, both sets of analog outputs (OUT and

BUF) are enabled. There is no common mode

AC waveform output for an attenuator setting

of 1/64.

DC test modes create precision level-shifted

and buffered versions of the voltage reference

input as precision DC common mode and DC

differential analog outputs. The absolute accu-

racy of the DC test modes is highly dependent

on the absolute accuracy of the voltage refer-

ence input voltage.

Maximum

OUT+

2.5 Vpp

Common

Mode

5.3.1

DC Common Mode

OUT-

The first DC test mode (MODE 4) creates a

matched DC common mode analog output

voltage as a baseline measurement for gain

calibration and differential pulse tests. In mode

4, both sets of analog outputs (OUT and BUF)

are enabled.

CS4373A

MODE 6

Maximum

BUF+

2.5 Vpp

Common

Mode

BUF-

5.3.2

DC Differential

Figure 9. AC Common Mode

The second DC test mode (MODE 5) creates

a precision differential DC analog output volt-

age as the final measurement for gain calibra-

tion and as the step/pulse output for

differential pulse tests. In mode 5, both sets of

analog outputs (OUT and BUF) are enabled.

Gross leakage in the sensor channel can be

detected by applying a full-scale AC common

mode signal. If there is a significant differential

mismatch in the channel due to sensor leak-

age, the AC common mode signal will be con-

20

DS699F2

CS4373A

In DC differential output mode (MODE 5) the channel. By first measuring the differential off-

level-shifting buffer circuitry adds low-level set of the DC common mode output (MODE 4)

32 kHz switched-capacitor noise to the DC and then measuring the DC differential mode

output. This noise is out of the measurement

bandwidth for systems designed with

amplitude (MODE 5), a precise offset correct-

ed volts-to-codes conversion ratio can be cal-

culated. This known ratio is then used to

normalize the full-scale amplitude using the

CS5376A digital filter GAIN registers to match

other channels in the measurement network.

CS3301A / CS3302A

amplifiers

and

CS5371A / CS5372A modulators, and is re-

jected by the CS5376A digital filter. This

32 kHz switch-capacitor noise does not affect

DC system tests, though it may be visible on

an oscilloscope at high gain levels.

By switching between DC common mode

(MODE 4) and DC differential mode

(MODE 5), pulse waveforms can be created to

characterize the step response of the mea-

surement channel. If a pulse test requires pre-

cise timing control, an external controller

should directly toggle the MODE pins of the

CS4373A to avoid delays associated with writ-

ing to the CS5376A digital filter GPIO regis-

ters.

Approx

-0.15 V_DC

Common

OUT+

OUT-

Mode

CS4373A

MODE 4

Approx

-0.15 V_DC

Common

BUF+

Sensor impedance can be measured using

DC differential mode (MODE 5), provided

matched series resistors are installed between

the BUF analog outputs and the sensor. Ap-

plying the known DC differential voltage to the

resistor-sensor-resistor string permits a ratio-

metric sensor impedance calculation from the

measured voltage drop across the sensor.

BUF-

Mode

OUT+

Maximum

2.5 V_DC

Differential

OUT-

CS4373A

MODE 5

BUF+

Maximum

2.5 V_DC

Differential

Switching between DC differential mode

(MODE 5) and sleep mode (MODE 0, 7) can,

in the case of a moving-coil geophone, test ba-

sic parameters of the electro-mechanical

transfer function. The voltage relaxation char-

acteristic of the sensor when switching the an-

alog outputs from a differential DC voltage to

high impedance depends primarily on the geo-

phone resonant frequency and damping fac-

tor.

BUF-

Figure 10. DC Test Modes

By measuring both DC test modes

(MODE 4, 5), precision gain-calibration coeffi-

cients can be calculated for the measurement

DS699F2

21

CS4373A

VA+

VD

0.1µF

SWITCH

CONTROL

VA-

VD

10nF

C0G

MCLK

MSYNC

CAP+

CAP-

MCLK

SENSOR

MSYNC

TDATA

CH1 BUF

CH2 BUF

CH3 BUF

CH4 BUF

Route BUF as diff pair BUF+

BUF-

Analog

Switches

TBSDATA

CS4373A

GPIO

ELECTRONICS

MODE0

MODE1

MODE2

Route OUT as diff pair

Route VREF as diff pair

OUT+

OUT-

CH1,2,3,4 OUT

VA+

10 Ω

GPIO

VREF+

VREF-

ATT0

ATT1

ATT2

2.5 V

VREF

100µF

+

VA-

DGND

CS5376A

SIGNALS

VA-

0.1µF

Figure 11. Digital Inputs

6. DIGITAL INPUTS

The CS4373A is designed to operate with the

CS5376A digital filter. The digital filter gener-

ates one-bit ∆Σ test bit stream data (TDATA),

a master clock (MCLK) and a synchronization

signal (MSYNC). In addition, the digital filter

GPIO pins control the CS4373A operational

mode (MODE) and attenuator (ATT) settings.

CS4373A low-power ∆Σ circuitry. Details on

the setup and operation of the digital filter TBS

generator can be found in the CS5376A data

sheet.

6.2 MCLK Connection

The CS5376A digital filter generates the mas-

ter clock for CS4373A, typically 2.048 MHz,

from a synchronous CLK input from the exter-

6.1 TDATA Connection

The TDATA digital input expects encoded nal system. By default, MCLK is disabled at re-

one-bit ∆Σ data nominally at a 256 kHz rate.

The one’s density input range is approximately

25% minimum to 75% maximum, with differen-

tial mid-scale at 50% one’s density.

set and is enabled by writing the digital filter

CONFIG register. If MCLK is disabled during

operation, the CS4373A will enter power down

after approximately 40 µS.

The CS5376A digital filter test bit stream

(TBS) generator can encode two types of AC

MCLK must have low in-band jitter to guaran-

tee full analog performance, requiring a crys-

signals as over-sampled, one-bit ∆Σ data - a tal- or VCXO-based system clock into the

pure sine wave for THD and CMRR testing or

a triggerable impulse waveform for synchroni-

zation testing and impulse response charac-

terization. In the AC operational modes, the

CS4373A converts the over-sampled bit

stream digital data into precision differential or

common mode analog AC signals.

digital filter. Clock jitter on the digital filter ex-

ternal CLK input directly translates to jitter on

MCLK.

6.3 MSYNC Connection

The CS5376A digital filter also provides a syn-

chronization signal to the CS4373A. The

MSYNC signal is generated following a rising

edge received on the digital filter SYNC input.

By default MSYNC generation is disabled at

reset and is enabled by writing to the digital fil-

ter CONFIG register.

The CS5376A TBS sine mode encodes an ap-

proximately 5 V full-scale sine wave signal

pp

with a digital filter TBSGAIN register setting of

0x04B8F2. Because TBS impulse mode en-

codes frequencies above 100 Hz, a maximum

0x0078E5 TBSGAIN impulse mode register

setting is specified to guarantee stability of the

The input SYNC signal to the CS5376A digital

filter sets a common reference time t for mea-

0

22

DS699F2

CS4373A

surement events, thereby synchronizing ana-

log sampling across a measurement network.

The timing accuracy of the input SYNC signal

from measurement node to measurement

node must be +/- 1 MCLK to maximize

MSYNC analog sample synchronization accu-

racy.

put output (GPIO) pins through the digital filter

GPCFG registers. These GPIO pins are typi-

cally assigned to operate the CS4373A mode

and attenuator pins, along with the

CS3301A / CS3302A amplifiers input mux and

gain pins. The gain and attenuation settings of

the CS3301A / CS3302A amplifiers and

CS4373A are identically decoded to allow full-

scale performance testing at all system gain

ranges with shared GAIN and ATT control sig-

nals.

The CS4373A MSYNC input is rising-edge

triggered and resets the internal MCLK

counter/divider to guarantee synchronous op-

eration with other system devices. While the

MSYNC signal synchronizes the internal oper-

ation of the CS4373A, by default, it does not

synchronize the phase of the encoded digital

test bit stream (TBS) sine wave unless en-

abled in the digital filter TBSCFG register.

If precise timing control of operational modes

is required (for example, switching between

DC modes for pulse generation), an external

controller should directly toggle the MODE

pins of the CS4373A to avoid the delay asso-

ciated with writing to the CS5376A digital filter

GPCFG registers.

6.4 GPIO Connections

The CS5376A controls 12 general-purpose in-

DS699F2

23

CS4373A

VA+

VD

0.1µF

SWITCH

CONTROL

VA-

VD

10nF

C0G

MCLK

MSYNC

CAP+

CAP-

MCLK

SENSOR

MSYNC

TDATA

CH1 BUF

CH2 BUF

CH3 BUF

CH4 BUF

Route BUF as diff pair BUF+

BUF-

Analog

Switches

TBSDATA

CS4373A

GPIO

ELECTRONICS

MODE0

MODE1

MODE2

Route OUT as diff pair

Route VREF as diff pair

OUT+

OUT-

CH1,2,3,4 OUT

VA+

10 Ω

GPIO

VREF+

VREF-

ATT0

ATT1

ATT2

2.5 V

VREF

100µF

+

VA-

DGND

CS5376A

SIGNALS

VA-

0.1µF

Figure 12. Analog Outputs

7. ANALOG OUTPUTS

The CS4373A has multiple differential analog

mode voltage never exceeds +1.1 V with re-

outputs. The best possible analog perfor- spect to ground and never drops below -1.4 V

mance is achieved from the precision outputs

(OUT±), but with only minimal drive capability.

with respect to ground on either half. By defini-

tion, differential voltages are measured with

A buffered output (BUF±) can drive an external respect to the opposite half, not relative to

load, but with reduced analog performance.

The internal anti-alias filter requires a dedicat-

ed capacitor connection (CAP±) to eliminate

undesired high-frequency signals.

ground. A voltmeter differentially measuring

between SIG+ and SIG- in the above example

would read 1.767 V , or 5 V .

rms

pp

7.2 Analog Output Attenuation

7.1 Differential Signals

The CS4373A has seven analog output atten-

Differential AC signals out of the CS4373A uation settings from 1/1 to 1/64 selected with

consist of two halves with equal but opposite

magnitude varying about a common mode

the ATT2, ATT1, and ATT0 pins. At 1/64 atten-

uation in AC Common Mode (MODE 6) there

is no output signal amplitude due to the atten-

uator architecture.

voltage. A full-scale 5 V differential AC sig-

PP

nal centered on a -0.15 V common mode volt-

age will have:

SIG+ = -0.15 V + 1.25 V = +1.1 V

SIG- = -0.15 V - 1.25 V = -1.4 V

SIG+ is +2.5 V relative to SIG-

For the opposite case:

Selection ATT[2:0] Attenuation

dB

0

1

2

3

4

5

6

7

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1/1

1/2

0 dB

-6.02 dB

-12.04 dB

-18.06 dB

-24.08 dB

-30.10 dB

-36.12 dB

reserved

1/4

1/8

SIG+ = -0.15 V - 1.25 V = -1.4 V

SIG- = -0.15 V + 1.25 V = +1.1 V

SIG+ is -2.5 V relative to SIG-

So the total swing for SIG+ relative to SIG- is

1/16

1/32

1/64

reserved

(+2.5 V) - (-2.5 V) = 5 V differential. A similar

pp

calculation can be done for SIG- relative to

Table 3. Output Attenuation Settings

SIG+. It’s important to note that a 5 V differ-

pp

ential signal centered on a -0.15 V common

24

DS699F2

CS4373A

When enabled, attenuation is applied to both

the OUT and BUF differential analog outputs.

The OUT± pins connect directly into the inter-

nal attenuator resistors and so attenuation ac-

curacy is highly sensitive to load impedance

on the OUT± pins. Loading on the BUF± pins

does not affect attenuator accuracy.

AC BUF Only and sleep modes the OUT± pins

are high impedance.

7.4 BUF Buffered Output

The BUF± pins are buffered differential analog

outputs for testing external sensors such as

geophones or hydrophones. The buffered out-

puts have reduced performance specifications

compared with the OUT outputs, but are less

sensitive to external loading.

The attenuation settings of CS4373A match

the gain ranges of the CS3301A / CS3302A

differential amplifiers to enable full-scale test-

The BUF± outputs are enabled in all operation-

al modes except “AC OUT Only” mode

(MODE 2) and sleep modes (MODE 0, 7). In

AC OUT Only and sleep modes the BUF± pins

are high impedance to ensure they do not in-

terfere with sensor operation during normal

data acquisition.

ing

at

all

gain

ranges.

The

CS3301A / CS3302A amplifier gain settings

(GAIN) are decoded identical to the CS4373A

attenuator settings (ATT) and so can share

GPIO signals from the digital filter.

7.3 OUT Precision Output

The OUT± pins are precision differential ana-

log outputs for testing the high-performance

electronics measurement channel. These pre-

cision outputs have higher performance spec-

ifications than the BUF outputs, but with a

much higher sensitivity to external loading. Ex-

cessive resistive or capacitive loading on the

OUT± pins will degrade the analog perfor-

mance characteristics of the CS4373A in all

operational modes.

For sensor impedance testing, it is required to

place matched series resistors in between the

BUF± outputs and the differential sensor. With

known series resistors and a known DC differ-

ential source voltage, sensor resistance can

be calculated ratiometrically from the mea-

sured voltage drop across the sensor.

7.5 CAP Analog Output

The CS4373A requires a 10 nF C0G or NPO-

type capacitor connected differentially across

the CAP± pins. This capacitor creates an inter-

nal anti-alias filter to eliminate high-frequency

signals from the OUT± and BUF± analog out-

puts and helps to maintain the stability of the

low-power ∆Σ circuitry.

The OUT± precision output is optimized for di-

rect connection to the CS3301A / CS3302A

amplifier differential inputs, which have very

high input impedance. These amplifiers in-

clude a pin-controlled input multiplexer to

switch between an internal differential termina-

tion for noise tests and two external differential

inputs. One external amplifier input is typically

dedicated to sensor measurements and the

other to testing the electronics channel.

A COG, NPO or similar high-quality capacitor

is required for CAP± since other capacitor

types, such as X7R, do not have the required

linearity. Using a poor-quality capacitor on

CAP± will significantly degrade THD perfor-

mance in the AC operational modes.

The OUT± outputs are enabled in all opera-

tional modes except “AC BUF Only” mode

(MODE 3) and sleep modes (MODE 0, 7). In

DS699F2

25

CS4373A

To VA+

Regulator

Route VREF±as a differential pair

from the 100uF RC filter capacitor

100 µF

0.1 µF

Ω

10

To VREF+

2.500 V

VREF

0.1 µF

100 µF

0.1 µF

+

To VA-

Regulator

To VREF-

0.1 µF

Figure 13. Voltage Reference Circuit

8. VOLTAGE REFERENCE

The CS4373A requires a 2.500 V precision

voltage reference to be supplied to the VREF±

pins.

ogy LT1019AIS8-2.5 voltage reference yields

acceptable noise levels if the output is filtered

with a low-pass RC filter.

A separate RC filter is required for each sys-

tem device connected to a given voltage refer-

ence. By sharing a common RC filter, signal-

dependent sampling of the voltage reference

by one system device could cause unwanted

tones to appear in the measurement band-

width of another system device via common

impedance coupling.

8.1 VREF Power Supply

To guarantee proper regulation headroom for

the voltage reference device, the voltage refer-

ence GND pin should be connected to VA- in-

stead of system ground, as shown in

Figure 13. This connection results in VREF-

voltage equal to VA- and VREF+ voltage very

near ground potential [(VA-) + 2.500 VREF].

8.3 VREF PCB Routing

Power supply inputs to the voltage reference

device should be bypassed to system ground

with 0.1 µF capacitors placed as close as pos-

sible to the power and ground pins. In addition

to 0.1 µF local bypass capacitors, at least

To minimize the possibility of outside noise

coupling into the CS4373A voltage reference

input, the VREF± traces should be routed as a

differential pair from the large capacitor of the

100 µF of bulk capacitance to system ground voltage reference RC filter. Careful control of

should be placed on each power supply near

the voltage regulator outputs. Bypass capaci-

tors should be X7R, C0G, tantalum, or other

high-quality dielectric type.

the voltage reference source and return cur-

rents by routing VREF± as a differential pair

will improve immunity from external noise.

To further improve noise rejection of the

VREF± routing, include 0.1 µF bypass ca-

pacitors to system ground as close as possible

to the VREF+ and VREF- pins of the

CS4373A.

8.2 VREF RC Filter

A primary concern in selecting a precision volt-

age reference is noise performance in the

measurement bandwidth. The Linear Technol-

26

DS699F2

CS4373A

8.4 VREF Input Impedance

Since temperature drift of the voltage refer-

ence results in gain drift of the analog full-scale

amplitude, care should be taken to minimize

temperature drift effects through careful selec-

tion of passive components and the voltage

reference device itself. Gain drift specifications

of the CS4373A do not include the tempera-

ture drift effects of external passive compo-

nents or of the voltage reference device itself.

The switched-capacitor input architecture of

the VREF± inputs results in an input imped-

ance that depends on the internal capacitor

size and the clock frequency. With a 15 pF in-

ternal capacitor and a 2.048 MHz MCLK the

VREF input impedance is approximately

[1 / [(2.048 MHz) * (15 pF)]] = 32 kΩ.

While

the size of the internal capacitor is fixed, the

voltage reference input impedance will vary

with MCLK.

8.6 VREF Independence

If the test signal source is required to be fully

independent of the measurement channel, a

separate voltage reference device for the

CS4373A is required. Using a separate volt-

age reference minimizes the possibility of un-

detected ratiometric errors when the same

voltage reference is used by both the test sig-

nal source and the measurement channel.

The voltage reference external RC filter series

resistor creates a voltage divider with the

VREF input impedance to reduce the effective

applied input voltage. To minimize gain error

resulting from this voltage divider effect, the

RC filter series resistor should be the minimum

size recommended in the voltage reference

device data sheet.

Because modern precision voltage references

are highly reliable, requirements for separate

modulator and test DAC voltage references

should be considered carefully. In the unlikely

event of voltage reference failure independent

of other system components, the CS4373A

volts-to-codes ratio will be out of spec and per-

formance will be poor during system self-tests.

8.5 VREF Accuracy

The nominal voltage reference input is speci-

fied as 2.500 V across the VREF± pins, and all

CS4373A gain accuracy specifications are

measured with a nominal voltage reference in-

put. Any variation from a nominal VREF input

will proportionally vary the analog full-scale

gain accuracy.

DS699F2

27

CS4373A

To VA+

To VD

Regulator

100 uF

0.1 uF

100 uF

VA+

VA-

VD

CS4373A

GND

To VA-

Regulator

0.1 uF

100 uF

Figure 14. Power Supply Diagram

9. POWER SUPPLIES

The CS4373A has a positive analog power

supply pin (VA+), a negative analog power

supply pin (VA-), a digital power supply pin

(VD), and a ground pin (GND).

planes or routed traces. When routing power

traces, it is recommended to use a “star” rout-

ing scheme with the star point either at the

voltage regulator output or at a local power

supply bulk capacitor.

For proper operation, power must be supplied

to all power supply pins, and the ground pin

must be connected to system ground. The

CS4373A digital power supply (VD) and the

It is also recommended to dedicate a full PCB

layer to a solid ground plane, without splits or

routing. All bypass capacitors should connect

CS5376A

digital

power

supplies between the power supply circuit and the solid

(VDD1 / VDD2) must share a common power

supply voltage.

ground plane as near as possible to the device

power supply pins.

The CS4373A analog outputs are differentially

routed and do not normally require connection

to a separate analog ground. However, if a

separate analog ground is required, it should

be routed using a “star” routing scheme on a

separate layer from the solid ground plane and

connected to the ground plane only at the star

point. Be sure all active devices and passive

components connected to the analog ground

are included in the “star” route to ensure sen-

sitive analog currents do not return through the

ground plane.

9.1 Power Supply Bypassing

The VA+, VA-, and VD power supplies should

be bypassed to system ground with 0.1 µF ca-

pacitors placed as close as possible to the

power pins of the device. In addition to the

0.1 µF local bypass capacitors, at least 100 µF

bulk capacitance to system ground should be

placed on each power supply near the voltage

regulator output, with additional power supply

bulk capacitance placed among the analog

component route if space permits. Bypass ca-

pacitors should be X7R, C0G, tantalum, or

other high-quality dielectric type.

9.3 Power Supply Rejection

Power supply rejection of the CS4373A is fre-

quency dependent. The CS5376A digital filter

rejects power supply noise for frequencies

above the selected digital filter corner frequen-

cy. Power supply noise frequencies between

DC and the digital filter corner frequency are

9.2 PCB Layers and Routing

The CS4373A is a high-performance device,

and special care must be taken to ensure pow-

er and ground routing is correct. Power can be

supplied either through dedicated power

28

DS699F2

CS4373A

rejected

as

specified

in

the are battery powered and utilize DC-DC con-

verters to efficiently generate power supply

voltages. To minimize interference effects, op-

erate the DC-DC converter at a frequency

Power Supply Characteristics table.

9.4 SCR Latch-up

The VA- pin is tied to the CS4373A CMOS

substrate and must always be the most-nega-

tive voltage applied to the device to ensure

SCR latch-up does not occur. In general,

latch-up may occur when any pin voltage ex-

which is rejected by the digital filter, or operate

it synchronous to the MCLK rate.

A synchronous DC-DC converter whose oper-

ating frequency is derived from MCLK will the-

oretically minimize the potential for “beat

frequencies” to appear in the measurement

bandwidth. However this requires the source

clock to remain jitter-free within the DC-DC

converter circuitry. If clock jitter can occur with-

in the DC-DC converter (as in a PLL-based ar-

chitecture), it’s better to use a non-

synchronous DC-DC converter whose switch-

ing frequency is rejected by the digital filter.

ceeds

the

limits

of

the

Absolute Maximum Ratings table.

It is recommended to connect the VA- power

supply to system ground (GND) with a re-

verse-biased Schottky diode. At power up, if

the VA+ power supply ramps before the VA-

supply is established, the VA- pin voltage

could be pulled above ground potential

through the CS4373A device. If the VA- supply

is pulled 0.7 V or more above GND, SCR

latch-up can occur. A reverse-biased Schottky

diode will clamp the VA- voltage a maximum of

0.3 V above ground to ensure SCR latch-up

does not occur at power up.

During PCB layout, do not place high-current

DC-DC converters near sensitive analog com-

ponents. Carefully routing a separate DC-DC

“star” ground will help isolate noisy switching

currents away from the sensitive analog com-

ponents.

9.5 DC-DC Converters

Many low-frequency measurement systems

DS699F2

29

CS4373A

10. TERMINOLOGY

•

Signal-to-Noise Ratio (Dynamic Range) - Ratio of the rms magnitude of the full-scale signal to the integrated

rms noise from DC to 430 Hz. The following formula is used to calculate SNR:

(

rms magnitude of full scale signal

SNR = 20log

(

rms magnitude of noise floor

Total Harmonic Distortion - Ratio of the power of the fundamental frequency to the sum of the powers of all

harmonic frequencies from DC to 430 Hz. The following formula is used to calculate THD:

(

sum of the powers of the harmonic frequencies

THD = 10log

(

power of the fundamental frequency

Full-scale Bandwidth - The bandwidth in which the converter can generate a full-scale signal while maintaining

performance specifications.

•

Impulse Amplitude - The maximum amplitude of the output signal beyond the full-scale bandwidth.

Differential Output Level - The voltage between the analog output pins of the device.

Full-scale Accuracy - Variation in the measured output voltage from the theoretical full-scale output voltage at

1x attenuation. The following formula is used to calculate full-scale accuracy:

|

( |

measured full scale voltage - theoretical full scale voltage

theoretical full scale voltage

•100%

full scale accuracy =

(

•

Relative Accuracy - Variation in the measured output voltage from the theoretical attenuated output voltage at

each of the attenuation ranges. The following formula is used to calculate relative accuracy:

|

( |

measured attenuated voltage - theoretical attenuated voltage

theoretical attenuated voltage (relative to the measured full scale voltage)

•100%

relative accuracy =

(

•

Full Scale Drift - The variation of the measured full-scale voltage across the specified temperature range.

Common Mode Drift - The variation in the measured common mode voltage across the specified temperature

range.

30

DS699F2

CS4373A

11. PIN DESCRIPTION

Positive Capacitor Output

Negative Capacitor Output

Positive Buffered Output

CAP+

CAP-

BUF+

BUF-

OUT+

OUT-

VA+

GND

System Ground

Mode Select

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

MODE0

MODE1

MODE2

ATT0

2

3

Negative Buffered Output

4

Positive High Precision Output

Negative High Precision Output

Positive Analog Power Supply

Negative Analog Power Supply

Attenuation Range Select

Signal Bitstream Input

Positive Digital Power Supply

System Ground

5

ATT1

6

ATT2

7

VA-

TDATA

VD

8

Negative Voltage Reference VREF-

Positive Voltage Reference VREF+

9

GND

10

11

12

13

14

No Connect

NC

MCLK

MSYNC

DNC

Master Clock Input

Master Sync Input

Do Not Connect

DNC

Do Not Connect

Pin Name

Pin # I/O

Pin Description

1

2

O

I

Capacitor connection for internal anti-alias filter.

CAP+,

CAP-

3

4

Buffered differential analog output.

BUF+,

BUF-

5

6

Precision differential analog output.

OUT+,

OUT-

7

8

Analog power supply. Refer to the Specified Operating Conditions.

Voltage reference input. Refer to the Specified Operating Conditions.

VA+,

VA-

9

10

I

VREF-,

VREF+

17

18

19

20

21

I

Master Sync Input. Low to high transition resets the internal clock phasing.

Master Clock Input. CMOS compatible clock input.

System ground.

MSYNC

MCLK

GND

I

Digital power supply. Refer to the Specified Operating Conditions.

Test Bit Stream input from digital filter TBS generator.

VD

I

TDATA

DS699F2

31

CS4373A

Pin Name

Pin # I/O

Pin Description

22,

23,

24

I

Attenuation Range. Selects the output attenuation range.

ATT2,

ATT1,

ATT0

Attenuation

Selection ATT[2:0] Attenuation

dB

0

1

2

3

4

5

6

7

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1/1

1/2

0 dB

-6.02 dB

-12.04 dB

-18.06 dB

-24.08 dB

-30.10 dB

-36.12 dB

reserved

1/4

1/8

1/16

1/32

1/64

reserved

25,

26,

27

I

Mode Selection. Determines the operational mode of the device.

MODE2,

MODE1,

MODE0

Selection MODE[2:0]

Mode Description

Sleep mode.

0

1

2

3

4

5

6

7

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

AC OUT and BUF outputs.

AC OUT only, BUF tri-state.

AC BUF only, OUT tri-state.

DC common mode output.

DC differential output.

AC common mode output.

Sleep mode.

28

System ground.

GND

32

DS699F2

CS4373A

12. PACKAGE DIMENSIONS

28L SSOP PACKAGE DRAWING

N

D

E1¹

A2

A

E

∝

A1

b²

e

L

END VIEW

SEATING

PLANE

SIDE VIEW

1

2 3

TOP VIEW

INCHES

NOM

--

0.006

0.069

--

0.4015

0.307

0.209

0.026

0.0354

4°

MILLIMETERS

NOTE

DIM

A

A1

A2

b

D

E

E1

e

L

MIN

--

MAX

0.084

0.010

0.074

0.015

0.413

0.323

0.220

0.030

0.041

8°

MIN

--

NOM

--

0.15

1.75

--

10.20

7.80

5.30

0.65

0.90

4°

MAX

2.13

0.25

1.88

0.38

10.50

8.20

5.60

0.75

1.03

8°

0.002

0.064

0.009

0.390

0.291

0.197

0.022

0.025

0°

0.05

1.62

0.22

9.90

7.40

5.00

0.55

0.63

0°

2,3

1

∝

JEDEC #: MO-150

Controlling Dimension is Millimeters

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per

side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not

reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

DS699F2

33

CS4373A

13.ORDERING INFORMATION

Model

Temperature

Package

28-pin SSOP

CS4373A-ISZ (lead free)

-40 to +85 °C

14.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION

Model Number

Peak Reflow Temp

MSL Rating*

Max Floor Life

CS4373A-ISZ (lead free)

260 °C

3

7 Days

* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

15.REVISION HISTORY

Revision

PP1

PP2

PP3

F1

Date

Changes

MAR 2003

SEP 2005

NOV 2005

DEC 2005

DEC 2006

Preliminary release for CS4373.

Update for new CS4373A features and most-current characterization data.

Remove references to CS5378. Update for most-current characterization data.

Updated with final characterization data.

F2

Updated to final status with most-recent characterization data for Cirrus QPL pro-

cess.

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to www.cirrus.com

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject

to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant

information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale

supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus

for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third

parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,

copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-

sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent

does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-

ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE

IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE-

VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD

TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE

IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED

IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA-

TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER

AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH

THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks

or service marks of their respective owners.

34

DS699F2


型号：	CS4373A
厂家：	CIRRUS LOGIC
描述：	Low-power, High-performance Test DAC 低功耗，高性能的测试DAC 测试
文件：	总34页 (文件大小：728K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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