CS4461-DZZ [CIRRUS]
Multi-Bit A/D for Class-D Real-Time PSR Feedback; 多位A / D的D类实时PSR反馈
| 型号： | CS4461-DZZ |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | Multi-Bit A/D for Class-D Real-Time PSR Feedback |
| 文件： | 总11页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS4461
Multi-Bit A/D for Class-D Real-Time PSR Feedback
Features
General Description
z Advanced Multi-bit Delta-Sigma Architecture
The CS4461 is a complete analog-to-digital converter
for class-D real-time power supply rejection (PSR) feed-
back. It performs sampling and analog-to-digital
conversion, generating digital data for input to a
class-D modulator with real-time PSR feedback
capabilities.
z Real-time Feedback of Power Supply
Conditions (AC and DC)
z Filterless Digital Output Resulting in Very Low
Signal Delay
z 135 mW Power Consumption
The CS4461 uses a 5th-order, multi-bit delta-sigma
modulator followed by output data formatting. The ADC
uses a differential architecture which provides excellent
noise rejection.
z Supports Logic Levels Between 3.3 V and
5.0 V
z Differential Analog Architecture
z Modulator Overflow Detection
The CS4461 feeds back the AC and DC voltage compo-
nents and is ideal for class-D audio systems requiring
high power supply rejection.
z Interfaces Directly to the CS44800/CS44600
Class-D PWM Modulator
The CS4461 is available in a 24-pin TSSOP package in
both Commercial (-10° to +70° C) and Automotive
grade (-40° to +85° C). The CDB44800 Customer Dem-
onstration board is also available for device evaluation
and implementation suggestions. Please see “Ordering
Information” on page 11 for complete details.
z Multi-bit Conversion at up to 7.5 MHz
z Delivers Modulated Data Over 2-Wire Interface
VQ
REFGND
PSR_RESET PSR_EN
FILT+
Voltage Reference
OVERFLOW
PSR_MCLK
Output Data
AIN+
AIN-
+
LP Filter
DAC
PSR_SYNC
∆Σ
Formatting
PSR_DATA
-
S/H
GND
5.0 V
(VA)
3.3 V to 5.0 V
(VDP)
Copyright © Cirrus Logic, Inc. 2005
SEPTEMBER '05
DS650F1
(All Rights Reserved)
http://www.cirrus.com
CS4461
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 3
2. PIN DESCRIPTIONS ............................................................................................................................. 6
3. TYPICAL CONNECTION DIAGRAM .................................................................................................... 7
4. APPLICATIONS .................................................................................................................................... 8
4.1 Digital Connections ......................................................................................................................... 8
4.2 Analog Connections ....................................................................................................................... 8
4.3 Power-Up Sequence ...................................................................................................................... 9
4.4 Overflow Detection ......................................................................................................................... 9
4.5 Grounding and Power Supply Decoupling ...................................................................................... 9
5. PACKAGE DIMENSIONS ................................................................................................................. 10
6. ORDERING INFORMATION ............................................................................................................... 11
7. REVISION HISTORY ........................................................................................................................... 11
LIST OF FIGURES
Figure 1. Typical Connection Diagram......................................................................................................... 7
Figure 2. CS4461 Recommended Analog Input Buffer................................................................................ 8
2
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CS4461
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at typical supply voltages
and T = 25°C.)
A
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V.)
Parameter
Symbol
Min
Typ
Max
Unit
DC Power Supplies:
Positive Analog
Positive Digital
VA
VDP
4.75
3.1
5.0
3.3
5.25
5.25
V
V
Ambient Operating Temperature
Commercial (-CZZ)
Automotive (-DZZ)
TAC
TAA
-10
-40
-
-
+70
+85
°C
°C
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 1)
Parameter
Symbol
Min
Max
Units
DC Power Supplies:
Analog
Digital
VA
VDP
-0.3
-0.3
+6.0
+6.0
V
V
Input Current
(Note 2)
Iin
VIN
VIND
TA
-
GND - 0.7
-0.7
10
VA + 0.7
VDP + 0.7
+95
mA
V
Analog Input Voltage
(Note 3)
(Note 3)
Digital Input Voltage
V
Ambient Operating Temperature (Power Applied)
Storage Temperature
-50
°C
°C
Tstg
-65
+150
Notes:
1. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
3. The maximum over/under voltage is limited by the input current.
DS650F1
3
CS4461
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V, all voltages with respect to ground.
PSR_MCLK=12.288 MHz)
Parameter
Symbol
Min
Typ
Max
Unit
Power Supply Current
(Normal Operation)
VA
VDP = 5.0 V
VDP = 3.3 V
IA
ID
ID
-
-
-
17.5
22
14.5
21
26
17
mA
mA
mA
Power Supply Current
(Power-Down Mode) (Note 4)
VA
IA
ID
-
-
2
2
-
-
mA
mA
VDP = 5.0 V
Power Consumption
(Normal Operation)
mW
mW
mW
mW
VDP = 5.0 V
VDP = 3.3 V
VDP = 5.0 V
-
-
-
198
135
20
235
161
-
(Power-Down Mode)
ADC Power Supply Rejection Ratio (1 kHz)
(Note 5)
PSRR
-
65
-
dB
V
Q Nominal Voltage
-
-
-
2.5
25
0.01
-
-
-
V
kΩ
mA
Output Impedance
Maximum allowable DC current source/sink
FILT+ Nominal Voltage
-
-
-
5
18
0.01
-
-
-
V
kΩ
mA
Output Impedance
Maximum allowable DC current source/sink
Notes:
4. Power Down Mode is defined as PSR_RESET = Low with all clocks and data lines held static.
5. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram.
DIGITAL CHARACTERISTICS
Parameter
Symbol
VIH
Min
70%
-
Typ
Max
Units
High-Level Input Voltage
Low-Level Input Voltage
(% of VDP)
(% of VDP)
(% of VDP)
-
-
-
-
30%
-
V
V
V
VIL
High-Level Output Voltage at Io = 100 µA
Low-Level Output Voltage at Io = 100 µA
VOH
70%
(% of VDP)
VOL
-
-
15%
V
OVERFLOW Current Sink
Input Leakage Current
IOVERFLOW
Iin
-
-
-
-
4.0
10
mA
µA
THERMAL CHARACTERISTICS
Parameter
Allowable Junction Temperature
Symbol
Min
Typ
-
Max
135
-
Unit
°C
°C/W
-
-
Junction to Ambient Thermal Impedance
θJA
70
4
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CS4461
ANALOG CHARACTERISTICS
(Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is
10 Hz to 20 kHz.)
Parameter
Symbol
Min
Typ
Max
Unit
DC Accuracy
Gain Error
-
5
-
%
Gain Drift
-
100
ppm/°C
Analog Input Characteristics
Full-scale Differential Input Voltage
-CZZ
-DZZ
-
-
1.13*VA
1.13*VA
-
-
VPP
VPP
AIN+/AIN- Input Range
(VA = 5.0 V)
-CZZ
-DZZ
1.1
1.1
-
-
3.9
3.9
V
V
Input Impedance (Differential)
Common Mode Rejection Ratio
(Note 6)
18
-
-
-
-
kΩ
CMRR
82
dB
Notes:
6. Measured between AIN+ and AIN-
DS650F1
5
CS4461
2. PIN DESCRIPTIONS
PSR_RESET
FILT+
REFGND
VQ
1
24
23
22
21
20
19
18
17
16
15
14
13
GND
PSR_SYNC
PSR_DATA
PSR_MCLK
VDP
2
3
GND
4
GND
5
VA
6
GND
GND
7
VDP
AIN-
8
TEST
AIN+
9
GND
OVERFLOW
VDP
10
11
12
Top-Down View
24-pin TSSOP Package
PSR_EN
GND
VDP
Pin Name
VDP
#
Pin Descriprion
6
8
13
14
Digital Logic Power (Input) – Digital core and input/output power supply. Nominally +3.3 V or +5.0 V.
Supply decoupling should placed as close as possible to pin 6.
VA
19
Analog Power (Input) - Analog power supply. Nominally +5.0 V.
Ground (Input) - Ground reference for both analog and digital.
2
7
10
12
18
20
21
GND
Reset (Input) - When PSR_RESET is low, the CS4461 enters a low power mode and all internal states
are reset. On initial power up, PSR_RESET must be held low until the power supply is stable, and all
input clocks are stable in frequency and phase.
PSR_RESET
1
VQ
22
23
24
Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
Reference Ground (Input) - Ground reference for the internal sampling circuits.
REFGND
FILT+
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuit.
AIN+
AIN-
16
17
Differential PSR Analog Input (Input) - Signals are presented differentially to the delta-sigma modula-
tor via the AIN+/- pins.
PSR_MCLK
PSR_SYNC
PSR_DATA
PSR_EN
5
3
Master Clock (Input) - Clock source for the delta-sigma modulator and output data.
Synchronization Data Output (Output) - Used to synchronize the serial data in the PWM modulator.
PSR Serial Data Output (Output) - Power supply modulated and formatted serial data.
PSR Enable (Input) - A high to low transition on this pin will enable the PSR feedback circuit.
4
11
OVERFLOW
TEST
15
9
Overflow (Output, open drain) - Indicates a modulator overflow condition.
Test (Output) - This pin may toggle during normal operation and should be pulled low through a 47 kΩ
resistor to GND in order to minimize noise.
6
DS650F1
CS4461
3. TYPICAL CONNECTION DIAGRAM
+3.3 V or +5.0 V
0.1 µF
VDP
VDP
VDP
VDP
+5.0 V
22.1 Ω
22.1 Ω
22.1 Ω
VA
PSR_MCLK
PSR_SYNC
PSR_DATA
47 µF
0.1 µF
PWM
Modulator
with PSR
Processing
PSR_EN
PSR_RESET
AIN+
AIN-
See “CS4461 Recom-
mended Analog Input
Buffer” on page 8.
VDP
CS4461
47 kΩ
OVERFLOW
TEST
VQ
47 kΩ
1 µF
0.1 µF
GND
GND
GND
GND
GND
GND
GND
FILT+
47 µF
0.1 µF
REFGND
Figure 1. Typical Connection Diagram
DS650F1
7
CS4461
4. APPLICATIONS
4.1
Digital Connections
PSR_MCLK provides the system clock for the CS4461. PSR_SYNC and PSR_DATA provide the output of
the modulator to the class-D modulator with feedback capabilities. Series damping resistors should be used
on PSR_MCLK, PSR_SYNC, and PSR_DATA to minimize noise. These should be placed as close as pos-
sible to their signal source. The pin labeled TEST should also be pulled low to GND through a 47 kΩ resistor
to minimize noise coupling into the ADC modulator.
4.2
Analog Connections
The analog modulator samples the input at PSR_MCLK/4 (6.144 MHz with PSR_MCLK=24.576 MHz).
Figure 2 shows the suggested analog input filter. This filter topology will correctly buffer the power supply’s
AC and DC components for PSR processing by the class-D modulator. The use of capacitors which have a
large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade sig-
nal linearity. C0G dielectrics should be used wherever possible. R1 and R2 should be used to scale VP
(class-D amplifier high voltage power supply) to less than the CS4461 maximum AIN+/AIN- input voltage
(3.9 V).
2 kΩ
2 kΩ
120 pF
VP
+5.0 V
+5.0 V
R1
-
90.9 Ω
AIN+
+
-
90.9 Ω
649 Ω
+
R2
2200 pF
C0G
CS4461
120 pF
649 Ω
AIN-
Figure 2. CS4461 Recommended Analog Input Buffer
The following equation can be used to scale R1 and R2:
2 * (VP * (1 + % )) * (R2 / (R1 + R2)) < 3.9 V
VP_Ripple
Example (VP = 40 V, %
= 4%):
VP_Ripple
2 * (40 * (1 + 0.04)) * (1.96 kΩ / (40.2 kΩ + 1.96 kΩ) = 3.87 V
8
DS650F1
CS4461
4.3
Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies and clocks
are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the min-
imum specified operating voltages to prevent power glitch related issues.
The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a de-
lay between the release of reset and the generation of valid output, due to the finite output impedance of
FILT+ and the presence of the external capacitance.
4.4
4.5
Overflow Detection
The CS4461 includes modulator overflow detection, indicated on pin 15, OVERFLOW (open drain, active
low). OVERFLOW will go to a logical low as soon as an overrange condition is detected. The data will re-
main low until the condition is cleared.
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4461 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 1 shows the recommended power ar-
rangements, with VA and VDP connected to clean supplies. VDP, which powers the digital logic, may be
run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no
additional devices should be powered from VDP. Decoupling capacitors should be as near to the ADC as
possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulator. The FILT+
and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path
from FILT+ to GND. The CDB44800 evaluation board demonstrates the optimum layout and power supply
arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
DS650F1
9
CS4461
5. PACKAGE DIMENSIONS
24L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
A
E
∝
A1
b2
e
L
END VIEW
SEATING
PLANE
SIDE VIEW
1
2 3
TOP VIEW
INCHES
NOM
MILLIMETERS
NOM
NOTE
DIM
MIN
MAX
MIN
MAX
A
A1
A2
b
D
E
E1
e
L
--
0.002
0.03346
0.00748
0.303
0.248
0.169
--
--
0.004
0.0354
0.0096
0.307
0.2519
0.1732
0.026 BSC
0.024
0.043
0.006
0.037
0.012
0.311
0.256
0.177
--
--
--
--
1.10
0.15
0.95
0.30
7.90
6.50
4.50
--
0.05
0.85
0.19
7.70
6.30
4.30
--
0.90
0.245
7.80
6.40
4.40
0.65 BSC
0.60
4°
2,3
1
1
0.020
0°
0.028
8°
0.50
0°
0.70
8°
µ
4°
JEDEC #: MO-153
Controlling Dimension is Millimeters.
Notes:
1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not re-
duce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
10
DS650F1
CS4461
6. ORDERING INFORMATION
Product
Description
Package Pb-Free
Grade
Temp Range
Container
Rail
Tape & Reel
Rail
Order #
CS4461-CZZ
CS4461-CZZR
CS4461-DZZ
CS4461-DZZR
Commercial -10° to +70° C
Multi-bit A/D for
Class-D Real-time 24-TSSOP
PSR Feedback
CS4461
YES
-
Automotive -40° to +85° C
Tape & Reel
Evaluation board for
CDB44800 the CS44800/600
and the CS4461
-
-
-
-
CDB44800
7. REVISION HISTORY
Release
Date
Changes
A1
May 2004
1st Advance Release
Updated ordering information
F1
September 2005
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
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sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
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or service marks of their respective owners.
DS650F1
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