CS4912-CL [CIRRUS]
Consumer Circuit, CMOS, PQCC44, PLASTIC, MS-018, LCC-44;
| 型号： | CS4912-CL |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | Consumer Circuit, CMOS, PQCC44, PLASTIC, MS-018, LCC-44 商用集成电路 |
| 文件： | 总34页 (文件大小：589K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS4912
Multi-Function Digital Audio Processor
Features
Description
The CS4912 is a highly integrated and cost effective au-
dio processing system for a variety of applications. This
device integrates a 24-bit DSP with on-chip program and
data RAM, a stereo DAC, a full-duplex serial audio inter-
face, a digital audio transmitter, an asynchronous audio
input port, a serial control port, and a phase-locked loop
clock generator. The CS4912 may be coupled with an
ADC such as the CS5331 for 2-in / 2-out audio applica-
tions. A 2-in / 4-out system would include the CS4912
and a stereo CODEC (CS4222), and a 4-in / 6-out sys-
tem can be built using the CS4912 with two CODECs
and a small amount of external logic.
l 24-bit DSP with On-chip Program RAM, Data
RAM, and Stereo DAC
l 24x24 Multiplier with 48-bit Accumulator
l CD Quality Stereo DAC with Output Filter
2 ®
l I C or SPI Serial Control Port
l Integrated S/PDIF Digital Transmitter Port
l Serial Audio Port, up to 4 In/6 Out
l Asynchronous Audio Input Port
l Programmable Phase Locked Loop
l +5 Volt Only CMOS, 44-pin PLCC
The CS4912 is configured for specific applications by
DSP code loaded into the on-chip RAM. The device can
be initialized by an external microcontroller, or booted di-
rectly from a serial EEPROM using a small amount of
external logic. The CRD4912 board is an evaluation plat-
form for the CS4912, with complete documentation to
simplify the design process. CS4912 application firm-
ware kits are available for Car Audio Processing, Dolby
Pro Logic Decoding, and Reverb/Effects applications.
Ordering information for the application firmware kits is
included in the CRD4912 data sheet.
Crystal DSP Application Firmware Kits
l Car Audio Processing for Head or Amp Units
— Crossover Filters, Parametric or Graphic EQs
— Compressor, Peak Limiter, Noise Gate
— 4-channel Adjustable Time Delay
®
l Dolby Surround Pro Logic™ Decoder
— Multiple Output Configurations
— 3D Virtual Surround for 2 Speaker Playback
l Musical Instrument Reverb/Effects
ORDERING INFORMATION
CS4912-CL
44-pin PLCC
CRD4912-01
Reference Design Kit
SCK/SCL
SDA/CDOUT CDIN CS REQ
2
AUXLR
SERIAL CONTROL PORT (SPI OR I C)
AUXILIARY
AUDIO
AUXIN
AUXOUT
AUXCLK
AOUTM
AOUTL
AOUTR
PORT
STEREO DAC
ASYNC
AUDIO
PORT
FSYNC
SCLK
DSP
S/PDIF
TX
SDATA
TRANSMITTER
RESET
BOOT
PIO
XF1
XF2
XF3
XF4
PROG.
I/O PINS
PLL
+
CLOCK MANAGER
FLT CLKIN CLKOUT
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Preliminary Product Information
Cirrus Logic, Inc.
Copyright Cirrus Logic, Inc. 1998
(All Rights Reserved)
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
DEC ‘98
DS282PP2
1
CS4912
TABLE OF CONTENTS
SPECIFICATIONS/CHARACTERISTICS............................................................. 4
ANALOG CHARACTERISTICS................................................................... 4
D/A INTERPOLATION FILTER CHARACTERISTICS ................................ 4
ABSOLUTE MAXIMUM RATINGS .............................................................. 5
RECOMMENDED OPERATING CONDITIONS.......................................... 5
DIGITAL CHARACTERISTICS.................................................................... 5
SWITCHING CHARACTERISTICS - CLOCKS ........................................... 5
SWITCHING CHARACTERISTICS - EXTERNAL FLAGS .......................... 6
SWITCHING CHARACTERISTICS - PROGRAMMABLE INPUT/OUTPUT 6
SWITCHING CHARACTERISTICS - BOOT INITIALIZATION .................... 6
SWITCHING CHARACTERISTICS - CONTROL PORT ............................. 7
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT.................... 11
SWITCHING CHARACTERISTICS - AUXILIARY DIGITAL AUDIO PORT12
THEORY OF OPERATION ................................................................................ 13
Introduction ............................................................................................... 13
PROCESSOR .................................................................................................... 13
PERIPHERALS .................................................................................................. 13
Digital to Analog Converter ....................................................................... 13
Auxiliary Digital Audio Port ....................................................................... 15
Asynchronous Serial Input Port ................................................................ 15
Clock Generator ........................................................................................ 17
Digital Audio Transmitter .......................................................................... 17
Software Configurable Pins ...................................................................... 17
Serial Control Port .................................................................................... 18
Fast/Slow Mode ................................................................................. 18
I2C Mode ............................................................................................ 18
Rise Time on SCK/SCL ...................................................................... 21
SPI Mode ........................................................................................... 21
RESET ............................................................................................................... 23
BOOT PROCEDURE ......................................................................................... 23
POWER SUPPLY AND GROUNDING .............................................................. 24
PIN DESCRIPTIONS ......................................................................................... 27
Power Supplies .................................................................................. 28
Digital-to-Analog Converter ................................................................ 28
Digital Audio Transmitter .................................................................... 28
Clock Generator ................................................................................. 28
Control ................................................................................................ 29
Serial Control Port .............................................................................. 29
Auxiliary Digital Audio Port ................................................................. 30
Asynchronous Audio Port ................................................................... 30
PARAMETER DEFINITIONS ............................................................................. 31
PACKAGE DIMENSIONS ................................................................................. 32
2
I C is a registered trademark of Philips, Inc.
Surround Pro Logic is a trademark and Dolby is a registered trademark of Dolby, Inc.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available.Advance
product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts
to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice
and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this
information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no
license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval sys-
tem, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). Furthermore, no part of this publication
may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of
Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners
which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
DS282PP2
CS4912
LIST OF FIGURES
Figure. 1Boot Timing .................................................................................................. 6
Figure. 2SPI Control Port Timing ................................................................................ 8
Figure. 3I2C Control Port Timing .............................................................................. 10
Figure. 4Serial Audio Port Timing ............................................................................. 11
Figure. 5Auxiliary Audio Port Timing ........................................................................ 12
Figure. 6Typical Connection Diagram ...................................................................... 14
Figure. 7DAC block diagram .................................................................................... 14
Figure. 8I2S Formats ............................................................................................... 15
Figure. 9Right Justified Formats ............................................................................... 16
Figure. 10Left Justified Formats ............................................................................... 16
Figure. 11Asynchronous Serial Input Formats ......................................................... 17
Figure. 12CLKOUT Circuit ........................................................................................ 17
Figure. 13I2C Write Functional Timing Diagram ...................................................... 19
Figure. 14I2C Write Flow Diagram ........................................................................... 19
Figure. 15I2C Read Flow Diagram ........................................................................... 20
Figure. 16I2C Read Functional Timing Diagram ...................................................... 20
Figure. 17I2C Connection Diagram .......................................................................... 21
Figure. 18SPI Write Flow Diagram ........................................................................... 22
Figure. 19SPI Write Functional Timing Diagram ...................................................... 22
Figure. 20SPI Read Flow Diagram ........................................................................... 22
Figure. 21SPI Read Functional Timing Diagram ...................................................... 23
Figure. 22CS4912 Suggested Layout ...................................................................... 24
Figure. 23CS4912 Surface Mount Decoupling Layout ............................................. 25
Figure. 24DAC Frequency Response ....................................................................... 26
Figure. 25DAC Phase Response ............................................................................. 26
Figure. 26DAC Transition Band ................................................................................ 26
Figure. 27DAC Passband Ripple .............................................................................. 26
DS282PP2
3
CS4912
SPECIFICATIONS/CHARACTERISTICS
ANALOG CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5V; CLKIN = 12.288 MHz; Full-Scale Out-
put Sinewave, 1.125 kHz; Word Clock = 48 kHz (PLL in use); Logic 0 = GND, Logic 1 = VD+; Measurement Band-
width is 20 Hz to 20 kHz; Local components as shown in “Typical Connection Diagram”; SPI mode, I2S audio data;
unless otherwise specified.)
Parameter*
Dynamic Performance
Symbol
Min
Typ
Max
Unit
16
-
-
-
-
Bits
LSB
%
DAC Resolution
DNL
THD
±0.9
DAC Differential Nonlinearity
Total Harmonic Distortion
-
-
0.01
0.02
0.015
0.03
AOUTL, AOUTR (Note 1)
AOUTM
IDR
85
80
90
85
-
-
dB
Instantaneous Dynamic Range AOUTL, AOUTR (Note 1)
(DAC not muted, A weighted) AOUTM
-
-
85
-
-
dB
dB
Interchannel Isolation
(Note 1)
0.2
+0.2
Interchannel Gain Mismatch
Pass Band Flatness
-3.0
-
dB
2.66
2.7
2.88
3.0
3.2
3.3
Vpp
Full Scale Output Voltage
AOUTL, AOUTR (Note 1)
AOUTM
-
-
-
100
-
-
5
-
ppm/°C
Deg
Gain Drift
Deviation from Linear Phase
Out of Band Energy
Analog Output Load
-60
dB
(Fs/2 to 2 Fs)
8
-
-
-
-
kΩ
pF
Resistance
Capacitance
100
Power Supply
-
40
-
dB
Power Supply Rejection
Power Supply Consumption
(1 kHz)
-
-
20
100
40
140
mA
mA
VA+
VD+
D/A INTERPOLATION FILTER CHARACTERISTICS (See graphs toward the end of this
data sheet)
Parameter
Symbol
Min
Typ
Max
Unit
Hz
dB
Hz
Hz
dB
dB
s
0
-
0.476 Fs
Passband (-3 dB)
Passband Ripple
Transition Band
Stop Band
-
-
±0.1
0.442 Fs
-
0.567 Fs
≥0.567 Fs
-
-
-
-
-
50
57
-
-
-
Stop Band Rejection
Stop Band Rejection with Ext. 2 Fs RC filter
Group Delay
12/Fs
Notes: 1. 10 kΩ, 100 pF load for each analog signal (Left, Right).
30 kΩ, 100 pF load for analog Mono signal.
* Refer to Parameter Definitions at the end of this data sheet.
4
DS282PP2
CS4912
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to ground.)
Parameter
Symbol
Min
Max
Unit
VD+
VA+
-0.3
-0.3
-
6.0
6.0
0.4
V
V
V
DC Power Supplies
Positive Digital
Positive Analog
|VA+ - VD+|
Iin
-
±10
(VD+) + 0.4
125
mA
V
Input Current, Any Pin Except Supplies
Digital Input Voltage
VIND
TAmax
Tstg
-0.3
-55
-65
°C
°C
Ambient Operating Temperature (power applied)
Storage Temperature
150
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V; all voltages with respect
to ground.)
Parameter
Symbol
Min
Typ
Max
Unit
VD+
VA+
4.50
4.50
-
5.0
5.0
-
5.50
5.50
0.4
V
V
V
DC Power Supplies
Positive Digital
Positive Analog
|VA+ - VD+|
TA
0
-
+ 70
°C
Ambient Operating Temperature
DIGITAL CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5V ±10%; measurements performed under
static conditions.)
Parameter
High-Level Input Voltage
Symbol
Min
Typ
Max
Unit
VIH
2.2
2.5
-
-
-
-
V
V
SCK/SCL
VIL
VOH
VOL
Iin
-
-
-
-
-
0.8
-
V
V
Low-Level Input Voltage
VD x 0.9
High-Level Output Voltage at Io = -2.0 mA
Low-Level Output Voltage at Io = 2.0 mA
Input Leakage Current
-
-
VD x 0.1
1.0
V
µA
(Note 2)
SWITCHING CHARACTERISTICS - CLOCKS (TA = 25 °C; VA+, VD+ = 5 V; Inputs: Logic 0 =
DGND, Logic 1 = VD+, CL = 20 pF)
Parameter
Reference Clock Frequency
Symbol
CLKIN
Min
0.256
40
Typ
12.288
50
Max
30
Unit
MHz
%
CYCK
60
Reference Clock Duty Cycle
Alternate Clock
ALTCLK
-
-
512 Fs
768 Fs
-
-
Hz
Hz
P = 0
P = 1
CLKOUT
-
-
384 Fs
Hz
Clock Output
2. Not Valid for pin numbers 9, 12, 13, and 30 which are configured with on-chip pull-down resistors. Not
valid for pin number 29 which is a static input signal and should be tied to either VD+ or DGND.
DS282PP2
5
CS4912
SWITCHING CHARACTERISTICS - EXTERNAL FLAGS (TA = 25 °C; VA+, VD+ = 5 V;
Inputs: Logic 0 = DGND, Logic 1 = VD+, CL = 20 pF)
Parameter
Symbol
trxf
Min
Typ
Max
200
100
Unit
ns
-
-
-
-
Rise time of XF1-XF4
Fall time of XF1-XF4
(Note 3)
(Note 3)
tfxf
ns
SWITCHING CHARACTERISTICS - PROGRAMMABLE INPUT/OUTPUT
(TA = 25 °C; VA+, VD+ = 5 V; Inputs: Logic 0 = DGND, Logic 1 = VD+, CL = 20 pF)
Parameter
Symbol
fpio
Min
Typ
Max
350
200
200
200
200
Unit
kHz
ns
-
-
-
-
-
-
-
-
-
-
Input Frequency
Input Rise Time
Input Fall Time
Output Rise Time
Output Fall Time
trpio
tfpio
ns
trpo
ns
tfpo
ns
SWITCHING CHARACTERISTICS - BOOT INITIALIZATION
(TA = 25 °C; VA+, VD+ = 5 V; Inputs: Logic 0 = DGND, Logic 1 = VD+, CL = 20 pF)
Parameter
BOOT Rising to RESET Rising Setup Time
RESET Rising to Boot Falling Hold Time
CS Rising to RESET Rising Setup Time
RESET Rising to CS Hold Time
Symbol
tbsu
Min
350
450
200
400
50
Max
Unit
ns
-
-
-
-
-
-
-
tbh
ns
tcssu
tcsh
trlow
trsc
ns
ns
RESET Low Time
µs
SCK/SCL Delay Time from RESET Rising
(Note 4)
2
ms
µs
SCK/SCL falling to CS rising on last byte of download
tsfcr
3
Notes: 3. 2 kΩ pull-up to 5 V supply on XF1-XF4 pins
4. This delay is necessary after any rising edge of RESET to allow time for the part to initialize and for the
on-board PLL to stabilize.
t
t
bh
bsu
BOOT
t
rlow
t
RESET
cssu
2
(I C) CS
(SPI) CS
SCK/SCL
t
csh
t
t
sfcr
rsc
Figure 1. Boot Timing
6
DS282PP2
CS4912
SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25 °C; VA+, VD+ = 5 V;
Inputs: Logic 0 = DGND, Logic 1 = VD+, CL = 20 pF)
Parameter
Symbol
Min
Max
Unit
SPI Mode (CS = 0)
fsck
fsck
tcss
tr
-
-
350
2000
kHz
SCK/SCL Clock Frequency
(slow mode)
(fast mode)
20
-
-
ns
ns
CS Falling to SCK/SCL Rising
(slow mode)
50
Rise Time of Both CDIN and SCK/SCL Lines (slow mode)
tf
tf
-
-
300
50
ns
ns
Fall Time of Both CDIN and SCK/SCL Lines (slow mode)
(fast mode)
tscl
tscl
1100
150
-
-
ns
ns
SCK/SCL Low Time
(slow mode)
(fast mode)
tsch
tsch
1100
150
-
-
ns
ns
SCK/SCL High Time
(slow mode)
(fast mode)
tcdisu
250
50
-
-
ns
ns
Setup Time CDIN to SCK/SCL Rising
(slow mode)
(fast mode)
tcdih
tscdov
tscrh
trr
50
-
40
200
50
20
-
ns
ns
ns
ns
ns
ns
ns
ns
Hold Time SCK/SCL Rising to CDIN
(Note 5)
-
-
Transition Time from SCK/SCL to CDOUT Valid (Note 6)
Time from SCK/SCL Rising to REQ Rising
Rise Time for REQ
(Note 7)
(Note 7)
(Note 7)
-
trf
-
Fall Time for REQ
tscrl
0
Hold Time for REQ from SCK/SCL Rising
Time from SCK/SCL Falling to CS Rising
High Time Between Active CS
tsccsh
tcsht
20
200
-
-
Notes: 5. Data must be held for sufficient time to bridge 300(50) ns transition time of SCK/SCL.
6. CDOUT should NOT be sampled during this time period.
7. 2 kΩ Pull-up resistor to VD+, DSP clock is 36.864 MHz.
DS282PP2
7
CS4912
CS
t
css
t
scl
SCK/SCL
t
sch
t
t
r
r
A6
A5
t
A0
R/W
MSB
MSB
CDIN
CDOUT
REQ
t
cdih
cdisu
t
t
scdov
scdov
t
rf
t
sccsh
CS
t
csht
7
5
6
SCK/SCL
CDIN
LSB
LSB
A6
CDOUT
REQ
tri-state
t
rh
t
cscdo
t
t
scrl
scrh
Figure 2. SPI Control Port Timing
8
DS282PP2
CS4912
SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25 °C; VA+, VD+ = 5 V;
Inputs: Logic 0 = DGND, Logic 1 = VD+, CL = 20 pF)
Parameter
Symbol
Min
Max
Units
I2C Mode (CS=1)
fscl
-
-
100
400
kHz
SCK/SCL Clock Frequency
(slow mode)
(fast mode)
tbuf
thdst
tlow
4.7
4.0
-
-
µs
µs
µs
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
4.7
1.2
-
-
Clock Low Time
(slow mode)
(fast mode)
thigh
4.0
1.0
-
-
µs
Clock High Time
(slow mode)
(fast mode)
tsud
thdd
tr
250
-
-
ns
µs
ns
ns
ns
ns
SDA Setup Time to SCK/SCL Rising
SDA Hold Time from SCK/SCL Falling
Rise Time of Both SDA and SCK/SCL
Fall Time of Both SDA and SCK/SCL
Time from SCK/SCL Falling to CS4912 ACK
0
-
(Note 8)
(Note 9)
50
300
40
40
tf
-
tsca
tscsdv
-
-
Time from SCK/SCL Falling to SDA Valid During READ
Operation
tscrh
tscrl
trr
-
0
200
-
ns
ns
ns
ns
µs
Time from SCK/SCL Rising to REQ Rising
Hold Time for REQ from SCK/SCL Rising)
Rise Time for REQ
(Note 7)
-
50
20
-
(Note 7)
trf
-
Fall Time for REQ
tsusp
4.7
Setup Time for Stop Condition
Notes: 8. Data must be held for sufficient time to bridge the 300 ns transition time of SCK/SCL.
9. This rise time is shorter than the I2C specifications recommend, please refer to the section on SCP
communications for more information.
DS282PP2
9
CS4912
stop
start
A6
A5
A0
R/W
ACK
t
MSB
SDA
t
buf
scsdv
t
sud
0
6
1
7
8
0
SCK/SCL
t
t
t
t
t
t
t
sca
low
hdd
high
r
f
hdst
REQ
CS
t
rf
t
cssta
stop
LSB
ACK
scrl
SDA
7
8
SCK/SCL
t
t
rr
t
susp
REQ
CS
t
scrh
t
cssto
Figure 3. I2C Control Port Timing
10
DS282PP2
CS4912
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(TA = 25 °C; VA+, VD+ = 5 V; Inputs: Logic 0 = GND, Logic 1 = VD+; CL = 20 pF)
Parameter
Symbol Min
Typ
Max
Units
MHz
ns
-
-
-
-
-
-
-
-
-
12.5
SCLK Frequency
tsckl
tsckh
tsfds
tsfs
25
25
20
20
20
20
-
-
-
SCLK Pulse Width Low
SCLK Pulse Width High
ns
-
ns
SCLK rising to FSYNC edge delay
SCLK rising to FSYNC edge setup
SDATA valid to SCLK rising setup
SCLK rising to SDATA hold time
Rise time of SCLK
(Note 10)
(Note 10)
(Note 10)
(Note 10)
-
ns
tsss
tssh
tsclr
-
ns
-
ns
20
ns
Notes: 10. The Serial Audio Port table above assumes data is output on the falling edge and latched on the rising
edge (EDG = 1).
FSYNC
t
sfs
t
sfds
t
t
sckl sckh
SCLK
t
t
sss
ssh
t
sclr
SDATA
Figure 4. Serial Audio Port Timing
DS282PP2
11
CS4912
SWITCHING CHARACTERISTICS - AUXILIARY DIGITAL AUDIO PORT
Parameter
Symbol Min
Typ
Max Units
Fs
16
-
48
kHz
ns
Input Sample Rate
AUXCLK Period
(Note 11)
(Note 12)
tsclk
-
-
-
1/(32 Fs)
1/(64 Fs)
1/(128 Fs)
-
-
-
tlrun
tdoun
tdisu
tdiho
0
0
-
-
-
-
25
25
-
ns
ns
ns
ns
AUXCLK to AUXLR valid
AUXCLK to AUXOUT data valid
AUXIN data setup time to AUXCLK
AUXIN data hold time from AUXCLK
50
3
-
Notes: 11. Fs determined by clock input rate and configuration of on-chip PLL.
12. AUXCLK frequency selectable @ 32, 64, or 128 Fs.
Fs
T
sclk
AUXCLK
AUXLR
AUXOUT
AUXIN
T
lrun
T
doun
T
T
diho
disu
Figure 5. Auxiliary Audio Port Timing
12
DS282PP2
CS4912
reverse addressing are supported as well as auto
post-decrement addressing. Non-branching in-
structions are executed in a single instruction cycle.
For a sample rate (Fs) of 48 kHz, the DSP can exe-
cute up to 18 million instructions per second
(18 MIPS).
THEORY OF OPERATION
Introduction
The CS4912 is a highly integrated Digital Signal
Processor (DSP) system-on-a-chip which is well
suited for a number of audio signal processing ap-
plications. The large quantity of on-chip RAM and
6 integrated peripherals deliver system functional-
ity and flexibility while reducing system cost. The
PERIPHERALS
The CS4912 DSP core is integrated with six on-
RAM-based CS4912 may be configured for a num- chip peripheral devices: a stereo digital-to-analog
ber of different audio processing applications by
loading DSP code and parameter data into on-chip
RAM memories. The CS4912 may be booted via
converter (DAC), a bidirectional auxiliary serial
audio port, an asynchronous serial input port, a dig-
ital audio transmitter, a clock generator, and an
2
the serial control port from a microcontroller or di- SPI/I C serial control port. Each peripheral has I/O
rectly from ROM with a small amount of external
logic (see the CRD4912 reference design docu-
mapped data, control, and status registers. Some of
the peripherals have the ability to generate DSP in-
mentation for details). The serial control port can terrupts. The peripheral devices are described in
2
be configured to operate in either I C or SPI-com- more detail in the following paragraphs.
patible format. The control port may also be used
during run time to communicate with the CS4912
Digital to Analog Converter
The on-chip stereo DAC utilizes delta-sigma archi-
tecture. As shown in Figure 7, digital audio data is
interpolated to either 128 Fs or 192 Fs prior to the
delta-sigma modulator. The interpolation rate is
controlled by the DSP software. The interpolation
filter produces images which are attenuated by at
least 56 dB from 0.584 Fs to 128 Fs (192 Fs). After
interpolation, the audio data is sent to a third order
delta-sigma modulator. The modulator output data
stream is converted to an analog signal by a 1 bit
DAC and then reconstructed by a switched capaci-
tor filter and continuous time filters. The out-of-
band quantization noise from the delta-sigma mod-
ulator extends from 0.417 Fs to 128 Fs (192 Fs).
Out-of-band noise is further attenuated by the
switched capacitor filter and the continuous time
filters. The DAC’s total quantization noise and
thermal noise integrated over a 0.417 Fs to 128 Fs
(192 Fs) bandwidth is more than 50 dB below full
scale power.
DSP.
DSP application firmware kits are available from
Crystal for Dolby Pro Logic/Virtual Surround De-
coding applications, a variety of Car Audio Pro-
cessing applications, and Reverb/Chorus effects
processing applications. Contact your local sales
representative for details on the latest DSP firm-
ware kits available. Figure 6 shows a typical con-
nection diagram for the CS4912 in which a
microcontroller is used for loading the program
code. The CRD4912 Reference Design board pro-
vides system design and implementation details as
well as a flexible platform which can be used to
evaluate the performance of the CS4912 device and
associated DSP application firmware available
from Crystal.
PROCESSOR
The DSP has a fixed-point execution unit with a
24 x 24-bit multiplier, a 48-bit accumulator, and a
24-bit arithmetic logic unit (ALU). Modulo and bit
DS282PP2
13
CS4912
Note: 1 capacitor pair per power supply
Ferrite Bead
+5V
SUPPLY
1
µ
F
0.1
µF
1 µF 0.1 µF
+
+
+
0.1 µF
Ferrite Bead
1 µF
7
17 25 43
VD4
34
VA+
VD1
> 1.0
+
µ
F
600
LEFT
23
38
39
FSYNC
SCLK
AOUTL
AUXLR
AUXCLK
AUDIO
40k
22
21
0.0022
µ
F
AUDIO
SOURCE
SDATA
NPO
CS4912
> 1.0
+
µ
F
+5V
600
RIGHT
AUDIO
AOUTR
20
16
15
14
3
0.0022
NPO
µ
F
XF1
XF2
XF3
XF4
40k
> 1.0
+
µF
600
MONO
AUDIO
37
AOUTM
REQ
PROGRAM
ROM
OR
SERIAL
EEPROM
MICRO
CONTROLLER
OR
PROGRAMMABLE
LOGIC
2
0.0022
NPO
µ
F
40k
SCK/SCL
4
1
SDA/CDOUT
CDIN
44
CS
8
AUXOUT
AUXIN
9
41
40
RESET
BOOT
AUDIO
CODEC
10
11
AUXLR
AUXCLK
24
CLKOUT
5
S/PDIF
RECEIVER
30
TX
PIO
10k
31
19
FLT
RESERVED
RESERVED 28
RESERVED 29
27
0.47 µF
CLKIN
12.288 MHz
DGND1
DGND4 AGND1 AGND2
6
18 26 42
33
36
Figure 6. Typical Connection Diagram
Interpolation
Filter
128 (192) Fs
CT
Filter/
Buffer
Audio
Data Fs
SC
Filter
∆
-
Σ
AOUT
Line
Out
Modulator
Figure 7. DAC block diagram
14
DS282PP2
CS4912
An external passive lowpass filter with a single transition with the falling edge of AUXCLK. The
pole at F = 5 Fs should be connected to the AOUT
rising edge of AUXCLK samples AUXIN.
c
pins to further reduce out-of-band noise. The ana-
log outputs are single ended with a drive capability
down to 8 kΩ. For more information on delta-sig-
ma DAC architecture, please see Crystal applica-
tion note AN10, “18-bit Stereo D/A Converter with
Integrated Digital and Analog Filters”
Asynchronous Serial Input Port
The asynchronous serial input (ASI) port is de-
signed to receive compressed serial audio data in
audio decoding applications. Typical CS4912 ap-
plications use the AUX port for synchronous serial
audio data input. However, the ASI port can be
synchronized with the AUX port to provide an ad-
ditional 2 channels of serial audio data input.
Auxiliary Digital Audio Port
The auxiliary (AUX) port provides a full duplex
path for the internal DSP core to directly read and
write framed PCM digital audio data. The AUX
port is typically connected to ADC, DAC, or CO-
DEC devices.
The ASI port is implemented with 3 device pins:
SCLK, SDATA, and FSYNC. SCLK clocks the
SDATA input into an internal 24 bit shift register.
The active edge of SCLK is programmable (EDG),
and data is shifted in MSB first. The contents of the
The AUX port is implemented with four device
pins; AUXCLK, AUXIN, AUXOUT and AUXLR. shift register are loaded into the ASI input register
AUXCLK is an output pin utilized as the primary
synchronous clock. AUXIN is the serial audio data
either by transitions on FSYNC or by a bit counter
time out. A DSP interrupt can be generated when
input pin and AUXOUT is the serial audio data out- the ASI input register is loaded.
put pin. AUXLR is an output pin used for framing
FSYNC can clock shift register data into the ASI
the digital audio data, and cycles at the same rate as
the on-chip stereo DAC sample rate. The level of
AUXLR indicates the current data channel for
AUXOUT and AUXIN.
register on one or both edges. In dual edge mode
(PUL = 0), the level of FSYNC indicates left and
right channels of stereo audio data. The channel po-
larity of FSYNC is programmable (POL). The in-
The AUX port has the capability to support multi- put shift register is clocked on the first 24 SCLK
ple digital audio formats, illustrated in Figures 8 cycles after an FSYNC edge. Additional SCLK
through 10. For all modes, AUXLR and AUXOUT
Left Channel
Right Channel
LRCK
SCLK
AUXIN/
AUXOUT
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1LSB
Number of Channels
Output
SCLK Rate
Bit/Sample
Input
2
2
2
64 Fs
18
18
Undefined
128 Fs
Figure 8. I2S Formats
DS282PP2
15
CS4912
Right Channel
AUXLR
Left Channel
AUXCLK
AUXIN/
AUXOUT
1
0
19 18 17 16
9
8
7
6
5
4
3
2
1
0
19 18 17 16
9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10
15 14 13 12 11 10
32 clocks
Number of Channels
SCLK Rate
Bit/Sample
Input
Output
Undefined
Undefined
Undefined
2
2
2
32 Fs
64 Fs
16
16 or 18
18
128 Fs
Figure 9. Right Justified Formats
Left Channel
AUXLR
Right Channel
AUXCLK
AUXIN/
AUXOUT
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
64 clks
64 clks
AUXLR
AUXCLK
AUXOUT
Left Channel
Right Channel
MSB
LSB MSB
LSB MSB
LSB
MSB
AUXOUT #2
20 clks
LSB MSB
LSB MSB
LSB
MSB
AUXOUT #1
AUXOUT #3
20 clks
AUXOUT #5
20 clks
AUXOUT #4
20 clks
AUXOUT #6
20 clks
20 clks
AUXIN #1
20 clks
AUXIN
AUXIN #3
20 clks
AUXIN #2
20 clks
AUXIN #4
20 clks
Number of Channels
Output
SCLK Rate
Bit/Sample
Input
2
4
Undefined
6
64 Fs
18
20
128 Fs
Figure 10. Left Justified Formats
transitions are ignored until the next transition of reaches 16 (24). Transitions on FSYNC clear the
FSYNC transfers the data to the ASI register and a
DSP interrupt is generated.
bit counter. FSYNC can be toggled once to syn-
chronize the bit counter with the incoming data
stream, or on each word boundary. The ASI input
register will be continuously loaded every 16 (24)
SCLK periods. A programmable delay (DEL) can
be added to shift the timing between FSYNC and
SDATA by one period. Figure 11 shows the timing
for the various ASI formats.
In single edge (pulse) mode, the data length is pro-
grammable to either 16 or 24 bits, and the active
edge of FSYNC used to load the ASI register is
programmable (POL). The input shift register is
loaded into the ASI register when an FSYNC tran-
sition occurs, or when the internal bit counter
16
DS282PP2
CS4912
SCK
LEFT
LEFT
RIGHT
RIGHT
POL = 0
PUL = 0
POL = 1
PUL = 0
FSYNC
Formats
POL = 0
PUL = 1
POL = 1
PUL = 1
PUL = 0
DEL = 0
MSB 24 BITS, MAX
MSB 24 BITS, MAX
MSB
MSB
MSB 24 BITS, MAX
MSB 24 BITS, MAX
PUL = 0
DEL = 1
SDATA
Formats
PUL = 1
DEL = 0
MSB
MSB
PUL = 1
DEL = 1
Figure 11. Asynchronous Serial Input Formats
Clock Generator
DSP
Clock
÷Q
÷2
CLKOUT
The clock generator is a phase-locked loop (PLL)
based clock multiplier circuit that takes a reference
clock input (CLKIN) and produces an internal mas-
ter clock that has a fixed (but programmable) phase
and frequency relationship to the reference. The
PLL is configured to produce the appropriate inter-
nal master clock for a desired sample rate. All
clocks required for the internal peripherals are de-
rived from this master clock.
Figure 12. CLKOUT Circuit
Digital Audio Transmitter
The on-chip transmitter encodes digital audio data
according to the Sony/Philips Digital Interface For-
mat (S/PDIF). The bi-phase mark encoded data is
output on the TX pin MSB first. The TX pin is typ-
ically connected to an optical transmitter, or an
RS422 transmitter for driving 75 Ω transformer
coupled outputs. For more information on S/PDIF,
please refer to Crystal application note AN22,
“Overview of Digital Audio Interface Data Struc-
tures”.
The PLL requires an external capacitor which is
connected to the FLT pin. The typical value of the
FLT capacitor is 0.47 µF, which is sufficient for all
allowable CLKIN input frequencies. For optimum
analog performance, the capacitor must be as close
as possible to the FLT pin and layout precautions
taken to avoid noise coupling onto the FLT pin.
Software Configurable Pins
The CS4912 has five pins which can be configured
by software for various input/output uses. These
pins are the XF1-XF4 pins and the PIO pin. The
XF1-XF4 pins are general purpose open-drain out-
put pins. An external pull-up resistor (2.2 kΩ typi-
cal) to the digital supply on each XF pin is required
for proper operation.
The clock generator is physically implemented
with 2 device pins; CLKIN, and CLKOUT. The
CLKIN input pin is used as the reference clock in-
put to the PLL. The CLKOUT output frequency is
derived from the DSP clock, and can be used to
synchronize external devices. A diagram of the
CLKOUT circuit is shown in Figure 12. The value
of Q (10 bit) is set by the DSP software.
The PIO pin is bidirectional and is capable of gen-
erating a DSP interrupt. A pull-down resistor
DS282PP2
17
CS4912
2
(10 kΩ typical) to digital ground is required for
As an I C compatible port, bidirectional data is
communicated on the SDA pin MSB first. Input
data is sampled on the rising edge of SCK/SCL,
and output data transitions after the falling edge of
SCK/SCL. During data transmission, SDA should
only transition when SCK/SCL is low. Transitions
on SDA while SCK/SCL is high are interpreted by
the CS4912 as start or stop conditions. A high to
low transition on SDA while SCK/SCL is high is a
start condition. A low to high transition on SDA
while SCK/SCL is high is a stop condition.
SCK/SCL should be held low when inactive.
proper operation.
Serial Control Port
The serial control port (SCP) is an asynchronous
serial interface which provides interrupt and hand-
shaking signals between the DSP and an off-chip
serial bus master device. The SCP is physically im-
plemented with 5 device pins; SCK/SCL, CS,
SDA/CDOUT, CDIN, and REQ. The SCP can op-
2
erate in either I C or SPI compatible slave modes.
As a slave, the SCP cannot drive the clock signal.
2
In an I C system, each slave device is assigned a
Fast/Slow Mode
unique address. The LSB of the address byte is the
read/write bit. When the read/write bit is high, the
bus master is reading data from the slave, and low
if the bus master is writing data to the slave. The
Philips I C bus specification provides details of
this interface.
Following power-up or reset, the SCP operates in
fast mode. Slow mode (programmed in the DSP
software) is provided for compatibility with bus
masters that can only receive data on the falling
edge of SCK/SCL. Slow mode adds additional
skew to the output data to provide hold time for
these bus masters. In fast mode, the port can be op-
erated at much higher bit rates to facilitate faster
downloading of the DSP code. Since the CS4912 is
always a slave, fast mode will not affect operation
of other devices sharing the same communication
bus.
2
Address Checking
Immediately following power up, the CS4912 will
2
respond to any address on the I C bus. The SCP can
be configured to only respond to an assigned ad-
dress by initializing an address and enabling ad-
dress checking via the DSP software. If the CS4912
is the only device other than the bus master on the
I2C Mode
2
I C bus, address checking is optional. In systems
2
2
For normal I C operation, SCK/SCL, SDA, and
with multiple slave devices on the I C bus, the
REQ are used; CS and CDIN are typically connect-
ed to the digital supply. SCK/SCL is the serial
clock input which is always driven by an external
device. SDA is the bidirectional data pin which re-
quires a pull-up resistor (2.2 kΩ typical) to the dig-
ital supply. REQ is the active low service request
signal, which is driven low when the DSP writes
data to the SCP output register. The status of CS
sets the mode of the SCP during a reset condition.
If CS is high during a low to high transition on RE-
CS4912 should be held in reset until the master is
ready to boot the CS4912 with a unique address as-
signment and enable address checking. The as-
signed address should be used while downloading
DSP code to the CS4912 to avoid conflict with oth-
er devices on the bus.
I2C Write
The flow diagram for a typical I2C write sequence
is shown in Figure 13. Figure 14 shows the rela-
2
2
SET, the SCP mode is I C. It is important to note
tive timing of an I C write sequence. A write is ini-
that CS should be high when any reset is issued to
tiated with a start condition followed by the address
byte with the read/write bit cleared (low). After
2
ensure the mode remains I C.
18
DS282PP2
CS4912
each byte, the bus master must release the data line
on the falling edge of SCK/SCL on the D0 bit so the
CS4912 can drive SDA low during the ninth clock
to acknowledge the byte has been received. The
SCP will release SDA on the falling edge of the
ninth clock. The CS4912 will respond with an
ACK following the address byte if address check-
ing is disabled, or if address checking is enabled
and the received address is valid. After receiving a
valid ACK, the bus master then sends a byte of da-
ta. The CS4912 will respond with an ACK after
each byte received. To terminate the transaction,
the bus master issues a stop condition after the last
ACK. If no ACK is received by the bus master, a
stop condition should be issued and the transaction
restarted. ACK failures on address bytes are an in-
dication of fundamental communications problems
at the system level and should be resolved. ACK
failures on data bytes can occur if the DSP has not
read the previous byte out of the SCP input register
before the falling edge of SCK/SCL for the D0 bit.
SEND I2C START
WRITE ADDRESS BYTE
WITH MODE BIT
SET TO 0 FOR WRITE
GET ACK
SEND DATABYTE
GET ACK
Y
MORE DATA?
N
I2C Read
I2C STOP
2
A flow diagram for a typical I C read is shown in
Figure 13. I2C Write Flow Diagram
Figure 15. Figure 16 shows the relative timing dia-
gram of an I C read. If the DSP needs to send data
to an I C bus master, it writes a data byte to the SCP
output register which causes REQ to be asserted
low. The bus master must respond by reading the
data in the SCP before any subsequent write opera-
tions, or the data in the SCP will be lost.
2
knowledge the byte has been received. The CS4912
will respond with an ACK following the address
byte if address checking is disabled, or if address
checking is enabled and the received address is val-
id. If no ACK is received by the bus master after the
address byte is sent, a stop condition should be is-
sued and the transaction restarted.
2
To read from the SCP, the bus master sends a start
condition followed by the CS4912 address with the
read/write bit set (high). After the address byte is
sent, the bus master must release SDA on the fall-
ing edge of SCK/SCL on the D0 bit so the CS4912
can drive SDA low during the ninth clock to ac-
After sending an ACK for the address byte, the
SCP will then clock the contents of the SCP output
register into the shift register on the falling edge of
the ninth clock and the MSB will be driven onto
SDA. After receiving the ACK for the address byte
I2C Start
SCCLK
I2C Stop
SCDIO
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W ACK D7
D6
D5
D4
D3
D2
D1
D0
ACK D7
D6
D5
D4
D3
D2
D1
D0
ACK
Figure 14. I2C Write Functional Timing Diagram
DS282PP2
19
CS4912
on the ninth clock, the bus master then clocks 8 bits
of data out of the SCP shift register and responds
with an ACK after each byte. The bus master must
respond with an ACK to each byte received by
driving SDA low during the rising edge of the ninth
clock cycle. Failure to send an ACK prevents data
residing in the SCP output register from being
clocked into the SCP shift register.
N
REQ LOW?
Y
SEND I2C START
The behavior of the REQ line is dependent on when
data is written to the SCP output register in relation
to SCK/SCL. There are three cases of REQ behav-
ior:
WRITE ADDRESS BYTE
WITH MODE BIT
1) The REQ line will be de-asserted immediately
following the rising edge of SCK/SCL on the
D0 bit of the current byte being transferred if
there is no data in the SCP output register. The
REQ line is guaranteed to stay de-asserted
(high) until the rising edge of SCK/SCL for the
ACK. This signals the host that the transfer is
complete and a stop condition should be issued.
SET TO 1 FOR READ
GET ACK
READ DATABYTE
2) If data is written to the SCP output register pri-
or to the rising edge of SCK/SCL for the D0 bit,
REQ will remain asserted (low). Immediately
following the falling edge of SCK/SCL for the
ACK, the new data byte will be loaded into the
serial shift register. The bus master should con-
tinue to shift out this new byte.
Y
SEND ACK
REQ STILL LOW?
N
SEND NACK
3) If data is placed in the SCP output register by
the DSP between the rising edge of SCK/SCL
for the D0 bit, but before the rising edge of
SCK/SCL for the ACK, REQ will be de-assert-
SEND I2C STOP
Figure 15. I2C Read Flow Diagram
I2C Start
I2C Stop
SCCLK
SCDIO
INTREQ
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W ACK D7
D6
D5
D4
D3
D2
D1
D0
ACK D7
D6
D5
D4
D3
D2
D1
D0 NACK
Figure 16. I2C Read Functional Timing Diagram
20
DS282PP2
CS4912
ed (high) after the rising edge of SCK/SCL for
the last data bit, and will not be asserted again
until after the rising edge of SCK/SCL for the
ACK. Under these conditions, the data in the
SCP output register will not be clocked into the
shift register on the falling edge of SCK/SCL
for the ACK. A new read transaction is required
to read this data. The bus master should issue a
stop condition before reading the data.
SPI Mode
For normal SPI operation, SCK/SCL, CS, CDIN,
CDOUT and REQ are used. SCK/SCL is the serial
clock input which is always driven by an external
device. CS is the active low enable signal. CDIN is
the control data input. SDA/CDOUT is the SCP
data output. REQ is the active low request signal,
which is asserted low when there is data in the SCP
output register. The status of CS sets the mode of
the SCP during a reset condition. If CS is low dur-
ing a low to high transition of RESET, the SCP
mode is SPI. It is important to note that CS should
be low when any reset is issued to ensure the mode
remains SPI.
To determine if a read transaction has been com-
pleted, the bus master should sample the state of
REQ on the falling edge of the last data bit of each
byte, or send a stop condition following any rising
edge of REQ.
As an SPI compatible port, data on CDIN is
clocked into the SCP on the rising edge of
SCK/SCL. Data is output MSB first onto CDOUT
and transitions on the falling edge of SCK/SDA.
Rise Time on SCK/SCL
2
The Philips I C bus specification allows for rise
times of the SCK/SCL line up to 1 µs. The CS4912
does not meet this specification. If the I C bus mas-
2
ter has a rise time in excess of 50 ns the CS4912
will be unable to reliably communicate across the
bus. In cases where the CS4912 will be used in a
system where a longer rise time on SCK/SCL is ex-
pected, a CMOS compatible buffer should be used.
Figure 17 shows the necessary connections. Note
the buffer is only used for the SCK/SCL connection
to the CS4912.
SPI Write
An SPI write is initiated by asserting CS low. The
bus master then sends the SCP address byte with
the read/write bit cleared (low). A data byte is then
clocked into the SCP on the CDIN pin. The data
byte is transferred to the SCP input register on the
falling edge of the D0 bit and a DSP interrupt is
generated. Multiple bytes can be clocked into the
SCP while is CS asserted. CS is de-asserted (high)
following the falling edge of SCK/SCL for the D0
bit of the last byte.
Vcc Vcc
2.2 k
SDA
SCL
Ω
2.2 k
Ω
Figure 18 shows the sequence for an SPI write
transaction.
SDA
SCL
Figure 19 shows the relative timing diagram of an
SPI write transaction. A ‘write’ is defined as the
transfer of data from an SPI bus master to the
CS4912 serial control port via CDIN. A read trans-
fers data from the SCP to the bus master via CD-
OUT. A bus transaction is initiated when CS is
asserted low by the bus master. The SCP address
byte is then sent to the CS4912. The LSB of the ad-
dress is the read/write bit that is set (high) if the bus
2
I C Controller
to other
I C Devices
CS4912
2
Figure 17. I2C Connection Diagram
DS282PP2
21
CS4912
SPI START: CS (LOW)
N
WRITE ADDRESS BYTE
WITH MODE BIT
REQ LOW?
Y
SET TO 0 FOR WRITE
CS (LOW)
SEND DATABYTE
WRITE ADDRESS BYTE
WITH MODE BIT
Y
SET TO 1 FOR READ
MORE DATA?
N
READ DATA BYTE
CS (HIGH)
Figure 18. SPI Write Flow Diagram
Y
REQ STILL LOW?
N
master is reading data from the slave and cleared
(low) if the bus master is writing data to the slave.
Although not typical in SPI systems, address
2
checking can be used as described in the I C sec-
CS (HIGH)
tion.
Figure 20. SPI Read Flow Diagram
SPI Read
falling edge of SCK/SCL for the D0 bit of the ad-
dress byte and the MSB of the data byte will be
driven onto CDOUT. The bus master then reads the
contents of the SCP shift register.
If the DSP is required to send data to an SPI bus
master, it writes the data byte to the SCP output
register which causes REQ to be asserted low. The
bus master must respond by reading the data in the
SCP before any subsequent write operations, or the
data in the SCP will be lost.
The behavior of the REQ line is dependent on when
data is written to the SCP output register in relation
to SCK/SCL. There are three cases of REQ behav-
ior:
To read from the SCP in SPI mode, the bus master
asserts CS (low) and sends the CS4912 address
byte to the SCP via CDIN with the read/write bit set
(high). The SCP will then load the contents of the
SCP output register into the shift register on the
SCCLK
1) The REQ line will be de-asserted immediately
following the rising edge of the D1 data bit of
the current byte being transferred if there is no
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCDIN
CS
Figure 19. SPI Write Functional Timing Diagram
22
DS282PP2
CS4912
data in the SCP output register. This indicates
to the bus master that the transfer is complete
and CS should be de-asserted (high). The REQ
line is guaranteed to stay de-asserted (high) un-
til after the rising edge of SCK/SCL for the D0
bit.
RESET
The CS4912 provides three reset mechanisms, soft-
ware reset, hardware reset, and boot reset. Software
reset is initiated by the DSP software. On software
reset, the digital audio transmitter, the serial control
port, and the ALTCLK pin are disabled. The stereo
2) If data is written to the SCP output register pri- DAC is also muted. All interrupts except the debug
or to the rising edge of SCK/SCL for the D1 interrupt are disabled, all internal registers are
data bit, REQ will remain asserted (low). The cleared, control port address checking is disabled,
new data byte will be loaded into the serial shift and software execution is restarted. Internal RAM
register on the falling edge of SCK/SCL for the
D0 bit. The bus master should continue to shift
out this new byte.
is not cleared. Normal operation is resumed one in-
ternal clock cycle after the rising edge of RESET.
Hardware reset is initiated by holding the BOOT
3) If data is placed in the SCP output register by pin low while the RESET pin transitions from low
the DSP between the rising edge of SCK/SCL
for the D1 data bit, but before the rising edge of
SCK/SCL for the D0 data bit, REQ will be de-
asserted (high) after the rising edge of
SCK/SCL for the D1 bit, and will not be assert-
ed again until after the rising edge of SCK/SCL
for the D0 bit. Under these conditions, the data
in the SCP output register will not be clocked
into the shift register on the falling edge of
SCK/SCL for the D0 bit. A new read transac-
tion is required to read this data, and the bus
master should de-assert CS after the falling
edge of SCK/SCL for the D0 bit.
to high. Hardware reset has the same effect as soft-
ware reset.
Boot reset is initiated by holding the BOOT pin
high while the RESET pin transitions from low to
high. On boot reset, the DACs are muted, the inter-
nal registers are cleared, all interrupts except debug
are disabled, and the DSP begins execution at the
beginning of the internal ROM program. The be-
havior of the boot ROM program is described in the
following section. During power up, boot reset
conditions must be met in order to load a program
into the DSP.
BOOT PROCEDURE
To determine if a read transaction has been com-
pleted, the bus master should sample the state of
REQ on the falling edge of the D1 data bit of each
byte, or de-assert CS following any rising edge of
REQ after the falling edge of SCK/SCL for the D0
bit.
The boot ROM code transfers data through the SCP
to on-chip program and data RAM. After the mem-
ory has been loaded, the boot loader program issues
a software reset and the new program loaded into
RAM begins execution.
SCCLK
SCDIN
SCDOUT
CS
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
INTREQ
Figure 21. SPI Read Functional Timing Diagram
DS282PP2
23
CS4912
>
1/8"
Ground
Connection
Digital
Ground
Plane
Analog
Ground
Plane
Note that the CS4912
is oriented with its
digital pins towards the
digital end of the board.
+5V
Analog
Supply
Ferrite
Bead
CS4912
Digital Interface
Analog Signals &
Components
Figure 22. CS4912 Suggested Layout
The boot ROM loads blocks of data into consecu-
tive RAM addresses. The block data format con-
sists of a two byte block start address that contains
a data or program RAM identifier, and a two byte
data block length. The start address is contained in
the 12 LSBs of the start address. The 13th bit of the
start address is the data/program RAM identifier. A
one in this position indicates a program RAM des-
tination. The upper three bits of the start address are
discarded internally. Any number of blocks can be
loaded sequentially during boot. A two byte end-
of-block identifier (0xFFFF), and a three byte
check sum must follow the last data block. The
check sum is generated by summing all the previ-
ous data, address, and length bytes and truncating
to 24 bits. The check sum received by the control
port is compared to the value calculated internally.
POWER SUPPLY AND GROUNDING
To minimize noise and optimize system perfor-
mance, a multilayer board with power and ground
planes should be used. The digital and analog pow-
er and grounds should be separated on their respec-
tive plane layer. All digital circuitry and traces
should lie over the digital ground plane, and the
digital power and ground planes should not overlap
the analog power or ground plane.
To minimize noise on the power bus, digital power
should be connected to the CS4912 via a ferrite
bead, positioned closer than 1" to the device (see
Figure 22). The CS4912 VA+ pin should be de-
rived from the cleanest power source available. If
only one supply is available, use the suggested ar-
rangement in Figure 6.
If they do not match, the DSP writes the internally The CS4912 should be positioned such that the an-
calculated check sum to the SCP output register, alog pins (pins 29-39) are over the analog ground
and the processor enters an infinite loop. The check
sum written to the SCP output register causes REQ ground plane as illustrated in Figures 22 and 23.
to be asserted low, which is a key indicator to the The analog and digital grounds on the CS4912 are
plane, while the rest of the pins lay over the digital
bus master that the boot process was unsuccessful. not connected internally; the system designer is re-
The SCP shift register is still functional with the quired to connect them externally through a point-
DSP in a loop, and the check sum data is available
to be read by the bus master.
to-point connection across the ground split as
shown in Figure 22. Figure 23 illustrates the opti-
mum ground and decoupling layout for the CS4912
assuming a surface-mount socket and surface
mount decoupling capacitors. If the part is to be
24
DS282PP2
CS4912
Figure 23. CS4912 Surface Mount Decoupling Layout
socketed, find a socket with the minimum height ary. Traces bringing the power to the CS4912
which will minimize the socket impedance. Decou- should be wide thereby keeping the impedance
pling capacitors are placed as close as possible to
the device which, in this case, is the socket bound-
low.
DS282PP2
25
CS4912
Figure 24. DAC Frequency Response
Figure 25. DAC Phase Response
Figure 26. DAC Transition Band
Figure 27. DAC Passband Ripple
26
DS282PP2
CS4912
PIN DESCRIPTIONS
CDIN
SCK/SCL
REQ
CS
VD4
DGND4
RESET
SDA/CDOUT
TX
DGND1
VD1
BOOT
AOUTR
AOUTL
AOUTM
AGND2
NC
AUXOUT
AUXIN
AUXLR
AUXCLK
DBCLK
DBDA
XF4
6
4
2
1
44
42
40
7
39
38
37
36
35
34
33
32
31
30
29
8
9
10
11
12
13
14
15
16
17
top
view
VA+
AGND1
NC
XF3
FLT
XF2
PIO
18
20
22
24
26
28
RESERVED
RESERVED
CLKIN
VD2
DGND2
RESERVED
XF1
DGND3
SDATA
SCLK
VD3
CLKOUT
FSYNC
DS282PP2
27
CS4912
Power Supplies
VD1, VD2, VD3, VD4 - Positive Digital Power Supply, PINS 7, 17, 25, 43.
The +5 V supply connected to these pins powers the various digital subcircuits on the chip. See
the Power Supply and Grounding section in this data sheet for decoupling recommendations.
DGND1, DGND2, DGND3, DGND4 - Digital Ground, PINS 6, 18, 26, 42.
Digital power supply ground.
VA+ - Positive Analog Power Supply, PIN 34.
The +5 V supply connected to these pins powers the DACs and the PLL. Analog performance
is highly dependent on the quality of this supply. See the Power Supply and Decoupling section
in this data sheet for decoupling recommendations.
AGND1, AGND2 - Analog Ground, PIN 33, 36.
Analog power supply ground.
Digital-to-Analog Converter
AOUTL, AOUTR - Analog Outputs, Left and Right Channels, PINS 38, 39.
The DAC outputs are centered at approximately 2.2 V. An external filter is required to diminish
out-of-band noise. See Typical Connection Diagram, Figure 6.
AOUTM - Mono Analog Output, PIN 37.
Mono is the summation of AOUTL and AOUTR. Mono output is 180° out-of-phase with the
sum of AOUTL and AOUTR. Mono is centered at approximately 2.2 V. An external filter is
required to diminish out-of-band noise. See Typical Connection Diagram, Figure 6.
Digital Audio Transmitter
TX - Transmitter Output, PIN 5.
Biphase mark encoded data is output at logic levels from the TX pin. TX typically connects to
the input of an RS-422 or optical transmitter. With additional external circuitry, the port can
support either AES/EBU or S/PDIF formats.
Clock Generator
CLKOUT - Clock Output, PIN 24.
CLKOUT is typically used as the master clock input (MCLK) to synchronize external audio
converters such as ADCs, DACs or CODECs. CLKOUT can also be used to synchronize
digital peripherals such as microcontrollers. The output frequency is determined by a
programmable divider in the clock generator.
FLT - PLL Filter, PIN 31.
A capacitor (typically 0.47 µF) connected to this pin filters the control voltage for the on-chip
PLL. Trace length between the pin and capacitor should be minimized.
28
DS282PP2
CS4912
CLKIN - Clock Input, PIN 27.
CLKIN is the reference clock input to the PLL.
Control
DBCLK, DBDA - Debug Port, PINS 12, 13.
DBDA is the bidirectional debug port data pin, and requires a pull-up resistor to the digital
supply (typically 2.2 kΩ). DBCLK is the debug port clock input.
RESET - PIN 41.
The CS4912 enters a reset state while RESET is low. RESET is typically provided by a power
supply monitor IC.
BOOT - PIN 40.
Boot enable pin. If BOOT is high during a low to high transition of RESET, the boot ROM
program begins execution.
XF1, XF2, XF3, XF4 - External Flags, PINS 20, 16, 15, 14.
The XF pins are software controllable open drain outputs. An external pull-up resistor to the
digital supply is required (typically 2.2 kΩ) for proper operation.
PIO - Programmable Input/Output, PIN 30.
The PIO pin is a software controllable bidirectional pin. A pull-down resistor (typically 10 kΩ)
to the digital ground is required for proper operation.
RESERVED - PINS 19, 28, 29
These pins must be tied to ground for proper operation.
Serial Control Port
REQ - Request Output, PIN 3.
The REQ pin is asserted low when the control port needs servicing from an external device. A
pull-up resistor (typically 2.2 kΩ) to the digital supply is required for proper operation.
CS - Chip Select Input, PIN 44.
In SPI format, communication between the host and the CS4912 is initiated when the host
drives the CS pin low. CS also serves as the communication format select during reset or power
2
up. When CS is high during a reset or power up the SCP will be configured in I C mode.
When low, it is configured in SPI mode.
SCK/SCL - Serial Clock Input, PIN 2.
The SCK/SCL input clocks data into or out of the serial control port.
DS282PP2
29
CS4912
SDA/CDOUT - Serial Data I/O / Control Data Output, PIN 4.
2
In SPI mode, CDOUT is a data output for the serial control data. In I C interface mode, SDA
is the bidirectional data pin. A pull-up resistor (2.2 kΩ typical in I C mode) is required for
2
proper operation.
CDIN - Control Data Input, PIN 1.
2
In SPI mode, CDIN is the data input for the serial control port. It has no function in I C mode,
and should be tied to digital power or ground.
Auxiliary Digital Audio Port
AUXLR - Auxiliary Sample Clock Output, PIN 10.
AUXLR determines which channel is currently being input on the AUXIN pin or output on the
AUXOUT pin. AUXLR is typically connected to the frame clock (LRCLK or FSYNC) on an
external ADC or DAC.
AUXIN - Auxiliary Data Input, PIN 9.
Two’s complement MSB first serial audio data is input on this pin. The data is clocked by
AUXCLK and the channel is indicated by AUXLR. AUXIN is typically connected to the serial
audio data output pin (SDOUT) on an external ADC.
AUXOUT - Auxiliary Data Output, PIN 8.
Two’s complement MSB first serial audio data is output on this pin. The data is clocked by
AUXCLK and the channel is indicated by AUXLR. AUXOUT is typically connected to the
serial audio data input (SDIN) on an external DAC.
AUXCLK - Auxiliary Serial Clock Output, PIN 11.
AUXCLK shifts data into the device on the AUXIN pin and shifts data out of the device on the
AUXOUT pin. AUXCLK is typically connected to the serial audio data clock (SCLK) on an
external ADC or DAC.
Asynchronous Audio Port
FSYNC - Frame Synchronization Clock Input, PIN 23.
FSYNC transitions delineate left and right audio data, or the start of a data frame. Typically
used in compressed audio applications.
SCLK - Serial Clock Input, PIN 22.
SCLK is used to clock serial audio data into the device on SDATA. Typically used in
compressed audio applications.
SDATA - Serial Audio Data Input, PIN 21.
Audio data input to SDATA is clocked into the device by SCLK. Typically used in compressed
audio applications.
30
DS282PP2
CS4912
PARAMETER DEFINITIONS
Resolution
The number of bits in the audio input word of the DACs.
Differential Nonlinearity
The worst case deviation from the ideal code width; expressed in LSBs.
Total Harmonic Distortion (THD)
THD is the ratio of the test signal amplitude to the RMS sum of all the in-band harmonics of
the test signal.
Instantaneous Dynamic Range
The Signal-to-(Noise + Distortion) ratio (S/(N+D)) with a 1 kHz, -60 dB from full scale DAC
input signal, with 60 dB added to compensate for the small signal. Use of a small signal
reduces the harmonic distortion components of the noise to insignificant levels. Units are in dB.
Interchannel Isolation
The amount of 1 kHz signal present on the output of the grounded input channel with 1 kHz,
0 dB signal present on the other channel. Units are in dB.
Interchannel Gain Mismatch
The difference in output voltages for each channel with a full scale digital input. Units are in dB.
Frequency Response
Worst case variation in output signal level versus frequency over 10 Hz to 20 kHz. Units in dB.
Out of Band Energy
The ratio of the RMS sum of the energy from 0.46 Fs to 2.1 Fs compared to the RMS full-scale
signal value. Tested with a 48 kHz Fs, giving an out-of-band energy range of 22 kHz to
100 kHz.
DS282PP2
31
CS4912
PACKAGE DIMENSIONS
44L PLCC PACKAGE DRAWING
e
D2/E2
E1 E
B
D1
D
A1
A
INCHES
MILLIMETERS
DIM
A
A1
B
MIN
MAX
MIN
4.043
2.205
MAX
4.572
3.048
0.165
0.090
0.013
0.685
0.650
0.590
0.685
0.650
0.590
0.040
0.180
0.120
0.021
0.695
0.656
0.630
0.695
0.656
0.630
0.060
0.319
0.533
D
16.783
15.925
14.455
16.783
15.925
14.455
0.980
17.653
16.662
16.002
17.653
16.662
16.002
1.524
D1
D2
E
E1
E2
e
JEDEC # : MS-018
32
DS282PP2
• Notes •
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