CS49DV8C [CIRRUS]
32-bit Audio DSP Family; 32位音频DSP系列
| 型号： | CS49DV8C |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | 32-bit Audio DSP Family |
| 文件： | 总30页 (文件大小：537K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS49DV8C Data Sheet
FEATURES
• 32-bit Post-Processor Audio DSP supports Multichannel
Dolby® Volume
32-bit Dual Audio DSP Engine
featuring Multichannel Dolby® Volume
™
• Programmable through DSP Composer
• CS49DV8, supports up to 7.1 Channels of Dolby Volume
processing at 48 kHz, 44.1 kHz or 32 kHz.
The new CS49DV8C is the fastest time-to-market, mass-
production ready Multichannel Dolby Volume solution available.
The target applications for the CS49DV8C DSP are:
— Input Configurable for all input/output digital audio types
(I2S, LJ/RJ, and TDM)
— Soundbars
— 32-bit data path delivers uncompromised dynamic range
— 192 kHz capable integrated S/PDIF transmitter
— DAO can operate in master or slave mode (SCLK &
LRCLK)
— DTVs with Integrated Soundbars
— HDTV Stands/Furniture with Integrated Soundbars
— Automotive Head Units
— Automotive Outboard Amplifiers
— Blu-ray Disc® & DVD Receivers / HTiBs
• Integrated Clock Manager/PLL
— Capable of operating from a wide variety of external
crystals or external oscillators
• Input Fs Auto Detection, Reporting and Handling
• Sample rate conversion.
• Master & Slave Host Boot Capability via Serial Interface
• SPI interface capable of running up to 25 MHz during run
time
All of these applications and many more that use volume control
and are subject to playback from sources that do not have consis-
tent volume levels will benefit from the CS49DV8C Dolby Volume
solution.
• 1.8V Core and a 3.3V I/O that is tolerant to 5V input
Ordering Information
See page 27 for ordering information.
Serial
Control 1
Serial
Control 2
UART
GPIO
Debug
8 Ch. Audio In
STC
D
M
A
32-bit
DSP A
32-bit
DSP B
TMR1
TMR2
S/PDIF
S/PDIF
P
X
Y
P
X
Y
8 Ch PCM
Audio Out
PLL
Ext. Memory Controller
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Preliminary Product Information
Copyright 2008 Cirrus Logic (All Rights Reserved)
SEPT ‘08
DS868PP2
http://www.cirrus.com
CS49DV8C Data Sheet
32-bit Audio DSP Family
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
.
IMPORTANT NOTICE
“Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its sub-
sidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and
is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowl-
edgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, includ-
ing use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property
of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the informa-
tion only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as
copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPER-
TY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN
PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL
APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS
DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FIT-
NESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S
CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEM-
NIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS'
FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names in
this document may be trademarks or service marks of their respective owners.
Dolby is a registered trademarks of Dolby Laboratories, Inc. Dolby Volume is a trademark of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology
does not convey a license nor imply a right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in
any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories.
Motorola and SPI are trademarks of Motorola, Inc.
2
I C is a registered trademark of Philips Semiconductor.
Logic7 is a registered trademark of Harmon International Industries, Inc.
iPod is a registered trademark of Apple Computer, Inc.
Blu-ray and Blu-ray Disc are trademarks of SONY KABUSHIKI KAISHA CORPORATION .
2
Copyright 2008 Cirrus Logic, Inc.
DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
Table of Contents
1. Documentation Strategy .................................................................................................................5
2. Overview ..........................................................................................................................................5
2.1 Licensing .........................................................................................................................................................7
3. Firmware Supported .......................................................................................................................7
4. Hardware Functional Description .................................................................................................7
4.1 DSP Core ........................................................................................................................................................7
4.1.1 DSP Memory ......................................................................................................................................7
4.1.2 DMA Controller ...................................................................................................................................7
4.2 On-chip DSP Peripherals ................................................................................................................................8
4.2.1 Digital Audio Input Port (DAI) ..............................................................................................................8
4.2.2 Digital Audio Output Port (DAO) .........................................................................................................8
4.2.3 Serial Control Port 1 & 2 (I2C® or SPI™) ............................................................................................8
4.2.4 External Memory Interface .................................................................................................................8
4.2.5 GPIO ...................................................................................................................................................8
4.2.6 PLL-based Clock Generator ...............................................................................................................8
4.3 DSP I/O Description ........................................................................................................................................9
4.3.1 Multiplexed Pins .................................................................................................................................9
4.3.2 Termination Requirements ..................................................................................................................9
4.3.3 Pads ...................................................................................................................................................9
4.4 Application Code Security ...............................................................................................................................9
5. Characteristics and Specifications .............................................................................................10
5.1 Absolute Maximum Ratings ...........................................................................................................................10
5.2 Recommended Operating Conditions ...........................................................................................................10
5.3 Digital DC Characteristics .............................................................................................................................10
5.4 Power Supply Characteristics ....................................................................................................................... 11
5.5 Thermal Data (128-Pin LQFP) ...................................................................................................................... 11
5.6 Switching Characteristics— RESET ..............................................................................................................12
5.7 Switching Characteristics — XTI ...................................................................................................................13
5.8 Switching Characteristics — Internal Clock ...................................................................................................13
5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode ..............................................................14
5.10 Switching Characteristics — Serial Control Port - SPI Master Mode ..........................................................15
5.11 Switching Characteristics — Serial Control Port - I2C Slave Mode .............................................................16
5.12 Switching Characteristics — Serial Control Port - I2C Master Mode ...........................................................17
5.13 Switching Characteristics — UART .............................................................................................................18
5.14 Switching Characteristics — Digital Audio Slave Input Port ........................................................................19
5.15 Switching Characteristics — Digital Audio Output Port ...............................................................................20
5.16 Switching Characteristics — SDRAM Interface ...........................................................................................22
6. Ordering Information ....................................................................................................................27
7. Environmental, Manufacturing, and Handling Information ......................................................27
8. Device Pin-Out Diagram ...............................................................................................................28
8.1 128-Pin LQFP Pin-Out Diagram.................................................................................................................... 28
9. Package Mechanical Drawings ....................................................................................................29
9.1 128-Pin LQFP Package .................................................................................................................................29
10. Revision History ..........................................................................................................................30
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Copyright 2008 Cirrus Logic, Inc.
3
CS49DV8C Data Sheet
32-bit Audio DSP Family
List of Figures
Figure 1. RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. XTI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. Serial Control Port - SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Serial Control Port - SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. Serial Control Port - I2C Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Serial Control Port - I2C Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Digital Audio Input (DAI) Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Digital Audio Port Timing Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. External Memory Interface - SDRAM Burst Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. External Memory Interface - SDRAM Burst Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. External Memory Interface - SDRAM Auto Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. External Memory Interface - SDRAM Load Mode Register Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. 128-Pin LQFP Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. 128-Pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
List of Tables
Table 1. CS49DV8C Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Device and Firmware Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. CS49DV8C DSP Memory Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Environmental, Manufacturing, and Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6. 128-Pin LQFP Package Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4
Copyright 2008 Cirrus Logic, Inc.
DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
1. Documentation Strategy
The CS49DV8C data sheet describes the CS49DV8C family of multichannel audio DSPs. This
document should be used in conjunction with the following documents when evaluating or designing a
system around the CS49DV8C family of processors.
Table 1. CS49DV8C Related Documentation
Document Name
Description
CS49DV8C Data Sheet
This document
Detailed system design information including Typical
Connection Diagrams, boot-procedures, pin
descriptions, and other system configuration
information.
CS4953xx Hardware User’s Manual
Application note contains an Application
Programming Interface (API) used to control the
Dolby Volume firmware.
AN288PPH, “Dolby® Volume Module”
Includes detailed configuration and usage
information for the GUI development tool.
™
DSP Composer User’s Manual
The scope of the CS49DV8C Data Sheet is primarily the hardware specifications of the CS49DV8C
devices. This includes hardware functionality, characteristic data, pinout, and packaging information.
The intended audience for the CS49DV8C Data Sheet is the system PCB designer, MCU programmer,
and the quality control engineer.
2. Overview
The CS49DV8C DSP is designed to provide high-performance volume control using the Dolby Volume
algorithm. The CS49DV8, supports up to 7.1 Channels of Dolby Volume processing at 48 kHz, 44.1 kHz
or 32 kHz while leaving the 2nd core of the DSP completely available for even further processing
functions such as Quadruple Crossover Bass Management, Tone Control, and Multiband Parametric
EQ.
The CS49DV8C DSP, together with Cirrus Logic’s comprehensive library of audio processing algorithms,
enables the development of next-generation high-definition audio solutions. Cirrus Logic also provides a
broad array of digital interface products, and audio converters, to meet your audio system-level design
requirements.
The CS49DV8C is available in a 128-pin LQFP package.
Please refer to Table 2 on page 6 for the processor speed and available firmware for the CS49DV8C
product family.
DS868PP2
Copyright 2008 Cirrus Logic, Inc.
5
Table 2. Device and Firmware Selection Guide
Pre-
Process
Decode Processor A1
Mid-processor A1
Mid-processor B1
Post-processor1
• Tone Control
Device
• Re-EQ
• PEQ (up to 11 bands)
• Delay
• 7.1 Bass Manager
• Audio Manager
• 1:2 Upsampling
Dolby® Volume
(Runs on either DSP A or B)
See Section 3. for additional
concurrency information.
Dolby® Volume
(Runs on either DSP A or B)
See Section 3. for additional
concurrency information.
CS49DV8C
• Stereo PCM
• Multi-Channel PCM
(2:1 Downsampling Option)
(4:1 Downsampling Option)
300 MIPS
None
1. Processing may be restricted and dependent on firmware selected. Contact your Cirrus Logic FAE for concurrency matrix.
CS49DV8C Data Sheet
32-bit Audio DSP Family
2.1 Licensing
Licenses are required for Dolby Volume and for all of the third party audio processing algorithms. Please
contact your local Cirrus Sales representative for more information.
3. Firmware Supported
The suite of software available for the CS49DV8C family consists of operating systems (OS) and a
library of overlays. The overlays have been divided into three main groups called Decoders, Mid-
processors, and Post-processors. All software components are defined as follows:
• OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external
memory, processing host messages, calling audio-processing subroutines, auto-detection, error
concealment, etc.
• Dolby Volume - The CS49DV8C can run Dolby Volume on either DSP A or DSP B. On the DSP that
is not running Dolby Volume, it can run the firmware currently available on the CS4953xx family for
that DSP (A or B).
4. Hardware Functional Description
4.1 DSP Core
The CS49DV8C is a dual-core DSP with separate X and Y data and P code memory spaces. Each core
is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two
memory access control (MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four
X- and four Y-data registers, and 12 index registers.
Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between
peripherals such as the digital audio input (DAI) and digital audio output (DAO), external memory, or any
DSP core memory, all without the intervention of the DSP. The DMA engine offloads data move
instructions from the DSP core, leaving more MIPS available for signal processing instructions.
CS49DV8C functionality is controlled by application codes that are stored in on-board ROM or
downloaded to the CS49DV8C from a host MCU or external FLASH/EEPROM. Users can choose to use
standard audio post-processor modules which are available from Cirrus Logic.
4.1.1 DSP Memory
The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.
Table 3. CS49DV8C DSP Memory Sizes
Memory
DSP A
DSP B
Type
X
Y
P
16k SRAM, 32k ROM
24k SRAM, 32k ROM
8k SRAM, 32k ROM
10k SRAM, 8k ROM
16k SRAM, 16k ROM
8k SRAM, 24k ROM
4.1.2 DMA Controller
The powerful 12-channel DMA controller can move data between 8 on-chip resources. Each resource
has its own arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external
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Copyright 2008 Cirrus Logic, Inc.
7
CS49DV8C Data Sheet
32-bit Audio DSP Family
memory; and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start
address and increment controls. The service interval for each DMA channel as well as up to 6 interrupt
events, is programmable.
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI)
The 12-channel (6 line) DAI port supports a wide variety of data input formats. The port is capable of
accepting PCM or IEC61937. Up to 32-bit word lengths are supported. Additionally support is provided
for audio data input to the DSP via the DAI from an HDMI receiver.
The port has two independent slave-only clock domains. Each data input can be independently assigned
to a clock domain. The sample rate of the input clock domains can be determined automatically by the
DSP, which off-loads the task of monitoring the SPDIF receiver from the host. A time-stamping feature
allows the input data to be sample-rate converted via software.
4.2.2 Digital Audio Output Port (DAO)
There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports
data rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in
slave mode, or the ratio of the two clocks can be set to even multiples of each other in master mode. The
two ports can also be ganged together into a single clock domain. Each port has one serial audio pin that
can be configured as a 192 kHz SPDIF transmitter (data with embedded clock on a single line).
2
®
™
4.2.3 Serial Control Port 1 & 2 (I C or SPI )
There are two on-chip serial control ports that are capable of operating as master or slave in either I2C or
SPI modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an
external clock up to 25MHz in SPI mode. This high clock speed enables very fast code download,
control or data delivery. SCP2 defaults to master mode and is dedicated for booting from external serial
Flash memory or for audio sub-system control.
4.2.4 External Memory Interface
The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus.
4.2.5 GPIO
Many of the CS49DV8C peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an
output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge,
falling edge, active-low, or active-high.
4.2.6 PLL-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to
clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain
can be output on the DAO port for driving audio converters. The CS49DV8C defaults to running from the
external reference frequency and can be switched to use the PLL output after overlays have been
loaded and configured, either through master boot from an external FLASH or through host control. A
built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is
selectable between 1:1 (default) or 2:1.
8
Copyright 2008 Cirrus Logic, Inc.
DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
4.3 DSP I/O Description
4.3.1 Multiplexed Pins
Many of the CS49DV8C pins are multi-functional. For details on pin functionality please refer to the
CS4953xx Hardware User’s Manual.
4.3.2 Termination Requirements
Open-drain pins on the CS49DV8C must be pulled high for proper operation. Please refer to the
CS4953xx Hardware User’s Manual to identify which pins are open-drain and what value of pull-up
resistor is required for proper operation.
Mode select pins on the CS49DV8C are used to select the boot mode upon the rising edge of reset. A
detailed explanation of termination requirements for each communication mode select pin can be found
in the CS4953xx Hardware User’s Manual.
4.3.3 Pads
The CS49DV8C I/O operates from the 3.3 V supply and is 5 V tolerant.
4.4 Application Code Security
The external program code may be encrypted by the programmer to protect any intellectual property it
may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored
external to the device.
DS868PP2
Copyright 2008 Cirrus Logic, Inc.
9
CS49DV8C Data Sheet
32-bit Audio DSP Family
5. Characteristics and Specifications
Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and temperature. All
data sheet typical parameters are measured under the following conditions: T = 25 °C, CL = 20 pF, VDD = 1.8 V,
VDDA = VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.
5.1 Absolute Maximum Ratings
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
Parameter
Symbol
Min
Max
Unit
DC power supplies:
Core supply
PLL supply
I/O supply
VDD
VDDA
VDDIO
–0.3
–0.3
–0.3
-
2.0
3.6
3.6
0.3
V
V
V
V
|VDDA – VDDIO|
Input pin current, any pin except supplies
Input voltage on PLL_REF_RES
Input voltage on I/O pins
Iin
-
+/- 10
3.6
mA
V
Vfilt
Vinio
Tstg
-0.3
-0.3
–65
5.0
V
Storage temperature
150
°C
Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not
guaranteed at these extremes.
5.2 Recommended Operating Conditions
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
DC power supplies:
Core supply
PLL supply
I/O supply
VDD
VDDA
VDDIO
1.71
3.13
3.13
1.8
3.3
3.3
0
1.89
3.46
3.46
V
V
V
V
|VDDA – VDDIO|
Ambient operating temperature
Commercial Grade (CVZ/CVZR)
TA
0
+25
+ 70
°C
Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.
5.3 Digital DC Characteristics
(Measurements performed under static conditions.)
Parameter
High-level input voltage
Symbol
VIH
Min
Typ
Max
-
Unit
V
2.0
-
-
Low-level input voltage, except XTI
Low-level input voltage, XTI
Input Hysteresis
VIL
-
-
0.8
0.6
V
VILXTI
Vhys
-
V
0.4
-
V
High-level output voltage (IO = -4mA), except XTI,
SDRAM pins
VOH
VDDIO * 0.9
-
-
V
Low-level output voltage (IO = 4mA), except XTI,
SDRAM pins
VOL
-
VDDIO * 0.1
V
SDRAM High-level output voltage (IO = -8mA)
SDRAM Low-level output voltage (IO = 8mA)
VOH
VOL
IIN
VDDIO * 0.9
-
-
-
-
V
V
-
-
VDDIO * 0.1
5
Input leakage current (all digital pins with internal
pull-up resistors disabled)
μA
10
Copyright 2008 Cirrus Logic, Inc.
DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
Parameter
Symbol
Min
Typ
Max
Unit
Input leakage current (all digital pins with internal
pull-up resistors enabled, and XTI)
IIN-PU
-
-
50
μA
5.4 Power Supply Characteristics
(Measurements performed under operating conditions.)
Parameter
Min
Typ
Max
Unit
Power supply current:
Core and I/O operating: VDD1
PLL operating: VDDA
With external memory and most ports operating: VDDIO
-
-
-
500
3.5
120
-
-
-
mA
mA
mA
1.Dependent on application firmware and DSP clock speed.
5.5 Thermal Data (128-Pin LQFP)
Parameter
Symbol
Min
Typ
Max
Unit
Thermal Resistance (Junction to Ambient)
Two-layer Board1
θja
°C / Watt
-
-
48
40
-
-
Four-layer Board2
Thermal Resistance (Junction to Top of Package)
Two-layer Board1
ψjt
°C / Watt
-
-
.39
.33
-
-
Four-layer Board2
Notes: 1.Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20% of the top
and bottom layers.
2.Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20% of the top
and bottom layers and 0.5-oz copper covering 90% of the internal power plane and ground plane layers.
3.To calculate the die temperature for a given power dissipation
Τj = Ambient Temperature + [ (Power Dissipation in Watts) * θja
]
4.To calculate the case temperature for a given power dissipation
Τc = Τj - [ (Power Dissipation in Watts) * ψjt ]
DS868PP2
Copyright 2008 Cirrus Logic, Inc.
11
CS49DV8C Data Sheet
32-bit Audio DSP Family
5.6 Switching Characteristics— RESET
Parameter
Symbol
Trstl
Min
1
Max
Unit
μs
RESET minimum pulse width low
-
All bidirectional pins high-Z after RESET low
Configuration pins setup before RESET high
Configuration pins hold after RESET high
Trst2z
Trstsu
Trsthld
-
100
ns
50
20
-
-
ns
ns
RESET#
HS[3:0]
All Bidirectional
Pins
Trstsu
Trsthld
Trst2z
Trstl
Figure 1. RESET Timing
12
Copyright 2008 Cirrus Logic, Inc.
DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
5.7 Switching Characteristics — XTI
Parameter
External Crystal operating frequency1
XTI period
Symbol
Fxtal
Min
11.2896
33.3
Max
27
100
-
Unit
MHz
ns
Tclki
XTI high time
Tclkih
Tclkil
13.3
ns
XTI low time
13.3
-
ns
External Crystal Load Capacitance (parallel resonant)2
CL
10
18
50
pF
External Crystal Equivalent Series Resistance
ESR
W
1. Part characterized with the following crystal frequency values: 11.2896, 12.288, 18.432, 24.576, and 27
MHz.
2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a
CL outside this range should be avoided. The crystal oscillator circuit design should follow the crystal
manufacturer’s recommendation for load capacitor selection.
XTI
tclkih
tclkil
Tclki
Figure 2. XTI Timing
5.8 Switching Characteristics — Internal Clock
Parameter
Symbol
Min
Max
Unit
Internal DCLK frequency1
CS49DV8C-CVZ
Fdclk
MHz
Fxtal
150
CS49DV8C-CVZR
Internal DCLK period1
CS49DV8C-CVZ
DCLKP
ns
6.7
1/Fxtal
CS49DV8C-CVZR
1.After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains
locked until the next power-on reset.
DS868PP2
Copyright 2008 Cirrus Logic, Inc.
13
CS49DV8C Data Sheet
32-bit Audio DSP Family
5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode
.
Parameter
SCP_CLK frequency1
Symbol
fspisck
tspicss
tspickl
Min
-
Typical
Max
Units
MHz
ns
25
-
SCP_CS falling to SCP_CLK rising
SCP_CLK low time
24
20
20
5
-
ns
SCP_CLK high time
tspickh
tspidsu
tspidh
-
ns
Setup time SCP_MOSI input
-
ns
Hold time SCP_MOSI input
5
-
ns
SCP_CLK low to SCP_MISO output valid
SCP_CLK falling to SCP_IRQ rising
SCP_CS rising to SCP_IRQ falling
SCP_CLK low to SCP_CS rising
SCP_CS rising to SCP_MISO output high-Z
SCP_CLK rising to SCP_BSY falling
tspidov
tspiirqh
tspiirql
-
11
20
ns
-
ns
0
ns
tspicsh
tspicsdz
tspicbsyl
24
-
-
ns
20
ns
-
3 DCLKP+20
*
ns
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the
actual maximum speed of the communication port may be limited by the firmware application. Flow control using the
SCP_BSY pin should be implemented to prevent overflow of the input data buffer.At boot the maximum speed is
Fxtal/3.
tspicss
SCP_CS
tspickl
tspicsh
0
1
2
6
7
0
5
6
7
SCP_CLK
SCP_MOSI
SCP_MISO
SCP_IRQ
SCP_BSY
fspisck
tspickh
A6
A5
A0
R/W
MSB
MSB
LSB
LSB
tspidsu
tspidh
tspidov
tspicsdz
tspiirqh
tspiirql
tspibsyl
Figure 3. Serial Control Port - SPI Slave Mode Timing
Copyright 2008 Cirrus Logic, Inc.
14
DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
5.10 Switching Characteristics — Serial Control Port - SPI Master Mode
Parameter
SCP_CLK frequency1
Symbol Min
Typical
Max
Units
fspisck
-
Fxtal/2 (See MHz
Footnote 2)
SCP_CS falling to SCP_CLK rising 3
tspicss
-
11*DCLKP +
-
ns
(SCP_CLK PERIOD)/2
SCP_CLK low time
tspickl
tspickh
tspidsu
tspidh
18
18
11
5
-
-
ns
ns
ns
ns
ns
ns
ns
SCP_CLK high time
Setup time SCP_MISO input
Hold time SCP_MISO input
SCP_CLK low to SCP_MOSI output valid
SCP_CLK low to SCP_CS falling
SCP_CLK low to SCP_CS rising
-
-
tspidov
tspicsl
tspicsh
-
11
-
7
-
11*DCLKP +
-
(SCP_CLK PERIOD)/2
Bus free time between active SCP_CS
tspicsx
tspidz
3*DCLKP
-
ns
ns
SCP_CLK falling to SCP_MOSI output high-Z
-
20
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be
aware that the actual maximum speed of the communication port may be limited by the firmware
application.
2. See Section 5.7.
3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer
to a tested parameter.
tspicsx
tspicss
EE_CS
tspickl
tspicsh
tspicsl
1
2
6
7
0
7
0
5
6
SCP_CLK
SCP_MISO
SCP_MOSI
fspisck
tspickh
A6
A5
A0
R/W
MSB
MSB
LSB
LSB
tspidsu
tspidh
tspidov
tspidz
Figure 4. Serial Control Port - SPI Master Mode Timing
Copyright 2008 Cirrus Logic, Inc.
DS868PP2
15
CS49DV8C Data Sheet
32-bit Audio DSP Family
2
5.11 Switching Characteristics — Serial Control Port - I C Slave Mode
Parameter
SCP_CLK frequency1
Symbol Min
Typical
Max
Units
kHz
µs
fiicck
tiicckl
tiicckh
-
400
SCP_CLK low time
SCP_CLK high time
1.25
1.25
-
-
µs
SCP_SCK rising to SCP_SDA rising or falling for
START or STOP condition
tiicckcmd 1.25
µs
START condition to SCP_CLK falling
SCP_CLK falling to STOP condition
tiicstscl
tiicstp
tiicbft
1.25
2.5
3
-
-
-
µs
µs
µs
ns
ns
ns
ns
ns
ns
Bus free time between STOP and START conditions
Setup time SCP_SDA input valid to SCP_CLK rising
Hold time SCP_SDA input after SCP_CLK falling
SCP_CLK low to SCP_SDA out valid
SCP_CLK falling to SCP_IRQ rising
tiicsu
100
20
-
tiich
-
tiicdov
tiicirqh
tiicirql
tiicbsyl
18
-
3 DCLKP + 40
*
NAK condition to SCP_IRQ low
3 DCLKP + 20
*
SCP_CLK rising to SCB_BSY low
-
3 DCLKP + 20
*
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the
actual maximum speed of the communication port may be limited by the firmware application. Flow control using the
SCP_BSY pin should be implemented to prevent overflow of the input data buffer.
tiicckcmd
tiicckl
tiicr
tiicf
tiicckcmd
0
1
6
7
8
0
1
6
7
8
SCP_CLK
SCP_SDA
SCP_IRQ
SCP_BSY
tiicstp
tiicstscl
tiicckh
tiicdov
R/W
fiicck
tiicbft
A6
A0
ACK
MSB
ACK
LSB
tiicirqh
tiicirql
tiicsu
tiich
tiiccbsyl
Figure 5. Serial Control Port - I2C Slave Mode Timing
16
Copyright 2008 Cirrus Logic, Inc.
DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
2
5.12 Switching Characteristics — Serial Control Port - I C Master Mode
Parameter
Symbol
fiicck
Min
-
Max
Units
kHz
µs
SCP_CLK frequency1
SCP_CLK low time
SCP_CLK high time
400
tiicckl
1.25
1.25
1.25
-
-
tiicckh
µs
SCP_SCK rising to SCP_SDA rising or falling for START or
STOP condition
tiicckcmd
µs
START condition to SCP_CLK falling
tiicstscl
tiicstp
tiicbft
tiicsu
tiich
1.25
2.5
3
-
-
-
µs
µs
µs
ns
ns
ns
SCP_CLK falling to STOP condition
Bus free time between STOP and START conditions
Setup time SCP_SDA input valid to SCP_CLK rising
Hold time SCP_SDA input after SCP_CLK falling
SCP_CLK low to SCP_SDA out valid
100
20
-
-
tiicdov
18
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the
actual maximum speed of the communication port may be limited by the firmware application.
tiicckcmd
tiicckl
tiicr
tiicf
tiicckcmd
0
1
6
7
8
0
1
6
7
8
SCP_CLK
SCP_SDA
tiicstp
tiicstscl
tiicckh
tiicdov
R/W
fiicck
tiicbft
A6
A0
ACK
MSB
ACK
LSB
tiicsu
tiich
Figure 6. Serial Control Port - I2C Master Mode Timing
DS868PP2
Copyright 2008 Cirrus Logic, Inc.
17
CS49DV8C Data Sheet
32-bit Audio DSP Family
5.13 Switching Characteristics — UART
Parameter
UART_CLK period1
Symbol
tuclki
Min
266
40
5
Max
Unit
ns
-
60
-
UART_CLK duty cycle
-
%
Setup time for UART_RXD
tuckrxsu
tuckrxdv
tucktxdv
Hold time for UART_RXD
5
-
ns
ns
Delay from CLK transition to TXD transition
-
29
1. The minimum clock period is limited to DCLKP/32 or the minimum value, whichever is larger.
UART_CLK
tucktxdv
ttxen
ttxhz
UART_TXD
tuckrxsu
tuckrxdv
UART_RXD
UART_TX_EN
Figure 7. UART Timing
18
Copyright 2008 Cirrus Logic, Inc.
DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
5.14 Switching Characteristics — Digital Audio Slave Input Port
Parameter
Symbol
Tdaiclkp
-
Min
40
45
10
5
Max
Unit
ns
DAI_SCLK period
-
55
-
DAI_SCLK duty cycle
Setup time DAI_DATAn
Hold time DAI_DATAn
%
tdaidsu
tdaidh
ns
-
ns
DAI_SCLK
tdaidsu
tdaidh
DAI_DATAn
Figure 8. Digital Audio Input (DAI) Port Timing Diagram
DS868PP2
Copyright 2008 Cirrus Logic, Inc.
19
CS49DV8C Data Sheet
32-bit Audio DSP Family
5.15 Switching Characteristics — Digital Audio Output Port
Parameter
Symbol
Min
40
Max
-
Unit
ns
DAO_MCLK period
Tdaomclk
DAO_MCLK duty cycle
-
45
55
-
%
DAO_SCLK period for Master or Slave mode1
DAO_SCLK duty cycle for Master or Slave mode1
Master Mode (Output A1 Mode)1,2
Tdaosclk
-
40
ns
40
60
%
DAO_SCLK delay from DAO_MCLK rising edge,
DAO_MCLK as an input
tdaomsck
-
19
ns
DAO_LRCLK delay from DAO_SCLK transition, respectively3
DAO_SCLK delay from DAO_LRCLK transition, respectively3
tdaomstlr
tdaomlrts
tdaomdv
-
-
-
8
8
ns
ns
ns
DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition3
10
Slave Mode (Output A0 Mode)4
DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition3
tdaosdv
-
15
ns
DAO_LRCLK delay from DAO_SCLK transition, respectively3
DAO_SCLK delay from DAO_LRCLK transition, respectively3
tdaosstlr
tdaoslrts
-
-
30
15
ns
ns
1.Master mode timing specifications are characterized, not production tested.
2.Master mode is defined as the CS49DVxx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided
to produce DAO_SCLK, DAO_LRCLK.
3.This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point
at which the data is valid.
4.Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
tdaomlclk
tdaomclk
DAO_MCLK
DAO_SCLK
DAO_MCLK
DAO_SCLK
tdaomsck
tdaomsck
tdaomdv
DAOn_DATAn
DAO_LRCLK
DAOn_DATAn
tdaomlrts
tdaomstlr
DAO_LRCLK
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK
Figure 9. Digital Audio Port Timing Master Mode
20
Copyright 2008 Cirrus Logic, Inc.
DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
tdaosclk
tdaosstlr
DAO_LRCLK
DAO_SCLK
DAO_LRCLK
DAO_SCLK
tdaosclk
tdaoslrts
DAOn_DATAn
tdaosdv
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK
Figure 10. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)
DS868PP2
Copyright 2008 Cirrus Logic, Inc.
21
CS49DV8C Data Sheet
32-bit Audio DSP Family
5.16 Switching Characteristics — SDRAM Interface
Refer to Figure 11 through Figure 14.
(SD_CLKOUT = SD_CLKIN)
Parameter
SD_CLKIN high time
Symbol
tsdclkh
tsdclkl
Min
2.3
2.3
-
Typical
Max
Unit
ns
-
-
SD_CLKIN low time
ns
SD_CLKOUT rise/fall time
tsdclkrf
1
ns
SD_CLKOUT Frequency
150
MHz
%
SD_CLKOUT duty cycle
-
45
-
55
SD_CLKOUT rising edge to signal valid
Signal hold from SD_CLKOUT rising edge
SD_CLKOUT rising edge to SD_DQMn valid
SD_DQMn hold from SD_CLKOUT rising edge
SD_DATA valid setup to SD_CLKIN rising edge
SD_DATA valid hold to SD_CLKIN rising edge
SD_CLKOUT rising edge to ADDRn valid
tsdcmdv
tsdcmdh
tsddqv
tsddqh
tsddsu
tsddh
3.8
ns
1.1
3.8
-
-
-
-
-
-
ns
-
ns
1.38
1.3
1.38
-
ns
ns
ns
tsdav
3.8
ns
22
Copyright 2008 Cirrus Logic, Inc.
DS868PP2
SD_CLKOUT
SD_CS
tsdclkrf
tsdcmdv
tsdcmdh
SD_RAS
SD_CAS
SD_WE
tsddqh
tsddqv
SD_DQMn
11
00
SD_An
tsdav
tsddsu
tsddh
CAS=2
LSP1
MSP1
LSP2
MSP2
SD_Dn
LSP0
MSP0
LSP3
MSP3
SD_CLKIN
tsdclkl
tsdclkh
Figure 11. External Memory Interface - SDRAM Burst Read Cycle
SD_CLKOUT
tsdcmdv
tsdcmdh
SD_CS
SD_RAS
SD_CAS
SD_WE
LSP0
MSP0
LSP1
MSP1
LSP2
MSP2
LSP3
MSP3
SD_Dn
SD_An
tsdav
SD_DQMn
00
11
tsddqv
tsddqh
Figure 12. External Memory Interface - SDRAM Burst Write Cycle
SD_CLKOUT
tsdcmdv
tsdcmdv
tsdcmdh
SD_CS
SD_RAS
SD_CAS
SD_WE
SD_DQMn
SD_ADDRn
SD_DATAn
Figure 13. External Memory Interface - SDRAM Auto Refresh Cycle
SD_CLKOUT
tsdcmdv
tsdcmdh
SD_CS
SD_RAS
SD_CAS
SD_WE
SD_DQMn
SD_ADDRn
SD_DATAn
OPCODE
Figure 14. External Memory Interface - SDRAM Load Mode Register Cycle
CS49DV8C Data Sheet
32-bit Audio DSP Family
6. Ordering Information
The CS49DV8C family part number is described as follows:
CS49DVNNI-XYZ
where
NN - Product Number Variant
I - ROM ID Number
X - Product Grade
Y - Package Type
Z - Lead (Pb) Free
Table 4. Ordering Information
Part No.
Grade
Temp. Range
Container
Package
CS49DV8C-CVZ
CS49DV8C-CVZR
Commercial
Commercial
0 to +70 °C
0 to +70 °C
Tray
Reel
128-pin LQFP
7. Environmental, Manufacturing, and Handling Information
Table 5. Environmental, Manufacturing, and Handling Information
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
CS49DV8C-CVZ
CS49DV8C-CVZR
260 °C
260 °C
3
3
7 Days
7 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
27
Copyright 2008 Cirrus Logic, Inc.
DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
8. Device Pin-Out Diagram
8.1 128-Pin LQFP Pin-Out Diagram
1
5
SD_A0, EXT_A0
SD_A1, EXT_A1
GPIO38, PCP_WR# / DS#, SCP2_CLK
GPIO11, PCP_A3, AS#, SCP2_MISO / SDA
100
GPIO10, PCP_A2 / A10, SCP2_MOSI
VDDIO5
SD_A2, EXT_A2
GPOI9, SCP1_IRQ#
GND4
GPIO8, PCP_IRQ#, SCP2_IRQ#
SD_A3, EXT_A3
SD_A4, EXT_A4
GPIO7, SCP1_CS#, IOWAIT
GPIO6, PCP_CS#, SCP2_CS#
95 VDD4
EXT_CS2#
VDDIO7
GNDIO7
SD_A5, EXT_A5
GNDIO4
10
15
20
25
30
35
GPIO3, DDAC
GPIO2, UART_TXD
SD_A6, EXT_A6
90 SD_A7, EXT_A7
VDDIO4
VDD7
GPIO1, UART_RXD
GPIO0, UART_CLK
SD_A8, EXT_A8
SD_A9, EXT_A9
GND3
GND7
XTAL_OUT
XTI
85 SD_A11, EXT_A11
SD_A12, EXT_A12
VDD3
XTO
GNDA
128-Pin LQFP
PLL_REF_RES
SD_CLKEN
VDDA (3.3V)
SD_CLKIN
VDD8
80 SD_CLKOUT
SD_DQM1
GPIO14, DAI1_DATA3, TM3, DSD3
GPIO13, DAI1_DATA2, TM2, DSD2
GND8
SD_D8, EXT_D8
SD_D9, EXT_D9
GNDIO3
GPIO12, DAI1_DATA1, TM1, DSD1
DAI1_DATA0, TM0, DSD0
VDDIO8
75 SD_D10, EXT_D10
SD_D11, EXT_D11
VDDIO3
DAI1_SCLK, DSD-CLK
DAI1_LRCLK, DSD4
SD_D12, EXT_D12
SD_D13, EXT_D13
70 SD_D14, EXT_D14
SD_D15, EXT_D15
SD_D0, EXT_D0
GNDIO8
GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY#
GPIO43, BDI_CLK, DAI2_SCLK
BDI_DATA, DAI2_DATA, DSD5
GPIO26, DAO2_DATA3 / XMTB/UART_TX_EN
GNDIO2
DBDA
DBCK
EXT_WE#
65 SD_D1, EXT_D1
GPIO20, DAO2_DATA2, EE_CS#
Figure 15. 128-Pin LQFP Pin-Out
Copyright 2008 Cirrus Logic, Inc.
28
DS868PP2
CS49DV8C Data Sheet
32-bit Audio DSP Family
9. Package Mechanical Drawings
9.1 128-Pin LQFP Package
D
D1
E1
E
1
e
b
∝
A
A1
L
Figure 16. 128-Pin LQFP Package Drawing
Table 6. 128-Pin LQFP Package Characteristics
MILLIMETERS
INCHES
NOM
DIM
MIN
NOM
MAX
MIN
MAX
A
A1
b
---
---
1.60
0.15
0.27
---
---
---
.063”
.006”
.011”
0.05
0.17
---
.002”
.007”
0.22
.009”
.866”
.787”
.630”
.551”
.020”
3.5
D
22.00 BSC
20.00 BSC
16.00 BSC
14.00 BSC
0.50 BSC
3.5
D1
E
E1
e
q
0°
7°
0°
7°
L
0.45
0.60
0.75
.018”
.024”
.039” REF
.030”
L1
1.00 REF
TOLERANCES OF FORM AND POSITION
ddd
0.08
.003”
DS868PP2
Copyright 2008 Cirrus Logic, Inc.
29
CS49DV8C Data Sheet
32-bit Audio DSP Family
10. Revision History
Revision
PP1
Date
Changes
September 2, 2008
September 25, 2008
Initial Release.
PP2
Removed references to External Parallel Flash / SRAM Interface.
30
Copyright 2008 Cirrus Logic, Inc.
DS868PP2
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