CS5471-BS [CIRRUS]
DUAL CHANNEL DELTA SIGMA ANALOG TO DIGITAL CONVERTER; 双通道Δ-Σ模数转换器
| 型号： | CS5471-BS |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | DUAL CHANNEL DELTA SIGMA ANALOG TO DIGITAL CONVERTER |
| 文件： | 总14页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS5471
Dual-Channel Delta-Sigma Analog-to-Digital Converter
Features
Description
The CS5471 is a highly integrated Delta-Sigma (∆Σ) An-
alog-to-Digital Converter (ADC) developed for the Power
Measurement Industry. The CS5471 combines two ∆Σ
ADCs, decimation filters, and a serial interface on a sin-
gle chip. The CS5471 interfaces directly to a current
transformer or shunt to measure current, and resistive
divider or transformer to measure voltage. The product
features a serial interface for communication with a mi-
cro-controller or DSP. The product is initialized and fully
functional upon reset, and includes a Voltage Reference.
l Synchronous Sampling
l On-chip 1.2 V Reference (25 ppm/°C typ.)
l Power Supply Configurations:
– VA+ = +3 V; VA- = -2 V; VD+ = +3 V
– Supply tolerances 10%
l Power Consumption
– 10 mW Typical at VD+ = +3 V
l Simple Four-wire Serial Interface
l Charge Pump Driver output generates
negative power supply.
l Ground-Referenced Bipolar Inputs
ORDERING INFORMATION:
CS5471-BS -40°C to +85°C
20-pin SSOP
VA+
RESET
VD+
SE
GAIN
OWRS
SDO
∆Σ
x1, 20
IIN
IIN
4th Order
2nd Order
Modulator
∆Σ
Modulator
+
-
Decimation Filter
Decimation Filter
Serial
Interface
VIN
VIN
+
-
x1
FSO
SCLK
x1
VREFIN
Voltage
Reference
Pulse Output
Regulator
VREFOUT
CPD
CLOCK
XIN
AGND
VA-
DGND
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Preliminary Product Information
Copyright Cirrus Logic, Inc. 2001
JUL ‘01
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
(All Rights Reserved)
DS480PP5
1
CS5471
TABLE OF CONTENTS
3. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 3
ANALOG CHARACTERISTICS................................................................................................ 3
DIGITAL CHARACTERISTICS................................................................................................. 4
RECOMMENDED OPERATING CONDITIONS ....................................................................... 5
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5
SWITCHING CHARACTERISTICS .......................................................................................... 6
4. GENERAL DESCRIPTION ....................................................................................................... 7
4.1 Theory of Operation ........................................................................................................... 7
4.2 Performing Measurements ................................................................................................. 7
4.3 High Rate Digital Filters ..................................................................................................... 8
4.4 Serial Interface ................................................................................................................... 8
4.5 System Initialization ........................................................................................................... 9
4.6 Analog Inputs ..................................................................................................................... 9
4.7 Voltage Reference ............................................................................................................. 9
4.8 Using the Charge Pump Drive Pin ..................................................................................... 9
4.9 PCB Layout ...................................................................................................................... 10
5. PIN DESCRIPTION.................................................................................................................. 11
6. PACKAGE DIMENSIONS........................................................................................................ 13
LIST OF FIGURES
Figure 1. Serial Port Timing............................................................................................................. 6
Figure 2. Typical Connection Diagram............................................................................................ 7
Figure 3. Serial Port Data Transfer ................................................................................................. 8
Figure 4. Close-up of One Frame.................................................................................................... 9
Figure 5. Generating VA- with a Charge Pump............................................................................. 10
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales/cfm
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
2
CS5471
1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = -40 °C to +85 °C; +2.7V < VA+ < +3.5V; +2.7V < VD+ < +3.5V;
VA- = -2 V 10%; External VREF+ = 1.2 V; XIN = 4.000 MHz; AGND, DGND = 0.0V.) (See Notes 1 and 2)
Parameter
Accuracy (All Channels)
Symbol
Min
Typ
Max
Unit
Total Harmonic Distortion
THD
74
80
VA-
-
-
-
dB
dB
V
Common Mode Rejection
Common Mode + Signal on Input
Input Sampling Rate
(DC, 50, 60 Hz) CMRR
-
-
-
VA+
-
XIN/4
Hz
Analog Inputs (Current Channel)
Differential Input Voltage Range
[ (vIIN+) - (vIIN-) ]
Gain=20
Gain=1
IIN
-
-
40
800
-
-
mV
mV
Bipolar Offset
Gain=20 VOS
Gain=1 VOS
-
-
0.500
10
1
20
mV
mV
Crosstalk (Channel-to-Channel)
Input Capacitance
(50, 60 Hz)
-
-
-120
dB
Gain=20
Gain=1
IC
IC
-
-
-
-
20
1
pF
pF
Effective Input Impedance
(Note 3)
Gain=20
Gain=1
EII
EII
50
-
-
-
kΩ
kΩ
500
600
Noise (Referred to Input)
0-60 Hz
-
-
-
µVrms
µVrms
µVrms
µVrms
µVrms
µVrms
Gain=20
Gain=1
Gain=20
Gain=1
Gain=20
Gain=1
1
20
2.5
50
3.75
75
0-1 kHz
0-2 kHz
Analog Inputs (Voltage Channel)
Differential Input Voltage Range
[ (vVIN+) - (vVIN-) ]
VIN
800
-
mV0-pk
Bipolar Offset
Gain=1 VOS
(50, 60 Hz)
-
-
-
-
20
-
25
-120
0.2
4
mV
dB
Crosstalk with Current Channel
Input Capacitance
IC
-
pF
Effective Input Impedance
(Note 3)
EII
3
MΩ
Noise (Referred to Input)
0-60 Hz
0-1 kHz
-
-
-
-
-
-
20
50
75
µVrms
µVrms
µVrms
0-2 kHz
Dynamic Characteristics
High Rate Filter Output Word Rate
OWRS = “0” OWR
OWRS = “1” OWR
-
-
XIN/2048
XIN/1024
-
-
Hz
Hz
Notes: 1. Specifications guaranteed by design, characterization, and/or test.
2. Analog signals are relative to AGND and digital signals to DGND unless otherwise noted.
3. Effective Input Impedance (EII) varies with clock frequency (XIN) and Input Capacitance (IC)
EII = 1/(IC*XIN/4)
3
CS5471
ANALOG CHARACTERISTICS (Continued)
Parameter
Symbol
Min
Typ
Max
Unit
Reference Output
Output Voltage
REFOUT
1.15
-
20
6
1.25
50
10
-
V
ppm/°C
mV
Temperature Coefficient
-
-
Load Regulation
(Output Current 1µA Source or Sink)
∆VR
PSRR
Power Supply Rejection
Reference Input
60
-
dB
Input Voltage Range
Input Capacitance
Input CVF Current
Power Supplies
VREF+
1.15
1.2
1.25
10
1
V
-
-
-
-
pF
µA
Power Supply Currents
IA+
ID+
PSCA
PSCD
-
-
-
-
1.5
2.5
mA
mA
Power Consumption
(Note 4)
PC
-
-
-
15
-
mW
dB
Power Supply Rejection
(see Note 5)
(DC, 50, 60 Hz)
PSRR
60
Notes: 4. All outputs unloaded. All inputs CMOS level.
5. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3V, AGND = DGND = 0V, VA- = -2V
(using charge-pump circuit with CPD). In addition, a 106.07 mV rms (60 Hz) sinewave is imposed onto
the VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to VA-.
Instantaneous digital output data words are then collected for the channel under test. From these data
samples, the rms value (standard deviation) of the digital sinusoidal output signal is calculated, and this
rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need
to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage
is then defined as Veq. PSRR is then (in dB)
106.07
---------------
PSRR = 20 ⋅ log
Veq
DIGITAL CHARACTERISTICS (TA = -40 °C to +85 °C; +2.7V < VA+ < +3.5V; +2.7V < VD+ < +3.5V;
VA- = -2 V 10%; AGND, DGND = 0.0 V) (See Note 6)
Parameter
Symbol
VIH
Min
0.6 VD+
0.0
Typ
Max
VD+
0.8
-
Unit
V
High-Level Input Voltage
Low-Level Input Voltage
-
-
-
VIL
V
High-Level Output Voltage
Low-Level Output Voltage
I
out = -5.0 mA
Iout = 5.0 mA
(Note 7)
VOH
(VD+) - 1.0
V
VOL
-
-
0.4
V
Input Leakage Current
Iin
-
-
-
1
-
10
10
-
µA
µA
pF
3-State Leakage Current
Digital Output Pin Capacitance
IOZ
Cout
9
Notes: 6. All measurements performed under static conditions.
7. For OWRS and GAIN pins, input leakage current is 30 µA (Max).
4
CS5471
RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0.0 V)
Parameter
Symbol
Min
Typ
Max
Unit
DC Power Supplies
Positive Digital
Positive Analog
Negative Analog
VD+
VA+
VA-
2.7
2.7
-2.2
3.0
3.0
-2.0
3.5
3.5
-1.8
V
V
V
Voltage Reference Input
VREF+
-
1.2
-
V
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0.0 V; See Note 8.)
Parameter
Symbol
Min
Typ
Max
Unit
DC Power Supplies
Positive Digital
Positive Analog
Negative Analog
VD+
VA+
VA-
-0.3
-0.3
-2.5
-
-
+3.5
+3.5
-0.3
V
V
V
Input Current, Any Pin Except Supplies
Output Current
(Note 9 and 10)
IIN
-
-
-
-
-
-
-
-
10
25
mA
mA
mW
V
IOUT
PDN
VINA
VIND
TA
-
-
Power Dissipation
(Note 11)
All Analog Pins
All Digital Pins
500
Analog Input Voltage
VA- - 0.3
-0.3
-40
(VA+) + 0.3
(VD+) + 0.3
85
Digital Input Voltage
V
Ambient Operating Temperature
Storage Temperature
°C
°C
Tstg
-65
150
Notes: 8. All voltages with respect to AGND.
9. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins.
10. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power
supply pin is 50 mA.
11. Total power dissipation, including all input currents and output currents.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
5
CS5471
SWITCHING CHARACTERISTICS (TA = -40 °C to +85 °C; VA+, VD+ = 3.0 V 10%; VA- = -2 V
10%; DGND = AGND = 0.0 V; Logic Levels: Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50pF))
Parameter
Symbol
Min
3
Typ
4.000
-
Max
5
Unit
MHz
%
Master Clock Frequency
Master Clock Duty Cycle
Rise Times
(Note 12)
XIN
-
40
60
Any Digital Input (Note 13)
Any Digital Output
trise
-
-
-
50
1.0
-
µs
ns
Fall Times
Any Digital Input (Note 13)
Any Digital Output
tfall
-
-
-
50
1.0
-
µs
ns
Serial Port Timing
Serial Clock Frequency
(Note 12)
OWRS = “0”
OWRS = “1”
SCLK
SCLK
-
-
500
1000
-
-
kHz
kHz
Serial Clock
Pulse Width High (Note 12)
Pulse Width Low (Note 12)
t1
t2
-
-
0.5
0.5
-
-
SCLK
SCLK
SCLK falling to New Data Bit
FSO Falling to SCLK Rising Delay
FSO Pulse Width
t3
t4
t5
t6
t7
-
-
-
-
-
-
0.5
1
50
-
ns
SCLK
SCLK
ns
(Note 12)
(Note 12)
-
SE Rising to Output Enabled
SE Falling to Output in Tri-state
-
50
50
-
ns
Notes: 12. Device parameters are specified with a 4.000 MHz clock, OWRS = 1.
13. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
MSB(V1) MSB(V1) - 1
LSB(I2)
SDO
SCLK
FSO
t3
t1
t2
t 4
t 5
t 6
SE
t 6
Figure 1. Serial Port Timing
6
CS5471
2. GENERAL DESCRIPTION
2.1
Theory of Operation
The CS5471 is designed for single-phase power The CS5471 is designed to operate from a single
meter applications and interfaces to a current trans- +3V supply and provides a 40 mV and 800 mV
formers or shunt to measure current, and a resistive
divider or transformer to measure voltage.
input range for the current channel and 800 mV
range for the voltage channel. These voltages rep-
resent the maximum zero-to-peak voltage levels
that can be presented to the inputs. The CS5471 is
designed to accommodate common mode + signal
levels from VA- to VA+. Figure 2 illustrates the
CS5471 typical inputs and power supply connec-
tions.
The CS5471 combines two ∆Σ modulators and
decimation filters, one channel assigned for current
input that has programmable input gain amplifiers,
and one channel assigned for voltage input.
The CS5471 includes two decimation filters that
output data at a 2000 Hz or 4000 Hz output word
rate (OWR) when the input frequency at XIN =
4.096 MHz.
2.2
Performing Measurements
The converter outputs are transferred in 16-bit
signed (two’s complement) data formats as a per-
The device outputs data on a serial output port.
+3 V
VD+
VA+
REFIN
Optional
External
REFOUT
1.2 V
Reference
+
VIN
+
V
PHASE
-
VIN
IIN+
I
PHASE
NOTE: Current input channel
actually measures voltage.
IIN-
AGND
VA-
DGND
-2 V
Figure 2. Typical Connection Diagram
7
CS5471
centage of full scale. Table 1 below illustrates the
ideal relationship between the differential voltage
presented any one of the input channels and the
corresponding output code. Note that for the cur-
rent channels, the state of the GAIN input pin is as-
sumed to driven low, such that the PGA gain on the
current channels is 1x. If the PGA gain of the cur-
rent channels is set to 20x, then a +40 mV differen-
tial voltage presented across the “IIN+” and “IIN-”
pins will cause a (nominal) output code of 32767.
3
–256
1 – z
---------------------
–1
H(z) =
1 – z
If the OWRS pin is set to logic high, then the trans-
fer function is
Input Voltage
(mV0-pk)
Output Code Output Code
3
–128
1 – z
(hexadecimal)
(decimal)
---------------------
–1
H(z) =
+800
7FFF
32767
1 – z
0.0122 to 0.0366
-0.0122 to 0.0122
-0.0122 to -0.0366
-800
0001
1
0
0000
The above filter samples the modulator bit stream
at XIN/8 Hz and decimates to XIN/1024 Hz.
FFFF
-1
8000
-32768
2.4
Serial Interface
Table 1. Nominal Relationship for Differential Input
Voltage vs. Output Code, for all channels. (Assume PGA
gain is set to 1x.)
The CS5471 communicates with a target device via
a master serial data output port. Output data is pro-
vided on the SDO output synchronous with the
SCLK output.
2.3
High Rate Digital Filters
If the OWRS pin is set to logic low, the high-rate
A third output, FSO, is a framing signal used to sig-
nal the start of output data. These three outputs will
be driven as long as the SE (serial enable) input is
held high. Otherwise, these outputs will be high im-
pedance.
3
filters are implemented as fixed sinc filters with
the following transfer function:
This filter samples the modulator bit stream at
XIN/8 Hz and decimates to XIN/2048 Hz.
SCLK
FSO
Each data segment
is 16 bits long.
SDO
Channel 1 (V)
64 0-value bits
Channel 1 (I)
Figure 3. Serial Port Data Transfer
8
CS5471
96 SCLK Cycles
. . .
SCLK
FSO
. . .
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
. . .
SDO
All 0’s
Channel 1 ( V )
Channel 1 ( I )
Figure 4. Close-up of One Frame
Data out (SDO) changes as a result of SCLK fall-
ing, and always outputs valid data with SCLK ris-
ing. When data is being transferred, the SCLK
frequency is either 1/8 of the XIN input frequency
(when OWRS is held low) or 1/4 of the XIN input
frequency (when OWRS is held high). Any other
time, SCLK is held low. (See Figures 3 and 4.)
2.6
Analog Inputs
The analog inputs of the CS5471 are bipolar volt-
age inputs: One voltage channel input pair (VIN+
and VIN-) and current channel input pair (IIN+ and
IIN-). The CS5471 accommodates a full scale
range of 40 mV or 800 mV on the Current Chan-
nel and 800 mV on the Voltage Channel.
The framing signal (FSO) output is normally low,
but produces a high level pulse lasting one SCLK
period when the instantaneous voltage/current data
samples are about to be transmitted out of the serial
interface (after each A/D conversion cycle). Note
that SCLK is not active during FSO high.
2.7
Voltage Reference
The CS5471 is specified for operation with a
+1.2 V reference between the VREFIN and AGND
pins. The converter includes an internal 1.2 V ref-
erence (50 ppm/°C drift) that can be used by con-
necting the VREFOUT pin to the VREFIN pin of
the device. If higher accuracy/stability is required,
an external reference can be used.
For 96 SCLK periods after FSO falls, SCLK is ac-
tive and SDO produces valid output. Six channels
of 16 bit data are output, MSB first. First, the volt-
age and current measurements are output (in that
order). This is followed by four more 16-bit words
of zero-value data. SCLK will then be held low un-
til the next sample period.
2.8
Using the Charge Pump Drive Pin
The low, stable analog power consumption and su-
perior supply rejection of the CS5471 allow for the
use of a simple charge-pump negative supply gen-
erator. The use of a negative supply alleviates the
need for level shifting of the analog inputs. The
CPD pin and capacitor C1 provide the necessary
analog supply current as shown in Figure 5. The
Schottky diodes D1 and D2 are chosen for their low
forward voltages and high-speed capabilities. The
capacitor C2 provides the required charge storage
2.5
System Initialization
When power to the CS5471 is applied, the chip
must be held in a reset condition using the RESET
input.
A hardware reset is initiated when the RESET pin
is forced low with a minimum pulse width of 50 ns.
9
CS5471
and bypassing of the negative supply. The CPD 12.5%. Therefore, the value of C1 should be re-
output signal provides the charge pump driver sig- duced by 12.5%, making the new value for C1 to be
nal. The frequency of the charge pump driver sig-
nal is synchronous to XIN. The nominal average
frequency is 1 Mhz. The level on the VA- pin is fed
35 nF. For more information about the operation of
this type of charge pump circuit, the reader can re-
fer to Cirrus Logic, Inc.’s application note AN152:
back internally so that the CPD output will regulate Using the CS5521/24/28, and CS5525/26 Charge
the VA- level to -2/3 of VA+ level. Pump Drive for External Loads.
2.9 PCB Layout
For optimal performance, the CS5460A should be
placed entirely over an analog ground plane with
both the VA- and DGND pins of the device con-
nected to the analog plane. Place the analog-digital
plane split immediately adjacent to the digital por-
tion of the chip.
CPD
AGND
40 nF
C1
VA-
D2
BAT 85
BAT 85
D1
C2
1 µF
Note: Refer to the CDB5460A Evaluation Board for
suggested layout details and Applications Note
18 for more detailed layout guidelines. Before
layout, please call for our Free Schematic
Review Service.
Figure 5. Generating VA- with a Charge Pump
Note the value of C1 in Figure 5. The 40 nF value
is recommended when the input frequency present-
ed to the XIN pin is 4.00 MHz. If the user decides
to use an XIN frequency that is significantly differ-
ent than 4.00 MHz (if the XIN frequency is in-
creased/decreased by more than 5% of 4.00 MHz,
then it is recommended that the user should alter
the value of C1. The percentage change in the value
of C1 (with respect to a reference value of 40 nF)
should be inversely proportional to the percentage
change in the XIN frequency. For example, if the
XIN frequency is increased from 4.00 MHz to 4.5
MHz, this represents a percentage increase of
10
CS5471
3. PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Serial Clock Output
Serial Data Output
Frame Sync
Serial Port Enable
Current Input Gain
Analog Ground
SCLK
SDO
FSO
VD+
Digital Supply
Digital Ground
Charge Pump Drive
Master Clock
Reset
Output Word Rate Select
Differential Voltage Input 1
Differential Voltage Input 1
Differential Current Input 1
Differential Current Input 1
DGND
CPD
XIN
RESET
OWRS
VIN+
VIN-
SE
GAIN
AGND
VREFIN
Reference Input
Reference Output VREFOUT
Positive Analog Supply
Negative Analog Supply
VA+
VA-
IIN+
IIN-
Clock Generator
XIN - Master Clock Input
Control Pins and Serial Data I/O
SE - Serial Port Enable.
When SE is low, the output pins of the serial port are 3-stated.
SDO - Serial Port Output.
Data will be at a rate determined by SCLK.
FSO - Frame Signal Output.
Framing signal output for data transfer from SDO pin.
SCLK - Serial Clock Output.
A clock signal on this pin determines the output rate of data for SDO pin. Rate of SCLK is determined
by XIN frequency and state of OWRS input pin.
RESET - Reset.
When reset is taken low, all internal registers are set to their default states.
GAIN - Input Gain Control.
Sets input gain for current channel. A logic high sets internal gain to 1, a logic low level sets the gain to
20. If no connection is made to this pin, it will default to logic low level (through internal 200K resistor
to DGND).
OWRS - Output Word Rate Select.
When OWRS is set to logic low, the output word rate (OWR) at SDO pin is XIN/2048 (Hz). When set to
logic high, the OWR at SDO pin is XIN/1024 (Hz). If no connection is made to this pin, then OWRS will
default to logic low level (through internal 200K resistor to DGND).
11
CS5471
Measurement and Reference Input
IIN+, IIN- - Differential Current Input.
Differential analog input pins for current channel.
VIN+, VIN- - Differential Voltage Inputs.
Differential analog input pins for voltage channel.
VREFOUT - Voltage Reference Output.
The on-chip voltage reference is output from this pin. The voltage reference has a nominal magnitude of
1.2 V and is referenced to the AGND pin on the converter.
VREFIN - Voltage Reference Input.
The voltage input to this pin establishes the voltage reference for the on-chip modulator.
Power Supply Connections
VA+ - Positive Analog Supply.
The positive analog supply is nominally +3 V 10% relative to AGND.
VA- - Negative Analog Supply.
The negative analog supply is nominally -2 V 10% relative to AGND.
AGND - Analog Ground.
The analog ground pin for input signals.
VD+ - Positive Digital Supply.
The positive digital supply is nominally +3 V 10% relative to DGND.
DGND - Digital Ground.
The digital ground is typically at the same level as AGND.
CPD - Charge Pump Drive
This output pin drives the external charge pump circuitry to create a negative supply voltage.
12
CS5471
4. PACKAGE DIMENSIONS
20L SSOP PACKAGE DRAWING
N
D
1
E1
A2
A
E
∝
A1
2
e
b
L
END VIEW
SEATING
PLANE
SIDE VIEW
1
2
3
TOP VIEW
INCHES
NOM
--
0.006
0.068
--
0.2834
0.307
0.209
0.026
0.03
MILLIMETERS
NOTE
DIM
A
A1
A2
b
D
E
E1
e
L
MIN
--
MAX
0.084
0.010
0.074
0.015
0.295
0.323
0.220
0.030
0.041
8°
MIN
--
NOM
--
0.13
1.73
--
7.20
7.80
5.30
0.65
0.75
4°
MAX
2.13
0.25
1.88
0.38
7.50
8.20
5.60
0.75
1.03
8°
0.002
0.064
0.009
0.272
0.291
0.197
0.022
0.025
0°
0.05
1.62
0.22
6.90
7.40
5.00
0.55
0.63
0°
2,3
1
1
4°
∝
JEDEC #: MO-150
Controlling Dimension is Millimeters.
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
13
相关型号：
CS5480-INZ/B0
ADC, Delta-Sigma, 24-Bit, 1 Func, 3 Channel, Serial Access, CMOS, 4 X 4 MM, MO-220, QFN-24
CIRRUS
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