CS5504-BSZ [CIRRUS]
Low Power, 20-Bit A/D Converter; 低功耗， 20位A / D转换器
| 型号： | CS5504-BSZ |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | Low Power, 20-Bit A/D Converter |
| 文件： | 总24页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ow
Features
Description
The CS5504 is a 2-channel, fully differential 20-bit, seri-
al-output CMOS A/D converter. The CS5504 uses
charge-balanced (delta-sigma) techniques to provide a
low cost, high-resolution measurement at output word
rates up to 200 samples per second.
Delta-sigma A/D Converter
- 20-bit, No Missing Codes
- Linearity Error: ±0.0007%FS
2 Differential Inputs
- Pin-selectable Unipolar/Bipolar Ranges
The on-chip digital filter offers superior line rejection at
50 Hz and 60 Hz when the device is operated from a
32.768 kHz clock (output word rate = 20 Sps).
- Common Mode Rejection
105 dB @ dc
120 dB @ 50, 60 Hz
The CS5504 has on-chip self-calibration circuitry which
can be initiated at any time or temperature to ensure
minimum offset and full-scale errors.
Either 5V or 3.3V Digital Interface
On-chip Self-calibration Circuitry
Output Update Rates up to 200/Sps
Low Power Consumption: 4.4 mW
Low power, high-resolution and small package size
make the CS5504 an ideal solution for loop-powered
transmitters, panel meters, weigh scales and battery-
powered instruments.
ORDERING INFORMATION
See page 23.
CS5504-BS -40° to +85° C 20-pin SOIC
I
VREF+
12
VREF-
13
VA+ VA-
DGND VD+
14
15
16
17
2
CS
8
AIN1+
AIN1-
18
19
Serial
Interface
SCLK
SDATA
DRDY
10
4th-Order
Logic
Digital
Filter
Delta-Sigma
Modulator
MUX
9
20
AIN2+
AIN2-
11
4
7
CAL
1
A0
Calibration µC
BP/UP
Calibration SRAM
OSC
3
5
6
CONV XIN XOUT
g
CS5504
ANALOG CHARACTERISTICS (T = T
to T ; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ =
MAX
A
MIN
3.3V ± 5%; VREF+ = 2.5V, VREF- = 0V; f
= 32.768kHz; Bipolar Mode; R
= 1kΩ with a 10nF to GND
CLK
source
at AIN.) (Notes 1, 2)
Parameter*
Min
Typ
Max
Units
Specified Temperature Range
Accuracy
-40 to +85
°C
Linearity Error
-
0.0007
-
0.0015
±%FS
Bits
Differential Nonlinearity
Full Scale Error
(No Missing Codes)
20
-
-
±32
-
(Note 3)
(Note 4)
(Note 3)
(Note 4)
(Note 3)
(Note 4)
LSB
LSB
LSB
LSB
LSB
LSB
±4
Full Scale Drift
-
±8
Unipolar Offset
-
±8
±32
Unipolar Offset Drift
Bipolar Offset
-
-
±8
-
±4
±16
Bipolar Offset Drift
Noise (Referred to Output)
Analog Input
-
-
-
±4
-
2.6
LSB
rms
Analog Input Range:
Unipolar
Bipolar
(Note 5)
(Note 2)
-
-
0 to +2.5
-
-
V
V
±2.5
Common Mode Rejection:
dc
-
105
-
-
-
dB
dB
50, 60- Hz
120
Off Channel Isolation
Input Capacitance
-
-
-
120
15
5
-
-
-
dB
pF
nA
DC Bias Current
(Note 1)
(Note 6)
Power Supplies
DC Power Supply Currents:
I
I
I
-
-
-
465
425
40
600
-
-
µA
µA
µA
Total
Analog
Digital
Power Dissipation
-
-
4.4
80
6.0
-
mW
dB
Power Supply Rejection
Notes: 1. Both source resistance and shunt capacitance are critical in determining the CS5504’s source
impedance requirements. Refer to the text section Analog Input Impedance Considerations.
2. Specifications guaranteed by design, characterization and/or test.
3. Applies after calibration at the temperature of interest.
4. Total drift over the specified temperature range since calibration at power-up at 25 °C
5. Common mode voltage may be at any value as long as AIN+ and AIN- remain within the VA+ and
VA- supply voltages.
6. All outputs unloaded. All inputs CMOS levels.
* Refer to the Specification Definitions immediately following the Pin Description Section.
Specifications are subject to change without notice.
2
DS126F2
CS5504
DYNAMIC CHARACTERISTICS
Parameter
Symbol
Ratio
f /2
Units
Modulator Sampling Frequency
Output Update Rate (CONV = 1)
Filter Corner Frequency
f
Hz
Sps
Hz
s
s
clk
f
f /1622
clk
out
f
f /1928
clk
-3dB
Settling Time to 1/2 LSB (FS Step)
t
s
1/f
out
5V DIGITAL CHARACTERISTICS (T = T
to T ; VA+, VD+ = 5V ± 10%; VA- = -5V ± 10%;
MAX
A
MIN
DGND = 0.) (Notes 2, 7)
Parameter
Symbol
Min
Typ
Max
Units
High-Level Input Voltage:
XIN
V
V
3.5
2.0
-
-
-
-
V
V
IH
IH
All Pins Except XIN
Low-Level Input Voltage:
XIN
V
V
-
-
-
-
1.5
0.8
V
V
IL
All Pins Except XIN
IL
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
(Note 8)
V
(VD+)-1.0
-
-
-
V
OH
I
= 1.6 mA
V
-
-
-
-
0.4
±10
±10
-
V
OL
in
out
I
±1
-
µA
µA
pF
3-State Leakage Current
I
OZ
Digital Output Pin Capacitance
C
9
out
Notes: 7. All measurements are performed under static conditions.
8. I = -100 µA. This guarantees the ability to drive one TTL load. (V
= 2.4V @ I = -40 µA).
out
out
OH
3.3V DIGITAL CHARACTERISTICS (T = T
to T ; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%;
MAX
A
MIN
VA- = -5V ±10%; GND = 0V.) (Notes 2, 7)
Parameter
Symbol
Min
Typ
Max
Units
High-Level Input Voltage:
XIN
V
V
0.7VD+
0.6VD+
-
-
-
-
V
V
IH
IH
All Pins Except XIN
Low-Level Input Voltage:
XIN
V
V
-
-
-
-
0.3VD+
0.16VD+
V
V
IL
All Pins Except XIN
IL
V
OH
(VD+)-0.3
-
-
-
V
V
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
I
I
= -400 µA
= 400 µA
out
V
I
-
-
-
-
0.3
OL
out
in
±1
-
±10
±10
-
µA
µA
pF
3-State Leakage Current
I
OZ
Digital Output Pin Capacitance
C
out
9
DS126F2
3
CS5504
5V SWITCHING CHARACTERISTICS (T = T
to T ; VA+, VD+ = 5V ± 10%;
MAX
A
MIN
VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C = 50 pF.) (Note 2)
L
Parameter
Internal Oscillator
Symbol
Min
Typ
Max
Units
Master Clock Frequency
XIN
f
clk
30.0
30
32.768
-
53.0
330
kHz
kHz
External Clock
Master Clock Duty Cycle
Rise Times:
40
-
60
%
Any Digital Input
Any Digital Output
(Note 9)
(Note 9)
t
-
-
-
50
1.0
-
rise
µs
ns
Fall Times:
Any Digital Input
Any Digital Output
t
-
-
-
20
1.0
-
fall
µs
ns
Start-Up
Power-On Reset Period
Oscillator Start-up Time
Wake-up Period
(Note 10)
t
-
-
-
10
-
-
-
ms
ms
s
res
XTAL = 32.768 kHz (Note 11)
(Note 12)
t
500
osu
t
1800/f
wup
clk
clk
Calibration
CONV Pulse Width (CAL=1)
(Note 13)
t
100
-
-
-
ns
ns
s
ccw
CONV and CAL High to Start of Calibration
Start of Calibration to End of Calibration
Conversion
t
-
-
2/f +200
scl
clk
t
3246/f
-
cal
Set Up Time
A0 to CONV High
A0 after CONV High
t
50
100
100
-
-
-
-
-
ns
ns
ns
ns
s
sac
hca
cpw
Hold Time
t
-
CONV Pulse Width
t
t
-
CONV High to Start of Conversion
t
-
2/f +200
scn
bus
buh
clk
Set Up Time
BP/UP stable prior to DRDY falling
BP/UP stable after DRDY falls
(Note 14)
Notes: 9. Specified using 10% and 90% points on waveform of interest.
10. An internal power-on-reset is activated whenever power is applied to the device.
82/f
-
-
-
-
clk
Hold Time
t
0
-
-
ns
s
Start of Conversion to End of Conversion
t
1624/f
con
clk
11. Oscillator start-up time varies with the crystal parameters. This specification does not apply when
using an external clock source.
12. The wake-up period begins once the oscillator starts; or when using an external f , after the
clk
power-on reset time elapses.
13. Calibration can also be initiated by pulsing CAL high while CONV=1.
14. Conversion time will be 1622/f if CONV remains high continuously.
clk
4
DS126F2
CS5504
3.3V SWITCHING CHARACTERISTICS (T = T
to T ; VA+ = 5V ± 10%; VD+ = 3.3V ±
MAX
A
MIN
5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C = 50 pF.) (Note 2)
L
Parameter
Internal Oscillator
Symbol
Min
Typ
Max
Units
Master Clock Frequency
XIN
f
clk
30.0
30
32.768
-
53.0
330
kHz
kHz
External Clock
Master Clock Duty Cycle
Rise Times:
40
-
60
%
Any Digital Input
Any Digital Output
(Note 9)
(Note 9)
t
-
-
-
50
1.0
-
rise
µs
ns
Fall Times:
Any Digital Input
Any Digital Output
t
-
-
-
20
1.0
-
fall
µs
ns
Start-Up
Power-On Reset Period
Oscillator Start-up Time
Wake-up Period
(Note 10)
t
-
-
-
10
-
-
-
ms
ms
s
res
XTAL = 32.768 kHz (Note 11)
(Note 12)
t
500
osu
t
1800/f
wup
clk
clk
Calibration
CONV Pulse Width (CAL=1)
(Note 13)
t
100
-
-
-
ns
ns
s
ccw
CONV and CAL High to Start of Calibration
Start of Calibration to End of Calibration
Conversion
t
-
-
2/f +200
scl
clk
t
3246/f
-
cal
Set Up Time
Hold Time
A0 to CONV High
A0 after CONV High
t
50
100
100
-
-
-
-
-
ns
ns
ns
ns
s
sac
hca
cpw
t
-
CONV Pulse Widh
t
t
-
CONV High to Start of Conversion
t
-
2/f +200
scn
bus
buh
clk
Set Up Time
Hold Time
BP/UP stable prior to DRDY falling
BP/UP stable after DRDY falls
82/f
-
-
-
-
-
clk
t
0
-
ns
s
Start of Conversion to End of Conversion
(Note 14)
t
1624/f
con
clk
DS126F2
5
CS5504
XIN
XIN/2
CAL
t
ccw
CONV
t
t
cal
scl
STATE
Standby
Calibration
Standby
Figure 1. Calibration Timing (Not to Scale)
XIN
XIN/2
A0
t
t
hca
sac
CONV
t
cpw
DRDY
BP/UP
t
bus
t
buh
t
t
con
scn
STATE
Standby
Conversion
Standby
Figure 2. Conversion Timing (Not to Scale)
6
DS126F2
CS5504
5V SWITCHING CHARACTERISTICS (T = T
to T ; VA+, VD+ = 5V ± 10%;
MAX
A
MIN
VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C = 50 pF.) (Note 2)
L
Parameter
Symbol
Min
Typ
Max
Units
Serial Clock
Serial Clock
f
0
-
2.5
MHz
sclk
Pulse Width High
Pulse Width Low
t
200
200
-
-
-
-
ns
ns
ph
t
pl
Access Time:
CS Low to data valid (Note 15)
t
-
60
200
ns
csd
Maximum Delay Time:
(Note 16)
SCLK falling to new SDATA bit
t
-
150
310
ns
dd
Output Float Delay:
CS high to output Hi-Z (Note 17)
SCLK falling to Hi-Z
t
t
-
-
60
160
150
300
ns
ns
fd1
fd2
Notes: 15. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 f cycles plus 200 ns. To
clk
guarantee proper clocking of SDATA when using asynchronous CS, SCLK should not be taken high
sooner than 2/f + 200 ns after CS goes low.
clk
16. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the
serial port shifting mechanism before falling edges can be recognized.
17. If CS is returned high before all data bits are output, the SDATA output will complete the current data
bit and then go to high impedance.
3.3V SWITCHING CHARACTERISTICS (T = T
to T ; VA+ = 5V ± 10%; VD+ = 3.3V ±
MAX
A
MIN
5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C = 50 pF.) (Note 2)
L
Parameter
Symbol
Min
Typ
Max
Units
Serial Clock
Serial Clock
f
0
-
1.25
MHz
sclk
Pulse Width High
Pulse Width Low
t
200
200
-
-
-
-
ns
ns
ph
t
pl
Access Time:
CS Low to data valid (Note 15)
t
-
100
200
ns
csd
Maximum Delay Time:
(Note 16)
SCLK falling to new SDATA bit
t
dd
-
400
600
ns
Output Float Delay:
CS high to output Hi-Z (Note 17)
SCLK falling to Hi-Z
t
t
-
-
70
320
150
500
ns
ns
fd1
fd2
DS126F2
7
CS5504
DRDY
CS
t
t
fd1
csd
SDATA(o) Hi-Z
MSB
MSB-1
MSB-2
t
dd
SCLK(i)
DRDY
CS
t
csd
SDATA(o) Hi-Z
MSB
MSB-1
LSB+2
LSB+1
LSB
t
t
t
fd2
dd
ph
SCLK(i)
t
pl
Figure 3. Timing Relationships; Serial Data Read (Not to Scale)
8
DS126F2
CS5504
RECOMMENDED OPERATING CONDITIONS (DGND = 0V) (Note 18)
Parameter
Symbol
Min
Typ
Max
Units
DC Power Supplies:
Positive Digital
(VA+) - (VA-)
VD+
3.15
4.5
4.5
0
5.0
10
5.0
-5.0
5.5
11
11
V
V
V
V
V
diff
Positive Analog
Negative Analog
VA+
VA-
-5.5
Analog Reference Voltage
(VREF+)-
1.0
2.5
3.6
V
(Note 19) (VREF-)
Analog Input Voltage: (Note 20)
Unipolar
Bipolar
VAIN
0
-
-
(VREF+)-(VREF-)
(VREF+)-(VREF-)
V
V
VAIN -((VREF+)-(VREF-))
Notes: 18. All voltages with respect to ground.
19. The CS5504 can be operated with a reference voltage as low as 100 mV; but with a
corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference
may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and VA-.
20. The CS5504 can accept input voltages up to the analog supplies (VA+ and VA-). In unipolar mode
the CS5504 will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-))
and will output all 0’s if the input becomes more negative than 0 Volts. In bipolar mode the CS5504
will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output
all 0’s if the input becomes more negative in magnitude than -((VREF+)-(VREF-)).
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Min
Typ
Max
Units
DC Power Supplies:
Digital Ground
(Note 21) DGND
(Note 22) VD+
VA+
-0.3
-0.3
-0.3
+0.3
-
-
-
-
(VD+)-0.3
6.0 or VA+
12
V
V
V
V
Positive Digital
Positive Analog
Negative Analog
VA-
-6.0
Input Current, Any Pin Except Supplies
Output Current
(Notes 23, 24)
I
-
-
-
-
-
-
-
-
mA
mA
mW
V
in
±10
±25
I
-
-
out
Power Dissipation (Total)
(Note 25)
500
Analog Input Voltage
AIN and VREF pins
V
INA
(VA-)-0.3
-0.3
-40
(VA+)+0.3
(VD+)+0.3
85
Digital Input Voltage
V
V
IND
Ambient Operating Temperature
Storage Temperature
T
°C
°C
A
T
-65
150
stg
Notes: 21. No pin should go more positive than (VA+)+0.3V.
22. VD+ must always be less than (VA+) +0.3V, and can never exceed +6.0 V.
23. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin.
24. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power
supply pin is ± 50 mA.
25. Total power dissipation, including all input currents and output currents.
* WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
DS126F2
9
CS5504
GENERAL DESCRIPTION
tion of this command will not occur until the
complete wake-up period elapses. If no com-
mand is given, the device enters the standby
state.
The CS5504 is a low power, 20-bit, monolithic
CMOS A/D converter designed specifically for
measurement of dc signals. The CS5504 in-
cludes a delta-sigma charge-balance converter, a
voltage reference, a calibration micro controller
with SRAM, a digital filter and a serial interface.
Calibration
After the initial application of power, the
CS5504 must enter the calibration state prior to
performing accurate conversions. During calibra-
tion, the chip executes a two-step process. The
device first performs an offset calibration and
then follows this with a gain calibration. The
two calibration steps determine the zero refer-
ence point and the full scale reference point of
the converter’s transfer function. From these
points it calibrates the zero point and a gain
slope to be used to properly scale the output
digital codes when doing conversions.
The CS5504 is optimized to operate from a
32.768 kHz crystal but can be driven by an ex-
ternal clock whose frequency is between 30 kHz
and 330 kHz. When the digital filter is operated
with a 32.768 kHz clock, the filter has zeros pre-
cisely at 50 and 60 Hz line frequencies and
multiples thereof.
The CS5504 uses a "start convert" command to
latch the input channel selection and to start a
convolution cycle on the digital filter. Once the
filter cycle is completed, the output port is up-
dated. When operated with a 32.768 kHz clock
the ADC converts and updates its output port at
20 samples/sec. The output port operates in a
synchronous externally-clocked interface format.
The calibration state is entered whenever the
CAL and CONV pins are high at the same time.
The state of the CAL and CONV pins at power-
on are recognized as commands, but will not be
executed until the end of the 1800 clock cycle
wake-up period.
THEORY OF OPERATION
If CAL and CONV become active (high) during
the 1800 clock cycle wake-up time, the con-
verter will wait until the wake-up period elapses
before executing the calibration. If the wake-up
time has elapsed, the converter will be in the
standby mode waiting for instruction and will
enter the calibration cycle immediately if CAL
and CONV become active. The calibration lasts
for 3246 clock cycles. Calibration coefficients
are then retained in the SRAM (static RAM) for
use during conversion.
Basic Converter Operation
The CS5504 A/D converter has three operating
states. These are stand-by, calibration, and con-
version. When power is first applied, an internal
power-on reset delay of about 10 ms resets all of
the logic in the device. The oscillator must then
begin oscillating before the device can be con-
sidered functional. After the power-on reset is
applied, the device enters the wake-up period for
1800 clock cycles after clock is present. This
allows the delta-sigma modulator and other cir-
cuitry (which are operating with very low
currents) to reach a stable bias condition prior to
entering into either the calibration or conversion
states. During the 1800 cycle wake-up period,
the device can accept an input command. Execu-
The states of A0 and BP/UP are ignored during
calibration but should remain stable throughout
the calibration period to minimize noise.
When conversions are performed in unipolar
mode or in bipolar mode, the converter uses the
same calibration factors to compute the digital
10
DS126F2
CS5504
output code. The only difference is that in bipo-
lar mode the on-chip microcontroller offsets the
computed output word by a code value of
8000H. This means that the bipolar measure-
ment range is not calibrated from full scale
positive to full scale negative. Instead it is cali-
brated from the bipolar zero scale point to full
scale positive. The slope factor is then extended
below bipolar zero to accommodate the negative
input signals. The converter can be used to con-
vert both unipolar and bipolar signals by
changing the BP/UP pin. Recalibration is not re-
quired when switching between unipolar and
bipolar modes.
Conversion
The conversion state can be entered at the end of
the calibration cycle, or whenever the converter
is idle in the standby mode. If CONV is taken
high to initiate a calibration cycle ( CAL also
high), and remains high until the calibration cy-
cle is completed (CAL is taken low after CONV
transitions high), the converter will begin a con-
version upon completion of the calibration
period. The device will perform a conversion on
the input channel selected by A0 when CONV
transitions high. Table 1 indicates the multi-
plexer channel selection truth table.
At the end of the calibration cycle, the on-chip
micro controller checks the logic state of the
CONV signal. If the CONV input is low the de-
vice will enter the standby mode where it waits
for further instruction. If the CONV signal is
high at the end of the calibration cycle, the con-
verter will enter the conversion state and
perform a conversion on the input channel. The
CAL signal can be returned low any time after
calibration is initiated. CONV can also be re-
turned low, but it should never be taken low and
then taken back high until the calibration period
has ended and the converter is in the standby
state. If CONV is taken low and then high
again with CAL high while the converter is cali-
brating, the device will interrupt the current
calibration cycle and start a new one. If CAL is
taken low and CONV is taken low and then high
during calibration, the calibration cycle will
continue as the conversion command is disre-
garded. The state of BP/UP is not important
during calibrations.
A0
0
1
Channel Addressed
AIN1
AIN2
Table 1. Multiplexer Truth Table
The A0 input is latched internal to the CS5504
when CONV rises. A0 has internal pull-down
circuits which default the multiplexer to channel
AIN1.
The BP/UP pin is not a latched input. The
BP/UP pin controls how the output word from
the digital filter is processed. In bipolar mode
the output word computed by the digital filter is
offset by 80000H (see Understanding Converter
Calibration). BP/UP can be changed after a con-
version is started as long as it is stable for 82
clock cycles of the conversion period prior to
DRDY falling. If one wishes to intermix meas-
urement of bipolar and unipolar signals on
various input channels, it is best to switch the
BP/UP pin immediately after DRDY falls and
leave BP/UP stable until DRDY falls again.
If an "end of calibration" signal is desired, pulse
the CAL signal high while leaving the CONV
signal high continuously. Once the calibration is
completed, a conversion will be performed. At
the end of the conversion, DRDY will fall to in-
dicate the first valid conversion after the
calibration has been completed.
The digital filter in the CS5504 has a Finite Im-
pulse Response and is designed to settle to full
accuracy in one conversion time.
If CONV is left high, the CS5504 will perform
continuous conversions. The conversion time
will be 1622 clock cycles. If conversion is initi-
DS126F2
11
CS5504
ated from the standby state, there may be up to
two XIN clock cycles of uncertainty as to when
conversion actually begins. This is because the
internal logic operates at one half the external
clock rate and the exact phase of the internal
clock may be 180° out of phase relative to the
XIN clock. When a new conversion is initiated
from the standby state, it will take up to two
XIN clock cycles to begin. Actual conversion
will use 1624 clock cycles before DRDY goes
low to indicate that the serial port has been up-
dated. See the Serial Interface Logic section of
the data sheet for information on reading data
from the serial port.
as the maximum signal magnitude stays within
the supply voltages.
The A/D converter is intended to measure dc or
low frequency inputs. It is designed to yield ac-
curate conversions even with noise exceeding
the input voltage range as long as the spectral
components of this noise will be filtered out by
the digital filter. For example, with a 3.0 volt
reference in unipolar mode, the converter will
accurately convert an input dc signal up to
3.0 volts with up to 15% overrange for 60 Hz
noise. A 3.0 volt dc signal could have a 60 Hz
component which is 0.5 volts above the maxi-
mum input of 3.0 (3.5 volts peak; 3.0 volts dc
plus 0.5 volts peak noise) and still accurately
convert the input signal (XIN = 32.768 kHz).
This assumes that the signal plus noise ampli-
tude stays within the supply voltages.
In the event the A/D conversion command
(CONV going positive) is issued during the con-
version state, the current conversion will be
terminated and a new conversion will be initi-
ated.
The CS5504 converters output data in binary
format when converting unipolar signals and in
offset binary format when converting bipolar
signals. Table 2 outlines the output coding for
both unipolar and bipolar measurement modes.
Voltage Reference
The CS5504 uses a differential voltage reference
input. The positive input is VREF+ and the
negative input is VREF-. The voltage between
VREF+ and VREF- can range from 1 volt mini-
mum to 3.6 volts maximum. The gain slope will
track changes in the reference without recalibra-
tion, accommodating ratiometric applications.
Unipolar Input
Voltage
Output
Codes
Bipolar Input
Voltage
>(VREF - 1.5 LSB)
VREF - 1.5 LSB
FFFFF >(VREF - 1.5 LSB)
FFFFF
VREF - 1.5 LSB
FFFFE
Analog Input Range
80000
VREF/2 - 0.5 LSB
-0.5 LSB
7FFFF
The analog input range is set by the magnitude
of the voltage between the VREF+ and VREF-
pins. In unipolar mode the input range will
equal the magnitude of the voltage reference. In
bipolar mode the input voltage range will equate
to plus and minus the magnitude of the voltage
reference. While the voltage reference can be as
great as 3.6 volts, its common mode voltage can
be any value as long as the reference inputs
VREF+ and VREF- stay within the supply volt-
ages for the A/D. The differential input voltage
can also have any common mode value as long
00001
+ 0.5 LSB
-VREF + 0.5 LSB
00000
<(+ 0.5 LSB)
00000
<(VREF + 0.5 LSB)
Note: Table excludes common mode voltage on the
signal and reference inputs.
Table 2. Output Coding
12
DS126F2
CS5504
Converter Performance
tor to its final value. The voltage on the output
of the buffer may differ up to 100 mV from the
actual input voltage due to the offset voltage of
the buffer. Timing allows one half of a XIN
clock cycle for the voltage on the sample capaci-
tor to settle to its final value.
The CS5504 A/D converter has excellent linear-
ity performance. Calibration minimizes the
errors in offset and gain. The CS5504 device
has no missing code performance to 20-bits.
The converter achieves Common Mode Rejec-
tion (CMR) at dc of 105 dB typical, and CMR at
50 and 60 Hz of 120 dB typical.
An equation for the maximum acceptable source
resistance is derived.
−1
The CS5504 can experience some drift as tem-
perature changes. The CS5504 uses
chopper-stabilized techniques to minimize drift.
Measurement errors due to offset or gain drift
can be eliminated at any time by recalibrating
the converter.
Rs
max
=
V
e
2XIN (15pF + C
EXT
) ln
15pF(100mv)
V +
e
(15pF + C
)
EXT
This equation assumes that the offset voltage of
the buffer is 100 mV, which is the worst case.
The value of Ve is the maximum error voltage
Analog Input Impedance Considerations
The analog input of the CS5504 can be modeled
as illustrated in Figure 4 (the model ignores the
multiplexer switch resistance). Capacitors (15 pF
each) are used to dynamically sample each of
the inputs (AIN+ and AIN-). Every half XIN cy-
cle the switch alternately connects the capacitor
to the output of the buffer and then directly to
the AIN pin. Whenever the sample capacitor is
switched from the output of the buffer to the
AIN pin, a small packet of charge (a dynamic
demand of current) is required from the input
source to settle the voltage of the sample capaci-
which is acceptable. C
of any external or stray capacitance.
is the combination
EXT
For a maximum error voltage (Ve) of 600 nV in
the CS5504 (1/4LSB at 20-bits), the above equa-
tion indicates that when operating from a
32.768 kHz XIN, source resistances up to 84 kΩ
in the CS5504 are acceptable in the absence of
external capacitance (C
= 0).
EXT
The VREF+ and VREF- inputs have nearly the
same structure as the AIN+ and AIN- inputs.
Therefore, the discussion on analog input imped-
ance applies to the voltage reference inputs as
well.
AIN+
15 pF
+
V
V
≤
≤
100 mV
100 mV
Digital Filter Characteristics
os
os
Internal
Bias
-
Voltage
The digital filter in the CS5504 is the combina-
tion of a comb filter and a low pass filter. The
comb filter has zeros in its transfer function
which are optimally placed to reject line interfer-
ence frequencies (50 and 60 Hz and their
multiples) when the CS5504 is clocked at
AIN-
15 pF
+
-
Figure 4. Analog Input Model
DS126F2
13
CS5504
0
-20
X1 = 32.768kHz
X2 = 330.00kHz
Frequency
Notch
Depth
(dB)
Frequency Minimum
Attenuation
-40
(Hz)
50
(Hz)
(dB)
55.5
58.4
62.2
68.4
74.9
87.9
94.0
104.4
-60
125.6
126.7
145.7
136.0
118.4
132.9
102.5
108.4
50±1%
60
60±1%
-80
100
120
150
180
200
240
100±1%
120±1%
150±1%
180±1%
200±1%
240±1%
-100
-120
-140
XIN = 32.768 kHz
120 160 200
-160
X1
X2
0
0
40
80
240
402.83 805.66 1208.5 1611.3 2014.2 2416.9
Frequency (Hz)
Figure 5. Filter Magnitude Plot to 260 Hz
Table 3. Filter Notch Attenuation (XIN = 32.768 kHz)
180
135
90
0
Flatness
Frequency dB
-20
1
2
-0.010
-0.041
-0.093
-0.166
-0.259
-0.374
-0.510
-0.667
-0.846
-1.047
-3.093
-40
-60
3
45
4
5
0
6
-80
7
-45
8
9
-100
-120
-140
-90
10
17
XIN = 32.768 kHz
XIN = 32.768 kHz
-135
-180
0
5
10 15 20 25 30 35 40 45 50
0
5
10 15 20 25 30 35 40 45 50
Frequency (Hz)
Frequency (Hz)
Figure 6. Filter Magnitude Plot to 50 Hz
Figure 7. Filter Phase Plot to 50 Hz
of these interference frequencies even if the fun-
damental line frequency should vary ± 1% from
32.768 kHz. Figures 5, 6 and 7 illustrate the
magnitude and phase characteristics of the filter.
Figure 5 illustrates the filter attenuation from dc
to 260 Hz. At exactly 50, 60, 100, and 120 Hz
the filter provides over 120 dB of rejection. Ta-
ble 3 indicates the filter attenuation for each of
the potential line interference frequencies when
the converter is operating with a 32.768 kHz
clock. The converter yields excellent attenuation
its specified frequency.
The -3dB corner fre-
quency of the filter when operating from a
32.768 kHz clock is 17 Hz. Figure 7 illustrates
that the phase characteristics of the filter are pre-
cisely linear phase.
14
DS126F2
CS5504
If the CS5504 is operated at a clock rate other
than 32.768 kHz, the filter characteristics, in-
cluding the comb filter zeros, will scale with the
operating clock frequency. Therefore, optimum
rejection of line frequency interference will oc-
cur with the CS5504 running at 32.768 kHz.
crystal with tight specifications for both initial
frequency and for drift over temperature. To
maintain excellent frequency stability, these
crystals are specified only over limited operating
temperature ranges (i.e. -10 °C to +60 °C) by the
manufacturers. Applications of these crystals
with the CS5504 does not require tight initial
tolerance or low tempco drift. Therefore, a lower
cost crystal with looser initial tolerance and tem-
pco will generally be adequate for use with the
CS5504. Also check with the manufacturer
about wide temperature range application of
their standard crystals. Generally, even those
crystals specified for limited temperature range
will operate over much larger ranges if fre-
quency stability over temperature is not a
requirement. The frequency stability can be as
bad as ±3000 ppm over the operating tempera-
ture range and still be typically better than the
line frequency (50 Hz or 60 Hz) stability over
cycle-to-cycle during the course of a day.
Anti-Alias Considerations for Spectral
Measurement Applications
Input frequencies greater than one half the out-
put word rate (CONV = 1) may be aliased by
the converter. To prevent this, input signals
should be limited in frequency to no greater than
one half the output word rate of the converter
(when
CONV =1). Frequencies close to the modulator
sample rate (XIN/2) and multiples thereof may
also be aliased. If the signal source includes
spectral components above one half the output
word rate (when CONV = 1) these components
should be removed by means of low-pass filter-
ing prior to the A/D input to prevent aliasing.
Spectral components greater than one half the
output word rate on the VREF inputs (VREF+
and VREF-) may also be aliased. Filtering of the
reference voltage to remove these spectral com-
ponents from the reference voltage is desirable.
Serial Interface Logic
The digital filter in the CS5504 takes 1624 clock
cycles to compute an output word once a con-
version begins. At the end of the conversion
cycle, the filter will attempt to update the serial
port. Two clock cycles prior to the update
DRDY will go high. When DRDY goes high
just prior to a port update it checks to see if the
port is either empty or unselected (CS = 1). If
the port is empty or unselected, the digital filter
will update the port with a new output word.
When new data is put into the port DRDY will
go low.
Crystal Oscillator
The CS5504 is designed to be operated using a
32.768 kHz "tuning fork" type crystal. One end
of the crystal should be connected to the XIN
input. The other end should be attached to
XOUT. Short lead lengths should be used to
minimize stray capacitance.
Reading Serial Data
Over the industrial temperature range (-40 to
+85 °C) the on-chip gate oscillator will oscillate
with other crystals in the range of 30 kHz to 53
kHz. The chip will operate with external clock
frequencies from 30 kHz to 330 kHz over the in-
dustrial temperature range. The 32.768 kHz
crystal is normally specified as a time-keeping
SDATA is the output pin for the serial data.
When CS goes low after new data becomes
available (DRDY goes low), the SDATA pin
comes out of Hi-Z with the MSB data bit pre-
sent. SCLK is the input pin for the serial clock.
If the MSB data bit is on the SDATA pin, the
DS126F2
15
CS5504
first rising edge of SCLK enables the shifting
mechanism. This allows the falling edges of
SCLK to shift subsequent data bits out of the
port. Note that if the MSB data bit is output and
the SCLK signal is high, the first falling edge of
SCLK will be ignored because the shifting
mechanism has not become activated. After the
first rising edge of SCLK, each subsequent fall-
ing edge will shift out the serial data. Once the
LSB is present, the falling edge of SCLK will
cause the SDATA output to go to Hi-Z and
DRDY to return high. The serial port register
will be updated with a new data word upon the
completion of another conversion if the serial
port has been emptied, or if the CS is inactive
(high).
The following power supply options are possi-
ble:
VA+ = +5V to +10V, VA- = 0V,
VD+ = +5V
VD+ = +5V
VA+ = +5V,
VA+ = +5V,
VA- = -5V,
VA- = 0V to -5V, VD+ = +3.3V
The CS5504 cannot be operated with a 3.3V
digital supply if VA+ is greater than +5.5V.
Figure 8 illustrates the System Connection Dia-
gram for the CS5504 using a single +5V supply.
Note that all supply pins are bypassed with
0.1 µF capacitors and that the VD+ digital sup-
ply is derived from the VA+ supply.
Figure 9 illustrates the CS5504 using dual sup-
plies of +5 and -5V.
CS can be operated asynchronously to the
DRDY signal. The DRDY signal need not be
monitored as long as the CS signal is taken low
for at least two XIN clock cycles plus 200 ns
prior to SCLK being toggled. This ensures that
CS has gained control over the serial port.
Figure 10 illustrates the CS5504 using dual sup-
plies of +10V analog and +5V digital.
When using separate supplies for VA+ and
VD+, VA+ must be established first. VD+
should never become more positive than VA+
under any operating condition. Remember to in-
vestigate transient power-up conditions, when
one power supply may have a faster rise time.
Power Supplies and Grounding
The analog and digital supply pins to the
CS5504 are brought out on separate pins to
minimize noise coupling between the analog and
digital sections of the chip. Note that there is no
analog ground pin. No analog ground pin is re-
quired because the inputs for measurement and
for the voltage reference are differential and re-
quire no ground. In the digital section of the
chip the supply current flows into the VD+ pin
and out of the DGND pin. As a CMOS device,
the CS5504 requires that the supply voltage on
the VA+ pin always be more positive than the
voltage on any other pin of the device. If this
requirement is not met, the device can latch-up
or be damaged. In all circumstances the VA+
voltage must remain more positive than the VD+
or DGND pins; VD+ must remain more positive
than the DGND pin.
16
DS126F2
CS5504
10
Ω
+5V
Analog
Supply
0.1
0.1
µ
µF
F
14
VA+
17
VD+
4
7
Calibration
Control
CAL
Optional
Clock
Source
5
6
XIN
Bipolar/
Unipolar
Input Select
XOUT
BP/UP
AIN1+
32.768 kHz
CS5504
18
19
8
SCLK
Serial
Data
Interface
10
9
Analog*
Signal
Sources
AIN1-
AIN2+
AIN2-
SDATA
DRDY
11
20
2
*Unused analog inputs should
be tied to signal ground
CS
A0
Control
Logic
12
13
1
VREF+
VREF-
+
Voltage
Reference
3
CONV
DGND
-
16
VA-
15
Unused Logic
inputs must be
connected to
VD+ or DGND
Figure 8. CS5504 System Connection Diagram Using Single Supply
DS126F2
17
CS5504
10
Ω
+5V
Analog
Supply
0.1
0.1
µ
µ
F
F
14
VA+
17
VD+
4
7
Calibration
Control
CAL
Optional
Clock
Source
5
6
XIN
Bipolar/
Unipolar
Input Select
XOUT
BP/UP
AIN1+
32.768 kHz
CS5504
18
19
8
SCLK
Serial
Data
Interface
10
9
Analog*
Signal
Sources
AIN1-
AIN2+
AIN2-
SDATA
DRDY
11
20
2
*Unused analog inputs should
be tied to signal ground
CS
A0
Control
Logic
12
13
1
VREF+
VREF-
+
Voltage
Reference
3
CONV
DGND
-
16
0.1
µ
F
VA-
15
Unused Logic
-5V
Analog
Supply
inputs must be
connected to
VD+ or DGND
Figure 9. CS5504 System Connection Diagram Using Dual Supplies
18
DS126F2
CS5504
Note: VD+ should never be more positive than VA+
+10V
Analog
Supply
+5V
Digital
Supply
0.1
0.1
µ
µ
F
F
14
17
VD+
VA+
4
7
Calibration
Control
CAL
Optional
Clock
Source
5
6
XIN
Bipolar/
Unipolar
Input Select
XOUT
BP/UP
AIN1+
32.768 kHz
CS5504
18
19
8
SCLK
Serial
Data
Interface
10
9
Analog*
Signal
Sources
AIN1-
AIN2+
AIN2-
SDATA
DRDY
11
20
2
*Unused analog inputs should
be tied to signal ground
CS
A0
Control
Logic
12
13
1
VREF+
VREF-
+
Voltage
Reference
3
CONV
DGND
-
16
VA-
15
Unused Logic
inputs must be
connected to
VD+ or DGND
Figure 10. CS5504 System Connection Diagram Using Dual Supply,
+10V Analog, +5V Digital
DS126F2
19
CS5504
PIN DESCRIPTIONS*
1
2
20
19
18
17
16
15
14
13
12
11
MULTIPLEXER SELECTION INPUT
CHIP SELECT
A0
CS
DRDY
SDATA
SCLK
VD+
DATA READY
SERIAL DATA OUTPUT
3
CONVERT CONV
SERIAL CLOCK INPUT
4
CALIBRATE
CRYSTAL IN
CAL
XIN
POSITIVE DIGITAL POWER
DIGITAL GROUND
5
DGND
VA-
6
CRYSTAL OUT
XOUT
NEGATIVE ANALOG POWER
POSITIVE ANALOG POWER
VOLTAGE REFERENCE INPUT
VOLTAGE REFERENCE INPUT
DIFFERENTIAL ANALOG INPUT
7
BIPOLAR/UNIPOLAR BP/UP
DIFFERENTIAL ANALOG INPUT AIN1+
DIFFERENTIAL ANALOG INPUT AIN2+
VA+
8
VREF-
VREF+
AIN2-
9
10
DIFFERENTIAL ANALOG INPUT
AIN1-
*Pinout applies to both PDIP and SOIC
Clock Generator
XIN; XOUT - Crystal In; Crystal Out, Pins 5, 6.
A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the
device into a lower powered state (approximately 70% power reduction).
Serial Output I/O
CS - Chip Select, Pin 2.
This input allows an external device to access the serial port.
DRDY - Data Ready, Pin 20.
Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new
output word has been placed into the serial port. DRDY will return high after all data bits are
shifted out of the serial port or two master clock cycles before new data becomes available if
the CS pin is inactive (high).
SDATA - Serial Data Output, Pin 19.
SDATA is the output pin of the serial output port. Data from this pin will be output at a rate
determined by SCLK. Data is output MSB first and advances to the next data bit on the falling
edges of SCLK. SDATA will be in a high impedance state when not transmitting data.
SCLK - Serial Clock Input, Pin 18.
A clock signal on this pin determines the output rate of the data from the SDATA pin. This pin
must not be allowed to float.
20
DS126F2
CS5504
Control Input Pins
CAL - Calibrate, Pin 4.
When taken high the same time that the CONV pin is taken high the converter will perform a
self-calibration which includes calibration of the offset and gain scale factors in the converter.
CONV - Convert, Pin 3.
The CONV pin initiates a calibration cycle if it is taken from low to high while the CAL pin is
high, or it initiates a conversion if it is taken from low to high with the CAL pin low. If
CONV is held high (CAL low) the converter will do continuous conversions.
BP/UP - Bipolar/Unipolar, Pin 7.
The BP/UP pin selects the conversion mode of the converter. When high the converter will
convert bipolar input signals; when low it will convert unipolar input signals.
A0 - Multiplexer Selection Input, Pin 1.
Selects the input channel for conversion. A0=0=AIN1. A0 is latched when CONV transitions
from low to high. This input has a pull-down resistor internal to the chip.
Measurement and Reference Inputs
AIN1+, AIN2+, AIN1-, AIN2- - Differential Analog Inputs, Pins 8, 9, 10, 11.
Analog differential inputs to the delta-sigma modulator.
VREF+, VREF- - Differential Voltage Reference Inputs, Pins 12, 13.
A differential voltage reference on these pins operates as the voltage reference for the
converter. The voltage between these pins can be any voltage between 1.0 and 3.6 volts.
Power Supply Connections
VA+ - Positive Analog Power, Pin 14.
Positive analog supply voltage. Nominally +5 volts.
VA- - Negative Analog Power, Pin 15.
Negative analog supply voltage. Nominally -5volts.
VD+ - Positive Digital Power, Pin 17.
Positive digital supply voltage. Nominally +5 volts or +3.3 volts.
DGND - Digital Ground, Pin 16.
Digital Ground.
DS126F2
21
CS5504
SPECIFICATION DEFINITIONS
Linearity Error
The deviation of a code from a straight line which connects the two endpoints of the A/D
Converter transfer function. One endpoint is located 1/2 LSB below the first code transition
and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in
percent of full-scale.
Differential Nonlinearity
The deviation of a code’s width from the ideal width. Units in LSBs.
Full Scale Error
3
The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - ⁄2 LSB].
Units are in LSBs.
Unipolar Offset
The deviation of the first code transition from the ideal (1⁄2 LSB above the voltage on the AIN-
pin.) when in unipolar mode (BP/UP low). Units are in LSBs.
Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1⁄2 LSB below
the voltage on the AIN- pin.) when in bipolar mode (BP/UP high). Units are in LSBs
22
DS126F2
CS5504
ORDERING INFORMATION
Model
Package
Temperature
CS5504-BP
20-pin Plastic DIP
CS5504-BS
-40 to +85 °C
20-pin SOIC
CS5504-BSZ(lead free)
ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
CS5504-BP
Peak Reflow Temp
260 °C
MSL Rating*
Max Floor Life
1
No Limit
240 °C
2
3675DDayasys
CS5504-BS
3
260 °C
CS5504-BSZ (lead free)
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
REVISION HISTORY
Revision
Date
Changes
F1
MAR 1995
AUG 2005
First Final Release
F2
Updated device ordering info. Updated legal notice. Added MSL data..
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
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to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
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or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
DS126F2
23
CS5504
- NOTES -
24
DS126F2
相关型号：
CS5505-AS-R
ADC, Delta-Sigma, 16-Bit, 1 Func, 4 Channel, Serial Access, CMOS, PDSO24, 0.300 INCH, SOIC-24
CIRRUS
CS5505-ASZ-R
ADC, Delta-Sigma, 16-Bit, 1 Func, 4 Channel, Serial Access, CMOS, PDSO24, 0.300 INCH, LEAD FREE, SOIC-24
CIRRUS
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