CS61535A_09 [CIRRUS]
T1/E1 Line Interface; T1 / E1线路接口
| 型号： | CS61535A_09 |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | T1/E1 Line Interface |
| 文件： | 总36页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Jul ’09
CONFIDENTIAL
CS61535A
T1/E1 Line Interface
Features
General Description
The CS61535A combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
Provides Analog PCM Line Interface
•
for T1 and E1 Applications
The device features a transmitter jitter attenuator mak-
ing it ideal for use in asynchronous multiplexor systems
with gapped transmit clocks. The CS61535A provides a
matched, constant impedance output stage to insure
signal quality on mismatched, poorly terminated lines.
Provides Line Driver, and Data and
Clock Recovery Functions
•
Transmit Side Jitter Attenuation
Starting at 6 Hz, with > 300 UI of Jitter
Tolerance
•
The IC uses a digital Delay-Locked-Loop clock and
data recovery circuit which is continuously calibrated
from a crystal reference to provide excellent stability
and jitter tolerance.
Applications
Low Power Consumption
(typically 175 mW)
•
• Interfacing network transmission equipment such as
SONET multiplexor and M13 to a DSX-1 cross connect.
B8ZS/HDB3/AMI Encoders/Decoders
•
• Interfacing customer premises equipment to a CSU.
• Interfacing to E1 links.
14 dB of Transmitter Return Loss
•
Compatible with SONET, M13 , CCITT
G.742, and Other Asynchronous
Muxes
•
Ordering Information
CS61535A-IL1Z
28 Pin PLCC (Lead-free)
CS61535A-IL1 28 Pin PLCC (j-leads)
[ ] = Pin Function in
( ) = Pin Function in Host Mode
Extended Hardware Mode
(CLKE) (INT) (SDI) (SDO)
XTALIN XTALOUT MODE TAOS LEN0 LEN1 LEN2
TGND TV+
9
10
5
28
23
24
25
14
15
13
16
TTIP
2
TCLK
JITTER
ATTENUATOR
PULSE
SHAPER
CONTROL
3
4
TRING
TPOS
[TDATA]
TNEG
[TCODE]
RCLK
LINE DRIVER
AMI,
B8ZS,
HDB3
LINE RECEIVER
19
RTIP
8
CLOCK &
DATA
RECOVERY
CODER
20
17
7
RRING
RPOS
[RDATA]
RNEG
LOOP
BACK
6
MTIP
SIGNAL
QUALITY
[RCODE]
MRING
[PCS]
DPM
[BPV]
DRIVER
18
MONITOR
MONITOR
11
26
27
1
12
21
22
[AIS]
RLOOP LLOOP
(CS) (SCLK)
ACLKI LOS
RV+ RGND
Cirrus Logic, Inc.
JUL ’09
Copyright @ Cirrus Logic, Inc. 2009
http://www.cirrus.com
(All Rights Reserved)
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CS61535A
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Min
Max
Units
DC Supply
(referenced to RGND,TGND=0V)
RV+
-
6.0
V
TV+
-
(RV+) + 0.3
V
V
Input Voltage, Any Pin
Input Current, Any Pin
Ambient Operating Temperature
(Note 1)
(Note 2)
Vin
Iin
TA
RGND-0.3
-10
(RV+) + 0.3
10
85
150
mA
°C
°C
-40
-65
Storage Temperature
Tstg
WARNING:Operations at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Notes: 1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V.
2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND
can withstand a continuous current of 100 mA.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Units
DC Supply
Ambient Operating Temperature
(Note 3) RV+, TV+
TA
4.75
-40
5.0
25
5.25
85
V
°C
Power Consumption
Power Consumption
(Notes 4, 5)
(Notes 4, 6)
PC
PC
-
-
290
175
350
-
mW
mW
Notes: 3. TV+ must not exceed RV+ by more than 0.3V.
4. Power consumption while driving line load over operating temperature range. Includes IC and load.
Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF load.
5. Assumes 100% ones density and maximum line length at 5.25V.
6. Assumes 50% ones density and 300ft. line length at 5.0V.
2
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CS61535A
DIGITAL CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V 5%; GND = 0V)
Parameter
Symbol
Min
Typ
Max
Units
High-Level Input Voltage
Pins 1-4, 17, 18, 23-28
Low-Level Input Voltage
Pins 1-4, 17, 18, 23-28
(Notes 7, 8, 9)
(Notes 7, 8, 9)
(Notes 7, 8, 10)
(Notes 7, 8, 10)
VIH
VIL
2.0
-
-
-
-
-
0.8
-
V
V
V
High-Level Output Voltage (I
= -40 μA)
OUT
VOH
VOL
4.0
Pins 6-8, 11, 12, 25
Low-Level Output Voltage (I
= 1.6 mA)
OUT
Pins 6-8, 11, 12, 23, 25
-
-
-
-
-
-
-
-
0.4
10
0.2
-
V
μA
V
V
V
Input Leakage Current (Except Pin 5)
Low-Level Input Voltage, Pin 5
High-Level Input Voltage, Pin 5
Mid-Level Input Voltage, Pin 5
VIL
VIH
VIM
(RV+) - 0.2
2.3
(Note 11)
2.7
Notes: 7. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40μA).
8. In Host Mode, pin 23 is an open drain output and pin 25 is a tristate output.
9. Pins 17 and 18 of the CS61535A are digital inputs in the Extended Hardware Mode.
10. Output drivers will drive CMOS logic levels into a CMOS load.
11. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating.
ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V 5%; GND = 0V)
Parameter
Min
Typ
Max
Units
Jitter Attenuator
Jitter Attenuation Curve Corner Frequency
(Note 12)
-
6
-
Hz
T1 Jitter Attenuation in Remote Loopback
(Note 13)
Jitter Freq. [Hz]
Amplitude [UIpp]
10
10
10
10
5
3.0
20
35
40
40
6.0
30
35
50
50
-
-
-
-
-
dB
dB
dB
dB
dB
100
500
1k
10k, 40k
0.3
E1 Jitter Attenuation in Remote Loopback
(Note 14)
Jitter Freq. [Hz]
Amplitude [UIpp]
10
1.5
1.5
1.5
1.5
0.2
3.0
20
30
35
35
6.0
32
43
50
50
-
-
-
-
-
dB
dB
dB
dB
dB
100
400
1k
10k, 100k
Attenuator Input Jitter Tolerance
(Note 15)
12
23
-
UI
Notes: 12. Not production tested. Parameters guaranteed by design and characterization.
13. Attenuation measured at the demodulator output of an HP3785B with input jitter equal to 3/4 of
measured jitter tolerance using a measurement bandwidth of 1 Hz (10<f<100Hz), 4Hz (100<f<1000
Hz) and 10 Hz (f> 1kHz) centered around the jitter frequency. With a 215-1 PRBS data pattern.
Crystal must meet specifcations in Appendix A.
14. Jitter measured at the demodulator output of an HP3785A using a measurement
bandwidth not to exceed 20 Hz centered around the jitter frequency. With a 215-1 PRBS data pattern.
Crystal must meet specifications in Appendix A.
15. Output jitter increases significantly when attenuator input jitter tolerance is exceeded.
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CS61535A
ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V 5%; GND = 0V)
Parameter
Min
Typ
Max
Units
Transmitter
AMI Output Pulse Amplitudes
(Note 16)
(Note 17)
(Note 18)
(Note 19)
(Note 20)
2.14
2.7
2.37
3.0
2.6
3.3
3.3
3.6
V
V
V
V
E1, 75 Ω
E1, 120 Ω
2.7
3.0
T1, FCC Part 68
T1, DSX-1
2.4
3.0
E1 Zero (space) level (LEN2/1/0 = 0/0/0)
-0.237
-0.3
-
-
0.237
0.3
V
V
75Ω application
(Note 17)
(Note 18)
120Ω application
Recommended Output Load at TTIP and TRING
-
75
-
Ω
Jitter Added During Remote Loopback
(Note 21)
-
-
-
-
0.005
0.008
0.010
0.015
0.02
0.025
0.025
0.05
UI
UI
UI
UI
10Hz - 8kHz
8kHz - 40kHz
10Hz - 40kHz
Broad Band
Power in 2kHz band about 772kHz
Power in 2kHz band about 1.544MHz
(referenced to power in 2kHz band at 772kHz)
(Notes 12, 16)
(Notes 12, 16)
12.6
-29
15
-38
17.9
-
dBm
dB
Positive to Negative Pulse Imbalance
(Notes 12, 16)
-
-5
-5
0.2
-
-
0.5
5
5
dB
%
%
T1, DSX-1
E1 amplitude at center of pulse
E1 pulse width at 50% of nominal amplitude
Transmitter Return Loss
(Notes 12, 16, 22)
8
14
10
-
-
-
-
-
-
dB
dB
dB
51 kHz to 102 kHz
102 kHz to 2.048 MHz
2.048 MHz to 3.072 MHz
Transmitter Short Circuit Current
(Notes 12, 23)
-
-
50
mA RMS
Notes: 16. Using a 0.47 μF capacitor in series with the primary of a transformer recommended
in the Applications Section.
17. Amplitude measured at the transformer (CS61535A-1:1 or 1:1.26) output across a
75 Ω load for line length setting LEN2/1/0 = 0/0/0.
18. Amplitude measured at the transformer (CS61535A-1:1.26) output across a
120 Ω load for line length setting LEN2/1/0 = 0/0/0.
19. Amplitude measured at the transformer (CS61535A-1:1.15) output across a
100 Ω load for line length setting LEN2/1/0 = 0/1/0.
20. Amplitude measured across a 100 Ω load at the DSX-1 cross-connect for line length settings
LEN2/1/0 = 0/1/1, 1/0/0, 1/0/1, 1/1/0 and 1/1/1 after the length of #22 AWG ABAM equivalent cable
specified in Table 3. The CS61535A requires a 1:1.15 transformer.
21. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK.
22. Return loss = 20 log10 ABS((z1 +z0)/(z1-z0)) where z1 = impedance of the transmitter, and
z0 = impedance of line load. Measured with a repeating 1010 data pattern with LEN2/1/0 = 0/0/0
and a 1:1 transformer terminated with a 75Ω load, or a 1:1.26 transformer terminated with a
120Ω load.
23. Measured broadband through a 0.5 Ω resistor across the secondary of a 1:1.26 transformer
during the transmission of an all ones data pattern for LEN2/1/0 = 0/0/0.
4
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CS61535A
ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V 5%; GND = 0V)
Parameter
Driver Performance Monitor
Min
Typ
Max
Units
MTIP/MRING Sensitivity:
Differential Voltage Required for Detection
-
0.60
-
V
Receiver
RTIP/RRING Input Impedance
Sensitivity Below DSX (0dB = 2.4V)
-
50k
-
-
-
Ω
dB
-13.6
Data Decision Threshold
60
53
45
65
65
50
70
77
55
% of peak
% of peak
% of peak
T1, DSX-1
(Note 24)
(Note 25)
(Note 26)
T1, DSX-1
T1, FCC Part 68 and E1
Data Decision Threshold
T1
E1
-
-
65
50
-
-
% of peak
% of peak
Allowable Consecutive Zeros before LOS
160
175
190
bits
Receiver Input Jitter Tolerance
10kHz - 100kHz
2kHz
(Note 27)
(Note 28)
0.4
6.0
300
-
-
-
-
-
-
UI
UI
UI
10Hz and below
Loss of Signal Threshold
0.25
0.30
0.50
V
Notes: 24. For input amplitude of 1.2 Vpk to 4.14 Vpk.
25. For input amplitude of 0.5 Vpk to 1.2 Vpk and from 4.14 Vpk to RV+.
26. For input amplitude of 1.05 Vpk to 3.3 Vpk.
27. Jitter tolerance increases at lower frequencies. See Figure 11.
28. LOS goes high after 160 to 190 consecutive zeros are received. A zero is output on RPOS and
RNEG (or RDATA) for each bit period where the input signal amplitude remains below the data
decision threshold. The analog input squelch circuit operates when the input signal amplitude above
ground on the RTIP and RRING pins falls within the squelch range long enough for the internal
slicing threshold to decay within this range. Operation of the squelch causes zeros to be output on
RPOS and RNEG as long as the input amplitude remains below 0.25V. During receive LOS, pulses
greater than 0.25V in amplitude may be output on RPOS and RNEG. LOS returns low after the ones
density reaches 12.5% (based upon 175 bit periods starting with a one and containing
less than 100 consecutive zeros) as prescribed in ANSI T1.231-1993.
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CS61535A
T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V 5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol
Min
Typ
Max
Units
Crystal Frequency
ACLKI Duty Cycle
ACLKI Frequency
RCLK Duty Cycle
(Note 29)
fc
-
40
-
-
-
6.176000
-
60
-
-
-
MHz
%
MHz
%
%
t
pwh3/tpw3
faclki
pwh1/tpw1
-
(Note 30)
(Notes 31, 32)
1.544
78
29
t
RCLK Cycle Width
(Note 32)
tpw1
tpwh1
tpwl1
320
130
100
648
190
458
980
240
850
ns
ns
ns
Rise Time, All Digital Outputs
Fall Time, All Digital Outputs
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
RDATA Valid Before RCLK Falling
RPOS/RNEG Valid Before RCLK Rising
RPOS/RNEG Valid After RCLK Falling
RDATA Valid After RCLK Falling
RPOS/RNEG Valid After RCLK Rising
TCLK Frequency
(Note 33)
(Note 33)
tr
tf
tsu2
th2
tsu1
tsu1
tsu1
th1
th1
th1
ftclk
tpwh2
-
-
25
25
150
150
150
150
150
150
-
-
-
-
85
85
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
-
(Note 34)
(Note 35)
(Note 31)
(Note 34)
(Note 35)
(Note 31)
274
274
274
274
274
274
1.544
-
-
TCLK Pulse Width
(Notes 12, 31, 34, 36, 37)
80
150
-
-
500
500
(Notes 35, 36, 37)
Notes: 29. Crystal must meet specifications described in Appendix A.
30. ACLKI provided by an external source or TCLK, but not RCLK.
31. Hardware Mode, or Host Mode (CLKE = 0).
32. RCLK cycle width will vary with extent by which pulses displaced by jitter. Specified under worst case
jitter conditions: 0.4 UI AMI data displacement for T1 and 0.2 UI AMI data displacement for E1.
33. At max load of 1.6 mA and 50 pF.
34. Host Mode (CLKE = 1).
35. Extended Hardware Mode.
36. The maximum TCLK burst rate is 5 MHz and tpw2(min) = 200 ns. The maximum gap size that can
be tolerated on TCLK is 12 VI.
37. The transmitted pulse width does not depend on the TCLK duty cycle.
t
pw1
EXTENDED
HARDWARE
MODE OR
RCLK
HOST MODE
(CLKE = 1)
t
t
pwh1
pwl1
t
t
h1
su1
RPOS
RNEG
RDATA
BPV
HARDWARE
MODE OR
HOST MODE
(CLKE = 0)
RCLK
Figure 1. Recovered Clock and Data Switching Characteristics
6
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CS61535A
E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V 5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol
Min
Typ
Max
Units
Crystal Frequency
ACLKI Duty Cycle
ACLKI Frequency
RCLK Duty Cycle
RCLK Cycle Width
(Note 29)
fc
-
40
-
8.192000
-
60
-
MHz
%
MHz
%
ns
ns
ns
t
pwh3/tpw3
faclki
pwh1/tpw1
tpw1
tpwh1
tpwl1
-
(Note 30)
(Notes 31, 32)
(Note 32)
2.048
29
488
140
348
t
-
-
310
670
190
500
90
120
RCLK Cycle Width
(Note 32)
tpw1
tpwh1
tpwl1
320
488
348
140
670
ns
ns
ns
-
-
100
-
Rise Time, All Digital Outputs
Fall Time, All Digital Outputs
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
RDATA Valid Before RCLK Falling
RPOS/RNEG Valid Before RCLK Rising
RPOS/RNEG Valid After RCLK Falling
RDATA Valid After RCLK Falling
RPOS/RNEG Valid After RCLK Rising
TCLK Frequency
(Note 33)
(Note 33)
tr
tf
tsu2
th2
tsu1
tsu1
tsu1
th1
th1
th1
ftclk
tpwh2
-
-
25
25
100
100
100
100
100
100
-
-
-
-
85
85
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
-
(Note 34)
(Note 35)
(Note 31)
(Note 34)
(Note 35)
(Note 31)
194
194
194
194
194
194
2.048
-
-
TCLK Pulse Width
(Notes 31, 34, 36, 37)
(Notes 35, 36, 37)
80
150
-
-
340
340
t
t
r
f
90%
10%
90%
10%
Figure 2. Signal Rise and Fall Characteristics
Any Digital Output
t
pw2
t
t
pwh2
su2
t
pw3
TCLK
t
t
pwh3
h2
TPOS/TNEG
ACLKI
Figure 3b. Alternate External Clock Characteristics
Figure 3a. Transmit Clock and Data Switching
Characteristics
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CS61535A
SWITCHING CHARACTERISTICS (TA = -40° to 85°C; TV+, RV+ = 5%;
Inputs: Logic 0 = 0V, Logic 1 = RV+)
Parameter
Symbol
Min
Typ
Max
Units
SDI to SCLK Setup Time
SCLK to SDI Hold Time
SCLK Low Time
tdc
tcdh
tcl
tch
tr, tf
tcc
tcch
tcwh
tcdv
tcdz
tsu4
th4
50
50
240
240
-
50
50
250
-
-
-
-
-
-
-
-
-
-
-
-
-
50
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK High Time
SCLK Rise and Fall Time
CS to SCLK Setup Time
SCLK to CS Hold Time
CS Inactive Time
SCLK to SDO Valid
CS to SDO High Z
(Note 38)
(Note 39)
-
200
-
100
-
-
-
-
Input Valid To PCS Falling Setup Time
PCS Rising to Input Invalid Hold Time
PCS Active Low Time
50
50
250
-
-
-
tpcsl
Notes: 38. For CLKE = 0, CS must remain low at least 50 ns after the 16th falling edge of SCLK.
39. Output load capacitance = 50pF.
t
cwh
CS
t
t
cch
ch
t
cc
t
cl
SCLK
SDI
t
t
cdh
cdh
t
dc
LSB
LSB
MSB
CONTROL BYTE
DATA BYTE
Figure 4. Serial Port Write Timing Diagram
8
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CS61535A
CS
t
cdz
SCLK
t
cdv
SDO
HIGH Z
CLKE = 1
Figure 5. Serial Port Read Timing Diagram
PCS
t
t
h4
su4
t
pcsl
LEN0/1/2, TAOS,
RLOOP, LLOOP,
RCODE, TCODE
VALID INPUT DATA
Figure 6. Extended Hardware Mode Parallel Chip Select Timing Diagram
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CS61535A
THEORY OF OPERATION
ꢕꢑꢃꢑꢁꢍ ꢖꢃꢏꢖꢃꢀꢕ<ꢚꢂꢑꢃꢇꢃꢕꢖꢐꢃ4!ꢃ?ꢏꢒꢙꢌꢂꢃ>!ꢃꢕꢖꢐꢃ?ꢏꢒꢙꢌꢂꢑ
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Enhancements in CS61535A
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢈꢊꢃꢔ ꢍꢐꢂꢑꢃ ꢕꢌꢂꢃ +ꢕꢌꢐ ꢕꢌꢂꢃ' ꢍꢐꢂ!ꢃ :.$
ꢘꢂꢖꢐꢂꢐꢃ+ꢕ ꢌꢐ ꢕꢌꢂꢃ'ꢍꢐꢂ !ꢃꢕ ꢖꢐꢃ+ꢍ ꢑꢘꢃ'ꢍꢐꢂ3ꢃ"ꢖ
+ꢕꢌꢐ ꢕꢌꢂꢃꢕꢖꢐꢃ:.ꢘꢂꢖꢐꢂꢐꢃ+ꢕꢌꢐ ꢕꢌꢂꢃ'ꢍꢐꢂꢑ!ꢃꢐꢏꢑꢗꢌꢂꢘꢂ
ꢋꢏꢖꢑꢃꢕꢌꢂꢃꢙꢑꢂꢐꢃꢘꢍꢃꢗꢍꢖꢓꢏꢒꢙꢌꢂꢃꢕꢖꢐꢃꢔꢍꢖꢏꢘꢍꢌꢃꢘꢁꢂꢃꢐꢂꢎꢏꢗꢂ3
ꢀꢁꢂꢃ:.ꢘꢂꢖꢐꢂꢐꢃ+ꢕꢌꢐ ꢕꢌꢂꢃ'ꢍꢐꢂꢃꢋꢌꢍꢎꢏꢐꢂꢑꢃꢕꢃ ꢋꢕꢌꢕꢚꢚꢂꢚ
ꢗꢁꢏꢋꢃꢑꢂꢚꢂꢗꢘꢃꢏꢖꢋꢙꢘꢃ ꢁꢏꢗꢁꢃꢚꢕꢘꢗꢁꢂꢑꢃꢘꢁꢂꢃꢗꢍꢖꢘꢌꢍꢚꢃꢏꢖꢋꢙꢘꢑ
ꢕꢚꢚꢍ ꢏꢖꢒꢃꢏ ꢖꢐꢏꢎꢏꢐꢙꢕꢚꢃ" ꢄꢑꢃ ꢘꢍꢃ< ꢂꢃ ꢗꢍꢖꢓꢏꢒꢙꢌꢂꢐꢃ ꢙꢑꢏꢖꢒꢃ ꢕ
ꢗꢍꢔꢔꢍꢖꢃꢑꢂꢘꢃꢍꢓꢃꢗꢍꢖꢘꢌꢍꢚꢃꢚꢏꢖꢂꢑ3ꢃ"ꢖꢃꢘꢁꢂꢃ+ꢍꢑꢘꢃ'ꢍꢐꢂ!ꢃꢕꢖ
ꢂ.ꢘꢂꢌꢖꢕꢚꢃꢋꢌꢍꢗꢂꢑꢑꢍꢌꢃꢔꢍꢖꢏꢘꢍꢌꢑꢃꢕꢖꢐꢃꢗꢍꢖꢓꢏꢒꢙꢌꢂꢑꢃꢘꢁꢂꢃꢐꢂ$
ꢎꢏꢗꢂꢃꢘꢁꢌꢍꢙꢒꢁꢃꢕꢃꢑꢂꢌ ꢏꢕꢚꢃꢏꢖꢘꢂꢌꢓꢕꢗꢂ3ꢃꢀꢁ ꢂꢌꢂꢃꢕꢌꢂꢃꢘꢁꢏꢌꢘꢂꢂꢖ
ꢔꢙꢚꢘꢏ$ꢓꢙꢖꢗꢘꢏꢍꢖꢃꢋꢏꢖꢑ ꢃ ꢁꢍꢑ ꢂꢃꢓꢙꢖꢗꢘꢏꢍꢖ ꢕꢚꢏꢘ#ꢃꢏ ꢑꢃꢐꢂꢘ ꢂꢌ$
ꢔꢏꢖꢂꢐꢃ<#ꢃꢘꢁꢂꢃꢍꢋꢂꢌꢕꢘꢏꢖꢒꢃꢔꢍꢐꢂꢃ0ꢑꢂꢂꢃꢀꢕ<ꢚꢂꢃ413
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊꢃꢋꢌꢍꢎꢏꢐꢂꢑꢃꢁꢏꢒꢁꢂꢌꢃꢋꢂꢌꢓꢍꢌꢔꢕꢖꢗꢂꢃꢕꢖꢐ
ꢔꢍꢌꢂꢃꢓꢂꢕꢘꢙꢌꢂꢑꢃꢘꢁꢕꢖꢃꢘꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢃꢏꢖꢗꢚꢙꢐꢏꢖꢒꢛ
• ꢈꢜꢝꢃꢚꢍ ꢂꢌꢃꢋꢍ ꢂꢌꢃꢗꢍꢖꢑꢙꢔꢋꢘꢏꢍꢖ!
• "ꢖꢘꢂꢌꢖꢕꢚꢚ#ꢃꢔ ꢕꢘꢗꢁꢂꢐꢃꢘꢌꢕ ꢖꢑꢔꢏꢘꢘꢂꢌꢃꢍꢙ ꢘꢋꢙꢘꢃꢏꢔ ꢋꢂꢐ$
ꢕꢖꢗꢂꢃꢓꢍꢌꢃꢏꢔꢋꢌꢍꢎꢂꢐꢃꢑꢏꢒꢖꢕꢚꢃ%ꢙꢕꢚꢏꢘ#!
• &ꢋꢘꢏꢍꢖꢕꢚꢃꢊ'"!ꢃ()*ꢅ!ꢃ+,(ꢉꢃꢂꢖꢗꢍꢐꢂꢌ-ꢐꢂꢗꢍꢐꢂꢌ
ꢍꢌꢃꢂ.ꢘꢂꢌꢖꢕꢚꢃꢚꢏꢖꢂꢃꢗꢍꢐꢏꢖꢒꢃꢑꢙꢋꢋꢍꢌꢘ!
• /ꢂꢗꢂꢏꢎꢂꢌꢃꢊ"ꢅꢃ0ꢙꢖꢓꢌꢕꢔꢂꢐꢃꢕꢚꢚꢃꢍꢖꢂꢑ1ꢃꢐꢂꢘꢂꢗꢘꢏꢍꢖ!
• ꢊ2ꢅ"ꢃꢀꢇ34ꢉ ꢇ$ꢇ55ꢉꢃꢗꢍ ꢔꢋꢚꢏꢕꢖꢘꢃꢌ ꢂꢗꢂꢏꢎꢂꢌꢃ6 ꢍꢑꢑ
ꢍꢓꢃꢅꢏꢒꢖꢕꢚꢃ06&ꢅ1ꢃꢁꢕꢖꢐꢚꢏꢖꢒ!
• ꢀꢌꢕꢖꢑꢔꢏꢘꢘꢂꢌꢃꢀ ꢀ"7ꢃꢕ ꢖꢐꢃꢀ /"28ꢃꢍ ꢙꢘꢋꢙꢘꢑꢃꢕ ꢌꢂ
ꢓꢍꢌꢗꢂꢐꢃꢚꢍ ꢃ ꢁꢂꢖꢃꢀꢄ69ꢃꢏꢑꢃꢑꢘꢕꢘꢏꢗ!
Transmitter
• ꢀꢁꢂꢃ,ꢌꢏ ꢎꢂꢌꢃ7ꢂꢌꢓ ꢍꢌꢔꢕꢖꢗꢂꢃ'ꢍꢖꢏꢘꢍꢌꢃꢍꢋꢂꢌ ꢕꢘꢂꢑ
ꢍꢎꢂꢌꢃꢕꢃ ꢏꢐꢂꢌꢃꢌꢕꢖꢒꢂꢃꢍꢓꢃꢏꢖꢋꢙꢘꢃꢑꢏꢒꢖꢕꢚꢃꢚꢂꢎꢂꢚꢑ3
• :ꢚꢏꢔꢏꢖꢕꢘꢏꢍꢖꢃꢍꢓ ꢃꢘꢁ ꢂꢃꢌ ꢂ%ꢙꢏꢌꢂꢔꢂꢖꢘꢃꢘ ꢁꢕꢘꢃꢕ ꢃꢌ ꢂꢓꢂꢌ$
ꢂꢖꢗꢂꢃꢗꢚꢍꢗ;ꢃ<ꢂꢃꢏꢖꢋꢙꢘꢃꢍꢖꢃꢘꢁꢂꢃꢊꢄ69"ꢃꢋꢏꢖ3
ꢀꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢌꢃꢘꢕ;ꢂꢑꢃꢐꢕꢘꢕꢃꢓꢌꢍꢔꢃꢕ ꢃꢀꢇꢃ0ꢍꢌꢃ:ꢇ1ꢃꢘꢂꢌ$
ꢔꢏꢖꢕꢚ!ꢃꢕꢘꢘꢂꢖꢙꢕꢘꢂꢑ ꢃ@ꢏꢘꢘꢂꢌ !ꢃꢕꢖꢐꢃꢋꢌꢍꢐꢙꢗꢂꢑ ꢃꢋꢙ ꢚꢑꢂꢑꢃꢍ ꢓ
ꢕꢋꢋꢌꢍꢋꢌꢏꢕꢘꢂꢃꢑ ꢁꢕꢋꢂ3ꢃꢀꢁ ꢂꢃꢘ ꢌꢕꢖꢑꢔꢏꢘꢃꢗ ꢚꢍꢗ;!ꢃꢀꢄ 69!
ꢕꢖꢐꢃꢘꢌꢕꢖꢑꢔꢏꢘꢃꢐꢕꢘꢕ!ꢃꢀ7&ꢅꢃAꢃꢀ2:8ꢃꢍꢌꢃꢀ,ꢊꢀꢊ!ꢃꢕꢌꢂ
ꢑꢙꢋꢋꢚꢏꢂꢐꢃ ꢑ#ꢖꢗꢁꢌꢍꢖꢍꢙꢑꢚ#3ꢃ ,ꢕꢘꢕꢃꢏꢑ ꢃꢑ ꢕꢔꢋꢚꢂꢐꢃ ꢍꢖꢃꢘ ꢁꢂ
ꢓꢕꢚꢚꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃꢘꢁꢂꢃꢏꢖꢋꢙꢘꢃꢗꢚꢍꢗ;!ꢃꢀꢄ693
:.ꢏꢑꢘꢏꢖꢒꢃꢐꢂꢑꢏꢒꢖꢑꢃꢙꢑꢏꢖꢒꢃꢘꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢃꢗꢕꢖꢃ<ꢂꢃꢗꢍꢖꢎꢂꢌꢘꢂꢐ
ꢘꢍꢃꢘꢁꢂꢃꢁꢏꢒꢁꢂꢌꢃꢋꢂꢌꢓꢍꢌꢔꢕꢖꢗꢂ!ꢃꢋꢏꢖ$ꢗꢍꢔꢋꢕꢘꢏ<ꢚꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊ
ꢏꢓꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢃꢘꢌꢕꢖꢑꢓꢍꢌꢔꢂꢌꢃꢏꢑꢃꢌꢂꢋꢚꢕꢗꢂꢐꢃ<#ꢃꢕꢃꢋꢏꢖ $ꢗꢍꢔ$
ꢋꢕꢘꢏ<ꢚꢂꢃꢘꢌꢕꢖꢑꢓꢍꢌꢔꢂꢌꢃ ꢏꢘꢁꢃꢕꢃꢖꢂ ꢃꢘꢙꢌꢖꢑꢃꢌꢕꢘꢏꢍꢃꢕꢖꢐꢃꢘꢁꢂꢃ=3=
Ωꢃꢌꢂꢑꢏꢑꢘꢍꢌꢃꢙꢑꢂꢐꢃꢏꢖꢃ:ꢇꢃ>ꢈꢃΩꢃꢕꢋꢋꢚꢏꢗꢕꢘꢏꢍꢖꢑꢃꢏꢑꢃꢑꢁꢍꢌꢘꢂꢐ3
:ꢏꢘꢁꢂꢌꢃꢀ ꢇꢃ0,ꢅB$ꢇꢃꢍ ꢌꢃ2ꢂ ꢘ ꢍꢌ;ꢃ"ꢖꢘ ꢂꢌꢓꢕꢗꢂ1ꢃꢍꢌꢃ: ꢇ
83>ꢜꢉꢃꢋꢙꢚꢑꢂꢃꢑꢁꢕꢋꢂꢑꢃꢔꢕ#ꢃ<ꢂꢃꢑꢂ ꢚꢂꢗꢘꢂꢐ3ꢃ7ꢙꢚꢑꢂꢃꢑꢁꢕꢋ$
ꢏꢖꢒꢃꢕꢖꢐ ꢃꢑꢏꢒꢖ ꢕꢚꢃꢚ ꢂꢎꢂꢚꢃꢕꢌ ꢂꢃꢐ ꢂꢘꢂꢌꢔꢏꢖꢂꢐꢃ<# ꢃC ꢚꢏꢖꢂ
ꢚꢂꢖꢒꢘꢁꢃꢑ ꢂꢚꢂꢗꢘCꢃꢏꢖ ꢋꢙꢘꢑꢃꢕꢑ ꢃꢑ ꢁꢍ ꢖꢃꢏꢖ ꢃꢀꢕ<ꢚꢂꢃꢉ 3ꢃꢀꢁ ꢂ
Introduction to Operating Modes
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢈꢊꢃꢑ ꢙꢋꢋꢍꢌꢘꢑꢃꢘ ꢁꢌꢂꢂꢃꢍ ꢋꢂꢌꢕꢘꢏꢖꢒꢃꢔ ꢍꢐꢂꢑ
ꢁꢏꢗꢁꢃꢕꢌꢂꢃꢑꢂꢚꢂꢗꢘꢂꢐꢃ<#ꢃꢘꢁꢂꢃꢚꢂꢎꢂꢚꢃꢍꢓꢃꢘꢁꢂꢃ'&,:ꢃꢋꢏꢖ
MODE
EXTENDED
HARDWARE
TDATA
TCODE
BPV
RDATA
AIS
RCODE
-
PCS
LEN0
LEN1
LEN2
RLOOP
LLOOP
TAOS
MODE
FUNCTION
PIN HARDWARE
HOST
TPOS
TNEG
RNEG
RPOS
DPM
MTIP
MRING
-
INT
SDI
SDO
CS
SCLK
CLKE
EXTENDED
HARDWARE
<0.2V
HOST
HARDWARE
3
4
6
7
TPOS
TNEG
RNEG
RPOS
DPM
TRANSMITTER
MODE-PIN
INPUT LEVEL
FLOAT, or
2.5V
>(RV+) - 0.2V
INDIVIDUAL
CONTROL
LINES &
RECEIVER/DPM
CONTROL
SERIAL
μ-PROCESSOR
PORT
INDIVIDUAL
CONTROL
LINES
11
17
18
18
23
24
25
26
27
28
CONTROL
METHOD
MTIP
MRING
-
PARALLEL
CHIP
SELECT
LINE CODE
ENCODER &
DECODER
AMI,
B8ZS,
HDB3
LEN0
LEN1
LEN2
RLOOP
LLOOP
TAOS
NONE
NO
NONE
NO
AIS DETECTION
YES
DRIVER
PERFORM-
ANCE MONITOR
YES
NO
YES
Table 1. Differences in Operating Modes
Table 2. Pin Definitions
10
DS40F3
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
HARDWARE MODE
TAOS LLOOP RLOOP
LEN0/1/2
CONTROL
TPOS
TNEG
TTIP
JITTER
ATTENUATOR
TRANSMIT
TRANSFORMER
LINE DRIVER
TRING
MRING
MTIP
CS62180B
FRAMER
CIRCUIT
DRIVER MONITOR
LINE RECEIVER
CS61535A
DPM
RTIP
RPOS
RNEG
RECEIVE
TRANSFORMER
RRING
EXTENDED HARDWARE MODE
TCODE RCODE
TAOS LLOOP RLOOP PCS LEN0/1/2
CONTROL
TTIP
JITTER
TDATA
TRANSMIT
TRANSFORMER
LINE DRIVER
ATTENUATOR
TRING
AMI
HIGH
SPEED
MUX
CS61535A
B8ZS,
HDB3,
CODER
RTIP
(e.g., M13)
AIS
RECEIVE
TRANSFORMER
RDATA
LINE RECEIVER
DETECT
RRING
BPV
AIS
HOST MODE
CLKE
P SERIAL PORT
5
μ
CONTROL
CONTROL
TPOS
TNEG
TTIP
TRANSMIT
TRANSFORMER
JITTER
ATTENUATOR
LINE DRIVER
TRING
CS62180B
FRAMER
CIRCUIT
MRING
MTIP
CS61535A
DRIVER MONITOR
DPM
RTIP
RPOS
RNEG
RECEIVE
TRANSFORMER
LINE RECEIVER
RRING
Figure 7. Overview of Operating Modes
DS40F3
11
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
LEN2 LEN1 LEN0 OPTION SELECTED
APPLICATION
ꢏꢐꢘꢁꢃ ꢏꢚ ꢚꢃꢔꢂꢂ ꢘꢃꢘ ꢁꢂꢃ 83>ꢜꢉꢃ ꢋꢙꢚꢑꢂꢃꢑ ꢁꢕꢋꢂꢃꢘ ꢂꢔꢋꢚꢕꢘꢂ
ꢑꢁꢍ ꢖꢃꢏꢖꢃ?ꢏꢒꢙꢌꢂꢃ5!ꢃꢕꢖꢐꢃꢑꢋꢂꢗꢏꢓꢏꢂꢐꢃꢏꢖꢃꢀꢕ<ꢚꢂꢃ=3
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0-133 FEET
133-266 FEET
266-399 FEET
399-533 FEET
533-655 FEET
DSX-1
ABAM
(AT&T 600B
or 600C)
?ꢍꢌꢃ: ꢇꢃꢕ ꢋꢋꢚꢏꢗꢕꢘꢏꢍꢖꢑ!ꢃꢘꢁ ꢂꢃꢄ ꢅꢆꢇꢈꢉꢈꢊꢃꢐ ꢌꢏꢎꢂꢌꢃꢋꢌꢍ$
ꢎꢏꢐꢂꢑꢃꢇ=ꢃꢐ(ꢃꢍꢓꢃꢌꢂꢘꢙꢌꢖꢃꢚꢍꢑꢑꢃꢐꢙꢌꢏꢖꢒꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢑꢑꢏꢍꢖ
ꢍꢓꢃ<ꢍꢘ ꢁꢃꢔꢕꢌ;ꢑ ꢃꢕꢖ ꢐꢃꢑ ꢋꢕꢗꢂꢑ3ꢃꢀ ꢁꢏꢑꢃꢏꢔꢋꢌꢍꢎꢂꢑꢃꢑ ꢏꢒꢖꢕꢚ
%ꢙꢕꢚꢏꢘ#ꢃ<# ꢃꢔ ꢏꢖꢏꢔꢏDꢏꢖꢒꢃꢌ ꢂꢓꢚꢂꢗꢘꢏꢍꢖꢑꢃꢍ ꢓꢓꢃꢘ ꢁꢂꢃꢘ ꢌꢕꢖꢑ$
ꢔꢏꢘꢘꢂꢌ3ꢃꢅꢏꢔꢏꢚꢕꢌꢃꢚꢂꢎꢂꢚꢑꢃꢍꢓꢃꢌꢂꢘꢙꢌꢖꢃꢚꢍꢑꢑꢃꢕꢌꢂꢃꢋꢌꢍꢎꢏꢐꢂꢐ
ꢓꢍꢌꢃꢀꢇꢃꢕꢋꢋꢚꢏꢗꢕꢘꢏꢍꢖꢑ3
AT&T CB113
(CS61535A only)
0
0
1
REPEATER
0
0
0
0
1
1
0
0
1
CCITT G.703
2.048 MHz E1
FCC Part 68, Option A CSU NETWORK
INTERFACE
ANSI T1.403
Table 3. Line Length Selection
ꢀꢁꢂꢃꢄꢅꢆꢇ ꢈꢉꢈꢊꢃꢘꢌ ꢕꢖꢑꢔꢏꢘꢘꢂꢌꢃ ꢏꢚꢚꢃꢐꢂꢘꢂꢗꢘꢃꢕꢃꢓꢕꢏꢚꢂꢐ
ꢀꢄ69!ꢃꢕꢖꢐꢃ ꢏꢚꢚꢃꢓꢍꢌꢗꢂꢃꢘꢁꢂꢃꢀꢀ"7ꢃꢕꢖꢐꢃꢀ/"28ꢃꢍꢙꢘ$
ꢋꢙꢘꢑꢃꢚꢍ 3
ꢄꢅꢆꢇꢈꢉꢈꢊꢃꢚꢏꢖꢂꢃꢐꢌꢏꢎꢂꢌꢃꢏꢑꢃꢐꢂꢑꢏꢒꢖꢂꢐꢃꢘꢍꢃꢐꢌꢏꢎꢂꢃꢕꢃ>ꢈꢃΩ
ꢂ%ꢙꢏꢎꢕꢚꢂꢖꢘꢃꢚꢍꢕꢐ3
?ꢍꢌꢃꢀꢇꢃ,ꢅB$ꢇꢃꢕꢋꢋꢚꢏꢗꢕꢘꢏꢍꢖꢑ!ꢃꢚꢏꢖꢂꢃꢚꢂꢖꢒꢘꢁꢑꢃꢓꢌꢍꢔꢃꢜꢃꢘꢍ
ꢆꢈꢈꢃꢓꢂꢂꢘꢃ0ꢕꢑꢃꢔꢂꢕꢑꢙꢌꢂꢐꢃꢓꢌꢍꢔꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢌꢃꢘꢍꢃꢘꢁꢂ
,ꢅB$ꢇꢃꢗ ꢌꢍꢑꢑꢃꢗ ꢍꢖꢖꢂꢗꢘ1ꢃꢕꢌ ꢂꢃꢑ ꢂꢚꢂꢗꢘꢕ<ꢚꢂ3ꢃꢀꢁꢂꢃꢓ ꢏꢎꢂ
ꢋꢕꢌꢘꢏꢘꢏꢍꢖꢃꢕ ꢌꢌꢕꢖꢒꢂꢔꢂꢖꢘꢃꢔ ꢂꢂꢘꢑꢃꢊ2ꢅ"ꢃꢀ ꢇ3ꢇꢜ4$ꢇ55ꢉ
ꢌꢂ%ꢙꢏꢌꢂꢔꢂꢖꢘꢑꢃ ꢁꢂꢖꢃꢙꢑꢏꢖꢒꢃꢊ(ꢊ'ꢃꢗꢕ<ꢚꢂ3ꢃꢊꢃꢘ#ꢋꢏꢗꢕꢚ
ꢍꢙꢘꢋꢙꢘꢃꢋꢙ ꢚꢑꢂꢃꢏꢑ ꢃꢑ ꢁꢍ ꢖꢃꢏꢖꢃ?ꢏ ꢒꢙꢌꢂꢃ )3ꢃꢀ ꢁꢂꢑꢂꢃꢋꢙ ꢚꢑꢂ
ꢑꢂꢘꢘꢏꢖꢒꢑꢃ ꢗꢕꢖꢃ ꢕꢚꢑꢍꢃ <ꢂꢃꢙꢑ ꢂꢐꢃꢘꢍ ꢃꢔ ꢂꢂꢘꢃꢄꢄ "ꢀꢀꢃꢋꢙ ꢚꢑꢂ
ꢑꢁꢕꢋꢂꢃꢌꢂ%ꢙꢏꢌꢂꢔꢂꢖꢘꢑꢃꢓꢍꢌꢃꢇ3ꢈ==ꢃ'+Dꢃꢍꢋꢂꢌꢕꢘꢏꢍꢖ3ꢃ
NORMALIZED
AMPLITUDE
1.0
AT&T CB 119
SPECIFICATION
0.5
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ꢍꢋꢘꢏꢔꢕꢚꢃꢋꢙ ꢚꢑꢂꢃ ꢏꢐꢘꢁꢃꢓ ꢍꢌꢃ, ꢅB$ꢇꢃ0 ꢉꢈꢜꢃꢖ ꢑ13ꢃꢀ ꢁꢂ
ꢄꢅꢆꢇꢈꢉꢈꢊꢃꢕꢙꢘꢍꢔꢕꢘꢏꢗꢕꢚꢚ#ꢃꢕꢐ@ꢙꢑꢘꢑꢃꢘꢁꢂꢃꢋꢙꢚꢑꢂꢃ ꢏꢐꢘꢁ
<ꢕꢑꢂꢐꢃꢙꢋꢍꢖꢃꢘꢁꢂꢃCꢚꢏꢖꢂꢃꢚꢂꢖꢒꢘꢁꢃCꢃꢑꢂꢚꢂꢗꢘꢏꢍꢖꢃꢔꢕꢐꢂ3
0
CS61535A
OUTPUT
PULSE SHAPE
-0.5
0
250
750
500
TIME (nanoseconds)
1000
ꢀꢁꢂꢃ:ꢇꢃ83>ꢜꢉꢃꢋꢙꢚꢑꢂꢃꢑꢁꢕꢋꢂꢃꢏꢑꢃꢑꢙꢋꢋꢍꢌꢘꢂꢐꢃ ꢏꢘꢁꢃꢚꢏꢖꢂ
ꢚꢂꢖꢒꢘꢁꢃꢑ ꢂꢚꢂꢗꢘꢏꢍꢖꢃ6 :24-ꢇ-ꢜEꢜ-ꢜ-ꢜ3ꢃꢀ ꢁꢂꢃꢋ ꢙꢚꢑꢂ
Figure 8. Typical Pulse Shape at DSX-1 Cross Connect
For coaxial cable, For shielded twisted
75Ω
load
and pair, 120Ω load and
transformer specified transformer specified
in Application Section. in Application Section.
Nominal peak voltage of a mark (pulse)
Peak voltage of a space (no pulse)
Nominal pulse width
2.37 V
0 0.237 V
3 V
0 0.30 V
244 ns
Ratio of the amplitudes of positive and negative
pulses at the center of the pulse interval
0.95 to 1.05*
Ratio of the widths of positive and negative
pulses at the nominal half amplitude
0.95 to 1.05*
* When configured with a 0.47 μF nonpolarized capacitor in series with the TX transformer
primary as shown in Figures A1, A2 and A3.
Table 4. CCITT G.703 Specifications
12
DS40F3
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
0
Percent of
nominal
peak
a) Minimum Attenuation Limit
10
20
30
40
269 ns
voltage
AT&T 62411
Requirements
120
110
100
90
244 ns
194 ns
b) Maximum
Attenuation
Limit
80
50
60
Measured Performance
50
1
10
100
1 k
10 k
Frequency in Hz
Figure 10. Typical Jitter Attenuation Curve
10
0
Nominal Pulse
ꢘꢕꢚꢃꢘꢍꢃꢑꢂꢘꢃꢏꢘꢑꢃꢍꢑꢗꢏꢚꢚꢕꢘꢏꢍꢖꢃꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃꢘꢍꢃꢘꢁꢂꢃꢕꢎꢂꢌꢕꢒꢂ
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ꢏꢖꢃꢘꢁꢂꢃ?"?&3
-10
-20
219 ns
488 ns
Jitter Tolerance of Jitter Attenuator
Figure 9 . Mask of the Pulse at the 2048 kbps Interface
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ꢉꢃꢇ-4ꢃꢍꢌꢃꢐꢏ ꢎꢏꢐꢂꢃ<#ꢃ=ꢃꢇ- 4ꢃꢘꢍꢃꢋꢌꢂ ꢎꢂꢖꢘꢃꢘꢁꢂꢃꢍꢎꢂꢌꢓꢚꢍ
ꢍꢌꢃꢙ ꢖꢐꢂꢌꢓꢚꢍ 3ꢃFꢁꢂꢖꢃꢕꢃꢐ ꢏꢎꢏꢐꢂꢃ< #ꢃꢉꢃꢇ -4ꢃ ꢍꢌꢃ =ꢃ ꢇ-4
ꢍꢗꢗꢙꢌꢑ!ꢃꢘꢁꢂꢃꢐꢕꢘꢕꢃ<ꢏꢘꢃ ꢏꢚꢚꢃ<ꢂꢃꢐꢌꢏꢎꢂꢖꢃꢍꢖꢃꢘꢍ ꢃꢘꢁꢂꢃꢚꢏꢖꢂ
ꢂꢏꢘꢁꢂꢌꢃꢕꢖꢃꢂꢏꢒꢁꢘꢁꢃ<ꢏꢘꢃꢋꢂꢌꢏꢍꢐꢃꢂꢕꢌꢚ#ꢃꢍꢌꢃꢕꢖꢃꢂ ꢏꢒꢁꢘꢁꢃ<ꢏꢘ
ꢋꢂꢌꢏꢍꢐꢃꢚꢕꢘꢂ3
Fꢁꢂꢖꢃꢕꢖ #ꢃꢘ ꢌꢕꢖꢑꢔꢏꢘꢃ ꢗꢍꢖꢘꢌꢍꢚꢃꢋꢏꢖ ꢃ0 ꢀꢊ&ꢅ!ꢃ6 :2ꢜ$4
ꢍꢌꢃ6 6&&71ꢃꢏꢑ ꢃ ꢘꢍꢒꢒꢚꢂꢐ!ꢃꢘꢁ ꢂꢃꢘꢌꢕꢖ ꢑꢔꢏꢘꢘꢂꢌꢃꢑ ꢘꢕ<ꢏꢚꢏDꢂꢑ
ꢏꢘꢁꢏꢖꢃ44 ꢃ<ꢏꢘ ꢃꢋꢂꢌꢏ ꢍꢐꢑ3ꢃꢀꢁ ꢂꢃꢘꢌꢕ ꢖꢑꢔꢏꢘꢘꢂꢌꢃ ꢏꢚꢚ ꢃꢘꢕ; ꢂ
ꢚꢍꢖꢒꢂꢌꢃꢘꢍ ꢃꢑꢘ ꢕ<ꢏꢚꢏDꢂꢃ ꢁꢂ ꢖꢃ/6 &&7ꢃꢏ ꢑꢃꢑ ꢂꢚꢂꢗꢘꢂꢐꢃ< ꢂ$
ꢗꢕꢙꢑꢂꢃꢘꢁꢂꢃꢘꢏꢔꢏꢖꢒꢃꢗꢏꢌꢗꢙꢏꢘꢌ#ꢃꢔꢙꢑꢘꢃꢕꢐ@ꢙꢑꢘꢃꢘꢍꢃꢘꢁꢂꢃꢖꢂ
ꢓꢌꢂ%ꢙꢂꢖꢗ#3
Jitter Attenuator
ꢀꢁꢂꢃ@ꢏꢘꢘꢂꢌꢃꢕꢘꢘꢂꢖꢙꢕꢘꢍꢌꢃꢏꢑꢃꢐꢂꢑꢏꢒꢖꢂꢐꢃꢘꢍꢃꢌꢂꢐꢙꢗꢂꢃ ꢕꢖꢐꢂꢌ
ꢕꢖꢐꢃ@ꢏꢘꢘꢂꢌꢃꢏꢖꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢃꢗꢚꢍꢗ;ꢃꢑꢏꢒꢖꢕꢚ3ꢃ"ꢘꢃꢗ ꢍꢖꢑꢏꢑꢘꢑ
ꢍꢓꢃꢕꢃꢉ4ꢃ<ꢏꢘꢃ?"?&!ꢃꢕꢃꢗꢌ#ꢑꢘꢕꢚꢃꢍꢑꢗꢏꢚꢚꢕꢘꢍꢌ!ꢃꢕꢃꢑꢂꢘꢃꢍꢓꢃꢚꢍꢕꢐ
ꢗꢕꢋꢕꢗꢏꢘꢍꢌꢑꢃꢓꢍꢌꢃꢘꢁꢂꢃꢗꢌ#ꢑꢘꢕꢚ!ꢃꢕꢖꢐꢃꢗꢍꢖꢘꢌꢍꢚꢃꢚꢍꢒꢏꢗ3ꢃꢀꢁꢂ
@ꢏꢘꢘꢂꢌꢃꢕꢘꢘꢂꢖꢙꢕꢘꢍꢌꢃꢂ. ꢗꢂꢂꢐꢑꢃꢘꢁꢂꢃ@ꢏꢘ ꢘꢂꢌꢃꢕꢘꢘ ꢂꢖꢙꢕꢘꢏꢍꢖꢃꢌꢂ$
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83>=43ꢃꢊꢃꢘ#ꢋꢏꢗꢕꢚꢃ@ꢏꢘꢘꢂꢌꢃꢕꢘꢘꢂꢖꢙꢕꢘꢏꢍꢖꢃꢗꢙꢌꢎꢂꢃꢏꢑꢃꢑꢁꢍ ꢖ
ꢏꢖꢃ?ꢏꢒꢙꢌꢂꢃꢇꢜ3
Fꢁꢂꢖꢃꢘꢁꢂꢃꢀꢄ69ꢃꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃꢏꢑꢃꢗꢚꢍꢑꢂꢃꢘꢍꢃꢘꢁꢂꢃꢗꢂꢖꢘꢂꢌ
ꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃꢍ ꢓꢃꢘ ꢁꢂꢃ ꢗꢌ#ꢑꢘꢕꢚꢃ ꢍꢑꢗꢏꢚꢚꢕꢘꢍꢌ!ꢃꢘꢁ ꢂꢃꢁ ꢏꢒꢁꢃꢓꢌꢂ$
%ꢙꢂꢖꢗ#ꢃ@ꢏꢘꢘꢂꢌꢃꢘꢍꢚꢂꢌꢕꢖꢗꢂꢃꢏꢑꢃ4ꢉꢃH"ꢃ< ꢂꢓꢍꢌꢂꢃꢘꢁꢂꢃꢐꢏꢎꢏꢐꢂ
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ꢗꢂꢖꢘꢂꢌꢃꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃꢍꢓꢃꢘꢁꢂꢃꢍꢑꢗꢏꢚꢚꢕꢘꢍꢌꢃꢕꢖꢐꢃꢘꢁꢂꢃꢀꢄ69
ꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃꢐꢂꢎꢏꢕꢘꢂꢃꢓꢌꢍꢔꢃꢍꢖꢂꢃꢕꢖꢍꢘꢁꢂꢌ!ꢃꢘꢁꢂꢃ@ꢏꢘꢘꢂꢌꢃꢘꢍꢚ$
ꢂꢌꢕꢖꢗꢂꢃꢏꢑ ꢃꢌꢂꢐꢙꢗꢂꢐ3ꢃꢊꢑ ꢃꢘꢁꢏꢑ ꢃꢓ ꢌꢂ%ꢙꢂꢖꢗ#ꢃꢐꢂꢎꢏꢕꢘꢏꢍꢖ
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ꢁꢏꢒꢁꢃꢓꢌꢂ%ꢙ ꢂꢖꢗꢏꢂꢑꢃꢏꢑ ꢃꢌꢂꢐ ꢙꢗꢂꢐꢃꢘꢍ ꢃꢇ4ꢃH"ꢃ< ꢂꢓꢍꢌꢂꢃꢘꢁꢂ
ꢙꢖꢐꢂꢌꢓꢚꢍ -ꢍꢎꢂꢌꢓꢚꢍ ꢃꢗꢏ ꢌꢗꢙꢏꢘꢌ#ꢃꢏꢑ ꢃ ꢕꢗꢘꢏꢎꢕꢘꢂꢐ3ꢃ "ꢖꢃꢕꢋ$
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ꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃ ꢏꢚꢚꢃ<ꢂꢃꢋ ꢌꢂꢗꢏꢑꢂꢚ#ꢃꢕ ꢚꢏꢒꢖꢂꢐꢃ ꢏ ꢘꢁꢃꢘ ꢁꢂ
ꢀꢁꢂꢃ@ꢏꢘꢘꢂꢌꢃꢕꢘꢘꢂꢖꢙꢕꢘꢍꢌꢃ ꢍꢌ;ꢑꢃꢏꢖꢃꢘꢁꢂ ꢃꢓꢍꢚꢚꢍ ꢏꢖꢒꢃꢔꢕꢖ$
ꢖꢂꢌ3ꢃ, ꢕꢘꢕꢃꢍ ꢖꢃꢀ7&ꢅꢃꢕꢖꢐꢃꢀ2:8ꢃ0ꢍꢌꢃꢀ, ꢊꢀꢊ1ꢃꢕꢌꢂ
ꢌꢏꢘꢘꢂꢖꢃꢏꢖꢘꢍꢃꢘꢁꢂꢃ@ꢏꢘꢘꢂꢌꢃꢕꢘꢘꢂꢖꢙꢕꢘꢍꢌRꢑꢃ?"?&ꢃ<#ꢃꢀꢄ693
ꢀꢁꢂꢃꢌꢕꢘꢂꢃꢕꢘꢃ ꢁꢏꢗꢁꢃꢐꢕꢘꢕꢃꢏꢑꢃꢌꢂꢕꢐꢃꢍꢙꢘꢃꢍꢓꢃꢘꢁꢂꢃ?"?&ꢃꢕꢖꢐ
ꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢐꢃꢏꢑꢃꢐꢂꢘꢂꢌꢔꢏꢖꢂꢐꢃ<#ꢃꢘꢁꢂꢃꢍꢑꢗꢏꢚꢚꢕꢘꢍꢌ3ꢃ6ꢍꢒꢏꢗ
ꢗꢏꢌꢗꢙꢏꢘꢑꢃꢕꢐ@ꢙꢑꢘꢃꢘꢁꢂꢃꢗꢕꢋꢕꢗꢏꢘꢏꢎꢂꢃꢚꢍꢕꢐꢏꢖꢒꢃꢍꢖꢃꢘꢁꢂꢃꢗꢌ#ꢑ$
DS40F3
13
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
RTIP
Data
RPOS
RNEG
RCLK
1 : 2
Data
Level
Slicer
Sampling
&
Clock
Extraction
RRING
Clock
Phase
Edge
Detector
Selector
ACLKI or
Oscillator in Jitter
Attenuator
Continuously
Calibrated
Delay Line
Figure 11. Receiver Block Diagram
ꢖꢍꢘꢃꢕꢎꢕꢏꢚꢕ<ꢚꢂꢃꢍꢖꢃꢘꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊꢃ ꢁꢂꢖꢃꢊꢄ69"ꢃꢏꢑ
ꢒꢌꢍꢙꢖꢐꢂꢐ3
ꢀꢄ69ꢃ ꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃ ꢐꢙꢂꢃꢘ ꢍꢃꢕ ꢚꢚꢍ ꢕ<ꢚꢂꢃꢀ ꢄ69ꢃꢘ ꢍꢚꢂꢌ$
ꢕꢖꢗꢂ!ꢃꢋ ꢕꢌꢘꢃꢘ ꢍꢃꢋ ꢕꢌꢘꢃꢎ ꢕꢌꢏꢕꢘꢏꢍꢖꢑ!ꢃꢗ ꢌ#ꢑꢘꢕꢚꢃꢘ ꢍꢃꢗ ꢌ#ꢑꢘꢕꢚ
ꢎꢕꢌꢏꢕꢘꢏꢍꢖꢑ!ꢃꢕꢖꢐꢃꢗꢌ#ꢑꢘꢕꢚꢃꢘꢂꢔꢋꢂꢌꢕꢘꢙꢌꢂꢃꢐꢌꢏꢓꢘ3ꢃꢀꢁꢂꢃꢍꢑ$
ꢗꢏꢚꢚꢕꢘꢍꢌꢃꢘꢂꢖꢐꢑꢃꢘꢍꢃꢘꢌꢕꢗ;ꢃꢚꢍ ꢃꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃ@ꢏꢘꢘꢂꢌꢃꢑꢍꢃ@ꢏꢘꢘꢂꢌ
ꢘꢍꢚꢂꢌꢕꢖꢗꢂꢃꢏꢖꢗꢌꢂꢕꢑꢂꢑꢃꢕꢑꢃ@ꢏꢘꢘꢂꢌꢃꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃꢐꢂꢗꢌꢂꢕꢑꢂꢑ3
Receiver
ꢀꢁꢂꢃꢌꢂꢗꢂꢏꢎꢂꢌꢃꢂ.ꢘꢌꢕꢗꢘꢑꢃꢐꢕꢘꢕꢃꢕꢖꢐꢃꢗꢚꢍꢗ;ꢃꢓꢌꢍꢔꢃꢕꢖꢃꢊ'"
0ꢊꢚꢘꢂꢌꢖꢕꢘꢂꢃ'ꢕꢌ;ꢃ"ꢖꢎꢂꢌꢑꢏꢍꢖ1ꢃꢗꢍꢐꢂꢐꢃꢑꢏꢒꢖꢕꢚꢃꢕꢖꢐꢃꢍꢙꢘ$
ꢋꢙꢘꢑꢃꢗꢚꢍꢗ;ꢃꢕꢖꢐꢃꢑ#ꢖꢗꢁꢌꢍꢖꢏDꢂꢐꢃꢐꢕꢘꢕ3ꢃꢀꢁꢂꢃꢌꢂꢗꢂꢏꢎꢂꢌꢃꢏꢑ
ꢑꢂꢖꢑꢏꢘꢏꢎꢂꢃꢘꢍꢃꢑ ꢏꢒꢖꢕꢚꢑꢃꢍꢎꢂꢌꢃꢘꢁꢂꢃꢂꢖꢘꢏꢌꢂꢃꢌꢕꢖꢒꢂꢃꢍꢓꢃꢗꢕ<ꢚꢂ
ꢚꢂꢖꢒꢘꢁꢑꢃꢕꢖꢐꢃꢌ ꢂ%ꢙꢏꢌꢂꢑꢃꢖꢍꢃꢂ%ꢙꢕꢚꢏDꢕꢘꢏꢍꢖꢃꢍꢌꢃꢊ6 (&
0ꢊꢙꢘꢍꢔꢕꢘꢏꢗꢃ6ꢏꢖꢂꢃ(ꢙꢏꢚꢐꢃ&ꢙꢘ1ꢃꢗꢏꢌꢗꢙꢏꢘꢑ3ꢃꢀꢁꢂꢃꢑꢏꢒꢖꢕꢚꢃꢏꢑ
ꢌꢂꢗꢂꢏꢎꢂꢐꢃꢍꢖꢃ<ꢍꢘꢁꢃꢂꢖꢐꢑꢃꢍꢓꢃꢕꢃꢗꢂꢖ ꢘꢂꢌ$ꢘꢕꢋꢋꢂꢐ!ꢃꢗꢂꢖꢘꢂꢌ$
ꢒꢌꢍꢙꢖꢐꢂꢐꢃꢘꢌ ꢕꢖꢑꢓꢍꢌꢔꢂꢌ3ꢃꢀ ꢁꢂꢃꢘꢌ ꢕꢖꢑꢓꢍꢌꢔꢂꢌꢃꢏꢑ
ꢗꢂꢖꢘꢂꢌ$ꢘꢕꢋꢋꢂꢐꢃꢍꢖꢃꢘ ꢁꢂꢃ"ꢄꢃꢑ ꢏꢐꢂ3ꢃꢀꢁꢂꢃꢗꢚꢍꢗ;ꢃꢕꢖꢐꢃꢐꢕꢘꢕ
ꢌꢂꢗꢍꢎꢂꢌ#ꢃꢗꢏꢌꢗꢙꢏꢘꢃꢂ.ꢗꢂꢂꢐꢑꢃꢘꢁꢂꢃ@ꢏꢘꢘꢂꢌꢃꢘꢍꢚꢂꢌꢕꢖꢗꢂꢃꢑꢋꢂꢗꢏ$
ꢓꢏꢗꢕꢘꢏꢍꢖꢑꢃꢍ ꢓꢃ7ꢙ<ꢚ ꢏꢗꢕꢘꢏꢍꢖꢑꢃ=ꢉ) ꢜ4!ꢃ=ꢉ )ꢜꢇ!ꢃꢆ 4=ꢇꢇ
ꢕꢔꢂꢖꢐꢂꢐ!ꢃꢀ /$ꢀꢅJ$ꢜꢜꢜꢇ>ꢜ!ꢃꢕꢖꢐꢃꢄꢄ"ꢀ ꢀꢃ/: ꢄ3
83)4ꢉ3
ꢀꢁꢂꢃꢗꢌ#ꢑꢘꢕꢚꢃꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃꢔꢙꢑꢘꢃ<ꢂꢃ=ꢃ ꢘꢏꢔꢂꢑꢃꢘꢁꢂꢃꢖꢍꢔꢏ$
ꢖꢕꢚꢃꢑꢏꢒꢖꢕꢚꢃꢓꢌꢂ%ꢙꢂꢖꢗ#ꢛꢃꢆ3ꢇ>ꢆꢃ'+Dꢃꢓꢍꢌꢃꢇ3 ꢈ==ꢃ'+D
ꢍꢋꢂꢌꢕꢘꢏꢍꢖIꢃ)3ꢇ54ꢃ'+ Dꢃꢓꢍꢌꢃ43ꢜ=) ꢃ'+ Dꢃꢕ ꢋꢋꢚꢏꢗꢕ$
ꢘꢏꢍꢖꢑ3ꢃ" ꢖꢘꢂꢌꢖꢕꢚꢃꢗꢕꢋꢕꢗꢏꢘꢍꢌ ꢑꢃꢚꢍꢕꢐꢃꢘ ꢁꢂꢃꢗ ꢌ#ꢑꢘꢕꢚ!
ꢗꢍꢖꢘꢌꢍꢚꢚꢏꢖꢒꢃꢘꢁꢂꢃꢍꢑꢗꢏꢚꢚꢕꢘꢏꢍꢖꢃꢓꢌꢂ%ꢙꢂꢖꢗ#3ꢃꢀꢁꢂꢃꢗꢌ#ꢑꢘꢕꢚ
ꢔꢙꢑꢘꢃ<ꢂꢃꢐꢂꢑꢏꢒꢖꢂꢐꢃꢑꢍꢃꢘꢁꢕꢘꢃꢍꢎꢂꢌꢃꢍꢋꢂꢌꢕꢘꢏꢖꢒꢃꢘꢂꢔꢋꢂꢌꢕ$
ꢘꢙꢌꢂ!ꢃꢘꢁ ꢂꢃꢍ ꢑꢗꢏꢚꢚꢕꢘꢍꢌꢃꢓ ꢌꢂ%ꢙꢂꢖꢗ#ꢃ ꢌꢕꢖꢒꢂꢃꢂ .ꢗꢂꢂꢐꢑꢃꢘꢁ ꢂ
ꢑ#ꢑꢘꢂꢔꢃꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃꢘꢍꢚꢂꢌꢕꢖꢗꢂ3ꢃTo obtain optimum
ꢋꢂꢌꢓꢍꢌꢔꢕꢖꢗꢂ, the crystal usedꢃ must meet the
specifications in Appendix A3
Transmit All Ones Select
ꢊꢃ<ꢚꢍꢗ;ꢃꢐꢏꢕꢒꢌꢕꢔꢃꢍꢓꢃꢘꢁꢂꢃꢌꢂꢗꢂꢏꢎꢂꢌꢃꢏꢑꢃꢑꢁꢍ ꢖꢃꢏꢖꢃ?ꢏꢒ$
ꢙꢌꢂꢃꢇꢇ3ꢃꢀ ꢁꢂꢃꢘ ꢍ ꢃ ꢚꢂꢕꢐꢑꢃꢍꢓ ꢃꢘꢁ ꢂꢃ ꢘꢌꢕꢖꢑꢓꢍꢌꢔꢂꢌꢃ0 /ꢀ"7
ꢕꢖꢐꢃ//"281ꢃꢁꢕꢎꢂꢃꢍꢋꢋꢍꢑꢏꢘꢂꢃꢋꢍꢚꢕꢌꢏꢘ#ꢃꢕꢚꢚꢍ ꢏꢖꢒꢃꢘꢁꢂ
ꢌꢂꢗꢂꢏꢎꢂꢌꢃꢘꢍꢃꢘꢌꢂꢕꢘꢃ/ꢀ"7ꢃꢕꢖꢐꢃ//"28ꢃꢕꢑꢃꢙꢖꢏꢋꢍꢚꢕꢌꢃꢑꢏꢒ$
ꢖꢕꢚꢑ3ꢃꢄꢍꢔ ꢋꢕꢌꢕꢘꢍꢌꢑꢃꢕ ꢌꢂꢃꢙꢑꢂꢐ ꢃꢘꢍꢃꢐ ꢂꢘꢂꢗꢘꢃꢋ ꢙꢚꢑꢂꢑꢃꢍ ꢖ
/ꢀ"7ꢃꢕꢖꢐꢃ//"283ꢃꢀꢁꢂꢃꢗꢍꢔꢋꢕꢌꢕꢘꢍꢌꢃꢘꢁꢌꢂꢑꢁꢍꢚꢐꢑꢃꢕꢌꢂ
ꢐ#ꢖꢕꢔꢏꢗꢕꢚꢚ#ꢃꢂꢑꢘꢕ<ꢚꢏꢑꢁꢂꢐꢃꢕꢘꢃꢕꢃꢋꢂꢌꢗꢂꢖꢘꢃꢍꢓꢃꢘꢁ ꢂꢃꢋꢂꢕ;
ꢚꢂꢎꢂꢚꢃ0ꢈꢜꢝꢃꢍꢓꢃꢋ ꢂꢕ;ꢃꢓꢍꢌꢃ: ꢇ!ꢃꢆꢈꢝꢃꢍꢓꢃꢋꢂ ꢕ;ꢃꢓꢍꢌꢃꢀ ꢇI
ꢏꢘꢁꢃꢘꢁꢂꢃꢑꢚꢏꢗꢏꢖꢒꢃꢚꢂꢎꢂꢚꢃꢑꢂꢚꢂꢗꢘꢂꢐꢃ<#ꢃ6:24-ꢇ-ꢜ13
ꢀꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢌꢃꢋꢌꢍꢎꢏꢐꢂꢑꢃꢓꢍꢌꢃꢕꢚꢚꢃꢍꢖꢂꢑꢃꢏꢖꢑꢂꢌꢘꢏꢍꢖꢃꢕꢘ
ꢘꢁꢂꢃꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃꢍꢓꢃꢊꢄ69"3ꢃꢀꢌꢕꢖꢑꢔꢏꢘꢃꢕꢚꢚꢃꢍꢖꢂꢑꢃꢏꢑꢃꢑꢂ$
ꢚꢂꢗꢘꢂꢐꢃ ꢁꢂ ꢖꢃꢀꢊ&ꢅꢃꢒꢍꢂ ꢑꢃꢁ ꢏꢒꢁ!ꢃꢕ ꢖꢐꢃꢗ ꢕꢙꢑꢂꢑ
ꢗꢍꢖꢘꢏꢖꢙꢍꢙꢑꢃꢍꢖ ꢂꢑꢃꢘꢍ ꢃ<ꢂꢃꢘ ꢌꢕꢖꢑꢔꢏꢘꢘꢂꢐꢃꢍꢖꢃꢘ ꢁꢂꢃꢚ ꢏꢖꢂ
0ꢀꢀ"7ꢃꢕꢖꢐꢃꢀ/"2813ꢃ"ꢖꢃꢘꢁꢏꢑꢃꢔꢍꢐꢂ!ꢃꢘꢁꢂꢃꢀ7&ꢅꢃꢕꢖꢐ
ꢀ2:8ꢃ0ꢍꢌꢃꢀ,ꢊꢀꢊ1ꢃꢏꢖꢋꢙꢘꢑꢃꢕꢌꢂꢃꢏꢒꢖꢍꢌꢂꢐ3ꢃꢊꢃꢀꢊ&ꢅ
ꢌꢂ%ꢙꢂꢑꢘꢃ ꢏꢚꢚꢃ<ꢂꢃꢏ ꢒꢖꢍꢌꢂꢐꢃꢏ ꢓꢃꢌꢂꢔꢍꢘꢂ ꢃꢚꢍꢍ ꢋ<ꢕꢗ;ꢃꢏ ꢑꢃꢏ ꢖ
ꢂꢓꢓꢂꢗꢘ3ꢃꢊꢄ69"ꢃ@ꢏꢘꢘꢂꢌꢃ ꢏꢚꢚꢃ<ꢂꢃꢕꢘꢘꢂꢖꢙꢕꢘꢂꢐ3ꢃꢀꢊ&ꢅꢃꢏꢑ
14
DS40F3
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
ꢀꢁꢂꢃꢌꢂꢗꢂꢏꢎꢂꢌꢃꢙꢑꢂꢑꢃꢕꢖꢃꢂꢐꢒꢂꢃꢐꢂꢘꢂꢗꢘꢍꢌꢃꢕꢖꢐꢃꢕꢃꢗꢍꢖꢘꢏꢖꢙ$
ꢍꢙꢑꢚ#ꢃꢗ ꢕꢚꢏ<ꢌꢕꢘꢂꢐꢃꢐ ꢂꢚꢕ#ꢃꢚ ꢏꢖꢂꢃꢘ ꢍꢃꢒ ꢂꢖꢂꢌꢕꢘꢂꢃꢘ ꢁꢂ
ꢌꢂꢗꢍꢎꢂꢌꢂꢐꢃꢗꢚꢍꢗ;3ꢃꢀꢁꢂꢃꢐꢂꢚꢕ#ꢃꢚꢏꢖꢂꢃꢐꢏꢎꢏꢐꢂꢑꢃꢏꢘꢑꢃꢌꢂꢓꢂꢌ$
ꢂꢖꢗꢂꢃꢗꢚꢍꢗ;!ꢃꢊꢄ69"ꢃꢍꢌ ꢃꢘꢁꢂꢃ@ꢏꢘꢘꢂꢌꢃꢕꢘ ꢘꢂꢖꢙꢕꢘꢍꢌRꢑ
ꢍꢑꢗꢏꢚꢚꢕꢘꢍꢌ!ꢃꢏꢖꢘꢍꢃꢇꢉꢃꢂ%ꢙꢕꢚꢃꢐꢏꢎꢏꢑꢏꢍꢖꢑꢃꢍꢌꢃꢋꢁꢕꢑꢂꢑ3ꢃꢄꢍꢖ$
ꢘꢏꢖꢙꢍꢙꢑꢃꢗꢕꢚꢏ<ꢌꢕꢘꢏꢍꢖꢃꢕꢑꢑꢙꢌꢂꢑꢃꢘꢏꢔꢏꢖꢒꢃꢕꢗꢗꢙꢌꢕꢗ#!ꢃꢂꢎꢂꢖ
ꢏꢓꢃꢘꢂꢔꢋꢂꢌꢕꢘꢙꢌꢂꢃꢍꢌꢃꢋꢍ ꢂꢌꢃꢑꢙꢋꢋꢚ#ꢃꢎꢍꢚꢘꢕꢒꢂꢃꢓꢚꢙꢗꢘꢙꢕꢘꢂ3
ꢘꢁꢂꢃ+ꢍꢑꢘꢃ'ꢍꢐꢂ!ꢃꢄ69:ꢃꢐꢂꢘꢂꢌꢔꢏꢖꢂꢑꢃꢘꢁꢂꢃꢗꢚꢍꢗ;ꢃꢋꢍ$
ꢚꢕꢌꢏꢘ#ꢃꢓꢍꢌꢃ ꢁꢏꢗꢁꢃꢍꢙꢘꢋꢙꢘꢃꢐꢕꢘꢕꢃꢏꢑꢃꢑꢘꢕ<ꢚꢂꢃꢕꢖꢐꢃꢎꢕꢚꢏꢐꢃꢕꢑ
ꢑꢁꢍ ꢖꢃꢏꢖꢃꢀꢕ<ꢚꢂꢃꢈ3
MODE
(pin 5)
CLKE
(pin 28)
DATA
CLOCK Clock Edge for
Valid Data
LOW
(<0.2V)
X
RPOS
RNEG
RCLK
RCLK
Rising
Rising
HIGH
(>(V+) - 0.2V)
LOW
RPOS
RNEG
SDO
RCLK
RCLK
SCLK
Rising
Rising
Falling
ꢀꢁꢂꢃꢚꢂꢕꢐꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃꢕ ꢖꢃꢏꢖꢗꢍꢔꢏꢖꢒꢃꢐꢕꢘꢕꢃꢋꢙꢚꢑꢂꢃꢘꢌꢏꢒ$
ꢒꢂꢌꢑꢃꢘꢁꢂꢃꢗꢚꢍꢗ;ꢃꢋꢁꢕꢑꢂꢃꢑꢂꢚꢂꢗꢘꢍꢌ3ꢃꢀꢁꢂꢃꢋꢁꢕꢑꢂꢃꢑꢂꢚꢂꢗꢘꢍꢌ
ꢗꢁꢍꢍꢑꢂꢑꢃꢍꢖꢂꢃꢍꢓꢃꢘꢁꢂꢃꢇꢉꢃꢕꢎꢕꢏꢚꢕ<ꢚꢂꢃꢋꢁꢕꢑꢂꢑꢃ ꢁꢏꢗꢁꢃꢘꢁꢂ
ꢐꢂꢚꢕ#ꢃꢚꢏꢖꢂꢃꢋꢌꢍꢐꢙꢗꢂꢑꢃꢓꢍꢌꢃꢂꢕꢗꢁꢃ<ꢏꢘꢃꢋꢂꢌꢏꢍꢐ3ꢃꢀꢁꢂꢃꢍꢙꢘ$
ꢋꢙꢘꢃꢓ ꢌꢍꢔꢃ ꢘꢁꢂꢃꢋꢁ ꢕꢑꢂꢃꢑꢂ ꢚꢂꢗꢘꢍꢌꢃꢓ ꢂꢂꢐꢑꢃꢘꢁꢂ ꢃ ꢗꢚꢍꢗ;ꢃ ꢕꢖꢐ
ꢐꢕꢘꢕꢃ ꢌꢂꢗꢍꢎꢂꢌ#ꢃꢗꢏ ꢌꢗꢙꢏꢘꢑꢃ ꢁꢏ ꢗꢁꢃ ꢒꢂꢖꢂꢌꢕꢘꢂꢃꢘ ꢁꢂꢃ ꢌꢂꢗꢍꢎ$
ꢂꢌꢂꢐꢃꢗꢚꢍ ꢗ;ꢃꢕ ꢖꢐꢃꢑꢕ ꢔꢋꢚꢂꢃꢘꢁꢂ ꢃꢏ ꢖꢗꢍꢔꢏꢖꢒꢃꢑꢏ ꢒꢖꢕꢚꢃꢕꢘ
ꢕꢋꢋꢌꢍꢋꢌꢏꢕꢘꢂꢃꢏꢖꢘꢂꢌꢎꢕꢚꢑꢃꢘꢍꢃꢌꢂꢗꢍꢎꢂꢌꢃꢘꢁꢂꢃꢐꢕꢘꢕ3ꢃꢀꢁꢂꢃ@ꢏꢘꢘꢂꢌ
ꢘꢍꢚꢂꢌꢕꢖꢗꢂꢃꢍ ꢓꢃꢘꢁ ꢂꢃꢌ ꢂꢗꢂꢏꢎꢂꢌꢃ ꢂ.ꢗꢂꢂꢐꢑꢃ ꢘꢁꢕꢘꢃꢑ ꢁꢍ ꢖꢃꢏ ꢖ
?ꢏꢒꢙꢌꢂꢃꢇ43
HIGH
HIGH
X
RPOS
RNEG
SDO
RCLK
RCLK
SCLK
Falling
Falling
Rising
(>(V+) - 0.2V)
MIDDLE
(2.5V)
RDATA
RCLK
Falling
X = Don’t care
Table 5. Data Output/Clock Relationship
Jitter and Recovered Clock
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊꢃꢕꢌꢂꢃꢐꢂꢑꢏꢒꢖꢂꢐꢃꢓꢍꢌꢃꢂꢌꢌꢍꢌꢃꢓꢌꢂꢂꢃꢗꢚꢍꢗ;
ꢕꢖꢐꢃꢐ ꢕꢘꢕꢃꢌꢂꢗꢍ ꢎꢂꢌ#ꢃꢓꢌꢍꢔ ꢃꢕꢖꢃꢊ'"ꢃꢂ ꢖꢗꢍꢐꢂꢐꢃꢐꢕꢘꢕ
ꢑꢘꢌꢂꢕꢔꢃꢏꢖꢃꢘꢁꢂꢃꢋꢌꢂꢑꢂꢖꢗꢂꢃꢍꢓꢃꢔꢍꢌꢂꢃꢘꢁꢕꢖꢃꢜ3=ꢃꢙꢖꢏꢘꢃꢏꢖꢘꢂꢌ$
ꢎꢕꢚꢑꢃꢍꢓ ꢃ@ꢏꢘ ꢘꢂꢌꢃꢕꢘ ꢃꢁꢏ ꢒꢁꢃꢓ ꢌꢂ%ꢙꢂꢖꢗ#3ꢃꢀ ꢁꢂꢃꢗ ꢚꢍꢗ;
ꢌꢂꢗꢍꢎꢂꢌ#ꢃꢗꢏꢌꢗꢙꢏꢘꢃꢏꢑꢃ ꢕꢚꢑꢍꢃꢘꢍꢚꢂꢌꢕꢖꢘꢃꢍꢓꢃ ꢚꢍꢖꢒꢃꢑꢘꢌꢏꢖꢒꢑꢃꢍꢓ
Dꢂꢌꢍꢑ3ꢃꢀ ꢁꢂꢃ ꢂꢐꢒꢂꢃꢍ ꢓꢃꢕꢖꢃꢏ ꢖꢗꢍꢔꢏꢖꢒꢃꢐ ꢕꢘꢕꢃ<ꢏꢘ ꢃꢗꢕꢙ ꢑꢂꢑ
ꢘꢁꢂꢃꢗꢏꢌꢗꢙꢏꢘꢌ#ꢃꢘꢍꢃꢗꢁꢍꢍꢑꢂꢃꢕꢃꢋꢁꢕꢑꢂꢃꢓꢌꢍꢔꢃꢘꢁꢂꢃꢐꢂꢚꢕ#ꢃꢚꢏꢖꢂ
ꢁꢏꢗꢁꢃꢔ ꢍꢑꢘꢃꢗꢚꢍ ꢑꢂꢚ#ꢃꢗꢍ ꢌꢌꢂꢑꢋꢍꢖꢐꢑꢃ ꢏꢘꢁꢃꢘꢁ ꢂꢃꢕꢌꢌꢏꢎ ꢕꢚ
ꢘꢏꢔꢂꢃꢍꢓꢃꢘꢁꢂ ꢃꢐꢕꢘꢕꢃꢂꢐꢒꢂ!ꢃꢕꢖꢐꢃꢘꢁꢕꢘꢃꢗꢚꢍꢗ;ꢃꢋꢁꢕꢑꢂꢃꢘꢌꢏꢒ$
ꢒꢂꢌꢑꢃꢕꢃꢋꢙꢚꢑꢂꢃ ꢁꢏꢗꢁꢃꢏꢑꢃꢘ#ꢋꢏꢗꢕꢚꢚ#ꢃꢇ=ꢜꢃꢖꢑꢃꢏꢖꢃꢐꢙꢌꢕꢘꢏꢍꢖ3
ꢀꢁꢏꢑꢃꢋꢁ ꢕꢑꢂꢃꢍꢓꢃ ꢘꢁꢂꢃꢐꢂꢚ ꢕ#ꢃꢚꢏꢖ ꢂꢃ ꢏꢚꢚꢃꢗꢍꢖ ꢘꢏꢖꢙꢂꢃꢘꢍꢃ<ꢂ
ꢑꢂꢚꢂꢗꢘꢂꢐꢃꢙꢖꢘꢏꢚꢃꢕꢃꢐꢕꢘꢕꢃ<ꢏꢘꢃꢕꢌꢌꢏꢎꢂꢑꢃ ꢁꢏꢗꢁꢃꢏꢑꢃꢗꢚꢍꢑꢂꢌꢃꢘꢍ
ꢕꢖꢍꢘꢁꢂꢌꢃꢍꢓꢃꢘꢁꢂꢃꢇꢉꢃꢋꢁꢕꢑꢂꢑ!ꢃꢗꢕꢙꢑꢏꢖꢒꢃꢕꢃꢖꢂ ꢃꢋꢁꢕꢑꢂꢃꢘꢍ
<ꢂꢃꢑꢂ ꢚꢂꢗꢘꢂꢐ3ꢃꢀ ꢁꢂꢃꢚꢕ ꢌꢒꢂꢑꢘꢃ@ꢙꢔ ꢋꢃꢕꢚ ꢚꢍ ꢂꢐꢃꢕꢚꢍꢖꢒꢃꢘꢁꢂ
ꢐꢂꢚꢕ#ꢃꢚꢏꢖꢂꢃꢏꢑꢃꢑꢏ.ꢃꢋꢁꢕꢑꢂꢑ3
300
100
28
PEAK
TO
10
PEAK
JITTER
(unit intervals)
1
.4
.1
0
10
100 300 700 1k
10k
100k
JITTER FREQUENCY (Hz)
Figure 12. Input Jitter Tolerance of Receiver
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊꢃꢍꢙꢘꢋꢙꢘꢑꢃꢕꢃꢗꢚꢍꢗ;ꢃꢏꢔꢔꢂꢐꢏꢕꢘꢂꢚ#ꢃꢙꢋꢍꢖ
ꢋꢍ ꢂꢌ$ꢙꢋ3ꢃꢀ ꢁꢂꢃꢗ ꢚꢍꢗ;ꢃꢌꢂꢗ ꢍꢎꢂꢌ#ꢃꢗꢏ ꢌꢗꢙꢏꢘꢃꢏꢑ ꢃꢗꢕꢚꢏ $
<ꢌꢕꢘꢂꢐ!ꢃꢕ ꢖꢐꢃꢘ ꢁꢂꢃꢐ ꢂꢎꢏꢗꢂꢃ ꢏꢚꢚꢃꢚꢍ ꢗ;ꢃꢍ ꢖꢘꢍꢃꢘꢁꢂ ꢃꢊ' "
ꢐꢕꢘꢕꢃꢏꢖꢋ ꢙꢘꢃꢏꢔ ꢔꢂꢐꢏꢕꢘꢂꢚ#3ꢃ "ꢓꢃꢚꢍꢑ ꢑꢃ ꢍꢓꢃꢑ ꢏꢒꢖꢕꢚꢃ ꢍꢗꢗꢙꢌꢑ!
ꢘꢁꢂꢃ/ ꢄ69ꢃꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃ ꢏꢚ ꢚꢃꢂ%ꢙꢕꢚꢃꢘꢁꢂ ꢃꢊꢄ6 9"ꢃꢓꢌꢂ$
%ꢙꢂꢖꢗ#3
Fꢁꢂꢖꢃꢕꢖꢃꢏꢖꢋꢙꢘꢃꢑꢏꢒꢖꢕꢚꢃꢏꢑꢃ@ꢏꢘꢘꢂꢌꢃꢓꢌꢂꢂ!ꢃꢘꢁꢂꢃꢋꢁꢕꢑꢂꢃꢑꢂ$
ꢚꢂꢗꢘꢏꢍꢖꢃ ꢏꢚꢚꢃꢍ ꢗꢗꢕꢑꢏꢍꢖꢕꢚꢚ#ꢃ@ ꢙꢔꢋꢃ< ꢂꢘ ꢂꢂꢖꢃꢘ ꢍ
ꢕꢐ@ꢕꢗꢂꢖꢘꢃꢋꢁꢕꢑꢂꢑꢃꢌꢂꢑꢙꢚꢘꢏꢖꢒꢃꢏꢖꢃ/ꢄ69ꢃ@ꢏꢘꢘꢂꢌꢃ ꢏꢘꢁꢃꢕꢖ
ꢕꢔꢋꢚꢏꢘꢙꢐꢂꢃ ꢍꢓꢃ ꢇ-ꢇꢉꢃH"ꢋꢋ3ꢃ ꢀꢁꢂꢑꢂꢃ ꢑꢏꢖꢒꢚꢂꢃ ꢋꢁꢕꢑꢂ
@ꢙꢔꢋꢑꢃꢕꢌꢂꢃꢐꢙꢂꢃꢘꢍꢃꢐꢏꢓꢓꢂꢌꢂꢖꢗꢂꢑꢃꢏꢖꢃꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃꢍꢓꢃꢘꢁꢂ
ꢏꢖꢗꢍꢔꢏꢖꢒꢃꢐꢕ ꢘꢕꢃꢕꢖ ꢐꢃꢘꢁꢂ ꢃꢗꢕꢚꢏ<ꢌꢕꢘꢏꢍꢖꢃꢗꢚꢍ ꢗ;ꢃꢏꢖꢋ ꢙꢘꢃꢘꢍ
ꢊꢄ69"3ꢃ?ꢍꢌꢃꢀ ꢇꢃꢍꢋꢂꢌꢕꢘꢏꢍꢖꢃꢍꢓꢃꢘꢁꢂ ꢃꢄꢅꢆꢇꢈꢉꢈꢊ!ꢃꢘꢁꢂ
ꢏꢖꢑꢘꢕꢖꢘꢕꢖꢂꢍꢙꢑꢃꢋꢂꢌꢏꢍꢐꢃꢗꢕꢖꢃ<ꢂꢃꢇ=-ꢇꢉꢃKꢃꢆ=)ꢃꢖꢑꢃEꢃꢆ5)
ꢖꢑꢃ0ꢇ !ꢆꢆ4!>ꢆ5ꢃ+D1ꢃꢍꢌꢃꢇ4-ꢇꢉꢃKꢃꢆ=)ꢃ ꢖꢑꢃEꢃꢈ5)ꢃ ꢖꢑ
0ꢇ!=4ꢈ!4ꢉꢇꢃ+D1ꢃ ꢁꢂꢖꢃ ꢕꢐ@ꢕꢗꢂꢖꢘꢃ ꢗꢚꢍꢗ;ꢃ ꢋꢁꢕꢑꢂꢑꢃ ꢕꢌꢂ
ꢗꢁꢍꢑꢂꢖ3ꢃꢊꢑꢃꢚꢍꢖꢒꢃꢕꢑꢃꢘꢁꢂꢃꢑꢕꢔꢂꢃꢋꢁꢕꢑꢂꢃꢏꢑꢃꢗꢁꢍꢑꢂꢖ!ꢃꢘꢁꢂ
"ꢖꢃꢘꢁꢂꢃ+ꢕꢌꢐ ꢕꢌꢂꢃ'ꢍꢐꢂ!ꢃꢐꢕꢘꢕꢃꢕꢘꢃ/7&ꢅꢃꢕꢖꢐꢃ/2:8
ꢏꢑꢃꢑꢘꢕ<ꢚꢂꢃꢕꢖꢐꢃꢔꢕ#ꢃ<ꢂꢃꢑꢕꢔꢋꢚꢂꢐꢃꢍꢖꢃꢘꢁꢂꢃꢌꢏꢑꢏꢖꢒꢃꢂꢐꢒꢂ
ꢍꢓꢃꢘꢁꢂꢃꢌꢂꢗꢍꢎꢂꢌꢂꢐꢃꢗꢚꢍꢗ;3ꢃ"ꢖꢃꢘꢁꢂꢃ:.ꢘꢂꢖꢐꢂꢐꢃ+ꢕꢌꢐ ꢕꢌꢂ
'ꢍꢐꢂ!ꢃꢐꢕꢘꢕꢃꢕꢘꢃ/,ꢊꢀꢊꢃꢏꢑꢃꢑꢘꢕ<ꢚꢂꢃꢕꢖꢐꢃꢔꢕ#ꢃ<ꢂꢃꢑ ꢕꢔ$
ꢋꢚꢂꢐꢃꢍꢖꢃꢘꢁꢂꢃꢓꢕꢚꢚꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃꢘꢁꢂꢃꢌꢂꢗꢍꢎꢂꢌꢂꢐꢃꢗꢚꢍꢗ;3ꢃ"ꢖ
DS40F3
15
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
ꢋꢂꢌꢏꢍꢐꢃ ꢏꢚ ꢚꢃ< ꢂꢃꢆ= )ꢃꢖꢑ3ꢃꢅꢏ ꢔꢏꢚꢕꢌꢃꢗ ꢕꢚꢗꢙꢚꢕꢘꢏꢍꢖꢑꢃꢁꢍꢚ ꢐ
ꢓꢍꢌꢃꢘꢁꢂꢃ:ꢇꢃꢌꢕꢘꢂ3
ꢗꢂꢏꢎꢂꢐ!ꢃꢍꢌ ꢃ ꢁ ꢂꢖꢃꢘ ꢁꢂꢃꢌ ꢂꢗꢂꢏꢎꢂꢐꢃꢑꢏ ꢒꢖꢕꢚꢃꢕꢔ ꢋꢚꢏꢘꢙꢐꢂ
ꢐꢌꢍꢋꢑꢃ<ꢂꢚꢍ ꢃꢕꢃꢜ3ꢉꢃLꢃꢋꢂꢕ;ꢃꢘꢁꢌꢂꢑꢁꢍꢚꢐ3
ꢀꢁꢂꢃꢗꢚꢍꢗ;ꢃꢌꢂꢗꢍꢎꢂꢌ#ꢃꢗꢏꢌꢗꢙꢏꢘꢃꢏꢑꢃꢐꢂꢑꢏꢒꢖꢂꢐꢃꢘꢍꢃꢕꢗꢗꢂꢋꢘꢃꢕꢘ
ꢚꢂꢕꢑꢘꢃꢜ3=ꢃH"ꢃꢍꢓꢃ@ꢏꢘꢘꢂꢌꢃꢕꢘꢃꢘꢁꢂꢃꢌꢂꢗꢂꢏꢎꢂꢌ3ꢃꢅꢏꢖꢗꢂꢃꢘꢁꢂꢃꢐꢕꢘꢕ
ꢑꢘꢌꢂꢕꢔꢃ ꢗꢍꢖꢘꢕꢏꢖꢑꢃꢏꢖ ꢓꢍꢌꢔꢕꢘꢏꢍꢖꢃꢍ ꢖꢚ#ꢃ ꢁꢂꢖ ꢃꢍꢖꢂ ꢑꢃꢕ ꢌꢂ
ꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢐ!ꢃꢕꢃꢗꢚꢍꢗ;-ꢐꢕꢘꢕꢃꢌꢂꢗꢍꢎꢂꢌ#ꢃꢗꢏꢌꢗꢙꢏꢘꢃꢔꢙꢑꢘꢃꢕꢑ$
ꢑꢙꢔꢂꢃꢕꢃDꢂꢌꢍꢃ ꢁꢂꢖꢃꢖꢍꢃꢑꢏꢒꢖꢕꢚꢃꢏꢑꢃꢔꢂꢕꢑꢙꢌꢂꢐꢃꢐꢙꢌꢏꢖꢒꢃꢕ
<ꢏꢘꢃꢋꢂꢌꢏꢍꢐ3ꢃ6ꢏ;ꢂ ꢏꢑꢂ!ꢃ ꢁꢂꢖꢃDꢂꢌꢍꢑꢃꢕꢌꢂꢃꢌꢂꢗꢂꢏꢎꢂꢐ!ꢃꢖꢍ
ꢏꢖꢓꢍꢌꢔꢕꢘꢏꢍꢖꢃꢏꢑꢃꢋꢌꢂꢑꢂꢖꢘꢃꢘꢍꢃꢙ ꢋꢐꢕꢘꢂꢃꢘꢁꢂꢃꢗꢚꢍꢗ;ꢃꢌꢂꢗꢍꢎ$
ꢂꢌ#ꢃꢗꢏꢌꢗꢙꢏꢘꢃꢌꢂꢒꢕꢌꢐꢏꢖꢒꢃꢘꢁꢂꢃꢘꢌꢂꢖꢐꢃꢍꢓꢃꢕꢃꢑꢏꢒꢖꢕꢚꢃ ꢁꢏꢗꢁꢃꢏꢑ
@ꢏꢘꢘꢂꢌꢂꢐ3ꢃꢀꢁꢂꢃꢌꢂꢑꢙꢚꢘꢃꢏꢑꢃꢘꢁꢕꢘꢃꢘ ꢍꢃꢍꢖꢂ ꢑꢃꢘꢁꢕꢘꢃꢕꢌꢂꢃꢑꢂꢋꢕ$
ꢌꢕꢘꢂꢐꢃ<# ꢃꢕꢃꢑꢘꢌꢏꢖꢒꢃꢍꢓꢃDꢂꢌꢍ ꢑꢃꢗꢕꢖ ꢃꢂ.ꢁꢏ<ꢏꢘꢃꢔ ꢕ.ꢏꢔꢙꢔ
ꢐꢂꢎꢏꢕꢘꢏꢍꢖꢃꢏꢖꢃꢋꢙꢚꢑꢂꢃꢕꢌꢌꢏꢎꢕꢚꢃꢘꢏꢔꢂ3ꢃ?ꢍꢌꢃꢂ.ꢕꢔꢋꢚꢂ!ꢃꢍꢖꢂ
ꢁꢕꢚꢓꢃꢍ ꢓꢃꢕꢃ ꢋꢂꢌꢏꢍꢐꢃ ꢍꢓꢃ@ ꢏꢘꢘꢂꢌꢃꢕꢘ ꢃꢇꢜꢜ ꢃ;+Dꢃꢍꢗ ꢗꢙꢌꢑꢃꢏꢖ ꢃꢈ
μꢑ!ꢃ ꢁꢏꢗꢁꢃꢏꢑꢃ>3>ꢃꢀꢇꢃ<ꢏꢘꢃꢋꢂꢌꢏꢍꢐꢑ3ꢃ"ꢓꢃꢘꢁꢂꢃ@ꢏꢘꢘꢂꢌꢃꢕꢔꢋꢚꢏ$
ꢘꢙꢐꢂꢃꢏꢑꢃꢜ3=ꢃH"!ꢃꢘꢁꢂꢖꢃꢕꢃꢍꢖꢂꢃꢋꢌꢂꢗꢂꢐꢂꢐꢃ<#ꢃꢑꢂꢎꢂꢖꢃDꢂꢌꢍꢑ
ꢗꢕꢖꢃꢁꢕꢎꢂꢃꢔꢕ.ꢏꢔꢙꢔꢃꢐꢏꢑꢋꢚꢕꢗꢂꢔꢂꢖꢘꢃꢏꢖꢃꢕꢌꢌꢏꢎꢕꢚꢃꢘꢏꢔꢂ!
ꢏ3ꢂ3ꢃꢂꢏꢘꢁꢂꢌꢃꢜ3=ꢃH"ꢃꢘꢍꢍꢃꢂꢕꢌꢚ#ꢃꢍꢌꢃꢜ3=ꢃH"ꢃꢘꢍꢍꢃꢚꢕꢘꢂ3ꢃ?ꢍꢌ
ꢘꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊ!ꢃꢘꢁꢂꢃꢐꢕꢘꢕꢃꢌꢂꢗꢍꢎꢂꢌ#ꢃꢗꢏꢌꢗꢙꢏꢘꢃꢗꢍꢌꢌꢂꢗꢘꢚ#
ꢕꢑꢑꢏꢒꢖꢑꢃꢕꢃꢌꢂꢗꢂꢏꢎꢂꢐꢃ<ꢏꢘꢃꢘꢍꢃꢏꢘꢑꢃꢋꢌꢍꢋꢂꢌꢃꢗꢚꢍꢗ;ꢃꢋꢂꢌꢏꢍꢐꢃꢏꢓ
ꢏꢘꢃꢏꢑ ꢃꢐꢏꢑ ꢋꢚꢕꢗꢂꢐꢃ<# ꢃꢚꢂꢑ ꢑꢃꢘꢁꢕ ꢖꢃꢆ-ꢇ ꢉꢃꢍꢓꢃꢕꢃ<ꢏꢘ ꢃ ꢋꢂꢌꢏꢍꢐ
ꢓꢌꢍꢔꢃꢏꢘꢑ ꢃꢍꢋꢘꢏꢔ ꢕꢚꢃꢚꢍ ꢗꢕꢘꢏꢍꢖ3ꢃꢀꢁꢂꢍ ꢌꢂꢘꢏꢗꢕꢚꢚ#!ꢃꢘꢁꢏ ꢑ
ꢍꢙꢚꢐꢃꢒꢏꢎꢂꢃꢕꢃ@ꢏꢘ ꢘꢂꢌꢃꢘꢍꢚꢂꢌꢕꢖꢗꢂꢃꢍꢓꢃꢜ3=ꢆꢃH"3ꢃꢀꢁꢂꢃꢕꢗ$
ꢘꢙꢕꢚꢃ@ ꢏꢘꢘꢂꢌꢃꢘꢍꢚꢂꢌ ꢕꢖꢗꢂꢃꢍꢓꢃꢘꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊ ꢃꢏꢑ ꢃꢍꢖꢚ#
ꢑꢚꢏꢒꢁꢘꢚ#ꢃꢚꢂꢑꢑꢃꢘꢁꢕꢖꢃꢘꢁꢂꢃꢏꢐꢂꢕꢚ3
ꢀꢁꢂꢃꢌꢂꢗꢂꢏꢎꢂꢌꢃꢌꢂꢋꢍꢌꢘꢑꢃꢚꢍꢑꢑꢃꢍꢓꢃꢑ ꢏꢒꢖꢕꢚꢃ<#ꢃꢑ ꢂꢘꢘꢏꢖꢒꢃꢘꢁꢂ
6ꢍꢑꢑꢃꢍꢓꢃꢅꢏꢒꢖꢕꢚꢃꢋꢏꢖ!ꢃ6&ꢅ!ꢃꢁꢏꢒꢁ3ꢃ"ꢓꢃ ꢘꢁꢂꢃꢑꢂꢌꢏꢕꢚꢃꢏꢖꢘꢂꢌ$
ꢓꢕꢗꢂꢃꢏ ꢑꢃꢙ ꢑꢂꢐ!ꢃꢘꢁꢂ ꢃ6&ꢅꢃ< ꢏꢘꢃ ꢏ ꢚꢚꢃ< ꢂꢃꢑ ꢂꢘꢃꢕ ꢖꢐꢃꢕꢖ
ꢏꢖꢘꢂꢌꢌꢙꢋꢘꢃꢏꢑ ꢑꢙꢂꢐꢃ ꢍꢖꢃ "2ꢀ3ꢃ 6&ꢅꢃ ꢏꢚꢚꢃꢒꢍ ꢃꢚꢍ ꢃ0 ꢕꢖꢐ
ꢓꢚꢕꢒꢃꢘꢁꢂꢃ"2ꢀꢃꢋꢏꢖꢃꢕꢒꢕꢏꢖꢃꢏꢓꢃꢑꢂꢌꢏꢕꢚꢃ"-&ꢃꢏꢑꢃꢙꢑꢂꢐ1ꢃ ꢁꢂꢖ
ꢕꢃꢎꢕ ꢚꢏꢐꢃꢑ ꢏꢒꢖꢕꢚꢃ ꢏꢑꢃꢐꢂꢘ ꢂꢗꢘꢂꢐ3ꢃ2ꢍꢘ ꢂꢃꢘꢁ ꢕꢘꢃꢏ ꢖꢃꢘꢁ ꢂꢃ+ꢍꢑ ꢘ
'ꢍꢐꢂ!ꢃ6&ꢅꢃꢏꢑꢃꢑꢏꢔꢙꢚꢘꢕꢖꢂꢍꢙꢑꢚ#ꢃꢕꢎꢕꢏꢚꢕ<ꢚꢂꢃꢓꢌꢍꢔꢃ<ꢍꢘꢁ
ꢘꢁꢂꢃꢌꢂꢒꢏꢑꢘꢂꢌꢃꢕꢖꢐꢃꢋꢏꢖꢃꢇ43
"ꢖꢃꢕꢃꢚꢍꢑꢑꢃꢍꢓꢃꢑꢏꢒꢖꢕꢚꢃꢑꢘꢕꢘꢂ!ꢃꢘꢁꢂꢃ/ꢄ69ꢃꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃ ꢏꢚꢚ
<ꢂꢃꢂ%ꢙꢕꢚꢃꢘꢍꢃꢘꢁꢂꢃꢊꢄ69"ꢃꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃꢑꢏꢖꢗꢂꢃꢊꢄ69"ꢃꢏꢑ
<ꢂꢏꢖꢒꢃꢙꢑꢂꢐꢃꢘꢍꢃꢗꢕꢚꢏ<ꢌꢕꢘꢂꢃꢘꢁꢂꢃꢗꢚꢍꢗ;ꢃꢌꢂꢗꢍꢎꢂꢌ#ꢃꢗꢏꢌꢗꢙꢏꢘ3
/ꢂꢗꢂꢏꢎꢂꢐꢃꢐꢕꢘꢕꢃꢏꢑꢃꢍꢙꢘꢋꢙꢘꢃꢍꢖꢃ/7&ꢅꢃꢕꢖꢐ ꢃ/2:8ꢃ0ꢍꢌ
/,ꢊꢀꢊ1ꢃꢌꢂꢒꢕꢌꢐꢚꢂꢑꢑꢃꢍꢓꢃ6&ꢅꢃꢑꢘꢕꢘꢙꢑ3ꢃꢀꢁꢂꢃ6&ꢅꢃꢌꢂ$
ꢘꢙꢌꢖꢑꢃꢘꢍꢃꢚꢍꢒꢏꢗꢃDꢂꢌꢍꢃ ꢁꢂꢖꢃꢘꢁꢂꢃꢍꢖꢂꢑꢃꢐꢂꢖꢑꢏꢘ#ꢃꢌꢂꢕꢗꢁꢂꢑ
ꢇ43ꢈꢝꢃ0<ꢕꢑꢂꢐꢃꢙꢋꢍꢖꢃꢇ>ꢈꢃ<ꢏꢘꢃꢋꢂꢌꢏꢍꢐꢑꢃꢑꢘꢕꢌꢏꢖꢒꢃ ꢏꢘꢁꢃꢕ
ꢍꢖꢂꢃꢕꢖꢐꢃꢗꢍꢖꢘꢕꢏꢖꢏꢖꢒꢃꢚꢂꢑꢑꢃꢘꢁꢕꢖꢃꢇꢜꢜꢃꢗꢍꢖꢑꢂꢗꢙꢘꢏꢎꢂꢃDꢂ$
ꢌꢍꢑ1ꢃꢕ ꢑꢃꢋ ꢌꢂꢑꢗꢌꢏ<ꢂꢐꢃꢏ ꢖꢃꢊ2ꢅ"ꢃꢀ ꢇ34ꢉꢇ$ꢇ55ꢉ3ꢃꢊ
ꢋꢍ ꢂꢌ$ꢙꢋꢃꢍꢌꢃꢔꢕꢖꢙꢕꢚꢃꢌꢂꢑꢂꢘꢃ ꢏꢚꢚꢃꢕꢚꢑꢍꢃꢑꢂꢘꢃ6&ꢅꢃꢁꢏꢒꢁ3
Local Loopback
ꢀꢁꢂꢃꢚꢍꢗ ꢕꢚꢃꢚ ꢍꢍꢋ<ꢕꢗ;ꢃꢔ ꢍꢐꢂꢃꢘꢕ ;ꢂꢑꢃꢗ ꢚꢍꢗ;ꢃꢕꢖ ꢐꢃꢐꢕ ꢘꢕ
ꢋꢌꢂꢑꢂꢖꢘꢂꢐꢃꢍꢖꢃꢀ ꢄ69!ꢃꢀ 7&ꢅ!ꢃꢕꢖꢐꢃꢀ 2:8ꢃ0 ꢍꢌ
ꢀ,ꢊꢀꢊ1ꢃꢕꢖꢐ ꢃꢍꢙꢘ ꢋꢙꢘꢑꢃꢏꢘꢃꢕꢘꢃ/ꢄ6 9!ꢃ/7& ꢅꢃꢕꢖꢐ
/2:8ꢃ 0ꢍꢌꢃ/,ꢊꢀꢊ13ꢃ6ꢍ ꢗꢕꢚꢃꢚꢍꢍ ꢋ<ꢕꢗ;ꢃꢏ ꢑꢃꢑ ꢂꢚꢂꢗꢘꢂꢐ
<#ꢃꢘꢕ;ꢏꢖꢒꢃꢋꢏꢖꢃ4>ꢃꢁꢏꢒꢁ!ꢃꢍꢌꢃ66&&7ꢃꢔꢕ#ꢃ<ꢂꢃꢑꢂꢚꢂꢗꢘꢂꢐ
ꢙꢑꢏꢖꢒꢃꢘꢁꢂꢃꢑꢂꢌꢏꢕꢚꢃꢏ ꢖꢘꢂꢌꢓꢕꢗꢂ3ꢃꢀꢁꢂꢃꢐꢕꢘꢕꢃꢍ ꢖꢃꢘ ꢁꢂꢃꢘꢌꢕꢖꢑ$
ꢔꢏꢘꢘꢂꢌꢃꢏꢖꢋ ꢙꢘꢑꢃꢏ ꢑꢃꢘꢌ ꢕꢖꢑꢔꢏꢘꢘꢂꢐꢃꢍ ꢖꢃꢘꢁ ꢂꢃꢚꢏ ꢖꢂꢃꢙ ꢖꢚꢂꢑꢑ
ꢀꢊ&ꢅꢃꢏꢑꢃꢑꢂꢚꢂꢗꢘꢂꢐꢃꢘꢍꢃꢗꢕꢙꢑꢂꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢑꢑꢏꢍꢖꢃꢍꢓꢃꢕꢖ
ꢕꢚꢚꢃꢍꢖꢂꢑ ꢃꢑ ꢏꢒꢖꢕꢚꢃꢏꢖꢑ ꢘꢂꢕꢐ3ꢃ/ꢂꢗ ꢂꢏꢎꢂꢌꢃꢏꢖꢋ ꢙꢘꢑꢃꢕ ꢌꢂꢃꢏꢒ $
ꢖꢍꢌꢂꢐꢃ ꢁꢂꢖꢃꢚꢍꢗꢕꢚꢃꢚꢍꢍꢋ<ꢕꢗ;ꢃꢏꢑꢃꢏꢖꢃꢂꢓꢓꢂꢗꢘ3ꢃꢀꢁꢂꢃ@ꢏꢘꢘꢂꢌ
ꢕꢘꢘꢂꢖꢙꢕꢘꢍꢌꢃ ꢏꢑꢃꢖꢍ ꢘꢃꢏ ꢖꢗꢚꢙꢐꢂꢐꢃꢏ ꢖꢃꢘꢁ ꢂꢃꢚꢍ ꢗꢕꢚꢃꢚꢍꢍ ꢋ<ꢕꢗ;
ꢐꢕꢘꢕꢃꢋꢕ ꢘꢁ3ꢃꢅꢂ ꢚꢂꢗꢘꢏꢍꢖꢃꢍ ꢓꢃꢚꢍ ꢗꢕꢚꢃꢚꢍ ꢍꢋ<ꢕꢗ;ꢃꢍꢎꢂ ꢌꢌꢏꢐꢂꢑ
ꢘꢁꢂꢃꢗꢁꢏꢋRꢑꢃꢚꢍꢑꢑꢃꢍꢓꢃꢑꢏꢒꢖꢕꢚꢃꢌꢂꢑꢋꢍꢖꢑꢂ3
"ꢖꢃꢘꢁꢂꢃꢂꢎꢂꢖꢘꢃꢍꢓꢃꢕꢃ ꢔꢕ.ꢏꢔꢙꢔꢃ@ꢏꢘꢘꢂꢌꢃꢁꢏꢘ!ꢃꢘꢁꢂꢃ/ꢄ69
ꢗꢚꢍꢗ;ꢃꢋ ꢂꢌꢏꢍꢐꢃꢏ ꢔꢔꢂꢐꢏꢕꢘꢂꢚ#ꢃꢕꢐ@ ꢙꢑꢘꢑꢃꢘꢍꢃꢕ ꢚꢏꢒꢖꢃꢏꢘ ꢑꢂꢚꢓ
ꢏꢘꢁꢃꢘꢁꢂꢃꢏꢖꢗꢍꢔꢏꢖꢒꢃꢐꢕꢘꢕꢃꢕꢖꢐꢃꢋꢌꢂꢋꢕꢌꢂꢃꢘꢍꢃꢕꢗ ꢗꢙꢌꢕꢘꢂꢚ#
ꢋꢚꢕꢗꢂꢃꢘꢁꢂꢃꢖꢂ.ꢘꢃꢍꢖꢂ!ꢃ ꢁꢂꢘꢁꢂꢌꢃꢏꢘꢃꢕꢌꢌꢏꢎꢂꢑꢃꢍꢖꢂꢃꢋꢂꢌꢏꢍꢐ
ꢚꢕꢘꢂꢌ!ꢃꢍꢌꢃꢕꢓꢘ ꢂꢌꢃꢕꢖꢍ ꢘꢁꢂꢌꢃꢑꢘꢌꢏꢖꢒꢃꢍꢓꢃDꢂ ꢌꢍꢑꢃꢕꢖꢐꢃꢏꢑ ꢃꢐꢏꢑ $
ꢋꢚꢕꢗꢂꢐꢃ<#ꢃ@ꢏ ꢘꢘꢂꢌ3ꢃ?ꢍꢌꢃꢕꢃꢔ ꢕ.ꢏꢔꢙꢔꢃꢂꢕꢌꢚ #ꢃ @ꢏꢘꢘꢂꢌꢃ ꢁꢏꢘ!
/ꢄ69ꢃꢃ ꢏꢚꢚꢃꢃꢁꢕꢎꢂꢃꢕꢃꢋꢂꢌꢏꢍꢐꢃꢍꢓꢃ>-ꢇꢉꢃKꢃꢆ=)ꢃꢖꢑꢃEꢃꢉ=5
ꢖꢑꢃ04!)ꢆꢈ!5ꢆꢇꢃ+D13ꢃ?ꢍꢌꢃꢕꢃꢔ ꢕ.ꢏꢔꢙꢔꢃꢚꢕꢘꢂꢃ@ꢏꢘꢘꢂꢌꢃꢁꢏꢘ!
/ꢄ69ꢃ ꢏꢚꢚꢃꢁꢕꢎꢂꢃꢕꢃꢋꢂꢌꢏꢍꢐꢃꢍꢓꢃꢇ5-ꢇꢉꢃKꢃꢆ=)ꢃꢖꢑꢃEꢃ5=>
ꢖꢑꢃ0ꢇ!ꢜꢈꢈ!))ꢜꢃ+D13
Loss of Signal
Remote Loopback
/ꢂꢗꢂꢏꢎꢂꢌꢃꢚꢍꢑꢑꢃꢍꢓꢃ ꢑꢏꢒꢖꢕꢚꢃꢏꢑꢃꢏꢖꢐꢏꢗꢕꢘꢂꢐꢃꢙꢋꢍꢖꢃꢌꢂꢗꢂꢏꢎ$
ꢏꢖꢒꢃꢇ> ꢈꢃꢗꢍ ꢖꢑꢂꢗꢙꢘꢏꢎꢂꢃD ꢂꢌꢍꢑ3ꢃꢊꢃꢐꢏꢒ ꢏꢘꢕꢚꢃꢗꢍ ꢙꢖꢘꢂꢌ
ꢗꢍꢙꢖꢘꢑꢃꢌꢂꢗꢂꢏꢎꢂꢐꢃDꢂꢌꢍꢑꢃ<ꢕꢑꢂꢐꢃꢍꢖꢃ/ꢄ69ꢃꢗ#ꢗꢚꢂꢑ3ꢃꢊ
Dꢂꢌꢍꢃꢏꢖꢋꢙꢘꢃꢏꢑꢃꢐꢂꢘꢂꢌꢔꢏꢖꢂꢐꢃꢂꢏꢘꢁꢂꢌꢃ ꢁꢂꢖꢃDꢂꢌꢍꢑꢃꢕꢌꢂꢃꢌꢂ$
"ꢖꢃꢌꢂꢔꢍꢘꢂꢃꢚꢍꢍꢋ<ꢕꢗ;!ꢃꢘꢁꢂꢃꢌꢂꢗꢍꢎꢂꢌꢂꢐꢃꢗꢚꢍꢗ;ꢃꢕꢖꢐꢃꢐꢕꢘꢕ
ꢏꢖꢋꢙꢘꢃꢍꢖ ꢃ/ꢀ"7ꢃꢕꢖ ꢐꢃ//"28ꢃꢕꢌꢂ ꢃꢑꢂꢖꢘꢃꢘꢁꢌꢍ ꢙꢒꢁꢃꢘꢁꢂ
@ꢏꢘꢘꢂꢌꢃꢕꢘꢘꢂꢖꢙꢕꢘꢍꢌꢃꢕꢖꢐꢃ<ꢕꢗ;ꢃꢍꢙꢘꢃꢍꢖꢃꢘꢁꢂꢃꢚꢏꢖꢂꢃꢎꢏꢕꢃꢀꢀ"7
ꢕꢖꢐꢃꢀ/"283ꢃꢀꢁꢂꢃꢌꢂꢗꢍꢎꢂꢌꢂꢐꢃꢏꢖꢗꢍꢔꢏꢖꢒꢃꢑꢏꢒꢖꢕꢚꢑꢃꢕꢌꢂ
ꢕꢚꢑꢍꢃꢑ ꢂꢖꢘꢃꢘꢍ ꢃ/ꢄ6 9!ꢃ/7 &ꢅꢃꢕꢖ ꢐꢃ/2: 8ꢃ0 ꢍꢌ
16
DS40F3
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
/,ꢊꢀꢊ13ꢃ/ꢂꢔꢍꢘꢂꢃꢚꢍꢍꢋ<ꢕꢗ;ꢃꢏꢑꢃꢑꢂꢚꢂꢗꢘꢂꢐꢃ<#ꢃꢘꢕ;ꢏꢖꢒ
Line Code Encoder/Decoder
ꢋꢏꢖꢃ4ꢆꢃꢁꢏꢒꢁ!ꢃꢍꢌꢃ/6&&7ꢃꢔꢕ#ꢃ<ꢂꢃꢑꢂꢚꢂꢗꢘꢂꢐꢃꢙꢑꢏꢖꢒꢃꢘꢁꢂ
ꢑꢂꢌꢏꢕꢚꢃꢏꢖ ꢘꢂꢌꢓꢕꢗꢂ3ꢃꢅꢏ ꢔꢙꢚꢘꢕꢖꢂꢍꢙꢑꢃꢑ ꢂꢚꢂꢗꢘꢏꢍꢖꢃꢍ ꢓꢃꢚꢍ ꢗꢕꢚ
ꢕꢖꢐꢃꢌꢂꢔꢍꢘꢂꢃꢚꢍꢍꢋ<ꢕꢗ;ꢃꢔꢍꢐꢂꢑꢃꢏꢑꢃꢖꢍꢘꢃꢎꢕꢚꢏꢐꢃ0ꢑꢂꢂꢃ/ꢂ$
ꢑꢂꢘ13
"ꢖꢃ:.ꢘꢂꢖꢐꢂꢐꢃ+ꢕꢌꢐ ꢕꢌꢂꢃ'ꢍꢐꢂ!ꢃꢘꢁꢌꢂꢂꢃꢚꢏꢖꢂꢃꢗꢍꢐꢂꢑꢃꢕꢌꢂ
ꢕꢎꢕꢏꢚꢕ<ꢚꢂꢛꢃꢊ'" !ꢃ( )*ꢅꢃꢕꢖꢐ ꢃ+,(ꢉ3 ꢃꢀ ꢁꢂꢃꢏ ꢖꢋꢙꢘꢃꢘꢍ
ꢘꢁꢂꢃꢂꢖꢗꢍꢐꢂꢌꢃꢏꢑꢃꢀ,ꢊꢀꢊ3ꢃꢀꢁꢂꢃꢍꢙꢘꢋꢙꢘꢑꢃꢓꢌꢍꢔꢃꢘꢁꢂꢃꢐꢂ$
ꢗꢍꢐꢂꢌꢃꢕꢌꢂꢃ/, ꢊꢀꢊꢃꢕꢖꢐꢃ(7L ꢃ0(ꢏꢋꢍꢚꢕꢌ ꢃLꢏꢍꢚꢕꢘꢏꢍꢖ
ꢅꢘꢌꢍ<ꢂ13ꢃꢀꢁꢂꢃꢂꢖꢗꢍꢐꢂꢌꢃꢕꢖꢐꢃꢐꢂꢗꢍꢐꢂꢌꢃꢕꢌꢂꢃꢑꢂꢚꢂꢗꢘꢂꢐꢃꢙꢑ$
ꢏꢖꢒꢃꢋ ꢏꢖꢑꢃ6 :24!ꢃ6 :2ꢇ!ꢃ6 :2ꢜ!ꢃꢀꢄ&,:ꢃꢕ ꢖꢐ
/ꢄ&,:ꢃꢕꢑꢃꢑꢁꢍ ꢖꢃꢏꢖꢃꢀꢕ<ꢚꢂꢃꢆ3
"ꢖꢃꢘꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊꢃ:.ꢘꢂꢖꢐꢂꢐꢃ+ꢕꢌꢐ ꢕꢌꢂꢃ'ꢍꢐꢂ!ꢃꢌꢂ$
ꢔꢍꢘꢂꢃꢚꢍꢍ ꢋ<ꢕꢗ;ꢃꢍꢗꢗꢙꢌ ꢑꢃ<ꢂꢓ ꢍꢌꢂꢃꢘꢁꢂꢃꢚꢏꢖꢂꢃꢗꢍꢐꢂ
ꢂꢖꢗꢍꢐꢂꢌ-ꢐꢂꢗꢍꢐꢂꢌ!ꢃꢏꢖꢑꢙꢌꢏꢖꢒꢃꢘꢁꢕꢘꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢐꢃꢑꢏꢒ$
ꢖꢕꢚꢃꢔ ꢕꢘꢗꢁꢂꢑꢃꢘꢁ ꢂꢃꢌ ꢂꢗꢂꢏꢎꢂꢐꢃꢑ ꢏꢒꢖꢕꢚ!ꢃꢂꢎꢂ ꢖꢃꢏꢖ ꢃꢘꢁꢂ
ꢋꢌꢂꢑꢂꢖꢗꢂꢃꢍ ꢓꢃꢌꢂ ꢗꢂꢏꢎꢂꢐꢃ< ꢏꢋꢍꢚꢕꢌꢃ ꢎꢏꢍꢚꢕꢘꢏꢍꢖꢑ3ꢃ ꢀꢁꢂꢃ ꢌꢂ$
ꢗꢍꢎꢂꢌꢂꢐꢃꢐꢕꢘꢕꢃ ꢏꢚꢚꢃꢕꢚꢑꢍꢃ<ꢂꢃꢐꢂꢗꢍꢐꢂꢐꢃꢕꢖꢐꢃꢍꢙꢘꢋꢙꢘꢃꢍꢖ
/,ꢊꢀꢊꢃꢏꢓꢃ/ꢄ&,:ꢃꢏꢑꢃꢚꢍ 3
LEN 2/1/0
000
010-111
TCODE
(Transmit
Encoder
Selection)
RCODE
(Receiver
Decoder
Selection)
HDB3
B8ZS
Encoder
LOW
HIGH
LOW
HIGH
Encoder
AMI
Encoder
HDB3
Decoder
Driver Performance Monitor
B8ZS
Decoder
AMI
Decoder
ꢀꢍꢃꢕꢏꢐꢃꢏꢖꢃꢂꢕꢌꢚ#ꢃꢐꢂꢘꢂꢗ ꢘꢏꢍꢖꢃꢕꢖ ꢐꢃꢂꢕ ꢑ#ꢃꢏꢑ ꢍꢚꢕꢘꢏꢍꢖꢃꢍꢓ
ꢖꢍꢖꢓꢙꢖꢗꢘꢏꢍꢖꢏꢖꢒꢃꢚꢏꢖ;ꢑ !ꢃꢘꢁꢂꢃ+ꢕꢌ ꢐ ꢕꢌꢂꢃꢕꢖꢐꢃ+ ꢍꢑꢘ
'ꢍꢐꢂꢑꢃꢍꢓꢃꢘꢁ ꢂꢃꢄꢅꢆ ꢇꢈꢉꢈꢊꢃꢕꢌꢂꢃꢕ<ꢚꢂꢃꢘꢍꢃꢔ ꢍꢖꢏꢘꢍꢌ
ꢘꢌꢕꢖꢑꢔꢏꢘꢃꢐꢌ ꢏꢎꢂꢃ ꢋꢂꢌꢓꢍꢌꢔꢕꢖꢗꢂꢃꢕꢖꢐ ꢃ ꢌꢂꢋꢍꢌꢘꢃ ꢁꢂꢖ ꢃ ꢘꢁꢂ
ꢐꢌꢏꢎꢂꢌꢃ ꢏꢑꢃꢖ ꢍꢃꢚ ꢍꢖꢒꢂꢌꢃꢍ ꢋꢂꢌꢕꢘꢏꢍꢖꢕꢚ3ꢃ ꢀꢁꢏꢑꢃꢓꢂꢕ ꢘꢙꢌꢂꢃꢗꢕ ꢖ
<ꢂꢃꢙꢑ ꢂꢐꢃꢘ ꢍꢃꢔꢍꢖꢏ ꢘꢍꢌꢃꢂꢏ ꢘꢁꢂꢌꢃ ꢘꢁꢂꢃꢐꢂ ꢎꢏꢗꢂRꢑꢃ ꢋꢂꢌꢓꢍꢌꢔ$
ꢕꢖꢗꢂꢃꢍꢌꢃꢘꢁꢂꢃꢋꢂꢌꢓꢍꢌꢔꢕꢖꢗꢂꢃꢍꢓꢃꢕ ꢃꢖꢂꢏꢒꢁ<ꢍꢌꢏꢖꢒꢃꢐꢌꢏꢎꢂꢌ3
ꢀꢁꢂꢃꢐꢌꢏꢎꢂꢌꢃꢋꢂꢌꢓꢍꢌꢔꢕꢖꢗꢂꢃꢔꢍꢖꢏꢘꢍꢌꢃꢏꢖꢐꢏꢗꢕꢘꢍꢌꢃꢏꢑꢃꢖ ꢍꢌ$
ꢔꢕꢚꢚ#ꢃꢕꢘꢃꢕꢃꢚꢍ ꢃ0Dꢂꢌꢍ1ꢃꢚꢍꢒꢏꢗꢃꢚꢂꢎꢂꢚ!ꢃꢕꢖꢐꢃꢒꢍꢂꢑꢃꢘꢍꢃꢁꢏꢒꢁ
ꢚꢂꢎꢂꢚꢃꢙꢋꢍ ꢖꢃꢐꢂ ꢘꢂꢗꢘꢏꢖꢒꢃꢐꢌ ꢏꢎꢂꢌꢃꢓ ꢕꢏꢚꢙꢌꢂ3ꢃ" ꢖꢃꢘ ꢁꢂꢃ+ ꢍꢑꢘ
'ꢍꢐꢂ!ꢃ ,7'ꢃꢏꢑ ꢃꢕꢎꢕ ꢏꢚꢕ<ꢚꢂꢃ ꢓꢌꢍꢔꢃ<ꢍꢘ ꢁꢃ ꢘꢁꢂꢃꢌꢂꢒꢏ ꢑꢘꢂꢌ
ꢕꢖꢐꢃꢋꢏꢖꢃꢇꢇ3
Table 6. Selection of Encoder/Decoder
Alarm Indication Signal
"ꢖꢃ:.ꢘꢂꢖꢐꢂꢐꢃ+ꢕꢌꢐ ꢕꢌꢂꢃ'ꢍꢐꢂ!ꢃꢘꢁꢂꢃꢌꢂꢗꢂꢏꢎꢂꢌꢃꢑꢂꢘꢑꢃꢘꢁꢂ
ꢍꢙꢘꢋꢙꢘꢃꢋ ꢏꢖꢃꢊ"ꢅꢃꢁꢏ ꢒꢁꢃ ꢁꢂ ꢖꢃꢚꢂꢑ ꢑꢃꢘꢁꢕꢖꢃ5ꢃDꢂꢌꢍꢑꢃꢕꢌꢂ
ꢐꢂꢘꢂꢗꢘꢂꢐꢃꢍꢙꢘꢃꢍꢓꢃ)ꢇ54ꢃ<ꢏꢘꢃꢋꢂꢌꢏꢍꢐꢑ3ꢃꢊ"ꢅꢃꢌꢂꢘꢙꢌꢖꢑꢃꢚꢍ
ꢁꢂꢖꢃ5ꢃꢍꢌꢃꢔꢍꢌꢂꢃDꢂ ꢌꢍꢑꢃ ꢕꢌꢂꢃꢐꢂꢘ ꢂꢗꢘꢂꢐꢃꢍꢙ ꢘꢃ ꢍꢓꢃ )ꢇ54
<ꢏꢘꢑ3
Parallel Chip Select
ꢀꢁꢂꢃꢐꢌꢏꢎꢂꢌꢃꢋꢂꢌꢓꢍꢌꢔꢕꢖꢗꢂꢃꢔꢍꢖꢏꢘꢍꢌꢃꢗꢍꢖꢑꢏꢑꢘꢑꢃꢍꢓꢃꢕꢖꢃꢕꢗ$
ꢘꢏꢎꢏꢘ#ꢃꢐꢂꢘꢂꢗꢘꢍꢌꢃꢘꢁꢕꢘꢃꢔꢍꢖꢏꢘꢍꢌꢑꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢐꢃꢑꢏꢒꢖꢕꢚ
ꢁꢂꢖꢃ'ꢀ"7ꢃꢏꢑꢃꢗꢍꢖꢖꢂꢗꢘꢂꢐꢃꢘꢍꢃꢀꢀ"7ꢃꢕꢖꢐꢃ'/"28ꢃꢏꢑ
ꢗꢍꢖꢖꢂꢗꢘꢂꢐꢃꢘꢍ ꢃꢀ /"283ꢃ,7'ꢃ ꢏꢚ ꢚꢃꢒꢍꢃꢁꢏ ꢒꢁꢃꢏꢓꢃꢘꢁ ꢂ
ꢕ<ꢑꢍꢚꢙꢘꢂꢃꢐꢏ ꢓꢓꢂꢌꢂꢖꢗꢂꢃ<ꢂ ꢘ ꢂꢂꢖꢃ'ꢀ "7ꢃꢕꢖ ꢐꢃ'/" 28
ꢐꢍꢂꢑꢃꢖꢍ ꢘꢃꢘꢌ ꢕꢖꢑꢏꢘꢏꢍꢖꢃꢕ <ꢍꢎꢂꢃꢍꢌ ꢃ<ꢂ ꢚꢍ ꢃꢕꢃꢘ ꢁꢌꢂꢑꢁꢍꢚꢐ
ꢚꢂꢎꢂꢚꢃ ꢏꢘꢁꢏꢖꢃꢕꢃꢘꢏꢔꢂ$ꢍꢙꢘꢃꢋꢂꢌꢏꢍꢐ3
"ꢖꢃ:.ꢘꢂꢖꢐꢂꢐꢃ+ꢕꢌꢐ ꢕꢌꢂꢃ'ꢍꢐꢂ!ꢃ7ꢄꢅꢃꢗꢕꢖꢃ<ꢂꢃꢙꢑꢂꢐꢃꢘꢍ
ꢒꢕꢘꢂꢃꢘꢁꢂꢃꢐꢏꢒꢏꢘꢕꢚꢃꢗꢍꢖꢘꢌꢍꢚꢃꢏꢖꢋꢙꢘꢑꢛꢃꢀꢄ&,:!ꢃ/ꢄ&,:!
6:2ꢜ!ꢃ6 :2ꢇ!ꢃ6 :24!ꢃ/ 6&&7!ꢃ6 6&&7ꢃꢕꢖꢐ
ꢀꢊ&ꢅ3ꢃ" ꢖꢋꢙꢘꢑꢃꢕꢌ ꢂꢃꢕꢗꢗꢂꢋꢘꢂꢐꢃꢍꢖꢃꢘꢁꢂꢑ ꢂꢃꢋꢏꢖꢑꢃꢍꢖꢚ#
ꢁꢂꢖꢃ7ꢄꢅꢃꢏꢑꢃꢚꢍ 3ꢃꢄꢁꢕꢖꢒꢂꢑꢃꢏꢖꢃꢏꢖꢋꢙꢘꢑꢃ ꢏꢚꢚꢃꢏꢔꢔꢂꢐꢏ$
ꢕꢘꢂꢚ#ꢃꢗꢁꢕꢖꢒꢂꢃꢘꢁꢂꢃꢍꢋꢂꢌꢕꢘꢏꢖꢒꢃꢑ ꢘꢕꢘꢂꢃꢍꢓꢃꢘꢁꢂꢃꢐꢂꢎꢏꢗꢂ3
ꢀꢁꢂꢌꢂꢓꢍꢌꢂ!ꢃ ꢁꢂꢖꢃꢗ#ꢗꢚꢏꢖꢒꢃ7ꢄꢅꢃꢘꢍꢃꢙꢋꢐꢕꢘꢂꢃꢘꢁꢂꢃꢍꢋꢂꢌ$
ꢕꢘꢏꢖꢒꢃꢑ ꢘꢕꢘꢂ!ꢃꢘꢁꢂ ꢃꢐꢏꢒ ꢏꢘꢕꢚꢃꢗꢍ ꢖꢘꢌꢍꢚꢃꢏꢖꢋ ꢙꢘꢑꢃꢑ ꢁꢍꢙꢚꢐꢃ< ꢂ
ꢑꢘꢕ<ꢚꢂꢃꢓꢍꢌꢃꢘꢁꢂꢃꢂꢖꢘꢏꢌꢂꢃ7ꢄꢅꢃꢚꢍ ꢃꢋꢂꢌꢏꢍꢐ3ꢃꢃꢀꢁꢂꢃꢗꢍꢖꢘꢌꢍꢚ
ꢏꢖꢋꢙꢘꢑꢃꢕꢌꢂꢃꢏꢒꢖꢍꢌꢂꢐꢃ ꢁꢂꢖꢃ7ꢄꢅꢃꢏꢑꢃꢃꢁꢏꢒꢁ3
Fꢁꢂꢖꢂꢎꢂꢌꢃꢔꢍꢌꢂꢃꢘꢁꢕꢖꢃꢍꢖꢂꢃꢚꢏꢖꢂꢃꢏꢖꢘꢂꢌꢓꢕꢗꢂꢃ"ꢄꢃꢌꢂꢑꢏꢐꢂꢑ
ꢍꢖꢃꢘꢁꢂꢃꢑꢕꢔꢂꢃꢗꢏꢌꢗꢙꢏꢘꢃ<ꢍꢕꢌꢐ!ꢃꢘꢁꢂꢃꢂꢓꢓꢂꢗꢘꢏꢎꢂꢖꢂꢑꢑꢃꢍꢓꢃꢘꢁꢂ
ꢐꢌꢏꢎꢂꢌꢃꢋꢂꢌꢓꢍꢌꢔꢕꢖꢗꢂꢃꢔꢍꢖꢏꢘꢍꢌꢃꢗꢕꢖꢃ<ꢂꢃꢔꢕ.ꢏꢔꢏDꢂꢐꢃ<#
ꢁꢕꢎꢏꢖꢒꢃꢂꢕꢗꢁꢃ"ꢄꢃꢔꢍꢖꢏꢘꢍꢌꢃꢋꢂꢌꢓꢍꢌꢔꢕꢖꢗꢂꢃꢍꢓꢃ ꢕꢃꢖꢂꢏꢒꢁ$
<ꢍꢌꢏꢖꢒꢃꢐꢂꢎ ꢏꢗꢂ!ꢃꢌꢕ ꢘꢁꢂꢌꢃꢘꢁꢕ ꢖꢃꢁꢕ ꢎꢏꢖꢒꢃꢏꢘ ꢃꢔ ꢍꢖꢏꢘꢍꢌꢃꢏꢘꢑ
ꢍ ꢖꢃꢋꢂꢌꢓꢍꢌꢔꢕꢖꢗꢂ3
Power On Reset / Reset
Hꢋꢍꢖꢃꢋꢍ ꢂꢌ$ꢙꢋ!ꢃꢘꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊꢃꢏꢑꢃꢁꢂꢚꢐꢃꢏꢖꢃꢕꢃ ꢑꢘꢕꢘꢏꢗ
ꢑꢘꢕꢘꢂꢃꢙ ꢖꢘꢏꢚꢃꢘꢁ ꢂꢃꢑ ꢙꢋꢋꢚ#ꢃꢗ ꢌꢍꢑꢑꢂꢑꢃꢕ ꢃꢘꢁꢌꢂ ꢑꢁꢍꢚꢐꢃꢍꢓꢃꢕꢋ$
DS40F3
17
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
CS
SCLK
SDI
R/W
0
0
0
0
1
0
0
D0
D0
D1
D1
D2
Data Input/Output
D2 D3 D4
D3
D4
D5
D5
D6
D7
Address/Command Byte
D6 D7
SDO
Figure 13. Input/Output Timing
ꢋꢌꢍ.ꢏꢔꢕꢘꢂꢚ#ꢃꢘꢁꢌꢂ ꢂꢃLꢍꢚꢘꢑ3ꢃF ꢁꢂꢖꢃꢘ ꢁꢏꢑꢃꢘꢁ ꢌꢂꢑꢁꢍꢚꢐꢃꢏꢑ
ꢗꢌꢍꢑꢑꢂꢐ!ꢃꢘꢁꢂꢃꢐꢂꢎꢏꢗꢂꢃ ꢏꢚꢚꢃꢐꢂꢚꢕ#ꢃꢓꢍꢌꢃꢕ<ꢍꢙꢘꢃꢇꢜꢃꢔꢑꢃꢘꢍ
ꢕꢚꢚꢍ ꢃꢘꢁꢂꢃꢋꢍ ꢂꢌꢃꢑꢙꢋꢋꢚ#ꢃꢘꢍꢃꢌꢂꢕꢗꢁꢃꢍꢋꢂꢌꢕꢘꢏꢖꢒꢃꢎꢍꢚꢘꢕꢒꢂ3
ꢊꢓꢘꢂꢌꢃꢘꢁꢏꢑꢃꢐꢂꢚꢕ#!ꢃꢗꢕꢚꢏ<ꢌꢕꢘꢏꢍꢖꢃꢍꢓꢃꢘꢁꢂꢃꢐꢂꢚꢕ#ꢃꢚꢏꢖꢂꢑꢃꢙꢑꢂꢐ
ꢏꢖꢃꢘꢁꢂ ꢃꢘꢌ ꢕꢖꢑꢔꢏꢘꢃꢕꢖ ꢐꢃꢌ ꢂꢗꢂꢏꢎꢂꢃꢑꢂꢗꢘ ꢏꢍꢖꢑꢃꢗꢍ ꢔꢔꢂꢖꢗꢂꢑ3
ꢀꢁꢂꢃ ꢐꢂꢚꢕ#ꢃꢚꢏꢖꢂꢑꢃꢗꢕꢖꢃ <ꢂꢃꢗꢕꢚꢏ<ꢌꢕꢘꢂꢐꢃꢍꢖꢚ#ꢃꢏꢓꢃꢕꢃꢌ ꢂꢓꢂꢌ$
ꢂꢖꢗꢂꢃꢗꢚꢍꢗ;ꢃꢏꢑꢃꢋ ꢌꢂꢑꢂꢖꢘ3ꢃꢀꢁꢂꢃꢌ ꢂꢓꢂꢌꢂꢖꢗꢂꢃꢗꢚꢍꢗ;ꢃꢓꢍꢌꢃꢘꢁꢂ
ꢌꢂꢗꢂꢏꢎꢂꢌꢃꢏꢑꢃꢋꢌꢍꢎꢏꢐꢂꢐꢃ<#ꢃꢊ ꢄ69"ꢃ0ꢍꢌꢃ<#ꢃꢘꢁꢂꢃꢗꢌ#ꢑꢘꢕꢚ
ꢍꢑꢗꢏꢚꢚꢕꢘꢍꢌꢃꢏꢓꢃꢊꢄ69"ꢃꢏꢑꢃꢖꢍꢘ ꢃꢋꢌꢂꢑꢂꢖꢘ13ꢃꢀꢁꢂꢃꢌꢂꢓꢂꢌꢂꢖꢗꢂ
ꢗꢚꢍꢗ;ꢃꢓꢍꢌꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢌꢃꢏꢑꢃꢋꢌꢍꢎꢏꢐꢂꢐꢃ<#ꢃꢀꢄ693ꢃꢀꢁꢂ
ꢏꢖꢏꢘꢏꢕꢚꢃꢗꢕꢚꢏ<ꢌꢕꢘꢏꢍꢖꢃꢑꢁꢍꢙꢚꢐꢃꢘꢕ;ꢂꢃꢚꢂꢑꢑꢃꢘꢁꢕꢖꢃ4ꢜꢃꢔꢑ3
ꢕꢗꢘꢂꢌꢏꢑꢘꢏꢗꢑꢃ ꢕꢖꢐꢃꢔ ꢍꢖꢏꢘꢍꢌꢃ ꢐꢂꢎꢏꢗꢂꢃꢑꢘ ꢕꢘꢙꢑ3ꢃꢀ ꢁꢂꢃꢑ ꢂꢌꢏꢕꢚ
ꢋꢍꢌꢘꢃꢌꢂꢕꢐ- ꢌꢏꢘꢂꢃꢘꢏꢔꢏꢖꢒꢃꢏꢑꢃꢏꢖꢐꢂꢋꢂꢖꢐꢂꢖꢘꢃꢍꢓꢃ ꢘꢁꢂꢃꢑ#ꢑ$
ꢘꢂꢔꢃꢘꢌꢕꢖꢑꢔꢏꢘꢃꢕꢖꢐꢃꢌꢂꢗꢂꢏꢎꢂꢃꢘꢏꢔꢏꢖꢒ3
,ꢕꢘꢕꢃꢘꢌꢕꢖꢑꢓꢂꢌꢑꢃꢕꢌꢂꢃꢏꢖꢏꢘꢏꢕꢘꢂꢐꢃ<#ꢃꢘꢕ;ꢏꢖꢒꢃꢘꢁꢂꢃꢗꢁꢏꢋꢃꢑꢂ$
ꢚꢂꢗꢘꢃꢏ ꢖꢋꢙꢘ!ꢃ ꢄꢅ!ꢃꢚ ꢍ ꢃ 0ꢄꢅꢃ ꢔꢙꢑꢘꢃꢏꢖ ꢏꢘꢏꢕꢚꢚ#ꢃ< ꢂꢃꢁ ꢏꢒꢁ13
ꢅꢄ69ꢃ ꢔꢕ#ꢃ< ꢂꢃꢂ ꢏꢘꢁꢂꢌꢃꢁꢏ ꢒꢁꢃꢍ ꢌꢃꢚꢍ ꢃ ꢁ ꢂꢖꢃ ꢄꢅꢃꢏ ꢖ$
ꢏꢘꢏꢕꢚꢚ#ꢃꢒꢍꢂ ꢑꢃꢚ ꢍ 3ꢃꢊꢐꢐ ꢌꢂꢑꢑꢃꢕ ꢖꢐꢃꢏ ꢖꢋꢙꢘꢃꢐꢕ ꢘꢕꢃ< ꢏꢘꢑꢃꢕꢌꢂ
ꢗꢚꢍꢗ;ꢂꢐꢃꢏꢖꢃꢍꢖꢃꢘ ꢁꢂꢃꢌꢏꢑꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃꢅꢄ6 93ꢃ,ꢕꢘꢕꢃꢍꢖ
ꢅ,&ꢃ ꢏꢑꢃꢎꢕ ꢚꢏꢐꢃꢕꢖꢐ ꢃꢑ ꢘꢕ<ꢚꢂꢃꢍꢖ ꢃꢘꢁꢂ ꢃꢓꢕꢚꢚ ꢏꢖꢒꢃꢂꢐꢒ ꢂꢃꢍꢓ
ꢅꢄ69ꢃ ꢁꢂꢖꢃꢄ69:ꢃꢏꢑꢃꢚꢍ !ꢃꢕꢖꢐꢃꢍꢖꢃꢘꢁꢂꢃꢌꢏꢑꢏꢖꢒꢃꢂꢐꢒꢂ
ꢍꢓꢃꢅꢄ69ꢃ ꢁꢂꢖꢃꢄ69:ꢃꢏꢑꢃꢁꢏꢒꢁ3ꢃꢃ,ꢕꢘꢕꢃꢘꢌꢕꢖꢑꢓꢂꢌꢑꢃꢕꢌꢂ
ꢘꢂꢌꢔꢏꢖꢕꢘꢂꢐꢃ<# ꢃꢑꢂꢘꢘꢏꢖꢒꢃꢄꢅꢃꢁꢏꢒꢁ3ꢃꢄꢅꢃꢔꢕ#ꢃꢒ ꢍꢃꢁꢏ ꢒꢁ
ꢖꢍꢃꢑꢍꢍꢖꢂꢌꢃꢘꢁꢕꢖꢃꢈꢜꢃꢖꢑ ꢃꢕꢓꢘꢂꢌꢃꢘꢁꢂꢃꢌꢏꢑꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃ ꢘꢁꢂ
ꢅꢄ69ꢃꢗ #ꢗꢚꢂꢃꢗꢍ ꢌꢌꢂꢑꢋꢍꢖꢐꢏꢖꢒꢃꢘꢍ ꢃꢘꢁꢂ ꢃꢚꢕꢑ ꢘꢃ ꢌꢏꢘ ꢂꢃ<ꢏꢘ 3
?ꢍꢌꢃꢕꢃ ꢑꢂꢌꢏꢕꢚꢃꢐꢕꢘꢕꢃꢌꢂꢕꢐ!ꢃꢄꢅꢃꢔꢕ#ꢃꢒꢍꢃꢁꢏꢒꢁꢃꢕꢖ#ꢃꢘꢏꢔꢂ
ꢘꢍꢃꢘꢂꢌꢔꢏꢖꢕꢘꢂꢃꢘꢁꢂꢃꢍꢙꢘꢋꢙꢘ3
"ꢖꢃꢍꢋꢂꢌꢕꢘꢏꢍꢖ!ꢃꢘꢁꢂꢃꢐꢂꢚꢕ#ꢃꢚꢏꢖꢂꢑꢃꢕꢌꢂꢃꢗꢍꢖꢘꢏꢖꢙꢍꢙꢑꢚ#ꢃꢗꢕꢚꢏ$
<ꢌꢕꢘꢂꢐ!ꢃꢔ ꢕ;ꢏꢖꢒꢃꢘꢁ ꢂꢃꢋꢂ ꢌꢓꢍꢌꢔꢕꢖꢗꢂꢃꢍ ꢓꢃꢘ ꢁꢂꢃꢐ ꢂꢎꢏꢗꢂ
ꢏꢖꢐꢂꢋꢂꢖꢐꢂꢖꢘꢃꢍꢓꢃꢋꢍ ꢂꢌꢃꢑꢙꢋꢋꢚ#ꢃꢍꢌꢃꢘꢂꢔꢋꢂꢌꢕꢘꢙꢌꢂꢃꢎꢕꢌꢏ$
ꢕꢘꢏꢍꢖꢑ3ꢃꢀ ꢁꢂꢃꢗꢍꢖꢘꢏꢖꢙꢍꢙꢑ ꢃꢗꢕꢚꢏ<ꢌꢕꢘꢏꢍꢖꢃꢓꢙ ꢖꢗꢘꢏꢍꢖ
ꢓꢍꢌꢂꢒꢍꢂꢑꢃꢕ ꢖ#ꢃꢌꢂ %ꢙꢏꢌꢂꢔꢂꢖꢘꢃꢘꢍꢃꢌꢂ ꢑꢂꢘꢃꢘꢁ ꢂꢃꢚꢏꢖ ꢂꢃꢏꢖꢘ ꢂꢌ$
ꢓꢕꢗꢂꢃ ꢁꢂꢖꢃꢏꢖꢃꢍꢋꢂꢌꢕꢘꢏꢍꢖ3ꢃ+ꢍ ꢂꢎꢂꢌ!ꢃꢕꢃꢌꢂꢑꢂꢘꢃꢓꢙꢖꢗꢘꢏꢍꢖ
ꢏꢑꢃꢕꢎꢕꢏꢚꢕ<ꢚꢂꢃ ꢁꢏꢗꢁꢃ ꢏꢚꢚꢃꢗꢚꢂꢕꢌꢃꢕꢚꢚꢃꢌꢂꢒꢏꢑꢘꢂꢌꢑ3
?ꢏꢒꢙꢌꢂꢃꢇꢉꢃꢑꢁꢍ ꢑꢃꢘꢁꢂꢃꢘꢏꢔꢏꢖꢒꢃꢌꢂꢚꢕꢘꢏꢍꢖꢑꢁꢏꢋꢑꢃꢓꢍꢌꢃꢐꢕ ꢘꢕ
ꢘꢌꢕꢖꢑꢓꢂꢌꢑꢃ ꢁꢂꢖꢃꢄ69:ꢃEꢃꢇ3ꢃFꢁꢂꢖꢃꢄ69:ꢃEꢃꢜ!ꢃꢐꢕꢘꢕ
ꢍꢙꢘꢋꢙꢘꢃꢓꢌꢍꢔꢃꢘꢁꢂꢃꢑꢂꢌꢏꢕꢚꢃꢋꢍꢌꢘ!ꢃꢅ,&!ꢃꢏꢑꢃꢎꢕꢚꢏꢐꢃꢍꢖꢃꢘꢁꢂ
ꢓꢕꢚꢚꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃꢅꢄ693ꢃ?ꢍꢌꢃꢄ69:ꢃEꢃꢇ!ꢃꢐꢕꢘꢕꢃ<ꢏꢘꢃ,>
ꢏꢑꢃꢁꢂꢚꢐꢃꢘꢍꢃꢘꢁꢂꢃꢓꢕꢚꢚꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃꢘꢁꢂꢃꢇꢆꢘꢁꢃꢗꢚꢍꢗ;ꢃꢗ#ꢗꢚꢂI
ꢓꢍꢌꢃꢄ 69:ꢃE ꢃꢜ! ꢃꢐ ꢕꢘꢕꢃ<ꢏ ꢘꢃ,> ꢃꢏꢑ ꢃꢁ ꢂꢚꢐꢃꢘꢍ ꢃꢘꢁ ꢂꢃꢌꢏ ꢑꢏꢖꢒ
ꢂꢐꢒꢂꢃꢍꢓꢃꢘꢁꢂꢃꢇ>ꢘꢁꢃꢗꢚꢍꢗ;ꢃꢗ#ꢗꢚꢂ3ꢃꢅ,&ꢃꢒꢍꢂꢑꢃꢘꢍꢃꢕꢃꢁꢏ ꢒꢁ
"ꢖꢃꢘꢁꢂꢃ +ꢕꢌꢐ ꢕꢌꢂꢃꢕꢖꢐꢃ :.ꢘꢂꢖꢐꢂꢐꢃ+ꢕꢌꢐ ꢕꢌꢂꢃꢔꢍꢐꢂꢑ!ꢃꢕ
ꢌꢂꢑꢂꢘꢃꢌꢂ%ꢙꢂꢑꢘꢃꢏꢑꢃꢔꢕꢐꢂꢃ<#ꢃꢑꢏꢔꢙꢚꢘꢕꢖꢂꢍꢙꢑꢚ#ꢃꢑꢂꢘꢘꢏꢖꢒꢃ<ꢍꢘꢁ
/6&&7ꢃꢕꢖꢐꢃ66&&7ꢃꢁꢏꢒꢁꢃꢓꢍꢌꢃꢕꢘꢃꢚꢂꢕꢑꢘꢃ4ꢜꢜꢃꢖꢑ3ꢃꢃ/ꢂꢑꢂꢘ
ꢏꢚꢚꢃꢏꢖꢏꢘꢏꢕꢘꢂꢃꢍꢖꢃꢘꢁꢂꢃꢓ ꢕꢚꢚꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃꢘꢁꢂꢃꢌꢂꢑ ꢂꢘꢃꢌꢂ%ꢙꢂꢑꢘ
0ꢓꢕꢚꢚꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃ/6&&7ꢃꢕꢖꢐꢃ66&&713ꢃꢃ"ꢖꢃꢘꢁꢂꢃ+ꢍꢑ ꢘ
'ꢍꢐꢂ!ꢃꢕꢃꢌꢂꢑ ꢂꢘꢃꢏꢑꢃꢏꢖꢏꢘꢏꢕꢘꢂꢐꢃ <#ꢃꢑꢏꢔꢙꢚꢘꢕꢖꢂꢍꢙꢑꢚ#ꢃ ꢌꢏꢘꢏꢖꢒ
/6&&7ꢃꢕꢖꢐꢃ66&&7ꢃꢘꢍꢃꢘꢁꢂꢃꢌꢂꢒꢏꢑꢘꢂꢌ3ꢃꢃ"ꢖꢃꢂꢏꢘꢁꢂꢌꢃꢔꢍꢐꢂ!
ꢕꢃꢌꢂꢑꢂꢘꢃ ꢏꢚꢚꢃꢑꢂꢘꢃꢕꢚꢚꢃꢌꢂꢒꢏꢑꢘꢂꢌꢑꢃꢘꢍꢃꢜꢃꢕꢖꢐꢃꢑꢂꢘꢃ6&ꢅꢃꢁꢏꢒꢁ3
Read/Write Select; 0 = write, 1 =
read
LSB, first bit
0
R/W
1
2
3
4
5
6
ADD0 LSB of address, Must be 0
ADD1 Must be 0
ADD2 Must be 0
ADD3 Must be 0
ADD4 Must be 1
Serial Interface
"ꢖꢃꢘꢁꢂꢃ+ꢍꢑꢘꢃ'ꢍꢐꢂ!ꢃꢋꢏꢖꢑꢃ4ꢉꢃꢘꢁꢌꢍꢙꢒꢁꢃ4)ꢃꢑꢂꢌꢎꢂꢃꢕꢑꢃꢕ
ꢔꢏꢗꢌꢍꢋꢌꢍꢗꢂꢑꢑꢍꢌ-ꢔꢏꢗꢌꢍꢗꢍꢖꢘꢌꢍꢚꢚꢂꢌꢃꢏꢖꢘꢂꢌ ꢓꢕꢗꢂ3ꢃ&ꢖꢂ
ꢂꢏꢒꢁꢘ$<ꢏꢘꢃꢌꢂꢒꢏꢑꢘꢂꢌꢃꢗꢕꢖꢃ<ꢂꢃ ꢌꢏꢘꢘꢂꢖꢃꢘꢍꢃꢎꢏꢕꢃꢘꢁꢂꢃꢅ,"ꢃꢋꢏꢖ
ꢍꢌꢃꢌꢂꢕꢐꢃꢓꢌꢍꢔꢃꢘꢁꢂꢃꢅ,&ꢃꢋ ꢏꢖꢃꢕꢘꢃꢘꢁꢂꢃꢗꢚꢍꢗ;ꢃꢌꢕꢘꢂꢃꢐꢂꢘꢂꢌ$
ꢔꢏꢖꢂꢐꢃ<#ꢃꢅꢄ6 93ꢃꢀ ꢁꢌꢍꢙꢒꢁꢃꢘꢁꢏꢑ ꢃꢌꢂꢒꢏꢑ ꢘꢂꢌ!ꢃꢕꢃꢁꢍꢑ ꢘ
ꢗꢍꢖꢘꢌꢍꢚꢚꢂꢌꢃꢗꢕꢖꢃ<ꢂꢃꢙꢑꢂꢐꢃꢘꢍꢃꢗꢍꢖꢘꢌꢍꢚꢃꢍꢋꢂꢌꢕꢘꢏꢍꢖꢕꢚꢃꢗꢁꢕꢌ$
-
Reserved - Must be 0
Table 7. Address/Command Byte
18
DS40F3
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
ꢏꢔꢋꢂꢐꢕꢖꢗꢂꢃꢑꢘꢕꢘꢂꢃꢂꢏꢘꢁꢂꢌꢃꢕꢓꢘꢂꢌꢃ<ꢏꢘꢃ,>ꢃꢏꢑꢃꢍꢙꢘꢋꢙꢘꢃꢍꢌꢃꢕꢘ
LSB: first bit in
0
1
2
3
4
LOS Loss of Signal
DPM Driver Performance Monitor
LEN0 Bit 0 - Line Length Select
LEN1 Bit 1 - Line Length Select
LEN2 Bit 2 - Line Lenght Select
ꢘꢁꢂꢃꢂꢖꢐꢃꢍꢓꢃꢘꢁꢂꢃꢁꢍꢚꢐꢃꢋꢂꢌꢏꢍꢐꢃꢍꢓꢃꢐꢕꢘꢕꢃ<ꢏꢘꢃ,>3
ꢊꢖꢃꢕ ꢐꢐꢌꢂꢑꢑ-ꢗꢍꢔꢔꢕꢖꢐꢃ<#ꢘ ꢂ!ꢃꢑ ꢁꢍ ꢖꢃꢏ ꢖꢃꢀꢕ<ꢚꢂꢃ>!
ꢋꢌꢂꢗꢂꢐꢂꢑꢃ ꢕꢃ ꢐꢕꢘꢕꢃ ꢌꢂꢒꢏꢑꢘꢂꢌ3ꢃꢀ ꢁꢂꢃꢓ ꢏꢌꢑꢘꢃ<ꢏ ꢘꢃꢍꢓ ꢃꢘꢁꢂ ꢃ ꢕꢐ$
ꢐꢌꢂꢑꢑ-ꢗꢍꢔꢔꢕꢖꢐꢃ< #ꢘꢂꢃꢐꢂ ꢘꢂꢌꢔꢏꢖꢂꢑꢃ ꢁꢂꢘꢁꢂꢌꢃꢕ ꢃꢌ ꢂꢕꢐ
ꢍꢌꢃꢕꢃ ꢌ ꢏꢘꢂꢃꢏꢑꢃꢌꢂ%ꢙꢂꢑꢘꢂꢐ3ꢃꢀꢁꢂꢃꢖꢂ.ꢘꢃꢑꢏ.ꢃ<ꢏꢘꢑꢃꢗꢍꢖꢘꢕꢏꢖ
ꢘꢁꢂꢃꢕꢐꢐ ꢌꢂꢑꢑ3ꢃꢀꢁꢂꢃꢄꢅꢆꢇ ꢈꢉꢈꢊꢃꢌꢂꢑꢋꢍꢖꢐꢑꢃꢘꢍ ꢃꢕꢐꢐꢌꢂꢑꢑ
ꢇꢆꢃ0ꢜꢜꢇꢜꢜꢜꢜ13ꢃꢀꢁꢂꢃꢚꢕꢑꢘꢃ<ꢏꢘꢃꢏꢑꢃꢏꢒꢖꢍꢌꢂꢐ3
Table 9. Output Data Bits 0 - 4
Bits
5 6 7
Status
ꢀꢁꢂꢃꢐꢕꢘꢕꢃꢌꢂꢒꢏꢑꢘꢂꢌ!ꢃꢑꢁꢍ ꢖꢃꢏꢖꢃꢀꢕ<ꢚꢂꢃ)!ꢃꢗꢕꢖꢃ<ꢂꢃ ꢌꢏꢘ$
ꢘꢂꢖꢃ ꢘꢍꢃ ꢘꢁꢂꢃ ꢑꢂꢌꢏꢕꢚꢃꢋ ꢍꢌꢘ3ꢃ ,ꢕꢘꢕꢃꢏ ꢑꢃ ꢏꢖꢋꢙꢘꢃꢍꢖ ꢃꢘꢁ ꢂꢃꢂ ꢏꢒꢁꢘ
ꢗꢚꢍꢗ;ꢃꢗ#ꢗ ꢚꢂꢑꢃꢏ ꢔꢔꢂꢐꢏꢕꢘꢂꢚ#ꢃꢓ ꢍꢚꢚꢍ ꢏꢖꢒꢃꢘꢁ ꢂꢃꢕꢐ$
ꢐꢌꢂꢑꢑ-ꢗꢍꢔꢔꢕꢖꢐꢃ<#ꢘꢂ3ꢃ(ꢏꢘꢑ ꢃꢜꢃꢕꢖꢐꢃꢇꢃꢕꢌ ꢂꢃꢙꢑ ꢂꢐꢃꢘꢍ
ꢗꢚꢂꢕꢌꢃꢕꢖꢃꢏꢖꢘ ꢂꢌꢌꢙꢋꢘꢃꢏꢑꢑꢙꢂꢐꢃꢓꢌꢍꢔꢃꢘꢁꢂꢃ"2ꢀꢃꢋꢏꢖ!ꢃ ꢁꢏꢗꢁ
ꢍꢗꢗꢙꢌꢑꢃꢏꢖꢃꢌꢂꢑꢋꢍꢖꢑꢂꢃꢘꢍꢃꢕꢃꢚꢍꢑꢑꢃꢍꢓꢃꢑꢏꢒꢖꢕꢚꢃꢍꢌꢃꢕꢃꢋꢌꢍ<ꢚꢂꢔ
ꢏꢘꢁꢃꢘꢁꢂꢃꢍꢙꢘꢋꢙꢘꢃꢐꢌꢏꢎꢂꢌ3ꢃ"ꢓꢃ <ꢏꢘꢑꢃꢜꢃꢍꢌꢃꢇꢃꢕꢌꢂꢃꢘꢌꢙ ꢂ!ꢃꢘꢁꢂ
ꢗꢍꢌꢌꢂꢑꢋꢍꢖꢐꢏꢖꢒꢃꢏꢖꢘꢂꢌꢌꢙꢋꢘꢃꢏꢑꢃꢑꢙꢋꢋꢌꢂꢑꢑꢂꢐ3ꢃꢅꢍꢃꢏꢓꢃꢕꢃꢚꢍꢑꢑ
ꢍꢓꢃꢑꢏꢒꢖꢕꢚꢃꢏꢖꢘꢂꢌꢌꢙꢋꢘꢃꢏꢑꢃꢗꢚꢂꢕꢌꢂꢐꢃ<#ꢃ ꢌꢏꢘꢏꢖꢒꢃꢕꢃꢇꢃꢘ ꢍꢃ<ꢏꢘ
ꢜ!ꢃꢘꢁꢂꢃꢏꢖꢘꢂꢌꢌꢙꢋꢘꢃ ꢏꢚꢚꢃ<ꢂꢃꢌꢂꢂꢖꢕ<ꢚꢂꢐꢃ<#ꢃ ꢌꢏꢘꢏꢖꢒꢃꢕꢃꢜꢃꢘꢍ
<ꢏꢘꢃꢜ3ꢃꢀꢁꢏꢑꢃꢁꢍꢚꢐꢑꢃꢓꢍꢌꢃ,7'ꢃꢕꢑꢃ ꢂꢚꢚ3
Reset has occurred or no program input.
TAOS in effect.
LLOOP in effect.
TAOS/LLOOP in effect.
RLOOP in effect
DPM changed state since last "clear DPM"
occured.
LOS changed state since last "clear LOS"
occured.
ꢜ ꢜ ꢜ
ꢜ ꢜ ꢇ
ꢜ ꢇ ꢜ
ꢜ ꢇ ꢇ
ꢇ ꢜ ꢜ
ꢇ ꢜ ꢇ
ꢇ ꢇ ꢜ
ꢇ ꢇ ꢇ
LOS and DPM have changed state since
last "clear LOS" and "clear DPM".
Table 10. Coding for Serial Output Bits 5, 6, 7
LSB: first bit in
0
1
2
3
4
5
6
7
clr LOS Clear Loss of Signal
clr DPM Clear Driver Performance Monitor
LEN0 Bit 0 - Line Length Select
LEN1 Bit 1 - Line Length Select
LEN2 Bit 2 - Line Lenght Select
RLOOP Remote Loopback
FꢌꢏꢘꢏꢖꢒꢃꢕꢃCꢜCꢃꢘꢍꢃꢂꢏꢘꢁꢂꢌ ꢃCꢄꢚꢂꢕꢌꢃ6&ꢅ Cꢃꢍꢌ ꢃCꢄ ꢚꢂꢕꢌ
,7'Cꢃꢂ ꢖꢕ<ꢚꢂꢑꢃꢘ ꢁꢂꢃꢗ ꢍꢌꢌꢂꢑꢋꢍꢖꢐꢏꢖꢒꢃꢏ ꢖꢘꢂꢌꢌꢙꢋꢘꢃꢓ ꢍꢌ
6&ꢅꢃꢍꢌꢃ,7'3
LLOOP Local Loopback
TAOS Transmit All Ones Select
MSB: last bit in
&ꢙꢘꢋꢙꢘꢃꢐꢕꢘꢕꢃꢓꢌꢍꢔꢃꢘꢁꢂꢃꢑꢂꢌꢏꢕꢚꢃꢏꢖꢘꢂꢌꢓꢕꢗꢂꢃꢏꢑꢃꢋꢌꢂꢑꢂꢖꢘꢂꢐ
ꢕꢑꢃꢑꢁꢍ ꢖꢃꢏꢖꢃꢀꢕ<ꢚꢂꢑꢃ5ꢃ ꢕꢖꢐꢃꢇꢜ3ꢃ(ꢏꢘꢑꢃ4!ꢃꢉꢃ ꢕꢖꢐꢃ=ꢃ ꢗꢕꢖ
<ꢂꢃ ꢌꢂꢕꢐꢃꢘ ꢍꢃ ꢎꢂꢌꢏꢓ#ꢃꢚ ꢏꢖꢂꢃꢚꢂ ꢖꢒꢘꢁꢃꢑ ꢂꢚꢂꢗꢘꢏꢍꢖ3ꢃ (ꢏꢘꢑꢃ ꢈ!ꢃꢆ
ꢕꢖꢐꢃ>ꢃꢔꢙꢑ ꢘꢃ<ꢂꢃꢐꢂ ꢗꢍꢐꢂꢐ3ꢃꢄꢍꢐꢂꢑꢃꢇꢜꢇ!ꢃꢇꢇꢜꢃꢕꢖꢐꢃꢇꢇꢇ
0<ꢏꢘꢑꢃꢈ!ꢃꢆꢃꢕꢖ ꢐꢃ>1 ꢃꢏꢖ ꢐꢏꢗꢕꢘꢂꢃ6 &ꢅꢃꢕꢖ ꢐꢃ, 7'ꢃꢑ ꢘꢕꢘꢂ
ꢗꢁꢕꢖꢒꢂꢑ3ꢃFꢌꢏꢘꢏꢖꢒꢃꢕꢃCꢇCꢃꢘꢍꢃꢘꢁꢂꢃCꢄꢚꢂꢕꢌꢃ6&ꢅCꢃꢕꢖꢐ-ꢍꢌ
Cꢄꢚꢂꢕꢌꢃ,7'Cꢃ<ꢏꢘꢑꢃꢏꢖꢃꢘꢁꢂꢃꢌꢂꢒꢏꢑꢘꢂꢌꢃꢕꢚꢑꢍꢃꢌꢂꢑꢂꢘꢑꢃꢑꢘꢕꢘꢙꢑ
<ꢏꢘꢑꢃꢈ!ꢃꢆ!ꢃꢕꢖꢐꢃ>3ꢃ
Table 8. Input Data Register
FꢌꢏꢘꢏꢖꢒꢃꢕꢃCꢇC ꢃꢘꢍꢃꢂꢏꢘꢁꢂꢌꢃCꢄꢚꢂꢕꢌ ꢃ6 &ꢅCꢃꢍꢌ ꢃC ꢄꢚꢂꢕꢌ
,7'Cꢃꢍꢎꢂꢌꢃꢘꢁꢂꢃꢑꢂꢌꢏꢕꢚꢃꢏꢖꢘꢂꢌꢓꢕꢗꢂꢃꢁꢕꢑꢃꢘꢁꢌꢂꢂꢃꢂꢓꢓꢂꢗꢘꢑꢛ
ꢇ1ꢃꢘꢁꢂꢃꢗꢙꢌꢌꢂꢖꢘꢃꢏꢖꢘꢂꢌꢌꢙꢋꢘꢃꢍꢖꢃꢘꢁꢂꢃꢑꢂꢌꢏꢕꢚꢃꢏꢖꢘꢂꢌꢓꢕꢗꢂ
ꢏꢚꢚꢃ<ꢂꢃꢗꢚꢂꢕꢌꢂꢐ3ꢃ02ꢍꢘꢂꢃꢘꢁꢕꢘꢃꢑꢏꢔꢋꢚ#ꢃꢌꢂꢕꢐꢏꢖꢒꢃꢘꢁꢂ
ꢌꢂꢒꢏꢑꢘꢂꢌꢃ<ꢏꢘꢑꢃ ꢏꢚꢚꢃꢖꢍꢘꢃꢗꢚꢂꢕꢌꢃꢘꢁꢂꢃꢏꢖꢘꢂꢌꢌꢙꢋꢘ1!
ꢅ,&ꢃꢒꢍꢂꢑꢃꢘꢍꢃꢕꢃꢁꢏ ꢒꢁꢃꢏꢔꢋꢂꢐꢕꢖꢗꢂꢃꢑꢘꢕꢘꢂꢃ ꢁꢂꢖꢃꢖꢍꢘꢃꢏꢖ
ꢙꢑꢂ3ꢃꢅ,&ꢃꢕꢖꢐꢃꢅ,"ꢃ ꢔꢕ#ꢃ<ꢂꢃꢘꢏꢂꢐꢃꢘꢍꢒꢂꢘꢁꢂꢌꢃꢏꢖꢃꢕꢋꢋꢚꢏ$
ꢗꢕꢘꢏꢍꢖꢑꢃ ꢁꢂꢌꢂꢃꢘ ꢁꢂꢃ ꢁꢍꢑꢘꢃꢋ ꢌꢍꢗꢂꢑꢑꢍꢌꢃ ꢁꢕꢑꢃ ꢕ
<ꢏꢐꢏꢌꢂꢗꢘꢏꢍꢖꢕꢚꢃ"-&ꢃꢋꢍꢌꢘ3
41ꢃꢍꢙꢘꢋꢙꢘꢃꢐꢕꢘꢕꢃ<ꢏꢘꢑꢃꢈ!ꢃꢆꢃꢕ ꢖꢐꢃ>ꢃ ꢏꢚꢚꢃ<ꢂꢃꢌꢂꢑꢂꢘꢃꢕꢑ
ꢕꢋꢋꢌꢍꢋꢌꢏꢕꢘꢂ!
ꢉ1ꢃꢓꢙꢘꢙꢌꢂꢃꢏꢖꢘꢂꢌꢌꢙꢋꢘꢑꢃꢓꢍꢌꢃꢘꢁꢂꢃꢗꢍꢌꢌꢂꢑꢋꢍꢖꢐꢏꢖꢒꢃ6&ꢅ
ꢍꢌꢃ,7'ꢃ ꢏꢚꢚꢃ<ꢂꢃꢋꢌꢂꢎꢂꢖꢘꢂꢐꢃꢓꢌꢍꢔꢃꢍꢗꢗꢙꢌꢏꢖꢒ13
DS40F3
19
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
Power Supply
ꢀꢁꢂꢃꢐꢂꢎꢏꢗꢂꢃꢍꢋꢂꢌꢕꢘꢂꢑꢃꢓꢌꢍꢔꢃꢕꢃꢑꢏꢖꢒꢚꢂꢃMꢈꢃLꢍꢚꢘꢃꢑꢙꢋꢋꢚ#3
ꢅꢂꢋꢕꢌꢕꢘꢂꢃꢋꢏ ꢖꢑꢃꢓ ꢍꢌꢃꢘꢌ ꢕꢖꢑꢔꢏꢘꢃꢕꢖ ꢐꢃꢌ ꢂꢗꢂꢏꢎꢂꢃꢑ ꢙꢋꢋꢚꢏꢂꢑ
ꢋꢌꢍꢎꢏꢐꢂꢃꢏꢖ ꢘꢂꢌꢖꢕꢚꢃꢏ ꢑꢍꢚꢕꢘꢏꢍꢖ3ꢃꢀ ꢁꢂꢑꢂꢃꢋꢏ ꢖꢑꢃ ꢑꢁꢍꢙꢚꢐꢃ <ꢂ
ꢗꢍꢖꢖꢂꢗꢘꢂꢐꢃꢂ.ꢘ ꢂꢌꢖꢕꢚꢚ#ꢃꢖꢂꢕꢌꢃꢘꢁ ꢂꢃꢐꢂꢎ ꢏꢗꢂꢃꢕꢖꢐꢃꢐꢂꢗꢍꢙ$
ꢋꢚꢂꢐꢃ ꢘꢍꢃ ꢘꢁꢂꢏꢌꢃꢌꢂ ꢑꢋꢂꢗꢘꢏꢎꢂꢃꢒꢌꢍ ꢙꢖꢐꢑ3ꢃꢀ LMꢃ ꢔꢙꢑꢘꢃꢖꢍ ꢘ
ꢂ.ꢗꢂꢂꢐꢃ/LMꢃ<#ꢃꢔꢍꢌꢂꢃꢘꢁꢕꢖꢃꢜ3ꢉL3
,ꢂꢗꢍꢙꢋꢚꢏꢖꢒꢃꢕꢖꢐꢃꢓꢏꢚꢘꢂꢌꢏꢖꢒꢃꢍꢓꢃꢘꢁꢂꢃꢋꢍ ꢂꢌꢃꢑꢙꢋꢋꢚꢏꢂꢑꢃꢏꢑ
ꢗꢌꢙꢗꢏꢕꢚꢃꢓꢍꢌꢃꢘꢁꢂ ꢃꢋꢌꢍꢋꢂꢌꢃꢍꢋꢂꢌꢕꢘꢏꢍꢖꢃꢍꢓꢃꢘꢁꢂ ꢃꢕꢖꢕꢚꢍꢒꢃꢗꢏꢌ$
ꢗꢙꢏꢘꢑꢃꢏꢖꢃ<ꢍꢘꢁꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢃꢕꢖꢐꢃꢌꢂꢗꢂꢏꢎꢂꢃꢋꢕꢘꢁꢑ3ꢃꢊꢃꢇ3ꢜ
μ?ꢃ ꢗꢕꢋꢕꢗꢏꢘꢍꢌꢃ ꢑꢁꢍꢙꢚꢐꢃ< ꢂꢃꢗ ꢍꢖꢖꢂꢗꢘꢂꢐꢃ <ꢂꢘ ꢂꢂꢖꢃꢀ LM
ꢕꢖꢐꢃꢀ82,!ꢃꢕꢖꢐꢃꢕꢃꢜ3ꢇꢃμ?ꢃꢗꢕꢋꢕꢗꢏꢘꢍꢌꢃꢑꢁꢍꢙꢚꢐꢃ<ꢂꢃꢗꢍꢖ$
ꢖꢂꢗꢘꢂꢐꢃ<ꢂꢘ ꢂꢂꢖꢃ /LMꢃꢕꢖꢐ ꢃ /82,3ꢃHꢑꢂꢃꢔ #ꢚꢕꢌꢃꢍꢌ
ꢗꢂꢌꢕꢔꢏꢗꢃꢗ ꢕꢋꢕꢗꢏꢘꢍꢌꢑꢃꢕꢖꢐ ꢃꢋꢚꢕ ꢗꢂꢃꢘ ꢁꢂꢔꢃꢕꢑ ꢃꢗꢚꢍ ꢑꢂꢚ#ꢃꢕꢑ
ꢋꢍꢑꢑꢏ<ꢚꢂꢃꢘꢍꢃꢘꢁꢂꢏꢌꢃꢌꢂꢑꢋꢂꢗꢘꢏꢎꢂꢃꢋꢍ ꢂꢌꢃꢑꢙꢋꢋꢚ#ꢃꢋꢏꢖꢑ3ꢃꢊ
ꢆ)ꢃμ?ꢃꢘꢕ ꢖꢘꢕꢚꢙꢔꢃꢗꢕ ꢋꢕꢗꢏꢘꢍꢌꢃꢑꢁꢍꢙꢚꢐꢃ<ꢂꢃꢕꢐꢐ ꢂꢐꢃꢗꢚ ꢍꢑꢂ
ꢘꢍꢃꢘ ꢁꢂꢃ/LM-/82,ꢃꢑ ꢙꢋꢋꢚ#3ꢃFꢏꢌꢂꢃ ꢌ ꢕꢋꢃ<ꢌ ꢂꢕꢐ$
<ꢍꢕꢌꢐꢏꢖꢒꢃꢍꢓꢃꢘꢁꢂꢃꢚꢏꢖꢂꢃꢏꢖꢘꢂꢌꢓꢕꢗꢂꢃꢏꢑꢃꢖꢍꢘꢃꢌꢂꢗꢍꢔꢔꢂꢖꢐꢂꢐ
<ꢂꢗꢕꢙꢑꢂꢃꢚ ꢂꢕꢐꢃꢌ ꢂꢑꢏꢑꢘꢕꢖꢗꢂꢃꢕ ꢖꢐꢃ ꢏꢖꢐꢙꢗꢘꢕꢖꢗꢂꢃꢑ ꢂꢌꢎꢂꢃꢘ ꢍ
ꢐꢂꢓꢂꢕꢘꢃꢘꢁꢂꢃꢓꢙꢖꢗꢘꢏꢍꢖꢃꢍꢓꢃꢘꢁꢂꢃꢐꢂꢗꢍꢙꢋꢚꢏꢖꢒꢃꢗꢕꢋꢕꢗꢏꢘꢍꢌꢑ3
20
DS40F3
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
ꢀꢁꢂꢃꢄꢁꢂꢅꢆꢇꢈꢃꢅꢆꢉꢊꢋꢈꢌꢍ
ACLKI
TCLK
TPOS
TAOS
LLOOP
RLOOP
LEN2
LEN1
LEN0
RGND
RV+
TNEG
MODE
RNEG
RPOS
RCLK
XTALIN
XTALOUT
DPM
4
3
2
1
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25
24
23
22
21
20
19
5
6
7
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view
8
9
10
11
RRING
RTIP
12 13 14 15 16 17 18
LOS
MRING
MTIP
TTIP
TGND
TRING
TV+
DS40F3
21
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
ꢎꢏꢍꢅꢋꢃꢅꢃꢆꢀꢁꢂꢃꢄꢁꢂꢅꢆꢇꢈꢃꢅꢆꢉꢊꢋꢈꢌꢍ
ACLKI
TCLK
TAOS
LLOOP
RLOOP
LEN2
LEN1
LEN0
RGND
RV+
TDATA
TCODE
MODE
BPV
4
3
2
1
28 27 26
25
24
23
22
21
20
19
5
6
RDATA
RCLK
XTALIN
XTALOUT
AIS
7
top
view
8
9
10
11
RRING
RTIP
12 13 14 15 16 17 18
LOS
PCS
TTIP
RCODE
TRING
TV+
TGND
22
DS40F3
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
ꢀꢈꢐꢍꢆꢇꢈꢃꢅꢆꢉꢊꢋꢈꢌꢍ
ACLKI
TCLK
TPOS
CLKE
SCLK
CS
TNEG
MODE
RNEG
RPOS
RCLK
XTALIN
XTALOUT
DPM
SDO
SDI
4
3
2
1
28 27 26
25
24
23
22
21
20
19
5
6
INT
7
top
view
8
RGND
RV+
9
10
11
RRING
RTIP
MRING
MTIP
TRING
TV+
12 13 14 15 16 17 18
LOS
TTIP
TGND
DS40F3
23
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
Power Supplies
RGND - Ground, Pin 22.
7ꢍ ꢂꢌꢃꢑꢙꢋꢋꢚ#ꢃꢒꢌꢍꢙꢖꢐꢃꢓꢍꢌꢃꢕꢚꢚꢃꢑꢙ<ꢗꢏꢌꢗꢙꢏꢘꢑꢃꢂ.ꢗꢂꢋꢘꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢃꢐꢌꢏꢎꢂꢌIꢃꢘ#ꢋꢏꢗꢕꢚꢚ#ꢃꢜꢃLꢍꢚꢘꢑ3
RV+ - Power Supply, Pin 21.
7ꢍ ꢂꢌꢃꢑꢙꢋꢋꢚ#ꢃꢓꢍꢌꢃꢕꢚꢚꢃꢑꢙ<ꢗꢏꢌꢗꢙꢏꢘꢑꢃꢂ.ꢗꢂꢋꢘꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢃꢐꢌꢏꢎꢂꢌIꢃꢘ#ꢋꢏꢗꢕꢚꢚ#ꢃMꢈꢃLꢍꢚꢘꢑ3
TGND - Ground, Transmit Driver, Pin 14.
7ꢍ ꢂꢌꢃꢑꢙꢋꢋꢚ#ꢃꢒꢌꢍꢙꢖꢐꢃꢓꢍꢌꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢃꢐꢌꢏꢎꢂꢌIꢃꢘ#ꢋꢏꢗꢕꢚꢚ#ꢃꢜꢃLꢍꢚꢘꢑ3
TV+ - Power Supply, Transmit Driver, Pin 15.
7ꢍ ꢂꢌꢃꢑꢙꢋꢋꢚ#ꢃꢓꢍꢌꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢃꢐꢌꢏꢎꢂꢌIꢃꢘ#ꢋꢏꢗꢕꢚꢚ#ꢃMꢈꢃLꢍꢚꢘꢑ3ꢃꢀLMꢃꢔꢙꢑꢘꢃꢖꢍꢘꢃꢂ.ꢗꢂꢂꢐꢃ/LMꢃ<#ꢃꢔꢍꢌꢂꢃꢘꢁꢕꢖ
ꢜ3ꢉꢃL3
Oscillator
XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10.
ꢊꢃꢆ3ꢇ>ꢆꢃ'+Dꢃ0ꢍꢌꢃ)3ꢇ54ꢃ'+D1ꢃꢗꢌ#ꢑꢘꢕꢚꢃꢑꢁꢍꢙꢚꢐꢃ<ꢂꢃꢗꢍꢖꢖꢂꢗꢘꢂꢐꢃꢕꢗꢌꢍꢑꢑꢃꢘꢁꢂꢑꢂꢃꢋꢏꢖꢑ3ꢃꢃ"ꢓꢃꢕꢃꢇ3ꢈ==ꢃ'+Dꢃ0ꢍꢌ
43ꢜ=)ꢃ'+D1ꢃꢗꢚ ꢍꢗ;ꢃꢏꢑꢃꢋꢌꢍꢎꢏꢐꢂꢐꢃꢍꢖꢃꢊꢄ69"ꢃ0ꢋꢏꢖꢃꢇ1!ꢃꢘꢁꢂꢃ@ꢏꢘꢘꢂꢌꢃꢕꢘꢘꢂꢖꢙꢕꢘꢍꢌꢃꢔꢕ#ꢃ<ꢂ ꢃꢐꢏꢑꢕ<ꢚꢂꢐꢃ<#ꢃꢘ#ꢏꢖꢒ
Bꢀꢊ6"2!ꢃ7ꢏꢖꢃ5ꢃꢘꢍꢃ/LMꢃꢘꢁꢌꢍꢙꢒꢁꢃꢕꢃꢇꢃ;Ωꢃꢌꢂꢑꢏꢑꢘꢍꢌ!ꢃꢕꢖꢐꢃꢓꢚꢍꢕꢘꢏꢖꢒꢃBꢀꢊ6&Hꢀ!ꢃ7ꢏꢖꢃꢇꢜ3
&ꢎꢂꢌꢐꢌꢏꢎꢏꢖꢒꢃꢘꢁꢂꢃꢍꢑꢗꢏꢚꢚꢕꢘꢍꢌꢃ ꢏꢘꢁꢃꢕꢖꢃꢂ.ꢘꢂꢌꢖꢕꢚꢃꢗꢚꢍꢗ;ꢃꢏꢑꢃꢖꢍꢘꢃꢑꢙꢋꢋꢍꢌꢘꢂꢐ3 See Appendix A for crystal
specifications.
Control
ACLKI - Alternate External Clock Input, Pin 1.
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊꢃꢐꢍꢂꢑꢃꢖꢍꢘꢃꢌꢂ%ꢙꢏꢌꢂꢃꢕꢃꢗꢚꢍꢗ;ꢃꢑꢏꢒꢖꢕꢚꢃꢘꢍꢃ<ꢂꢃꢏꢖꢋꢙꢘꢃꢍꢖꢃꢊꢄ69"ꢃ ꢁꢂꢖꢃꢕꢃꢗꢌ#ꢑꢘꢕꢚꢃꢏꢑꢃꢗꢍꢖꢖꢂꢗꢘꢂꢐ
<ꢂꢘ ꢂꢂꢖꢃꢋꢏꢖꢑꢃ5ꢃꢕꢖꢐꢃꢇꢜ3ꢃ"ꢓꢃꢕ ꢃꢗꢚꢍꢗ;ꢃꢏꢑꢃꢖꢍꢘꢃꢋꢌꢍꢎꢏꢐꢂꢐꢃꢍꢖꢃꢊꢄ 69"!ꢃꢘꢁꢏꢑꢃꢏꢖꢋꢙꢘꢃꢔꢙꢑꢘꢃ<ꢂꢃꢒꢌꢍꢙꢖꢐꢂꢐ3ꢃ"ꢓ
ꢊꢄ69"ꢃꢏꢑꢃꢒꢌꢍꢙꢖꢐꢂꢐ!ꢃꢘꢁꢂꢃꢍꢑꢗꢏꢚꢚꢕꢘꢍꢌꢃꢏꢖꢃꢘꢁꢂꢃ@ꢏꢘꢘꢂꢌꢃꢕꢘꢘꢂꢖꢙꢕꢘꢍꢌꢃꢏꢑꢃꢙꢑꢂꢐꢃꢘꢍꢃꢗꢕꢚꢏ<ꢌꢕꢘꢂꢃꢘꢁꢂꢃꢗꢚꢍꢗ;ꢃꢌꢂꢗꢍꢎꢂꢌ#
ꢗꢏꢌꢗꢙꢏꢘꢃꢕꢖꢐꢃꢀꢊ&ꢅꢃꢏꢑꢃꢖꢍꢘꢃꢕꢎꢕꢏꢚꢕ<ꢚꢂ3
CLKE - Clock Edge, Pin 28. (Host Mode)
ꢅꢂꢘꢘꢏꢖꢒꢃꢄ69:ꢃꢘꢍꢃꢚꢍꢒ ꢏꢗꢃꢇꢃꢗꢕꢙꢑꢂꢑꢃ/7&ꢅꢃꢕꢖꢐꢃ/2:8ꢃꢘꢍꢃ<ꢂꢃꢎꢕꢚ ꢏꢐꢃꢍꢖꢃꢘꢁꢂ ꢃꢓꢕꢚꢚꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃ/ꢄ69!ꢃꢕꢖꢐ
ꢅ,&ꢃꢘꢍꢃ<ꢂꢃꢎꢕꢚꢏꢐꢃꢍꢖꢃꢘꢁꢂꢃꢌꢏꢑꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃꢅꢄ693ꢃꢄꢍꢖꢎꢂꢌꢑꢂꢚ#!ꢃꢑꢂꢘꢘꢏꢖꢒꢃꢄ69:ꢃꢘꢍꢃꢚꢍꢒꢏꢗꢃꢜꢃꢗꢕꢙꢑꢂꢑꢃ/7&ꢅ
ꢕꢖꢐꢃ/2:8ꢃꢘꢍꢃ<ꢂꢃꢎꢕꢚ ꢏꢐꢃꢍꢖꢃꢘꢁꢂ ꢃꢌꢏꢑꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃ/ꢄ69!ꢃꢕꢖꢐꢃꢅ,&ꢃꢘꢍꢃ<ꢂꢃꢎꢕꢚ ꢏꢐꢃꢍꢖꢃ ꢘꢁꢂꢃꢓꢕꢚꢚꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓ
ꢅꢄ693
CS - Chip Select, Pin 26. (Host Mode)
ꢀꢁꢏꢑꢃꢋꢏꢖꢃꢔꢙꢑꢘꢃꢘꢌꢕꢖꢑꢏꢘꢏꢍꢖꢃꢓꢌꢍꢔꢃꢁꢏꢒꢁꢃꢘꢍꢃꢚꢍ ꢃꢘꢍꢃꢌꢂꢕꢐꢃꢍꢌꢃ ꢌꢏꢘꢂꢃꢘꢁꢂꢃꢑꢂꢌꢏꢕꢚꢃꢋꢍꢌꢘ3
INT - Receive Alarm Interrupt, Pin 23. (Host Mode)
8ꢍꢂꢑꢃꢚꢍ ꢃ ꢁꢂꢖꢃ6&ꢅꢃꢍꢌꢃ,7'ꢃꢗꢁꢕ ꢖꢒꢂꢃꢑꢘꢕꢘꢂꢃꢘꢍꢃꢓꢚꢕꢒꢃꢘꢁꢂꢃꢁꢍꢑꢘꢃꢋꢌꢍꢗꢂꢑꢑꢍꢌ3ꢃ"2ꢀꢃꢏꢑꢃꢗꢚꢂꢕꢌꢂꢐꢃ<#ꢃ ꢌꢏꢘꢏꢖꢒ
Cꢄꢚꢂꢕꢌꢃ6&ꢅCꢃꢍꢌꢃCꢄꢚꢂꢕꢌꢃ,7'Cꢃꢘꢍꢃꢘꢁꢂꢃꢌꢂꢒꢏꢑꢘꢂꢌ3ꢃ"2ꢀꢃꢏꢑꢃꢕꢖꢃꢍ ꢋꢂꢖꢃꢐꢌꢕꢏꢖꢃꢍꢙꢘꢋꢙꢘꢃꢕꢖꢐꢃꢑꢁꢍꢙꢚꢐꢃ<ꢂꢃꢘꢏꢂꢐꢃꢘꢍ
ꢘꢁꢂꢃꢋꢍ ꢂꢌꢃꢑꢙꢋꢋꢚ#ꢃꢘꢁꢌꢍꢙꢒꢁꢃꢕꢃꢌꢂꢑꢏꢑꢘꢍꢌ3
24
DS40F3
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended
Hardware Modes)
,ꢂꢘꢂꢌꢔꢏꢖꢂꢑꢃꢘꢁꢂꢃꢑꢁꢕꢋꢂꢃꢕꢖꢐꢃꢕꢔꢋꢚꢏꢘꢙꢐꢂꢃꢍꢓꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢐꢃꢋꢙꢚꢑꢂꢃꢘꢍꢃꢕꢗꢗꢍꢔꢔꢍꢐꢕꢘꢂꢃꢑꢂꢎꢂꢌꢕꢚꢃꢗꢕ<ꢚꢂꢃꢘ#ꢋꢂꢑ
ꢕꢖꢐꢃꢚꢂꢖ ꢒꢘꢁꢑ3ꢃꢅꢂꢂꢃꢀ ꢕ<ꢚꢂꢃꢉꢃꢓꢍꢌꢃꢏꢖꢓꢍ ꢌꢔꢕꢘꢏꢍꢖꢃꢍꢖꢃꢚꢏꢖ ꢂꢃ ꢚꢂꢖꢒꢘꢁꢃꢑ ꢂꢚꢂꢗꢘꢏꢍꢖ3ꢃ ꢊꢚꢑꢍꢃꢗꢍꢖ ꢘꢌꢍꢚꢑꢃꢘꢁꢂ ꢃ ꢌꢂꢗꢂꢏꢎꢂꢌ
ꢑꢚꢏꢗꢏꢖꢒꢃꢚꢂꢎꢂꢚꢃꢕꢖꢐꢃꢘꢁꢂꢃꢚꢏꢖꢂꢃꢗꢍꢐꢂꢃꢏꢖꢃ:.ꢘꢂꢖꢐꢂꢐꢃ+ꢕꢌꢐ ꢕꢌꢂꢃ'ꢍꢐꢂ3
LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes)
ꢅꢂꢘꢘꢏꢖꢒꢃ66&&7ꢃꢘꢍꢃꢕ ꢃꢚꢍꢒꢏꢗꢃꢇꢃꢌꢍꢙꢘꢂꢑꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢃꢗꢚꢍꢗ;ꢃꢕꢖꢐꢃꢐꢕꢘꢕꢃꢘꢁꢌꢍꢙꢒꢁꢃꢘꢍꢃꢘ ꢁꢂꢃꢌꢂꢗꢂꢏꢎꢂꢃꢗꢚꢍꢗ;ꢃꢕꢖꢐ
ꢐꢕꢘꢕꢃꢋꢏꢖꢑ3ꢃꢀ7&ꢅ-ꢀ2:8ꢃ0ꢍꢌꢃꢀ,ꢊꢀꢊ1ꢃꢕꢌꢂꢃꢑꢘꢏꢚꢚꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢐꢃꢙꢖꢚꢂꢑꢑꢃꢍꢎꢂꢌꢌꢏꢐꢐꢂꢖꢃ<#ꢃꢕꢃꢀꢊ&ꢅꢃꢌꢂ%ꢙꢂꢑꢘ3
"ꢖꢋꢙꢘꢑꢃꢍꢖꢃ/ꢀ"7ꢃꢕꢖꢐꢃ//"28ꢃꢕꢌꢂꢃꢏꢒꢖꢍꢌꢂꢐ3
MODE - Mode Select, Pin 5.
,ꢌꢏꢎꢏꢖꢒꢃꢘ ꢁꢂꢃ '&,:ꢃꢋ ꢏꢖꢃ ꢁꢏꢒꢁꢃꢋ ꢙꢘꢑꢃꢘ ꢁꢂꢃ ꢄꢅꢆꢇꢈꢉꢈꢊꢃꢚꢏ ꢖꢂꢃ ꢏꢖꢘꢂꢌꢓꢕꢗꢂꢃꢏ ꢖꢃꢘ ꢁꢂꢃ +ꢍꢑꢘꢃ'ꢍ ꢐꢂ3ꢃ"ꢖ ꢃꢘꢁ ꢂꢃꢁ ꢍꢑꢘ
ꢔꢍꢐꢂ!ꢃꢕꢃꢑꢂꢌꢏꢕꢚꢃꢗꢍꢖꢘꢌꢍꢚꢃꢋꢍꢌꢘꢃꢏꢑꢃꢙꢑꢂꢐꢃꢘꢍꢃꢗꢍꢖꢘꢌꢍꢚꢃꢘꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊꢃꢚꢏꢖꢂꢃꢏꢖꢘꢂꢌꢓꢕꢗꢂꢃꢕꢖꢐꢃꢐꢂꢘꢂꢌꢔꢏꢖꢂꢃꢏꢘꢑꢃꢑꢘꢕꢘꢙꢑ3
8ꢌꢍꢙꢖꢐꢏꢖꢒꢃꢘꢁꢂ ꢃ'& ,:ꢃꢋꢏꢖ ꢃꢋꢙꢘ ꢑꢃꢘꢁꢂ ꢃꢄꢅ ꢆꢇꢈꢉꢈꢊꢃꢚꢏ ꢖꢂꢃꢏ ꢖꢘꢂꢌꢓꢕꢗꢂꢃꢏꢖ ꢃꢘꢁꢂ ꢃ+ꢕ ꢌꢐ ꢕꢌꢂꢃ' ꢍꢐꢂ!ꢃ ꢁꢂꢌꢂ
ꢗꢍꢖꢓꢏꢒꢙꢌꢕꢘꢏꢍꢖꢃꢕꢖꢐꢃꢑꢘꢕꢘꢙꢑꢃꢕꢌꢂꢃꢗꢍꢖꢘꢌꢍꢚꢚꢂꢐꢃ<#ꢃꢐꢏꢑꢗꢌꢂꢘꢂꢃꢋꢏꢖꢑ3ꢃ?ꢚꢍꢕꢘꢏꢖꢒꢃꢘꢁꢂꢃ'&,:ꢃꢋꢏꢖꢃꢍꢌꢃꢐꢌꢏꢎꢏꢖꢒꢃꢏꢘꢃꢘꢍ
M43ꢈꢃL ꢃꢋꢙ ꢘꢑꢃꢘꢁ ꢂꢃꢄ ꢅꢆꢇꢈꢉꢈꢊꢃ ꢏꢖꢃ :.ꢘꢂꢖꢐꢂꢐꢃ+ꢕꢌ ꢐ ꢕꢌꢂꢃ'ꢍ ꢐꢂ!ꢃ ꢁꢂ ꢌꢂꢃꢗꢍ ꢖꢓꢏꢒꢙꢌꢕꢘꢏꢍꢖꢃꢕꢖꢐ ꢃꢑꢘ ꢕꢘꢙꢑꢃꢕ ꢌꢂ
ꢗꢍꢖꢘꢌꢍꢚꢚꢂꢐꢃ<#ꢃꢐꢏ ꢑꢗꢌꢂꢘꢂꢃꢋꢏꢖꢑ3ꢃFꢁꢂꢖꢃꢓꢚꢍꢕꢘꢏꢖꢒꢃ'&,:!ꢃꢘꢁꢂꢌꢂꢃꢑꢁꢍꢙꢚꢐꢃ<ꢂꢃꢖꢍꢃꢂ.ꢘ ꢂꢌꢖꢕꢚꢃꢚꢍꢕꢐꢃꢍꢖꢃꢘꢁꢂꢃꢋꢏꢖ3
'&,:ꢃꢐꢂꢓꢏꢖꢂꢑꢃꢘꢁꢂꢃꢑꢘꢕꢘꢙꢑꢃꢍꢓꢃꢇꢉꢃꢋꢏꢖꢑꢃ0ꢑꢂꢂꢃꢀꢕ<ꢚꢂꢃ413
PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode)
ꢅꢂꢘꢘꢏꢖꢒꢃ7ꢄꢅꢃꢁ ꢏꢒꢁꢃꢗꢕꢙ ꢑꢂꢑꢃꢘ ꢁꢂꢃꢄ ꢅꢆꢇꢈꢉꢈꢊꢃꢚ ꢏꢖꢂꢃꢏꢖꢘ ꢂꢌꢓꢕꢗꢂꢃꢘꢍ ꢃꢏꢒꢖ ꢍꢌꢂꢃꢘ ꢁꢂꢃꢀꢄ&,:!ꢃ/ꢄ&,:!ꢃ6:2ꢜ!
6:2ꢇ!ꢃ6:24!ꢃ/6&&7!ꢃ66&&7ꢃꢕꢖꢐꢃꢀꢊ&ꢅꢃꢏꢖꢋꢙꢘꢑ3ꢃ
RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode)
ꢅꢂꢘꢘꢏꢖꢒꢃ/ꢄ&,:ꢃꢚꢍ ꢃꢂꢖꢕ<ꢚꢂꢑꢃ()*ꢅꢃꢍꢌꢃ+,( ꢉꢃDꢂꢌꢍꢃꢑꢙ<ꢑꢘꢏꢘꢙꢘꢏꢍꢖꢃꢏꢖꢃꢘ ꢁꢂꢃꢌꢂꢗꢂꢏꢎꢂꢌꢃꢐꢂꢗꢍꢐꢂꢌ3ꢃꢅꢂꢘꢘꢏꢖꢒ
/ꢄ&,:ꢃꢁꢏꢒꢁꢃꢂꢖꢕ<ꢚꢂꢑꢃꢘꢁꢂꢃꢊ'"ꢃꢌꢂꢗꢂꢏꢎꢂꢌꢃꢐꢂꢗꢍꢐꢂꢌꢃ0ꢑꢂꢂꢃꢀꢕ<ꢚꢂꢃ)13
RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes)
ꢅꢂꢘꢘꢏꢖꢒꢃ/6 &&7ꢃꢘꢍꢃꢕꢃꢚꢍ ꢒꢏꢗꢃꢇꢃꢗꢕꢙꢑꢂꢑꢃꢘꢁꢂ ꢃꢌꢂꢗꢍꢎꢂꢌꢂꢐꢃꢗꢚꢍꢗ;ꢃꢕꢖꢐ ꢃꢐꢕꢘꢕꢃꢘꢍꢃ<ꢂꢃꢑ ꢂꢖꢘꢃꢘꢁꢌꢍ ꢙꢒꢁꢃꢘꢁꢂꢃ@ꢏꢘꢘꢂꢌ
ꢕꢘꢘꢂꢖꢙꢕꢘꢍꢌꢃ0ꢏꢓꢃꢕꢗꢘꢏꢎꢂ1ꢃꢕꢖꢐꢃꢘꢁꢌꢍꢙꢒꢁꢃꢘꢁꢂꢃꢐꢌꢏꢎꢂꢌꢃ<ꢕꢗ;ꢃꢘꢍꢃꢘꢁꢂꢃꢚꢏꢖꢂ3ꢃꢀꢁꢂꢃꢌꢂꢗꢍꢎꢂꢌꢂꢐꢃꢑꢏꢒꢖꢕꢚꢃꢏꢑꢃꢕꢚꢑꢍꢃꢑꢂꢖꢘꢃꢘꢍ
/ꢄ69ꢃꢕꢖꢐꢃ/7&ꢅ-/2:8ꢃ0ꢍꢌꢃ/,ꢊꢀꢊ13ꢃꢊꢖ#ꢃꢀꢊ&ꢅꢃꢌꢂ%ꢙꢂꢑꢘꢃꢏꢑꢃꢏꢒꢖꢍꢌꢂꢐ3
ꢅꢏꢔꢙꢚꢘꢕꢖꢂꢍꢙꢑꢚ#ꢃꢘꢕ;ꢏꢖꢒꢃ/6&&7ꢃꢕꢖꢐꢃ66&&7ꢃꢁꢏꢒꢁꢃꢓꢍꢌꢃꢕꢘꢃꢚꢂꢕꢑꢘꢃ4ꢜꢜꢃꢖꢑꢃꢏꢖꢏꢘꢏꢕꢘꢂꢑꢃꢕꢃꢐꢂꢎꢏꢗꢂꢃꢌꢂꢑꢂꢘ3
SCLK - Serial Clock, Pin 27. (Host Mode)
ꢄꢚꢍꢗ;ꢃꢙꢑꢂꢐꢃꢘꢍꢃꢌꢂꢕꢐꢃꢍꢌꢃ ꢌꢏꢘꢂꢃꢘꢁꢂꢃꢑꢂꢌꢏꢕꢚꢃꢋꢍꢌꢘꢃꢌꢂꢒꢏꢑꢘꢂꢌꢑ3ꢃꢅꢄ69ꢃꢗꢕꢖꢃ<ꢂꢃꢂꢏꢘꢁꢂꢌꢃꢁꢏꢒꢁꢃꢍꢌꢃꢚꢍ ꢃ ꢁꢂꢖꢃꢘꢁꢂꢃꢚꢏꢖꢂ
ꢏꢖꢘꢂꢌꢓꢕꢗꢂꢃꢏꢑꢃꢑꢂꢚꢂꢗꢘꢂꢐꢃꢙꢑꢏꢖꢒꢃꢘꢁꢂꢃꢄꢅꢃꢋꢏꢖ3
SDI - Serial Data Input, Pin 24. (Host Mode)
,ꢕꢘꢕꢃꢓꢍꢌꢃꢘꢁꢂꢃꢍꢖ$ꢗꢁꢏꢋꢃꢌꢂꢒꢏꢑꢘꢂꢌ3ꢃꢅꢕꢔꢋꢚꢂꢐꢃꢍꢖꢃꢘꢁꢂꢃꢌꢏꢑꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃꢅꢄ693
SDO - Serial Data Output, Pin 25. (Host Mode)
ꢅꢘꢕꢘꢙꢑꢃꢕꢖꢐꢃꢗꢍꢖꢘꢌꢍꢚꢃꢏꢖꢓꢍꢌꢔꢕꢘꢏꢍꢖꢃꢓꢌꢍꢔꢃ ꢘꢁꢂꢃꢍꢖ$ꢗꢁꢏꢋꢃꢌꢂꢒꢏꢑꢘꢂꢌ3ꢃ"ꢓꢃꢄ69:ꢃꢏꢑꢃꢁꢏꢒꢁꢃꢅ,&ꢃꢏꢑ ꢃꢎꢕꢚꢏꢐꢃꢍꢖꢃꢘꢁ ꢂ
ꢌꢏꢑꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃꢅꢄ693ꢃ"ꢓꢃꢄ69:ꢃꢏꢑꢃꢚꢍ ꢃꢅ,&ꢃꢏꢑꢃꢎꢕꢚꢏꢐꢃꢍꢖꢃꢘꢁꢂꢃꢓꢕꢚꢚꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃꢅꢄ693ꢃꢀꢁꢏꢑꢃꢋꢏꢖꢃꢒꢍꢂꢑꢃꢘꢍ
ꢕꢃꢁꢏꢒꢁ$ꢏꢔꢋꢂꢐꢕꢖꢗꢂꢃꢑꢘꢕꢘꢂꢃ ꢁꢂꢖꢃꢘꢁꢂꢃꢑꢂꢌꢏꢕꢚꢃꢋꢍꢌꢘꢃꢏꢑꢃ<ꢂꢏꢖꢒꢃ ꢌꢏꢘꢘꢂꢖꢃꢘꢍꢃꢍꢌꢃꢕꢓꢘꢂꢌꢃ<ꢏꢘꢃ,>ꢃꢏꢑꢃꢍꢙꢘꢋꢙꢘ3
DS40F3
25
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes)
ꢅꢂꢘꢘꢏꢖꢒꢃꢀꢊ&ꢅꢃꢘꢍꢃꢕꢃꢚꢍꢒꢏꢗꢃꢇꢃꢗꢕꢙꢑꢂꢑꢃꢗꢍꢖꢘꢏꢖꢙꢍꢙꢑꢃꢍꢖꢂꢑꢃꢘꢍꢃ<ꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢐꢃꢕꢘꢃꢘꢁꢂꢃꢓꢌꢂ%ꢙꢂꢖꢗ#ꢃꢐꢂꢘꢂꢌꢔꢏꢖꢂꢐ
<#ꢃꢊꢄ69"3
TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode)
ꢅꢂꢘꢘꢏꢖꢒꢃꢀꢄ&,:ꢃꢚꢍ ꢃꢂꢖꢕ<ꢚꢂꢑꢃ()*ꢅꢃꢍꢌꢃ+,(ꢉꢃDꢂ ꢌꢍꢃꢑꢙ<ꢑꢘꢏꢘꢙꢘꢏꢍꢖꢃꢏꢖꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢌꢃꢂꢖꢗꢍꢐꢂꢌ3ꢃꢅꢂꢘꢘꢏꢖꢒ
ꢀꢄ&,:ꢃꢁꢏꢒꢁꢃꢂꢖꢕ<ꢚꢂꢑꢃꢘꢁꢂꢃꢊ'"ꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢌꢃꢂꢖꢗꢍꢐꢂꢌꢃ3
Data
RCLK - Recovered Clock, Pin 8.
ꢀꢁꢂꢃꢌꢂꢗꢂꢏꢎꢂꢌꢃꢌꢂꢗꢍꢎꢂꢌꢂꢐꢃꢗꢚꢍꢗ;ꢃꢏꢑꢃꢍꢙꢘꢋꢙꢘꢃꢍꢖꢃꢘꢁꢏꢑꢃꢋꢏꢖ3
RDATA - Receive Data - Pin 7. (Extended Hardware Mode)
,ꢕꢘꢕꢃꢌꢂꢗꢍꢎꢂꢌꢂꢐꢃꢓꢌꢍꢔꢃꢘꢁꢂꢃ/ꢀ"7ꢃꢕꢖꢐꢃ//"28ꢃꢏꢖꢋꢙꢘꢑꢃꢏꢑꢃꢍꢙꢘꢋꢙꢘꢃꢕꢘꢃꢘꢁꢏꢑꢃꢋꢏꢖ!ꢃꢕꢓꢘꢂꢌꢃ<ꢂꢏꢖꢒꢃꢐꢂꢗꢍꢐꢂꢐꢃ<#ꢃꢘꢁꢂ
ꢚꢏꢖꢂꢃꢗꢍꢐꢂꢃꢐꢂꢗꢍꢐꢂꢌ3ꢃ/,ꢊꢀꢊꢃꢏꢑꢃ2/*3ꢃ/,ꢊꢀꢊꢃꢏꢑꢃꢑꢘꢕ<ꢚꢂꢃꢕꢖꢐꢃꢎꢕꢚꢏꢐꢃꢍꢖꢃꢘꢁꢂꢃꢓꢕꢚꢚꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃ/ꢄ693
RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and
Host Modes)
ꢀꢁꢂꢃꢌꢂꢗꢂꢏꢎꢂꢌꢃꢌꢂꢗꢍꢎꢂꢌꢂꢐꢃ2/*ꢃꢐꢏꢒꢏꢘꢕꢚꢃꢐꢕꢘꢕꢃꢏꢑꢃꢍꢙꢘꢋꢙꢘꢃꢍꢖꢃꢘꢁꢂꢑꢂꢃꢋꢏꢖꢑ3ꢃ"ꢖꢃꢘꢁꢂꢃ+ꢕꢌꢐ ꢕꢌꢂꢃ'ꢍꢐꢂ!ꢃ/7&ꢅ
ꢕꢖꢐꢃ/2:8ꢃꢕꢌꢂꢃꢑꢘꢕ<ꢚꢂꢃꢕꢖꢐꢃꢎꢕꢚꢏꢐꢃꢍꢖꢃꢘꢁꢂꢃꢌꢏꢑꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃ/ꢄ693ꢃ"ꢖꢃꢘꢁꢂꢃ+ꢍꢑꢘꢃ'ꢍꢐꢂ!ꢃꢄ69:ꢃꢐꢂꢘꢂꢌꢔꢏꢖꢂꢑ
ꢘꢁꢂꢃꢗꢚꢍꢗ;ꢃꢂꢐꢒꢂꢃꢓꢍꢌꢃ ꢁꢏ ꢗꢁꢃ/7&ꢅꢃꢕꢖ ꢐꢃ/2:8ꢃꢕꢌꢂꢃꢑꢘꢕ<ꢚꢂꢃꢕꢖꢐꢃꢎꢕꢚꢏꢐ3ꢃꢅꢂꢂꢃꢀꢕ<ꢚꢂꢃꢈ3ꢃꢊꢃꢋꢍꢑꢏꢘꢏꢎꢂꢃꢋꢙꢚꢑꢂ
0 ꢏꢘꢁꢃꢌꢂꢑꢋꢂꢗꢘꢃꢘꢍꢃꢒꢌꢍꢙꢖꢐ1ꢃꢌꢂꢗꢂꢏꢎꢂꢐꢃꢍꢖꢃꢘꢁꢂꢃ/ꢀ"7ꢃꢋꢏꢖꢃꢒꢂꢖꢂꢌꢕꢘꢂꢑꢃꢕꢃꢚꢍ ꢒꢏꢗꢃꢇꢃꢍꢖꢃ/7&ꢅ!ꢃꢕꢖꢐꢃꢕꢃꢋꢍ ꢑꢏꢘꢏꢎꢂ
ꢋꢙꢚꢑꢂꢃꢌꢂꢗꢂꢏꢎꢂꢐꢃꢍꢖꢃꢘꢁꢂꢃ//"28ꢃꢋꢏꢖꢃꢒꢂꢖꢂꢌꢕꢘꢂꢑꢃꢕꢃꢚꢍꢒꢏꢗꢃꢇꢃꢍꢖꢃ/2:83
RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20.
ꢀꢁꢂꢃ ꢊ'"ꢃꢌꢂꢗ ꢂꢏꢎꢂꢃꢑ ꢏꢒꢖꢕꢚꢃꢏꢑ ꢃꢏ ꢖꢋꢙꢘꢃꢘ ꢍꢃꢘ ꢁꢂꢑꢂꢃ ꢋꢏꢖꢑ3ꢃꢊꢃ ꢗꢂꢖꢘꢂꢌ$ꢘꢕꢋꢋꢂꢐ!ꢃꢗꢂ ꢖꢘꢂꢌ$ꢒꢌꢍꢙꢖꢐꢂꢐ!ꢃ 4ꢛꢇ!ꢃ ꢑꢘꢂꢋ$ꢙꢋ
ꢘꢌꢕꢖꢑꢓꢍꢌꢔꢂꢌꢃꢏꢑꢃꢌꢂ%ꢙꢏꢌꢂꢐꢃꢍꢖꢃꢘꢁꢂꢑꢂꢃꢏꢖꢋꢙꢘꢑ!ꢃꢕꢑꢃꢑꢁꢍ ꢖꢃꢏꢖꢃ?ꢏꢒ ꢙꢌꢂꢃꢊꢇꢃꢏꢖ ꢃꢘꢁꢂꢃApplicationsꢃꢑꢂꢗꢘꢏꢍꢖ3ꢃ,ꢕꢘꢕ
ꢕꢖꢐꢃꢗꢚꢍꢗ;ꢃꢕꢌꢂꢃꢌꢂꢗꢍꢎꢂꢌꢂꢐꢃꢕꢖꢐꢃꢍꢙꢘꢋꢙꢘꢃꢍꢖꢃ/ꢄ69ꢃꢕꢖꢐꢃ/7&ꢅ-/2:8ꢃꢍꢌꢃ/,ꢊꢀꢊ3
TCLK - Transmit Clock, Pin 2.
ꢀꢁꢂꢇ3ꢈ==ꢃ'+Dꢃ0ꢍꢌꢃ43ꢜ=)ꢃ'+D1ꢃꢘꢌꢕꢖꢑꢔꢏꢘꢃꢗꢚꢍꢗ;ꢃꢏꢑꢃꢏꢖꢋꢙꢘꢃꢍꢖꢃꢘꢁꢏꢑꢃꢋꢏꢖ3ꢃꢀ7&ꢅ-ꢀ2:8ꢃꢍꢌꢃꢀ ,ꢊꢀꢊꢃꢕꢌꢂ
ꢑꢕꢔꢋꢚꢂꢐꢃꢍꢖꢃꢘꢁꢂꢃꢓꢕꢚꢚꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃꢀꢄ693
TDATA - Transmit Data, Pin 3. (Extended Hardware Mode)
ꢀꢌꢕꢖꢑꢔꢏꢘꢘꢂꢌꢃ2/*ꢃꢏꢖꢋꢙꢘꢃꢐꢕꢘꢕꢃ ꢁꢏꢗꢁꢃꢋꢕꢑꢑꢂꢑꢃꢘꢁꢌꢍꢙꢒꢁꢃꢘꢁꢂꢃꢚꢏꢖꢂꢃꢗꢍꢐꢂꢃꢂꢖꢗꢍꢐꢂꢌ!ꢃꢕꢖꢐꢃꢏꢑꢃꢘꢁꢂꢖꢃꢐꢌꢏꢎꢂꢖꢃꢍꢖꢃꢘꢍ
ꢘꢁꢂꢃꢚꢏꢖꢂꢃꢘꢁꢌꢍꢙꢒꢁꢃꢀꢀ"7ꢃꢕꢖꢐꢃꢀ/"283ꢃꢀ,ꢊꢀꢊꢃꢏꢑꢃꢑꢕꢔꢋꢚꢂꢐꢃꢍꢖꢃꢘꢁꢂꢃꢓꢕꢚꢚꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃꢀꢄ693ꢃ
TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and
Host Modes)
"ꢖꢋꢙꢘꢑꢃꢓꢍꢌꢃꢗꢚꢍꢗ;ꢃꢕꢖꢐꢃꢐꢕꢘꢕꢃꢘꢍꢃ<ꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢐ3ꢃꢀꢁꢂꢃꢑꢏꢒꢖꢕꢚꢃꢏꢑꢃꢐꢌꢏꢎꢂꢖꢃꢍꢖꢃꢘꢍꢃꢘꢁꢂꢃꢚꢏꢖꢂꢃꢘꢁꢌꢍꢙꢒꢁꢃꢀꢀ"7ꢃꢕꢖꢐ
ꢀ/"283ꢃꢀ7&ꢅꢃꢕꢖꢐꢃꢀ2:8ꢃꢕꢌꢂꢃꢑꢕꢔꢋꢚꢂꢐꢃꢍꢖꢃꢘꢁꢂꢃꢓꢕꢚꢚꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃ ꢀꢄ693ꢃꢊꢃꢀ7&ꢅꢃꢏꢖꢋꢙꢘꢃꢗꢕꢙꢑꢂꢑꢃꢕ
ꢋꢍꢑꢏꢘꢏꢎꢂꢃꢋꢙꢚꢑꢂꢃꢘꢍꢃ<ꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢐ!ꢃ ꢁꢏꢚꢂꢃꢕꢃꢀ2:8ꢃꢏꢖꢋꢙꢘꢃꢗꢕꢙꢑꢂꢑꢃꢕꢃꢖꢂꢒꢕꢘꢏꢎꢂꢃꢋꢙꢚꢑꢂꢃꢘꢍꢃ<ꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢐ3
TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16.
ꢀꢁꢂꢃꢊ'"ꢃꢑꢏꢒꢖꢕꢚꢃꢏꢑꢃꢐꢌꢏꢎꢂꢖꢃꢘꢍꢃꢘꢁꢂꢃꢚꢏꢖꢂꢃꢘꢁꢌꢍꢙꢒꢁꢃꢘꢁꢂꢑꢂꢃꢋꢏꢖꢑ3ꢃ"ꢖꢃꢘꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊ!ꢃꢘꢁꢏꢑꢃꢍꢙꢘꢋꢙꢘꢃꢏꢑꢃꢐꢂꢑꢏꢒꢖꢂꢐ
ꢘꢍꢃꢐꢌꢏꢎꢂꢃꢕꢃ>ꢈꢃΩꢃꢚꢍꢕꢐ3ꢃꢊꢃꢇꢛꢇ!ꢃꢇꢛꢇ3ꢇꢈꢃꢍꢌꢃꢇꢛꢇ34ꢆꢃꢘꢌꢕꢖꢑꢓꢍꢌꢔꢂꢌꢃꢏꢑꢃꢌꢂ%ꢙꢏꢌꢂꢐꢃꢕꢑꢃꢑꢁꢍ ꢖꢃꢏꢖꢃ?ꢏꢒꢙꢌꢂꢃꢊꢇ3
26
DS40F3
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
Status
AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode)
ꢊ"ꢅꢃꢒꢍꢂꢑꢃꢁꢏꢒꢁꢃ ꢁꢂꢖꢃꢙꢖꢓꢌꢕꢔꢂꢐꢃꢕꢚꢚ$ꢍꢖꢂꢑꢃꢗꢍꢖꢐꢏꢘꢏꢍꢖꢃ0<ꢚꢙꢂꢃꢕꢚꢕꢌꢔ1ꢃꢏꢑꢃꢐꢂꢘꢂꢗꢘꢂꢐ!ꢃꢙꢑꢏꢖꢒꢃꢘꢁꢂꢃꢐꢂꢘꢂꢗꢘꢏꢍꢖ
ꢗꢌꢏꢘꢂꢌꢏꢕꢃꢍꢓꢃꢚꢂꢑꢑꢃꢘꢁꢕꢖꢃꢘꢁꢌꢂꢂꢃDꢂꢌꢍꢑꢃꢍꢙꢘꢃꢍꢓꢃ4ꢜ=)ꢃ<ꢏꢘꢃꢋꢂꢌꢏꢍꢐꢑ3
BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode)
(7Lꢃꢑꢘꢌꢍ<ꢂꢑꢃꢁꢏꢒꢁꢃ ꢁꢂꢖꢃꢕꢃ<ꢏꢋꢍꢚꢕꢌꢃꢎꢏꢍꢚꢕꢘꢏꢍꢖꢃꢏꢑꢃꢐꢂꢘꢂꢗꢘꢂꢐꢃꢏꢖꢃꢘꢁꢂꢃꢌꢂꢗꢂꢏꢎꢂꢐꢃꢑꢏꢒꢖꢕꢚ3ꢃꢃ()*ꢅꢃ0ꢍꢌꢃ+,(ꢉ1
Dꢂꢌꢍꢃꢑꢙ<ꢑꢘꢏꢘꢙꢘꢏꢍꢖꢑꢃꢕꢌꢂꢃꢖꢍꢘꢃꢓꢚꢕꢒꢒꢂꢐꢃꢕꢑꢃ<ꢏꢋꢍꢚꢕꢌꢃꢎꢏꢍꢚꢕꢘꢏꢍꢖꢑꢃꢏꢓꢃꢘꢁꢂꢃ()*ꢅꢃ0ꢍꢌꢃ+,(ꢉ1ꢃꢐꢂꢗꢍꢐꢂꢌꢃꢁꢕꢑꢃ<ꢂꢂꢖ
ꢂꢖꢕ<ꢚꢂꢐ3
DPM - Driver Performance Monitor, Pin 11. (Hardware and Host Modes)
,7'ꢃꢒꢍꢂꢑꢃꢁꢏꢒꢁꢃꢏꢓꢃꢖꢍꢃꢕꢗꢘꢏꢎꢏꢘ#ꢃꢏꢑꢃꢐꢂꢘꢂꢗꢘꢂꢐꢃꢍꢖꢃ'ꢀ"7ꢃꢕꢖꢐꢃ'/"283ꢃ
LOS - Loss of Signal, Pin 12.
6&ꢅꢃꢒꢍꢂꢑꢃꢁꢏꢒꢁꢃ ꢁꢂꢖꢃꢇ>ꢈꢃꢗꢍꢖꢑꢂꢗꢙꢘꢏꢎꢂꢃDꢂꢌꢍꢑꢃꢁꢕꢎꢂꢃ<ꢂꢂꢖꢃꢌꢂꢗꢂꢏꢎꢂꢐ3ꢃ?ꢍꢌꢃꢘꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊ!ꢃ6&ꢅꢃꢌꢂꢘꢙꢌꢖꢑ
ꢚꢍ ꢃ ꢁꢂꢖꢃꢘꢁꢂꢃꢍꢖꢂꢑꢃꢐꢂꢖꢑꢏꢘ#ꢃꢌꢂꢕꢗꢁꢂꢑꢃꢇ43ꢈꢝꢃ0<ꢕꢑꢂꢐꢃꢙꢋꢍꢖꢃꢇ>ꢈꢃ<ꢏꢘꢃꢋꢂꢌꢏꢍꢐꢑꢃꢑꢘꢕꢌꢘꢏꢖꢒꢃ ꢏꢘꢁꢃꢕꢃꢍꢖꢂꢃꢕꢖꢐ
ꢗꢍꢖꢘꢕꢏꢖꢏꢖꢒꢃꢚꢂꢑꢑꢃꢘꢁꢕꢖꢃꢇꢜꢜꢃꢗꢍꢖꢑꢂꢗꢙꢘꢏꢎꢂꢃDꢂꢌꢍꢑ1ꢃꢕꢑꢃꢋꢌꢂꢑꢗꢌꢏ<ꢂꢐꢃ<#ꢃꢊ2ꢅ"ꢃꢀꢇ34ꢉꢇ$ꢇ55ꢉ3
MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes)
ꢀꢁꢂꢑꢂꢃꢋꢏꢖꢑꢃꢕꢌꢂꢃꢖꢍꢌꢔꢕꢚꢚ#ꢃꢗꢍꢖꢖꢂꢗꢘꢂꢐꢃꢘꢍꢃꢀꢀ"7ꢃꢕꢖꢐꢃꢀ/"28ꢃꢕꢖꢐꢃꢔꢍꢖꢏꢘꢍꢌꢃꢘꢁꢂꢃꢍꢙꢘꢋꢙꢘꢃꢍꢓꢃꢕꢃꢄꢅꢆꢇꢈꢉꢈꢊ3
"ꢓꢃꢘꢁꢂꢃ"2ꢀꢃꢋꢏꢖꢃꢏꢖꢃꢘꢁꢂꢃꢁꢍꢑꢘꢃꢔꢍꢐꢂꢃꢏꢑꢃꢙꢑꢂꢐ!ꢃꢕꢖꢐꢃꢘꢁꢂꢃꢔꢍꢖꢏꢘꢍꢌꢃꢏꢑꢃꢖꢍꢘꢃꢙꢑꢂꢐ!ꢃ ꢌꢏꢘꢏꢖꢒꢃCꢄꢚꢂꢕꢌꢃ,7'Cꢃꢘꢍꢃꢘꢁꢂ
ꢑꢂꢌꢏꢕꢚꢃꢏꢖꢘꢂꢌꢓꢕꢗꢂꢃ ꢏꢚꢚꢃꢋꢌꢂꢎꢂꢖꢘꢃꢕꢖꢃꢏꢖꢘꢂꢌꢌꢙꢋꢘꢃꢓꢌꢍꢔꢃꢘꢁꢂꢃꢐꢌꢏꢎꢂꢌꢃꢋꢂꢌꢓꢍꢌꢔꢕꢖꢗꢂꢃꢔꢍꢖꢏꢘꢍꢌ3
DS40F3
27
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
28-pin PLCC
28
MILLIMETERS
INCHES
E
E1
DIM MIN NOM MAX MIN NOM MAX
A
A1
4.20 4.45 4.57 0.165 0.175 0.180
2.29 2.79 3.04 0.090 0.110 0.120
0.33 0.41 0.53 0.013 0.016 0.021
12.32 12.45 12.57 0.485 0.490 0.495
11.43 11.51 11.58 0.450 0.453 0.456
9.91 10.41 10.92 0.390 0.410 0.430
1.19 1.27 1.35 0.047 0.050 0.053
B
D/E
D1/E1
D2/E2
e
D1
D
e
B
A1
A
D2/E2
28
DS40F3
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
APPLICATIONS
+5V
+
+
68
μ
F
0.1
μ
F
1.0
μF
+5V
100 k
Ω
RGND
TGND
21
RV+
15
TV+
27
28
CLKE
ACLKI
LOS
SCLK
CS
26
23
24
25
1
12
11
Control
P
μ
&
INT
Serial
Port
Monitor
DPM
SDI
SDO
RV+
5
7
6
8
MODE
RPOS
RNEG
RCLK
CS61535A
IN
HOST
MODE
CT 2:1
19
RTIP
R1
R2
RECEIVE
LINE
Frame
Format
20
RRING
Encoder/
Decoder
3
4
2
TPOS
TNEG
TCLK
17
18
16
MTIP
MRING
TRING
0.47
F
μ
9
XTALIN
TRANSMIT
LINE
XTL
10
13
XTALOUT
TTIP
RGND TGND
22 14
DEVICE
FREQUENCY
MHz
CABLE
R1&2
Ω
Transmit
Transformer
Ω
1.544
2.048
2.048
100
120
75
200
240
150
1:1.15
1:1.26
1:1
CS61535A
Figure A1. Host Mode Configuration
Line Interface
ꢗꢍꢌꢂꢃꢍꢓꢃꢘꢁ ꢂꢃꢘꢌꢕꢖꢑꢓꢍꢌꢔꢂꢌꢃꢐꢙꢂꢃꢘꢍꢃꢕꢖ#ꢃ,ꢄꢃꢏꢔ<ꢕꢚꢕꢖꢗꢂ
ꢘꢁꢕꢘꢃꢔ ꢕ#ꢃ<ꢂꢃꢋꢌ ꢂꢑꢂꢖꢘꢃꢕꢘꢃꢘꢁꢂꢃꢐꢏ ꢓꢓꢂꢌꢂꢖꢘꢏꢕꢚꢃꢍ ꢙꢘꢋꢙꢘꢑ!
ꢀꢀ"7ꢃꢕ ꢖꢐꢃꢀ /"283ꢃ"ꢓꢃ,ꢄꢃꢑꢕ ꢘꢙꢌꢕꢘꢂꢑꢃꢘꢁꢂ ꢃꢘꢌꢕ ꢖꢑ$
ꢓꢍꢌꢔꢂꢌ!ꢃꢕꢃ, ꢄꢃꢍꢓ ꢓꢑꢂꢘꢃ ꢏꢚꢚꢃꢌ ꢂꢑꢙꢚꢘꢃꢐꢙ ꢌꢏꢖꢒꢃꢘ ꢁꢂ
ꢘꢌꢕꢖꢑꢔꢏꢑꢑꢏꢍꢖꢃꢍꢓꢃꢕꢃꢑꢋꢕꢗꢂꢃ0Dꢂꢌꢍ1ꢃꢕꢑꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢓꢍꢌꢔꢂꢌ
ꢘꢌꢏꢂꢑꢃꢘ ꢍꢃꢐꢙ ꢔꢋꢃꢘꢁ ꢂꢃꢗꢁ ꢕꢌꢒꢂꢃꢕ ꢖꢐꢃꢌ ꢂꢘꢙꢌꢖꢃꢘꢍ ꢃꢂ %ꢙꢏꢚꢏ<$
ꢌꢏꢙꢔ3ꢃꢀ ꢁꢂꢃ<ꢚꢍ ꢗ;ꢏꢖꢒꢃꢗ ꢕꢋꢕꢗꢏꢘꢍꢌꢃ ꢏ ꢚꢚꢃ; ꢂꢂꢋꢃ, ꢄ
ꢗꢙꢌꢌꢂꢖꢘꢃꢓꢌꢍꢔꢃꢓꢚꢍ ꢏꢖꢒꢃꢏꢖꢃꢘꢁꢂꢃꢘꢌꢕꢖꢑꢓꢍꢌꢔꢂꢌ3
?ꢏꢒꢙꢌꢂꢑꢃꢊ ꢇ$ꢊꢉꢃꢑ ꢁꢍ ꢃꢘ ꢁꢂꢃꢘ #ꢋꢏꢗꢕꢚꢃꢗꢍꢖ ꢓꢏꢒꢙꢌꢕꢘꢏꢍꢖꢑ
ꢓꢍꢌꢃꢏꢖꢘꢂꢌꢓꢕꢗꢏꢖꢒꢃꢘꢁꢂꢃ"3ꢄ3ꢃꢘꢍꢃꢕꢃꢚꢏꢖꢂꢃꢘꢁꢌꢍꢙꢒꢁꢃꢘꢌꢕꢖꢑꢔꢏꢘ
ꢕꢖꢐꢃꢌꢂꢗꢂꢏꢎꢂꢃꢘꢌꢕꢖꢑꢓꢍꢌꢔꢂꢌꢑ3ꢃ
ꢀꢁꢂꢃꢌ ꢂꢗꢂꢏꢎꢂꢌꢃꢘꢌ ꢕꢖꢑꢓꢍꢌꢔꢂꢌꢃꢏ ꢑꢃꢗꢂꢖ ꢘꢂꢌꢃꢘ ꢕꢋꢋꢂꢐꢃꢕ ꢖꢐ
ꢗꢂꢖꢘꢂꢌꢃꢒꢌꢍꢙꢖꢐꢂꢐꢃ ꢏꢘꢁꢃꢃꢌꢂꢑꢏꢑꢘꢍꢌꢑꢃ<ꢂꢘ ꢂꢂꢖꢃꢘꢁꢂꢃꢗꢂꢖꢘꢂꢌ
ꢘꢕꢋꢃꢕꢖꢐꢃꢂꢕꢗꢁꢃꢚꢂꢒꢃꢍꢖꢃꢘꢁꢂꢃ"3ꢄ3ꢃꢑꢏꢐꢂ3ꢃꢀꢁꢂꢑꢂꢃꢌꢂꢑꢏꢑꢘꢍꢌꢑ
ꢋꢌꢍꢎꢏꢐꢂꢃꢘꢁꢂꢃꢘꢂꢌꢔꢏꢖꢕꢘꢏꢍꢖꢃꢓꢍꢌꢃꢘꢁꢂꢃꢚꢏꢖꢂ3ꢃ
Selecting an Oscillator Crystal
ꢅꢋꢂꢗꢏꢓꢏꢗꢃꢗꢌ #ꢑꢘꢕꢚꢃꢋ ꢕꢌꢕꢔꢂꢘꢂꢌꢑꢃꢕꢌ ꢂꢃꢌ ꢂ%ꢙꢏꢌꢂꢐꢃꢓ ꢍꢌ
ꢋꢌꢍꢋꢂꢌꢃꢍꢋꢂ ꢌꢕꢘꢏꢍꢖꢃꢍꢓꢃꢘꢁ ꢂꢃꢄꢅꢆꢇ ꢈꢉꢈꢊ3ꢃ Refer to
?ꢏꢒꢙꢌꢂꢑꢃꢊꢇ$ꢊꢉꢃꢑꢁꢍ ꢃꢕꢃꢜ3=>ꢃμ?ꢃꢗꢕꢋꢕꢗꢏꢘꢍꢌꢃꢏꢖꢃꢑꢂꢌꢏꢂꢑ
ꢏꢘꢁꢃꢘꢁꢂ ꢃꢘꢌ ꢕꢖꢑꢔꢏꢘꢃꢘꢌ ꢕꢖꢑꢓꢍꢌꢔꢂꢌꢃꢋꢌ ꢏꢔꢕꢌ#3ꢃꢀꢁ ꢏꢑꢃꢗꢕ $
ꢋꢕꢗꢏꢘꢍꢌꢃꢏ ꢑꢃ ꢖꢂꢂꢐꢂꢐꢃꢘꢍ ꢃꢋꢌꢂ ꢎꢂꢖꢘꢃꢕꢖ #ꢃ<ꢙ ꢏꢚꢐꢙꢋꢃꢏ ꢖꢃꢘꢁ ꢂ
DS40F3
29
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
+5V
+
+
68
F
0.1
F
μ
1.0 F
μ
μ
RGND
28
TGND
21
RV+
15
TV+
TAOS
ACLKI
RLOOP
LLOOP
LOS
1
26
27
12
11
23
Control
&
Monitor
LEN0
LEN1
LEN2
Line
Length
Setting
24
25
DPM
CT 2:1
5
19
20
CS61535A
IN
HARDWARE
MODE
MODE
RTIP
R1
R2
RECEIVE
LINE
7
6
8
RPOS
RNEG
RCLK
RRING
Frame
Format
Encoder/
Decoder
3
4
2
17
18
16
TPOS
TNEG
TCLK
MTIP
MRING
TRING
0.47 μF
TRANSMIT
LINE
13
TTIP
9
XTALIN
XTL
10
XTALOUT
RGND TGND
22 14
Figure A2. Hardware Mode Configuration
+5V
+
+
68
F
0.1
F
μ
1.0 F
μ
μ
RGND
TGND
21
RV+
15
TV+
17
RCODE
PCS
18
6
23
BPV
LEN0
LEN1
LEN2
Line
28
1
24
25
TAOS
ACLKI
RLOOP
LLOOP
LOS
Length
Setting
Control
&
26
27
12
11
5
Monitor
CT 2:1
CS61535A
IN
EXTENDED
HARDWARE
MODE
19
20
RTIP
R1
R2
RECEIVE
LINE
AIS
MODE
TCODE
4
RRING
7
8
3
2
RDATA
RCLK
Frame
Format
Encoder/
Decoder
0.47 μF
TDATA
TCLK
16
13
TRING
TTIP
TRANSMIT
LINE
9
XTALIN
XTL
10
XTALOUT
RGND TGND
22 14
Figure A3. Extended Hardware Mode Configuration
30
DS40F3
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
Appendix A for crystal specifications3ꢃ
DS40F3
31
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
ꢘꢂꢌꢃꢘꢁꢂꢃꢓꢕꢚ ꢚꢏꢖꢒꢃꢂꢐꢒ ꢂꢃꢍꢓꢃꢀ ꢄ693ꢃꢀ ꢁꢂꢃꢄꢅꢆꢇꢈꢉ=ꢃꢌꢂ$
%ꢙꢏꢌꢂꢑꢃꢈꢜ ꢃꢖꢑ ꢃꢍꢓꢃꢁꢍ ꢚꢐꢃꢘꢏ ꢔꢂꢃ ꢍꢖꢃꢀ 7&ꢅꢃꢕꢖ ꢐꢃꢀ 2:8
ꢕꢓꢘꢂꢌꢃꢘꢁꢂꢃꢓꢕꢚꢚꢏꢖꢒꢃꢂꢐꢒꢂꢃꢍꢓꢃꢀ ꢄ6!ꢃꢕꢖꢐꢃꢜꢃꢖꢑꢃꢍꢓꢃꢑ ꢂꢘꢙꢋ
ꢘꢏꢔꢂ3
ꢉꢜꢃꢓꢌꢕꢔꢂꢃ04ꢈꢆꢃ<ꢏꢘꢑꢃꢋꢂꢌꢃꢓꢌꢕꢔꢂ1ꢃꢁꢕꢑꢃꢏꢘꢑꢃꢐꢕꢘꢕꢃꢔꢕꢋꢋꢂꢐ
ꢏꢖꢘꢍꢃꢘꢁꢂꢃꢆ=)ꢜꢃ< ꢏꢘꢃꢅ &2:ꢀꢃꢓꢌ ꢕꢔꢂ3ꢃꢀ ꢁꢂꢃꢔ ꢕꢋꢋꢏꢖꢒ
ꢐꢍꢂꢑꢃꢖꢍ ꢘꢃꢌ ꢂꢑꢙꢚꢘꢃꢏꢖ ꢃꢕꢃꢙꢖ ꢏꢓꢍꢌꢔꢃꢑ ꢋꢕꢗꢏꢖꢒꢃ<ꢂꢘ ꢂꢂꢖ
ꢑꢙꢗꢂꢑꢑꢏꢎꢂꢃꢀꢇꢃ0ꢍꢌꢃ: ꢇ1ꢃ<ꢏꢘꢑ3ꢃ/ꢕꢘꢁꢂꢌ!ꢃꢓꢍꢌꢃꢚꢍꢗ;ꢂꢐꢃLꢀ
ꢕꢋꢋꢚꢏꢗꢕꢘꢏꢍꢖꢑ!ꢃꢒꢕꢋꢑꢃꢕꢑꢃꢚꢕꢌꢒꢂꢃꢕꢑꢃ4=ꢃꢀꢇꢃ<ꢏꢘꢃꢋꢂꢌꢏꢍꢐꢑꢃꢍꢌ
ꢉ4ꢃ: ꢇꢃ<ꢏ ꢘꢃꢋꢂ ꢌꢏꢍꢐꢑꢃꢗꢕ ꢖꢃꢂ.ꢏ ꢑꢘꢃ <ꢂꢘ ꢂꢂꢖꢃꢑ ꢙꢗꢗꢂꢑꢑꢏꢎꢂ
<ꢏꢘꢑ3ꢃFꢏꢘꢁꢃꢓꢚ ꢍꢕꢘꢏꢖꢒꢃLꢀꢑ!ꢃꢘꢁꢂ ꢃꢒꢕꢋ ꢑꢃꢗ ꢕꢖꢃ< ꢂꢃꢂꢎꢂꢖ
ꢚꢕꢌꢒꢂꢌ3
ꢆ1ꢃ6&ꢅꢃꢍꢗꢗꢙꢌꢑꢃꢕꢓꢘꢂꢌꢃꢉꢇꢃꢗꢍꢖꢑꢂꢗꢙꢘꢏꢎꢂꢃDꢂꢌꢍꢑꢃꢍꢖꢃꢘꢁ ꢂ
ꢄꢅꢆꢇꢈꢉ=3ꢃ?ꢍꢌꢃꢘ ꢁꢂꢃꢄ ꢅꢆꢇꢈꢉꢈꢊꢃ6 &ꢅꢃꢍꢗ ꢗꢙꢌꢑꢃꢕꢓꢘ ꢂꢌ
ꢇ>ꢈꢃDꢂꢌꢍꢑ3
>1ꢃꢅꢏ ꢖꢗꢂꢃꢘꢁꢂ ꢃꢄꢅꢆꢇ ꢈꢉꢈꢊꢃꢌꢂꢗꢂ ꢏꢎꢂꢌꢑꢃꢕ ꢌꢂꢃꢗꢍ ꢖꢘꢏꢖꢙ$
ꢍꢙꢑꢚ#ꢃꢗꢕꢚꢏ<ꢌꢕꢘꢂꢐ!ꢃꢘꢁꢂꢌꢂꢃꢏꢑꢃꢖꢍꢃꢖꢂ ꢂꢐꢃꢘꢍꢃꢏꢑꢑꢙꢂꢃꢕꢃꢌꢂꢑꢂꢘ
ꢘꢍꢃꢏꢖꢏ ꢘꢏꢕꢚꢏDꢂꢃꢘꢁ ꢂꢃꢌ ꢂꢗꢂꢏꢎꢂꢌꢃꢘ ꢏꢔꢏꢖꢒꢃꢕ ꢑꢃ ꢏꢘꢁꢃꢘ ꢁꢂ
ꢄꢅꢆꢇꢈꢉ=3
ꢀꢁꢂꢃꢗꢏꢌꢗꢙꢏꢘꢃꢏꢖꢃ?ꢏꢒꢙꢌꢂꢃꢊꢈꢃꢂꢚꢏꢔꢏꢖꢕꢘꢂꢑꢃꢘꢁꢂꢃꢐꢂꢔꢙꢚꢘꢏ$
ꢋꢚꢂ.ꢏꢖꢒꢃ@ꢏꢘꢘꢂꢌꢃꢏꢖꢃꢕꢃꢘ ꢍ$ꢑꢘꢂꢋꢃꢕꢋꢋ ꢌꢍꢕꢗꢁ3ꢃꢀꢁꢂꢃꢓ ꢏꢌꢑꢘ
ꢑꢘꢂꢋꢃꢙꢑꢂꢑꢃꢕꢃ? "?&ꢃ ꢁꢏꢗꢁꢃꢏꢑꢃꢓꢏꢚꢚꢂꢐꢃꢕꢘꢃꢕꢃꢈꢇ3)=ꢃ'+D
ꢌꢕꢘꢂꢃ0 ꢁꢂꢖꢃꢀꢇꢃꢍꢌꢃ:ꢇꢃ<ꢏꢘꢑꢃꢕꢌꢂꢃꢋꢌꢂꢑꢂꢖꢘ1!ꢃꢕꢖꢐꢃ ꢁꢏꢗꢁ
ꢏꢑꢃꢂꢔꢋꢘꢏꢂꢐꢃꢕꢘꢃꢕꢃꢑꢙ<$ꢔꢙꢚꢘꢏꢋꢚꢂꢃꢍꢓꢃꢘꢁꢂꢃꢈꢇ3)=ꢃꢌꢕꢘꢂ3ꢃꢀꢁꢂ
?"?&ꢃꢏꢑ ꢃꢂ ꢔꢋꢘꢏꢂꢐꢃꢍ ꢖꢚ#ꢃ ꢁꢂꢖ ꢃꢏꢘꢃꢗ ꢍꢖꢘꢕꢏꢖꢑꢃꢐ ꢕꢘꢕ3
Fꢁꢂꢖꢃꢘꢁꢂꢃ?"?&ꢃꢏꢑ ꢃꢂꢔꢋꢘ#ꢃꢘꢁꢂꢃꢍꢙꢘꢋꢙꢘꢃꢗꢚꢍꢗ;ꢃꢏꢑꢃꢖꢍꢘ
ꢋꢙꢚꢑꢂꢐ3ꢃ
Using the CS61535A for SONET
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊꢃꢗꢕꢖꢃ<ꢂꢃꢕꢋꢋꢚꢏꢂꢐꢃꢘꢍꢃꢅ&2: ꢀꢃLꢀꢇ3ꢈ
ꢕꢖꢐꢃLꢀ 43ꢜꢃꢏꢖ ꢘꢂꢌꢓꢕꢗꢂꢃꢗ ꢏꢌꢗꢙꢏꢘꢑꢃꢕꢑ ꢃꢑ ꢁꢍ ꢖꢃꢏꢖꢃ?ꢏ ꢒ$
ꢙꢌꢂꢃꢊꢈ3ꢃꢀꢁꢂꢃꢅ&2:ꢀꢃꢐꢕꢘꢕꢃꢌꢕꢘꢂꢃꢏꢑꢃꢈꢇ3)=ꢃ'+D!ꢃꢕꢖꢐ
ꢁꢕꢑꢃ ꢆ=)ꢜꢃ< ꢏꢘꢑꢃꢋ ꢂꢌꢃꢓꢌꢕ ꢔꢂꢃ0ꢇ4 ꢈꢃꢙꢑꢃꢋꢂ ꢌꢃꢓꢌꢕꢔꢂ13ꢃꢊꢖ
ꢏꢖꢐꢏꢎꢏꢐꢙꢕꢚꢃꢀꢇꢃꢓꢌꢕꢔꢂꢃ0ꢇ5ꢉꢃ<ꢏꢘꢑꢃꢋꢂꢌꢃꢓꢌꢕꢔꢂ1ꢃꢍꢌꢃ7ꢄ'$
ꢀꢁꢂꢃꢑ ꢙ<$ꢔꢙꢚꢘꢏꢋꢚꢂꢃꢌꢕ ꢘꢂꢃ ꢗꢁꢍꢑꢂꢖꢃ ꢑꢁꢍꢙꢚꢐꢃ< ꢂꢃꢑ ꢚꢏꢒꢁꢘꢚ#
ꢓꢕꢑꢘꢂꢌꢃꢘꢁꢕꢖꢃꢘꢁꢂꢃꢘꢕꢌꢒꢂꢘꢃꢌꢕꢘꢂꢃ0ꢇ3ꢈ==ꢃꢍꢌꢃ43ꢜ=)ꢃ'+D1!
<ꢙꢘꢃꢕꢑ ꢃꢗꢚꢍꢑꢂꢃꢘꢍꢃꢘꢁꢂꢃꢘꢕꢌ ꢒꢂꢘꢃꢌ ꢕꢘꢂꢃꢕꢑꢃꢋꢍꢑ ꢑꢏ<ꢚꢂ3ꢃ? ꢍꢌ
51.84 MHz
Div By
Write
Clock
Empty
FIFO
TCLK2
TPOS
TNEG
Jitter
TCLK1
TSER
RSER
Driver
Attenuator
TSER
6480 to
193 bit
(or 256 bit)
Mapping
Circuit
CS62180B
CS61535A
Receiver
RSER
FIFO
RPOS
RNEG
RCLK2
RCLK2
RCLK1
Figure A5. SONET Application
32
DS40F3
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
ꢚꢍꢗ;ꢂꢐꢃLꢀ ꢃꢍꢋ ꢂꢌꢕꢘꢏꢍꢖ!ꢃ ꢀꢕ<ꢚꢂꢃꢊꢇꢃꢑ ꢁꢍ ꢑꢃꢋꢍ ꢘꢂꢖꢘꢏꢕꢚ
Transformers
ꢑꢙ<$ꢔꢙꢚꢘꢏꢋꢚꢂꢃꢐ ꢕꢘꢕꢃꢌꢕꢘꢂ ꢑ!ꢃꢕꢖ ꢐꢃꢘꢁ ꢂꢃꢏꢔ ꢋꢕꢗꢘꢃꢍꢖꢃꢘꢁ ꢍꢑꢂ
ꢌꢕꢘꢂꢑꢃꢍꢖꢃꢘꢁꢂꢃꢔꢕ.ꢏꢔꢙꢔꢃꢒꢕꢋꢃꢏꢖꢃꢘꢁꢂꢃꢍꢙꢘꢋꢙꢘꢃꢗꢚꢍꢗ;ꢃꢍꢓ
ꢘꢁꢂꢃ?" ?&!ꢃꢕꢖꢐꢃꢐꢂꢋꢘꢁꢃꢍꢓꢃ? "?&ꢃꢌꢂ%ꢙꢏꢌꢂꢐ3ꢃ? "?&
ꢐꢂꢋꢘꢁꢃ ꢏꢚꢚꢃꢁꢕ ꢎꢂꢃꢘꢍꢃ<ꢂꢃꢏꢖꢗ ꢌꢂꢕꢑꢂꢐꢃ ꢓꢍꢌꢃꢓꢚꢍꢕ ꢘꢏꢖꢒꢃ Lꢀ
ꢍꢋꢂꢌꢕꢘꢏꢍꢖ!ꢃ ꢏꢘꢁꢃ)ꢃ<ꢏꢘ ꢑꢃꢍꢓꢃ?"?&ꢃ ꢐꢂꢋꢘꢁꢃ<ꢂꢏꢖꢒꢃꢕꢐꢐꢂꢐ
ꢓꢍꢌꢃꢂꢕꢗꢁꢃꢋꢍꢏꢖꢘꢂꢌꢃꢕꢚꢏꢒꢖꢔꢂꢖꢘꢃꢗꢁꢕꢖꢒꢂꢃꢘꢁꢕꢘꢃꢗꢕꢖꢃꢍꢗꢗꢙꢌ3
/ꢂꢗꢍꢔꢔꢂꢖꢐꢂꢐꢃꢘꢌꢕꢖ ꢑꢔꢏꢘꢘꢂꢌꢃꢕꢖꢐꢃꢌ ꢂꢗꢂꢏꢎꢂꢌꢃꢘꢌꢕꢖꢑ $
ꢓꢍꢌꢔꢂꢌꢃꢑꢋ ꢂꢗꢏꢓꢏꢗꢕꢘꢏꢍꢖꢑꢃꢓ ꢍꢌꢃꢘꢁ ꢂꢃꢄꢅ ꢆꢇꢈꢉꢈꢊꢃꢕꢌ ꢂ
ꢑꢁꢍ ꢖꢃꢏꢖꢃꢀꢕ<ꢚꢂꢃꢊ43ꢃꢃꢀꢁꢂꢃꢘꢌꢕꢖꢑꢓꢍꢌꢔꢂꢌꢑꢃꢏꢖꢃꢀꢕ<ꢚꢂꢃꢊꢉ
ꢁꢕꢎꢂꢃ<ꢂꢂꢖꢃꢘꢂꢑꢘꢂꢐꢃꢕꢖꢐꢃꢌꢂꢗꢍꢔꢔꢂꢖꢐꢂꢐꢃꢓꢍꢌꢃꢙꢑꢂꢃ ꢏꢘꢁ
ꢘꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊ3ꢃ/ꢂꢓꢂꢌ ꢃꢘꢍꢃꢘꢁꢂꢃCꢀ ꢂꢚꢂꢗꢍꢔꢃꢀ ꢌꢕꢖꢑ$
ꢓꢍꢌꢔꢂꢌꢃ ꢅꢂꢚꢂꢗꢘꢏꢍꢖꢃ8ꢙꢏꢐ ꢂCꢃꢓꢍꢌꢃꢐꢂꢘ ꢕꢏꢚꢂꢐꢃꢑ ꢗꢁꢂꢔꢕꢘꢏꢗꢑ
ꢁꢏꢗꢁꢃꢑꢁꢍ ꢃꢁꢍ ꢃꢘꢍꢃꢗꢍꢖ ꢖꢂꢗꢘꢃꢘꢁꢂꢃꢚꢏꢖꢂꢃꢏꢖꢘꢂꢌꢓꢕꢗꢂꢃ"ꢄ
ꢏꢘꢁꢃꢕꢃꢋꢕꢌꢘꢏꢗꢙꢚꢕꢌꢃꢘꢌꢕꢖꢑꢓꢍꢌꢔꢂꢌ3
ꢀꢁꢂꢃꢍ <@ꢂꢗꢘꢏꢎꢂꢃꢘꢁꢕꢘꢃꢑ ꢁꢍꢙꢚꢐꢃ<ꢂꢃꢔ ꢂꢘꢃꢏꢖꢃꢋꢏꢗ;ꢏꢖꢒꢃꢕ
?"?&ꢃꢐꢂꢋꢘꢁꢃꢕꢖꢐꢃꢗꢚꢍꢗ;ꢃꢐꢏꢎꢏꢐꢂꢌꢃꢏꢑꢃ;ꢂꢂꢋꢃꢘꢁꢂꢃꢔꢕ.ꢏ$
ꢔꢙꢔꢃꢒꢕꢋꢃꢍꢖꢃꢘꢁꢂꢃꢍꢙꢘꢋꢙꢘꢃꢍꢓꢃꢘꢁꢂꢃ?"?&ꢃꢕꢘꢃꢇ4ꢃ<ꢏꢘ ꢑꢃꢍꢌ
ꢚꢂꢑꢑ3ꢃꢀ ꢂꢚꢎꢂꢃ<ꢏꢘꢑꢃꢏꢑꢃꢘꢁꢂꢃꢔꢕ.ꢏꢔꢙꢔꢃ@ꢏꢘꢘꢂꢌꢃ ꢁꢏꢗꢁꢃꢗꢕꢖ
<ꢂꢃꢏꢖꢋꢙꢘꢃꢘꢍꢃꢘꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊRꢑꢃ@ꢏꢘꢘꢂꢌꢃꢕꢘꢘꢂꢖꢙꢕꢘꢍꢌꢃ ꢏꢘꢁ$
ꢍꢙꢘꢃꢗꢕꢙꢑ ꢏꢖꢒꢃꢘꢁꢂꢃꢍꢎꢂꢌ ꢓꢚꢍ -ꢙꢖꢐꢂꢓꢚꢍ ꢃꢋꢌꢍꢘꢂꢗꢘꢏꢍꢖ
ꢗꢏꢌꢗꢙꢏꢘꢃꢘꢍꢃꢍꢋ ꢂꢌꢕꢘꢂ3ꢃ ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢉꢈꢊꢃꢘꢁꢂ ꢖꢃ ꢌꢂꢔꢍꢎꢂꢑ
ꢘꢁꢂꢃꢌꢂꢔꢕꢏꢖꢏꢖꢒꢃ@ꢏꢘꢘꢂꢌꢃꢓꢌꢍꢔꢃꢘꢁꢂꢃꢑꢏꢒꢖꢕꢚ3
"ꢖꢃꢕꢋꢋꢚꢏꢗꢕꢘꢏꢍꢖꢑꢃ ꢏꢘꢁꢃꢘꢁꢂꢃꢄꢅꢆꢇꢈꢉꢈꢊꢃ ꢁꢂꢌꢂꢃꢏꢘꢃꢏꢑꢃꢕꢐ$
ꢎꢕꢖꢘꢕꢒꢂꢍꢙꢑꢃꢘꢍꢃꢙꢑꢂꢃꢕꢃꢑꢏꢖꢒꢚꢂꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢌꢃꢘꢌꢕꢖꢑꢓꢍꢌꢔꢂꢌ
ꢓꢍꢌꢃ<ꢍꢘꢁꢃ>ꢈΩꢃꢕꢖꢐꢃꢇ4ꢜΩꢃ:ꢇꢃꢕꢋꢋꢚꢏꢗꢕꢘꢏꢍꢖꢑ!ꢃꢕꢃꢇꢛꢇ34ꢆ
ꢘꢌꢕꢖꢑꢓꢍꢌꢂꢌꢃꢔꢕ#ꢃ<ꢂꢃꢙꢑꢂꢐ3ꢃꢊꢚꢘꢁꢍꢙꢒꢁꢃꢘꢌꢕꢖꢑꢔꢏꢘꢘꢂꢌꢃꢌꢂ$
ꢘꢙꢌꢖꢃꢚꢍꢑꢑꢃ ꢏꢚꢚꢃ<ꢂꢃꢌꢂꢐꢙꢗꢂꢐꢃꢓꢍꢌꢃ>ꢈΩꢃꢕꢋꢋꢚꢏꢗꢕꢘꢏꢍꢖꢑ!ꢃꢘꢁꢂ
ꢋꢙꢚꢑꢂꢃꢕꢔ ꢋꢚꢏꢘꢙꢐꢂꢃ ꢏꢚꢚꢃ<ꢂꢃꢗꢍꢌꢌꢂꢗꢘꢃꢕꢗꢌ ꢍꢑꢑꢃꢕꢃ>ꢈꢃ Ω
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ꢘꢁꢂꢃꢍ ꢙꢘꢋꢙꢘꢃ@ ꢏꢘꢘꢂꢌꢃꢒꢂ ꢖꢂꢌꢕꢘꢂꢐꢃ<#ꢃꢘ ꢁꢂꢃꢄ ꢅꢆꢇꢈꢉꢈꢊRꢑ
ꢐꢏꢒꢏꢘꢕꢚꢃꢗꢚꢍꢗ;ꢃꢌꢂꢗꢍꢎꢂꢌ#3ꢃ
Target Rate
(MHz)
Clock
Resultant
Maximum Gap
FIFO Depth
Required
Divider
Rate (MHz)
bits
(μs)
6.2
3.9
3.4
1.544
1.544
2.048
32
33
25
1.620
1.571
2.074
10
6
21
26
34
7
Table A1. Locked VT FIFO Analysis
Parameter
CS61535A Receiver
CS61535A Transmitter
Turns Ratio
1:2 CT 5%
1:1 1.5 % for 75 Ω E1
1:1.15 5 % for 100 Ω T1
1:1.26 1.5 % for 120 Ω E1
Primary Inductance
Primary Leakage Inductance
Secondary Leakage Inductance
Interwinding Capacitance
ET-constant
1.5 mH min. @ 772 kHz
0.3 μH max. @ 772 kHz
0.4 μH max. @ 772 kHz
18 pF max.
600 μH min. @ 772 kHz
1.3 μH max. @ 772 kHz
0.4 μH max. @ 772 kHz
23 pF max.
16 V-μs min. for T1
12 V-μs min. for E1
16 V-μs min. for T1
12 V-μs min. for E1
Table A2. Transformer Specifications
DS40F3
33
ꢀꢁꢂꢃRꢄꢅ
ꢆꢇꢈꢉꢊꢋꢌꢈꢍꢊꢎꢏ
CS61535A
Application
Turns
Ratio(s)
Manufacturer
Part Number
Package Type
RX:
1:2CT
Pulse Engineering
Schott
Bel Fuse
Pulse Engineering
Schott
Bel Fuse
Pulse Engineering
Schott
PE-65351
67129300
0553-0013-HC
PE-65388
67129310
0553-0013-RC
PE-65389
1.5 kV through-hole, single
1.5 kV through-hole, single
1.5 kV through-hole, single
T1 & E1
TX:
T1
1:1.15
TX:
1:1.26
1:1
E1 (75 & 120 Ω)
67129320
Bel Fuse
Pulse Engineering
Bel Fuse
Pulse Engineering
Bel Fuse
0553-0013-SC
PE-65565
0553-0013-7J
PE-65566
RX &TX:
T1
RX &TX:
1:2CT
1:1.15
1:2CT
1:1.26
1:1
1.5 kV through-hole, dual
1.5 kV through-hole, dual
E1 (75 & 120 Ω)
0553-0013-8J
RX &TX:
T1
RX &TX:
1:2CT
1:1.15
1:2CT
1:1.26
1:1
Pulse Engineering
Bel Fuse
Pulse Engineering
Bel Fuse
PE-65765
S553-0013-06
PE-65766
1.5 kVsurface-mount, dual
1.5 kV surface-mount, dual
E1 (75 & 120 Ω)
S553-0013-07
RX :
1:2CT
Pulse Engineering
Pulse Engineering
PE-65835
PE-65839
3 kV through-hole, single
T1 & E1
EN60950, EN41003 approved
TX:
1:1.26
1:1
3 kV through-hole, single
EN60950, EN41003 approved
E1 (75 & 120 Ω)
Table A3. Recommended Transformers For The CS61535A
34
DS40F3
CS61535A
APPENDIX A. RECOMMENDED CRYSTAL SPECIFICATIONS
Cirrus Logic telecommunication devices that offer jitter attenuation require crystals with specifications for
frequency pullability. The crystal oscillation frequency is dictated by capacitive loading, which is con-
trolled by the chip. Therefore, the crystals must meet the following specifications.
6.176 MHz Crystal Performance Specifications
Parameter
Min
Typ
Max
Units
Total Frequency Range
Operating Frequency
(Note 1)
-
370
390
ppm
C
C
C
= 11.6 pF
= 19.0 pF
= 37.0 pF
(Note 2) 6.176803
-
-
MHz
MHz
MHz
load
load
load
6.175846
-
6.176000
-
6.176154
6.175197
(Note 3)
(Note 2)
8.192 MHz Crystal Performance Specifications
Parameter
Min
Typ
Max
Units
Total Frequency Range
Operating Frequency
(Note 1)
-
210
245
ppm
C
C
C
= 11.6 pF
= 19.0 pF
= 37.0 pF
(Note 2) 8.192410
-
-
MHz
MHz
MHz
load
load
load
8.191795
-
8.192000
-
8.192205
8.191590
(Note 3)
(Note 2)
Notes:
1. With C
varying from 11.6 to 37.0 pF at a given temperature.
load
2. Measured at -40 to 85°C.
3. Measured with Saunders 150D meter at 25 °C.
DS40F3
35
CS61535A
REVISION HISTORY
Revision
Date
Changes
F3
Jul ’09
Removed development system info. (No longer supported). Removed PDIP option.
Changed PLCC package option to lead-free.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to http://www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives
consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT-
ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND
CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR
CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO
FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUD-
ING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
36
DS40F3
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