CS8422-DNZR [CIRRUS]
24-bit, 192-kHz, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver; 24位， 192千赫，异步采样率转换器，集成数字音频接口接收器
| 型号： | CS8422-DNZR |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | 24-bit, 192-kHz, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver |
| 文件： | 总82页 (文件大小：714K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS8422
24-bit, 192-kHz, Asynchronous Sample Rate Converter with
Integrated Digital Audio Interface Receiver
Sample Rate Converter Features
Digital Audio Interface Receiver
Features
140 dB Dynamic Range
Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF Compatible Receiver
-120 dB THD+N
28 kHz to 216 kHz Sample Rate Range
2:1 Differential AES3 or 4:1 S/PDIF Input Mux
No External Master Clock Required
Supports Sample Rates up to 211 kHz
De-emphasis Filtering for 32 kHz, 44.1 kHz,
and 48 kHz
Recovered Master Clock Output: 64 x Fs,
96 x Fs, 128 x Fs, 192 x Fs, 256 x Fs,
384 x Fs, 512 x Fs, 768 x Fs, 1024 x Fs
Input/Output Sample Rate Ratios from 6:1 to
49.152 MHz Maximum Recovered Master
1:6
Clock Frequency
Ultra-low-jitter Clock Recovery
Master Mode Master Clock/Sample Rate Ratio
Support: 64, 96, 128, 192, 256, 384, 512, 768,
1024
High Input Jitter Tolerance
No External PLL Filter Components Required
Selectable and Automatic Clock Switching
16-, 18-, 20-, or 24-bit Data I/O
AES3 Direct Output and AES3 TX Pass-
through
Dither Automatically Applied and Scaled to
On-chip Channel Status Data Buffering
Output Resolution
Automatic Detection of Compressed Audio
Streams
Multiple Device Outputs are Phase Matched
Decodes CD Q Sub-Code
VL
Level Translators
SDIN
ISCLK
ILRCK
Serial
Audio
Input
SDOUT1
OSCLK1
OLRCK1
Serial
Audio
Output
Sample
Rate
Converter
2:1
MUX
3:1
MUX
RX0/RXP0
RX1/RXN0
RX2/RXP1
RX3/RXN1
TDM_IN
4:1
MUX
Receiver
Clock &
Data
Recovery
(PLL)
SDOUT2
OSCLK2
OLRCK2
Serial
Audio
Output
3:1
MUX
C or U Data Buffer
(First 5 Bytes)
VA
AGND
Clock
Generator
GPO0
GPO1
GPO2
GPO3
Format
Detect
General
Purpose
Outputs
Control Port & Registers
DGND
V_REG
Level Translators
XTI XTO
RMCK
SDA/
SCL/
AD1/
AD0/
CS
CDOUT CCLK CDIN
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Preliminary Product Information
Copyright Cirrus Logic, Inc. 2009
MAY '09
DS692PP2
(All Rights Reserved)
http://www.cirrus.com
CS8422
System Features
General Description
The CS8422 is a 24-bit, high-performance, monolithic
CMOS stereo asynchronous sample rate converter with
an integrated digital audio interface receiver that de-
codes audio data according to the EIAJ CP1201, IEC-
60958, AES3, and S/PDIF interface standards.
SPI™ or I²C® Software Mode and Stand-alone
Hardware Mode
Flexible 3-wire Digital Serial Audio Input Port
Audio data is input through the digital interface receiver
or a 3-wire serial audio input port. Audio is output
through one of two 3-wire serial audio output ports. Se-
rial audio data outputs can be set to 24-, 20-, 18-, or 16-
bit word-lengths. Data into the digital interface receiver
and serial audio input port can be up to 24-bits long. In-
put and output data can be completely asynchronous,
synchronous to an external clock through XTI, or syn-
chronous to the recovered master clock.
Dual Serial Audio Output Ports with
Independently Selectable Data Paths
Master or Slave Mode Operation for all Serial
Audio Ports
Time Division Multiplexing (TDM) Mode
The CS8422 can be controlled through the control port
in Software Mode or in a Stand-Alone Hardware Mode.
In Software Mode, the user can control the device
through an SPI or I²C control port.
Integrated Oscillator for use with External
Crystal
Target applications include digital recording systems
(DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), dig-
ital mixing consoles, high-quality D/A, effects
processors, computer audio systems, and automotive
audio systems.
Four General-purpose Output Pins (GPO)
+3.3 V Analog Supply (VA)
The CS8422 is available in a space-saving QFN pack-
age in both Commercial (-40° C to +85° C) and
Automotive (-40° C to +105° C) grades. The CDB4822
is also available for device evaluation and implementa-
tion suggestions. Please refer to “Ordering Information”
on page 80 for complete details.
+1.8 V to 5.0 V Digital Interface (VL)
Space-saving 32-pin QFN Package
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CS8422
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 9
1.1 Software Mode ................................................................................................................................. 9
1.2 Hardware Mode ............................................................................................................................. 11
2. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 13
RECOMMENDED OPERATING CONDITIONS .................................................................................. 13
ABSOLUTE MAXIMUM RATINGS ...................................................................................................... 13
PERFORMANCE SPECIFICATIONS - SAMPLE RATE CONVERTER .............................................. 14
DIGITAL FILTER CHARACTERISTICS .............................................................................................. 14
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 15
DIGITAL INTERFACE SPECIFICATIONS ........................................................................................... 16
SWITCHING SPECIFICATIONS ......................................................................................................... 17
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE ................................................. 20
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE .................................................. 21
3. TYPICAL CONNECTION DIAGRAMS ................................................................................................. 22
3.1 Software Mode .............................................................................................................................. 22
3.2 Hardware Mode ............................................................................................................................ 23
4. OVERVIEW ........................................................................................................................................... 24
5. THREE-WIRE SERIAL INPUT/OUTPUT AUDIO PORT ...................................................................... 24
5.1 Serial Port Clock Operation ........................................................................................................... 25
5.1.1 Master Mode ......................................................................................................................... 25
5.1.2 Slave Mode ........................................................................................................................... 25
5.1.3 Hardware Mode Control ........................................................................................................ 25
5.1.4 Software Mode Control .......................................................................................................... 25
5.1.5 Time Division Multiplexing (TDM) Mode ................................................................................ 27
5.1.5.1 TDM Master Mode ..................................................................................................... 27
5.1.5.2 TDM Slave Mode ....................................................................................................... 27
5.1.5.3 Hardware Mode Control ............................................................................................. 27
5.1.5.4 Software Mode Control .............................................................................................. 27
6. DIGITAL INTERFACE RECEIVER ....................................................................................................... 29
6.1 AES3 and S/PDIF Standards ......................................................................................................... 29
6.2 Receiver Input Multiplexer ............................................................................................................. 29
6.2.1 Hardware Mode Control ........................................................................................................ 29
6.2.2 Software Mode Control .......................................................................................................... 29
6.2.2.1 Single-Ended Input Mode .......................................................................................... 30
6.2.2.2 Differential Input Mode ............................................................................................... 30
6.3 Recovered Master Clock - RMCK .................................................................................................. 31
6.3.1 Hardware Mode Control ........................................................................................................ 31
6.3.2 Software Mode Control .......................................................................................................... 31
6.4 XTI System Clock Mode ................................................................................................................ 31
6.4.1 Hardware Mode Control ........................................................................................................ 32
6.4.2 Software Mode Control .......................................................................................................... 32
6.5 AES11 Behavior ............................................................................................................................. 32
6.6 Error and Status Reporting ............................................................................................................ 32
6.6.1 Software Mode ...................................................................................................................... 32
6.6.2 Hardware Mode Control ........................................................................................................ 33
6.7 Non-Audio Detection ...................................................................................................................... 33
6.7.1 Hardware Mode Control ........................................................................................................ 34
6.7.2 Software Mode Control .......................................................................................................... 34
6.8 Format Detection (Software Mode Only) ....................................................................................... 34
6.9 Interrupts (Software Mode Only) .................................................................................................... 34
6.10 Channel Status and User Data Handling ..................................................................................... 34
6.10.1 Hardware Mode Control ...................................................................................................... 34
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CS8422
6.10.2 Software Mode Control ........................................................................................................ 34
7. SAMPLE RATE CONVERTER (SRC) .................................................................................................. 37
7.1 SRC Data Resolution and Dither ................................................................................................... 37
7.1.1 Hardware Mode Control ........................................................................................................ 37
7.1.2 Software Mode Control .......................................................................................................... 37
7.2 SRC Locking .................................................................................................................................. 37
7.3 SRC Muting .................................................................................................................................... 38
7.4 SRC Master Clock ......................................................................................................................... 38
7.4.1 Hardware Mode Control ........................................................................................................ 39
7.4.2 Software Mode Control .......................................................................................................... 39
8. HARDWARE MODE CONTROL .......................................................................................................... 39
8.1 Hardware Mode Serial Audio Port Control ..................................................................................... 40
9. SOFTWARE MODE CONTROL ........................................................................................................... 42
9.1 Control Port Description ................................................................................................................ 42
9.1.1 SPI Mode ............................................................................................................................... 42
9.1.2 I²C Mode ................................................................................................................................ 43
9.1.3 Memory Address Pointer (MAP) ............................................................................................ 43
10. REGISTER QUICK REFERENCE ...................................................................................................... 44
11. SOFTWARE REGISTER BIT DEFINITIONS ...................................................................................... 47
11.1 CS8422 I.D. and Version Register (01h) ..................................................................................... 47
11.2 Clock Control (02h) ...................................................................................................................... 47
11.3 Receiver Input Control (03h) ........................................................................................................ 48
11.4 Receiver Data Control (04h) ........................................................................................................ 48
11.5 GPO Control 1 (05h) .................................................................................................................... 50
11.6 GPO Control 2 (06h) .................................................................................................................... 50
11.7 Serial Audio Input Clock Control (07h) ........................................................................................ 50
11.8 SRC Output Serial Port Clock Control (08h) ............................................................................... 51
11.9 Recovered Master Clock Ratio Control & Misc. (09h) ................................................................ 52
11.10 Data Routing Control(0Ah) ......................................................................................................... 52
11.11 Serial Audio Input Data Format (0Bh) ....................................................................................... 53
11.12 Serial Audio Output Data Format - SDOUT1 (0Ch) ................................................................... 54
11.13 Serial Audio Output Data Format - SDOUT2 (0Dh) .................................................................. 55
11.14 Receiver Error Unmasking (0Eh) .............................................................................................. 56
11.15 Interrupt Unmasking (0Fh) ......................................................................................................... 56
11.16 Interrupt Mode (10h) .................................................................................................................. 57
11.17 Receiver Channel Status (11h) ................................................................................................. 57
11.18 Format Detect Status (12h) ........................................................................................................ 58
11.19 Receiver Error (13h) ................................................................................................................. 58
11.20 Interrupt Status (14h) ................................................................................................................ 59
11.21 PLL Status (15h) ....................................................................................................................... 60
11.22 Receiver Status (16h) ............................................................................................................... 61
11.23 Fs/XTI Ratio (17h - 18h) ........................................................................................................... 62
11.24 Q-Channel Subcode (19h - 22h) ................................................................................................ 62
11.25 Channel Status Registers (23h - 2Ch) ....................................................................................... 62
11.26 IEC61937 PC/PD Burst preamble (2Dh - 30h) .......................................................................... 63
12. APPLICATIONS ................................................................................................................................. 64
12.1 Reset, Power Down, and Start-Up ............................................................................................... 64
12.2 Power Supply, Grounding, and PCB layout ................................................................................. 64
12.3 External Receiver Components ................................................................................................... 64
12.3.1 Attenuating Input signals ..................................................................................................... 65
12.3.2 Isolating Transformer Requirements ................................................................................... 66
12.4 Channel Status Buffer Management ............................................................................................ 66
12.4.1 AES3 Channel Status (C) Bit Management ........................................................................ 66
12.4.2 Accessing the E buffer ........................................................................................................ 67
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CS8422
12.4.3 Serial Copy Management System (SCMS) ......................................................................... 68
12.5 Jitter Attenuation .......................................................................................................................... 68
12.6 Jitter Tolerance ............................................................................................................................ 69
12.7 Group Delay ................................................................................................................................. 69
13. PERFORMANCE PLOTS ................................................................................................................... 70
14. PACKAGE DIMENSIONS .................................................................................................................. 79
15. THERMAL CHARACTERISTICS AND SPECIFICATIONS .............................................................. 79
16. ORDERING INFORMATION .............................................................................................................. 80
17. REFERENCES .................................................................................................................................... 80
18. REVISION HISTORY .......................................................................................................................... 81
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CS8422
LIST OF FIGURES
Figure 1.Non-TDM Slave Mode Timing ..................................................................................................... 19
Figure 2.TDM Slave Mode Timing ............................................................................................................ 19
Figure 3.Non-TDM Master Mode Timing ................................................................................................... 19
Figure 4.TDM Master Mode Timing .......................................................................................................... 19
Figure 5.SPI Mode Timing ........................................................................................................................ 20
Figure 6.I²C Mode Timing ......................................................................................................................... 21
Figure 7.Typical Connection Diagram, Software Mode ............................................................................. 22
Figure 8.Typical Connection Diagram, Hardware Mode ........................................................................... 23
Figure 9.Serial Audio Interface Format – I²S ............................................................................................. 26
Figure 10.Serial Audio Interface Format – Left-Justified ........................................................................... 26
Figure 11.Serial Audio Interface Format – Right-Justified (Master Mode only) ........................................ 26
Figure 12.Serial Audio Interface Format – AES3 Direct Output ................................................................ 26
Figure 13.TDM Master Mode Timing Diagram .......................................................................................... 28
Figure 14.TDM Slave Mode Timing Diagram ............................................................................................ 28
Figure 15.TDM Mode Configuration (All CS8422 outputs are slave) ........................................................ 28
Figure 16.TDM Mode Configuration (First CS8422 output is master, all others are slave) ....................... 28
Figure 17.Single-Ended Receiver Input Structure, Receiver Mode 1 ....................................................... 30
Figure 18.Differential Receiver Input Structure ......................................................................................... 31
Figure 19.C/U Data Outputs ...................................................................................................................... 36
Figure 20.Typical Connection Diagram for Crystal Circuit ........................................................................ 38
Figure 21.Hardware Mode Clock Routing ................................................................................................. 39
Figure 22.Control Port Timing in SPI Mode .............................................................................................. 42
Figure 23.Control Port Timing, I²C Slave Mode Write ............................................................................... 43
Figure 24.Control Port Timing, I²C Slave Mode Read ............................................................................... 43
Figure 25.De-Emphasis Filter Response .................................................................................................. 49
Figure 26.Professional Input Circuit - Differential Mode ............................................................................ 65
Figure 27.Transformerless Professional Input Circuit - Differential Mode ................................................. 65
Figure 28.S/PDIF MUX Input Circuit, Single-Ended Receiver Mode 1 Single-Ended Input Circuit –
Differential Mode ....................................................................................................................................... 65
Figure 29.S/PDIF MUX Input Circuit – Digital Mode ................................................................................. 65
Figure 30.TTL/CMOS Input Circuit – Differential Mode ............................................................................ 65
Figure 31.Receiver Input Attenuation – Single-ended Input ..................................................................... 66
Figure 32.Receiver Input Attenuation – Differential Input ......................................................................... 66
Figure 33.Channel Status Data Buffer Structure ....................................................................................... 67
Figure 34.Flowchart for Reading the E Buffer ........................................................................................... 67
Figure 35.CS8422 PLL Jitter Attenuation Characteristics ......................................................................... 68
Figure 36.Jitter Tolerance Template ......................................................................................................... 69
Figure 37.Wideband FFT – 0 dBFS 1 kHz Tone, 48 kHz:48 kHz ............................................................. 70
Figure 38.Wideband FFT – 0 dBFS 1 kHz Tone, 44.1 kHz:192 kHz ........................................................ 70
Figure 39.Wideband FFT – 0 dBFS 1 kHz Tone, 44.1 kHz:48 kHz .......................................................... 70
Figure 40.Wideband FFT – 0 dBFS 1 kHz Tone, 48 kHz:44.1 kHz .......................................................... 70
Figure 41.Wideband FFT – 0 dBFS 1 kHz Tone, 48 kHz:96 kHz ............................................................. 70
Figure 42.Wideband FFT – 0 dBFS 1 kHz Tone, 96 kHz:48 kHz ............................................................. 70
Figure 43.Wideband FFT – 0 dBFS 1 kHz Tone, 192 kHz:48 kHz ........................................................... 71
Figure 44.Wideband FFT – -60 dBFS 1 kHz Tone, 48 kHz:96 kHz .......................................................... 71
Figure 45.Wideband FFT – -60 dBFS 1 kHz Tone, 48 kHz:48 kHz .......................................................... 71
Figure 46.Wideband FFT – -60 dBFS 1 kHz Tone, 44.1 kHz:192 kHz ..................................................... 71
Figure 47.Wideband FFT – -60 dBFS 1 kHz Tone, 44.1 kHz:48 kHz ....................................................... 71
Figure 48.Wideband FFT – -60 dBFS 1 kHz Tone, 48 kHz:44.1 kHz ....................................................... 71
Figure 49.Wideband FFT – -60 dBFS 1 kHz Tone, 96 kHz:48 kHz .......................................................... 72
Figure 50.IMD – 10 kHz and 11 kHz -7 dBFS, 96 kHz:48 kHz ................................................................. 72
Figure 51.Wideband FFT – -60 dBFS 1 kHz Tone, 192 kHz:48 kHz ........................................................ 72
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DS692PP2
CS8422
Figure 52.IMD – 10 kHz and 11 kHz -7 dBFS, 48 kHz:44.1 kHz .............................................................. 72
Figure 53.IMD – 10 kHz and 11 kHz -7 dBFS, 44.1 kHz:48 kHz .............................................................. 72
Figure 54.Wideband FFT – 0 dBFS 20 kHz Tone, 44.1 kHz:48 kHz ........................................................ 72
Figure 55.Wideband FFT – 0 dBFS 80 kHz Tone, 192 kHz:192 kHz ....................................................... 73
Figure 56.Wideband FFT – 0 dBFS 20 kHz Tone, 48 kHz:96 kHz ........................................................... 73
Figure 57.Wideband FFT – 0 dBFS 20 kHz Tone, 48 kHz:48 kHz ........................................................... 73
Figure 58.Wideband FFT – 0 dBFS 20 kHz Tone, 96 kHz:48 kHz ........................................................... 73
Figure 59.Wideband FFT – 0 dBFS 20 kHz Tone, 48 kHz:44.1 kHz ........................................................ 73
Figure 60.THD+N vs. Output Sample Rate – 0 dBFS 1 kHz Tone, Fsi = 192 kHz ................................... 73
Figure 61.THD+N vs. Output Sample Rate – 0 dBFS 1 kHz Tone, Fsi = 48 kHz ..................................... 74
Figure 62.THD+N vs. Output Sample Rate – 0 dBFS 1 kHz Tone, Fsi = 96 kHz ..................................... 74
Figure 63.THD+N vs. Output Sample Rate – 0 dBFS 1 kHz Tone, Fsi = 44.1 kHz .................................. 74
Figure 64.Dynamic Range vs. Output Sample Rate – -60 dBFS 1 kHz Tone, Fsi = 192 kHz ................... 74
Figure 65.THD+N vs. Output Sample Rate – 0 dBFS 1 kHz Tone, Fsi = 32 kHz ..................................... 74
Figure 66.Dynamic Range vs. Output Sample Rate – -60 dBFS 1 kHz Tone, Fsi = 32 kHz ..................... 74
Figure 67.Dynamic Range vs. Output Sample Rate – -60 dBFS 1 kHz Tone, Fsi = 96 kHz ..................... 75
Figure 68.Dynamic Range vs. Output Sample Rate – -60 dBFS 1 kHz Tone, Fsi = 44.1 kHz .................. 75
Figure 69.Frequency Response – 0 dBFS Input ....................................................................................... 75
Figure 70.Passband Ripple - 192 kHz:48 kHz .......................................................................................... 75
Figure 71.Dynamic Range vs. Output Sample Rate – -60 dBFS 1 kHz Tone, Fsi = 48 kHz ..................... 75
Figure 72.Linearity Error – 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:48 kHz ...................................... 75
Figure 73.Linearity Error – 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:44.1 kHz ................................... 76
Figure 74.Linearity Error – 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:96 kHz ...................................... 76
Figure 75.Linearity Error – 0 to -140 dBFS Input, 200 Hz Tone, 96 kHz:48 kHz ...................................... 76
Figure 76.Linearity Error – 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:192 kHz ................................. 76
Figure 77.Linearity Error – 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:48 kHz ................................... 76
Figure 78.Linearity Error – 0 to -140 dBFS Input, 200 Hz Tone, 192 kHz:44.1 kHz ................................. 76
Figure 79.THD+N vs. Input Amplitude – 1 kHz Tone, 48 kHz:44.1 kHz ................................................... 77
Figure 80.THD+N vs. Input Amplitude – 1 kHz Tone, 48 kHz:96 kHz ...................................................... 77
Figure 81.THD+N vs. Input Amplitude – 1 kHz Tone, 96 kHz:48 kHz ...................................................... 77
Figure 82.THD+N vs. Input Amplitude – 1 kHz Tone, 44.1 kHz:192 kHz ................................................. 77
Figure 83.THD+N vs. Input Amplitude – 1 kHz Tone, 44.1 kHz:48 kHz ................................................... 77
Figure 84.THD+N vs. Input Amplitude – 1 kHz Tone, 192 kHz:48 kHz .................................................... 77
Figure 85.THD+N vs. Input Frequency – 0 dBFS, 48 kHz:44.1 kHz ......................................................... 78
Figure 86.THD+N vs. Input Frequency – 0 dBFS, 48 kHz:96 kHz ............................................................ 78
Figure 87.THD+N vs. Input Frequency – 0 dBFS, 44.1 kHz:48 kHz ......................................................... 78
Figure 88.THD+N vs. Input Frequency – 0 dBFS, 96 kHz:48 kHz ............................................................ 78
Figure 89.Total Power Supply Current vs. Differential Mode Receiver Input Sample Frequency ............. 78
DS692PP2
7
CS8422
LIST OF TABLES
Table 1. VLRCK Behavior ......................................................................................................................... 35
Table 2. PLL Clock Ratios ......................................................................................................................... 38
Table 3. Hardware Mode Control Settings ................................................................................................ 40
Table 4. Hardware Mode Serial Audio Format Control ............................................................................. 41
Table 5. Hardware Mode Serial Audio Port Clock Control ........................................................................ 41
Table 6. Summary of Software Register Bits ............................................................................................ 44
Table 7. GPO Pin Configurations .............................................................................................................. 50
Table 8. ISCLK/ILRCK Ratios and SISF Settings ..................................................................................... 53
Table 9. OSCLK1/OLRCK1 Ratios and SOSF1 Settings .......................................................................... 54
Table 10. OSCLK2/OLRCK2 Ratios and SOSF1 Settings ........................................................................ 55
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DS692PP2
CS8422
1. PIN DESCRIPTION
1.1
Software Mode
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
OSCLK2
RX0/RXP0
RX1/RXN0
VA
SDOUT2
VL
AGND
DGND
VD_FILT
V_REG
GPO2
GPO1
Thermal Pad
RX2/RXP1
RX3/RXN1
AD0/CS
AD1/CDIN
Top-Down View
32-Pin QFN Package
9
10
11
12
13
14
15
16
Pin Name
Pin # Pin Description
1
2
5
6
AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or S/PDIF
encoded digital data. RX[3:0] comprise the single-ended input multiplexer. RXP[1:0] comprise the
non-inverting inputs of the differential input multiplexer and RXN[1:0] comprise the inverting inputs
of the differential input multiplexer. Unused inputs should be tied to AGND/DGND.
RX[3:0],
RXP/RXN[1:0]
Analog Power (Input) - Analog power supply, nominally +3.3 V. Care should be taken to ensure
that this supply is as noise-free as possible, as noise on this pin will directly affect the jitter perfor-
mance of the recovered clock.
VA
3
4
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be
connected to a common ground area under the chip.
AGND
Address Bit 0 (I²C) / Software Chip Select (SPI) (Input) - A falling edge on this pin puts the
CS8422 into SPI Control Port Mode. With no falling edge, the CS8422 defaults to I²C Mode. In I²C
Mode, AD0 is a chip address pin. In SPI Mode, CS is used to enable the control port interface on
the CS8422. See “Control Port Description” on page 42.
AD0/CS
7
8
Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input) - In I²C Mode, AD1 is a chip address pin.
In SPI Mode, CDIN is the input data line to the control port interface. See “Control Port Description”
on page 42.
AD1/CDIN
Software Clock (Input) - Serial control interface clock used to clock control data bits into and out of
the CS8422.
SCL/CCLK
9
Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O
data line. In SPI Mode, CDOUT is the output data from the control port interface on the CS8422.
SDA/CDOUT
10
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9
CS8422
Pin Name
Pin # Pin Description
Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “SRC Master
Clock” on page 38 for more details.
XTI
11
12
13
Crystal Out (Output) - Crystal output for Master clock. See “SRC Master Clock” on page 38 for
more details.
XTO
Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDIN pin.
ILRCK
ISCLK
SDIN
14
15
Serial Audio Input Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin.
Serial Audio Input Data Port (Input) - Audio data serial input pin.
16
17
18
30
General Purpose Outputs (Output) - See page 50 for details. In I²C Mode, a 20 kΩ pull-up resistor
to VL on GPO2 will set AD2 chip address bit to 1, otherwise AD2 will be 0.
GPO[3:0]
V_REG
19
Voltage Regulator In (Input) - Regulator power supply input, nominally +3.3 V.
Digital Voltage Regulator (Output) - Digital core voltage regulator output. Should be connected to
digital ground through a 10 µF capacitor. Typically +2.5 V. Cannot be used as an external voltage
source.
VD_FILT
20
Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con-
nected to a common ground area under the chip.
DGND
21
VL
22
23
Logic Power (Input) - Input/Output power supply, typically +1.8 V, +2.5 V, +3.3 V, or +5.0 V.
Serial Audio Output 2 Data Port (Output) - Audio data serial output 2 pin.
SDOUT2
Serial Audio Output 2 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT2
pin.
OSCLK2
OLRCK2
24
25
Serial Audio Output 2 Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT2 pin.
Serial Audio Output 1 TDM Input (Input) - Time Division Multiplexing serial audio data input.
Should remain grounded when not used. See “Time Division Multiplexing (TDM) Mode” on
page 27.
TDM_IN
26
SDOUT1
OSCLK1
27
28
Serial Audio Output 1 Data Port (Output) - Audio data serial output 1 pin.
Serial Audio Output 1 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT 1
pin.
Serial Audio Output 1 Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT 1 pin.
OLRCK1
RMCK
29
31
Recovered Master Clock (Output) - Recovered master clock from the PLL. Frequency is 128x,
192x, 256x, 384x, 512x, 768x, or 1024x Fs, where Fs is the sample rate of the incoming AES3-
compatible data, or ISCLK/64.
Reset (Input) - When RST is low the CS8422 enters a low power mode and all internal states are
reset. On initial power up RST must be held low until the power supply is stable and all input clocks
are stable in frequency and phase.
RST
32
-
Thermal Pad - Thermal relief pad. Should be connected to the ground plane for optimized heat dis-
sipation.
THERMAL PAD
10
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CS8422
1.2
Hardware Mode
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
RXP0
RXN0
VA
OSCLK2
SDOUT2
VL
AGND
RXP1
RXN1
SAOF
DGND
VD_FILT
V_REG
TX/U
Thermal Pad
Top-Down View
32-Pin QFN Package
C
MS_SEL
9
10
11
12
13
14
15
16
Pin Name
Pin #
Pin Description
1
2
5
6
AES3/SPDIF Input (Input) - Differential receiver inputs carrying AES3 or S/PDIF encoded digital
data. RXP[1:0] comprise the non-inverting inputs of the differential input multiplexer; and RXN[1:0]
comprise the inverting inputs of the input multiplexer. Unused inputs should be tied to AGND.
RXP/RXN[1:0]
VA
Analog Power (Input) - Analog power supply, nominally +3.3 V. Care should be taken to ensure that
this supply is as noise-free as possible, as noise on this pin will directly affect the jitter performance of
the recovered clock.
3
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be
connected to a common ground area under the chip.
AGND
4
7
8
9
Serial Audio Output Format Select (Input) - Used to select the serial audio output format after
reset. See Table 4 on page 41 for format settings.
SAOF
Master/Slave Select (Input) - Used to select Master or Slave settings for the input and output serial
audio ports after reset. See Table 5 on page 41 for format settings.
MS_SEL
NV/RERR
Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is output by
default, RERR is selected by a 20 kΩ resistor to VL.
Validity Data/AUDIO (Output) - If a 20 kΩ pull-down is present on this pin, it will output serial Validity
10 data from the AES3 receiver, clocked by the rising and falling edges of OLRCK2 in master mode. If a
V/AUDIO
20 kΩ pull-up is present, the pin will be low when valid linear PCM data is present at the AES3 input.
Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “SRC Master Clock”
on page 38.
XTI
11
XTO
12 Crystal Out (Output) - Crystal output for Master clock. See “SRC Master Clock” on page 38.
DS692PP2
11
CS8422
Pin Name
Pin #
Pin Description
Buffered MCLK (Output) - Buffered output of XTI clock. If a 20 kΩ pull-up resistor to VL is present on
this pin, the SRC MCLK source will be the PLL clock, otherwise it will be the ring oscillator.
MCLK_OUT
13
TX Pin MUX Selection (Input) - Used to select the AES3-compatible receiver input for pass-through
to the TX pin.
TX_SEL
RX_SEL
14
15 Receiver MUX Selection (Input) - Used to select the active AES3-compatible receiver input.
Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status
16 block. Will go high for one subframe during each Z preamble following the first detected Z preamble.
If no Z preamble is detected, output is indeterminate. See Figure 19 on page 36 for more detail.
RCBL
C
Channel Status Data (Output) - Serial channel status data output from the AES3-compatible
17 receiver, clocked by the rising and falling edges of OLRCK2 in master mode. A 20 kΩ pull-up resistor
to VL must be present on this pin to put the part in Hardware Mode.
Receiver MUX Pass-through/User Data (Output) - If no 20 kΩ pull-up resistor is present on this pin
it will output a copy of the receiver mux input selected by the TX_SEL pin. If a 20 kΩ pull-up resistor
to VL is present on this pin, it will output serial User data from the AES3 receiver, clocked by the rising
TX/U
18
and falling edges of OLRCK2 in master mode.
V_REG
19 Voltage Regulator In (Input) - Regulator power supply input, nominally +3.3 V.
Digital Voltage Regulator Out (Output) - Digital core voltage regulator output. Should be connected
to digital ground through a 10 µF capacitor. Cannot be used as an external voltage source.
VD_FILT
20
Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con-
nected to a common ground area under the chip.
DGND
21
VL
22 Logic Power (Input) - Input/Output power supply, typically +1.8 V, +2.5 V, +3.3 V, or +5.0 V.
23 Serial Audio Output 2 Data Port (Output) - Audio data serial output 2 pin.
SDOUT2
OSCLK2
24 Serial Audio Output 2 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT2 pin.
Serial Audio Output 2 Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT2 pin.
OLRCK2
TDM_IN
25
Serial Audio Output 1 TDM Input (Input) - Time Division Multiplexing serial audio data input.
Grounded when not used. See “Time Division Multiplexing (TDM) Mode” on page 27 for details.
26
Serial Audio Output 1 Data Port (Output) - Audio data serial output 1 pin. A 20 kΩ pull-up to VL
SDOUT1
OSCLK1
OLRCK1
27
present on this pin will disable de-emphasis auto detect.
28 Serial Audio Output 1 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT1 pin.
Serial Audio Output 1 Left/Right Clock (Input/Output) - Word rate clock for the audio data on the
SDOUT1 pin.
29
SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking” on
page 37 for more details.
SRC_UNLOCK
RMCK
30
Recovered Master Clock (Output) - Recovered master clock from the PLL. Frequency is 128 x,
256 x, or 512 x Fs, where Fs is the sample rate of the incoming AES3-compatible data or ISCLK/64.
If a 20 kΩ pull-up to VL is present on this pin, the SDOUT2 MCLK source will be RMCK, otherwise it
will be the clock input through XTI-XTO.
31
Reset (Input) - When RST is low the CS8422 enters a low power mode and all internal states are
32 reset. On initial power up RST must be held low until the power supply is stable and all input clocks
are stable in frequency and phase.
RST
Thermal Pad - Thermal relief pad. Should be connected to the ground plane for optimized heat dissi-
pation.
THERMAL PAD
-
12
DS692PP2
CS8422
2. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per-
formance characteristics and specifications are derived from measurements taken at nominal supply voltages and
T = 25° C.)
A
RECOMMENDED OPERATING CONDITIONS
GND = 0 V, all voltages with respect to 0 V.
Parameter
Symbol
Min
Nominal
Max
Units
VL
VA
V_REG
1.71
3.135
3.135
3.3
3.30
3.30
5.25
3.465
3.465
V
V
V
Power Supply Voltage
Ambient Operating Temperature:
Commercial Grade
Automotive Grade
-40
-40
-
-
+85
+105
°C
°C
T
A
ABSOLUTE MAXIMUM RATINGS
DGND = AGND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent
damage to the device. Normal operation is not guaranteed at these extremes.
Parameter
Symbol
Min
Max
Units
VL
VA
V_REG
-0.3
-0.3
-0.3
6.0
4.3
4.3
V
V
V
Power Supply Voltage
Input Current, Any Pin Except Supplies (Note 1)
I
-
±10
mA
V
in
Input Voltage, Any Pin Except RXP[1:0], RXN[1:0], or
RX[3:0]
V
-0.3
VL+0.4
in
Input Voltage, RXP[1:0], RXN[1:0], or RX[3:0]
Ambient Operating Temperature (power applied)
Storage Temperature
V
-0.3
-55
-65
VA+0.4
+125
V
in
T
°C
°C
A
T
+150
stg
Notes:
1. Transient currents of up to 100 mA will not cause SCR latch-up.
DS692PP2
13
CS8422
PERFORMANCE SPECIFICATIONS - SAMPLE RATE CONVERTER
XTI-XTO = 24.576 MHz; Input signal = 1.000 kHz, Measurement Bandwidth = 20 to Fso/2 Hz, and
Word Width = 24-Bits. (Note 2)
Parameter
Min
Typ
Max
Units
Resolution
16
-
24
bits
Sample Rate
Slave XTI/2048
Master XTI/512
-
-
XTI/128
XTI/128
kHz
kHz
Sample Rate Ratio - Upsampling
Sample Rate Ratio - Downsampling
Interchannel Gain Mismatch
Interchannel Phase Deviation
Gain Error
-
-
-
1:6
6:1
-
Fsi:Fso
Fsi:Fso
dB
-
-
0.0
0.0
-
-
-0.2
-
-
Degrees
dB
0
Peak Idle Channel Noise Component
Dynamic Range - Unweighted (20 Hz to Fso/2, -60 dBFS Input)
32 kHz:48 kHz
-
-144
dBFS
-
-
-
-
-
-
-
140
141
138
140
141
140
141
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
44.1 kHz:48 kHz
44.1 kHz:192 kHz
48 kHz:44.1 kHz
48 kHz:96 kHz
96 kHz:48 kHz
192 kHz:32 kHz
Total Harmonic Distortion + Noise (20 Hz to Fso/2, 0 dBFS Input)
32 kHz:48 kHz
-
-
-
-
-
-
-
-134
-134
-133
-131
-135
-136
-137
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
44.1 kHz:48 kHz
44.1 kHz:192 kHz
48 kHz:44.1 kHz
48 kHz:96 kHz
96 kHz:48 kHz
192 kHz:32 kHz
Notes:
2. Fsi indicates the input sample rate. Fso indicates the output sample rate. Numbers separated by a colon
indicate the ratio of Fsi to Fso.
DIGITAL FILTER CHARACTERISTICS
Parameter
Min
Typ
Max
Units
0.4535*
min(Fsi,Fso)
-
-
Fs
Passband (Upsampling or Downsampling)
Passband Ripple
-
-
-
-
± 0.05
dB
Fs
dB
0.5465*Fso
Stopband (Downsampling)
Stopband Attenuation
Group Delay
-
-
125
See “Group Delay” on page 69
14
DS692PP2
CS8422
DC ELECTRICAL CHARACTERISTICS
AGND = DGND = 0 V; all voltages with respect to 0 V.
Parameter
Min
Typ
Max
Units
Power-Down Mode (Note 3)
Supply Current in power down
VA
V_REG
VL = 1.8 V
VL = 2.5 V
VL = 3.3 V
VL = 5.0 V
-
-
-
-
-
-
4.7
1
0.3
7.1
16.9
102.6
-
-
-
-
-
-
µA
µA
µA
µA
µA
µA
Normal Operation (Note 4)
-
-
-
-
-
-
7.6
9.4
2.7
3.8
5.2
24
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
Supply Current at 48 kHz Fsi and Fso
VA
V_REG
VL = 1.8 V
VL = 2.5 V
VL = 3.3 V
VL = 5.0 V
-
-
-
-
-
-
32.4
18.9
6.2
8.8
12
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
Supply Current at 192 kHz Fsi and Fso
VA
V_REG
VL = 1.8 V
VL = 2.5 V
VL = 3.3 V
VL = 5.0 V
50.4
Notes:
3. Power-Down Mode is defined as RST = LOW with all clocks and data lines held static and no crystal
attached across XTI - XTO.
4. Normal operation is defined as RST = HIGH. The typical values shown were measured with the digital
interface receiver in differential mode, serial audio output port 1 in master mode sourced by the SRC,
and serial audio output port 2 in master mode sourced by the AES3 receiver output.
DS692PP2
15
CS8422
DIGITAL INTERFACE SPECIFICATIONS
AGND = DGND = 0 V; all voltages with respect to 0 V.
Parameter
Symbol
Min
Typ
Max
+32
-
Units
μA
Input Leakage Current (Note 5)
I
-
-
-
in
Input Capacitance
I
8
pF
in
Digital Interface Receiver - RXP[1:0], RXN[1:0], RX[3:0]
Differential Input Sensitivity, RXP to RXN (Note 6)
Differential Input Impedance, RXP and RXN to GND
-
-
-
-
11
-
200
-
mVpp
kΩ
Single-Ended Input Sensitivity, RX pins, Receiver Input Mode 1
(Note 6)
200
mVpp
Single-Ended Input Impedance, RX pins, Receiver Input Mode 1
High-Level Input Voltage, RX pins in Digital mode
-
11
-
-
kΩ
V
0.55xVA
VA+0.3
V
IH
-
Low-Level Input Voltage, RX pins in Digital mode
V
-0.3
0.8
V
IL
Digital I/O
-
-
High-Level Output Voltage (I = -4 mA)
V
.77xVL
-
-
0.6
-
V
V
V
OH
OH
Low-Level Output Voltage (I = 4 mA)
V
OL
OL
-
High-Level Input Voltage
V
0.65xVL
IH
-
Low-Level Input Voltage
Input Hysteresis
V
-
-
0.3xVL
-
V
V
IL
0.2
Notes:
5. When a digital signal is sent to the AES RX pins, the pins will draw approximately 730 µA from the digital
signal’s supply from the time reset is de-asserted until the RX_MODE, RX_SEL, and INPUT_TYPE bits
in register 03h are properly configured to allow a digital input signal on the driven pins, see Section 11.3
on page 48.
6. Maximum sensitivity in accordance with AES3-2003 section 8.3.3. Measured with eye diagram height
at the specified voltage and width of at least 50% of one-half the biphase symbol period.
16
DS692PP2
CS8422
SWITCHING SPECIFICATIONS
Inputs: Logic 0 = 0 V, Logic 1 = VL; C = 20 pF.
L
Parameter
Symbol
Min
1
Typ
Max
-
Units
ms
RST pin Low Pulse Width (Note 7)
-
-
PLL Clock Recovery Sample Rate Range (Note 8)
28
216
kHz
RMCK Output Jitter (Note 9)
Differential RX Mode
Single-Ended RX Mode
-
-
200
475
-
-
ps RMS
ps RMS
RMCK Output Duty Cycle
XTI Frequency
45
12
50
-
55
27.000
49.152
-
%
MHz
MHz
ns
Crystal
Digital Clock Source
1.024
9
-
XTI Pulse Width High/Low
MCLK_OUT Duty Cycle
-
45
-
55
%
VL = 3.3 V, 5 V
RMCK Output Frequency
MCLK_OUT Frequency
Slave Mode
-
-
-
-
49.152
49.152
MHz
MHz
ISCLK Frequency
ISCLK High Time
ISCLK Low Time
-
-
-
-
-
-
-
-
-
-
49.152
MHz
ns
t
t
9.2
9.2
-
-
sckh
t
-
ns
sckl
OSCLK Frequency
OSCLK High Time
OSCLK Low Time
26.9
MHz
ns
16.7
16.7
5.7
4.2
-
-
sckh
t
-
ns
sckl
lcks
lckd
I/OLRCK Edge to I/OSCLK Rising Edge
I/OSCLK Rising Edge to I/OLRCK Edge
t
-
-
ns
t
ns
OSCLK Falling Edge/OLRCK Edge to SDOUT Output
Valid
t
13.7
ns
dpd
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
TDM Mode OLRCK High Time (Note 10)
t
2.2
5.5
20
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ds
t
dh
t
lrckh
TDM Mode OLRCK Rising Edge to OSCLK Rising Edge
t
5.3
4.2
fss
fsh
TDM Mode OSCLK Rising Edge to OLRCK Falling Edge
Master Mode
t
I/OSCLK Frequency (non-TDM Mode)
I/OLRCK Duty Cycle
48*Fsi/o
-
-
-
-
-
128*Fsi/o
50.5
55
MHz
%
49.5
I/OSCLK Duty Cycle
45
-
%
I/OSCLK Falling Edge to I/OLRCK Edge
OSCLK Falling Edge to SDOUT Output Valid
t
4.2
ns
lcks
t
-
4.6
ns
dpd
DS692PP2
17
CS8422
Parameter
Symbol
Min
Typ
Max
Units
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
t
2.2
-
-
ns
ds
dh
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
TDM Mode OSCLK Frequency (Note 11)
t
5.5
-
-
-
-
ns
MHz
ns
-
-
49.152
4.2
TDM Mode OSCLK Falling Edge to OLRCK Edge
t
fsm
VL = 1.8 V, 2.5 V
RMCK Output Frequency
MCLK_OUT Frequency
Slave Mode
-
-
-
-
31
31
MHz
MHz
ISCLK Frequency
-
9.2
9.2
-
-
-
-
-
-
-
-
-
-
49.152
MHz
ns
ISCLK High Time
t
t
-
sckh
ISCLK Low Time
t
-
ns
sckl
OSCLK Frequency
15.7
MHz
ns
OSCLK High Time
28.7
28.7
7.4
6.2
-
-
sckh
OSCLK Low Time
t
-
ns
sckl
lcks
lckd
I/OLRCK Edge to I/OSCLK Rising Edge
I/OSCLK Rising Edge to I/OLRCK Edge
t
-
-
ns
t
ns
OSCLK Falling Edge/OLRCK Edge to SDOUT Output
Valid
t
25.6
ns
dpd
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
TDM Mode OLRCK High Time (Note 10)
t
4.7
7.3
20
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ds
t
dh
t
lrckh
TDM Mode OLRCK Rising Edge to OSCLK Rising Edge
t
7.0
6.2
fss
fsh
TDM Mode OSCLK Rising Edge to OLRCK Falling Edge
Master Mode
t
I/OSCLK Frequency (non-TDM Mode)
I/OLRCK Duty Cycle
48*Fsi/o
-
-
-
-
-
128*Fsi/o
55
MHz
%
45
45
-
I/OSCLK Duty Cycle
55
%
I/OSCLK Falling Edge to I/OLRCK Edge
OSCLK Falling Edge to SDOUT Output Valid
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
t
5.7
ns
lcks
t
-
5.4
ns
dpd
t
4.7
-
-
ns
ds
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
TDM Mode OSCLK Frequency (Note 11)
TDM Mode OSCLK Falling Edge to OLRCK Edge
Notes:
t
7.3
-
-
-
-
ns
MHz
ns
dh
-
-
31
5.7
t
fsm
7. After powering up the CS8422, RST should be held low until the power supplies and clocks are settled.
8. If ISCLK is selected as the clock source for the PLL, then the Sample Rate = ISCLK/64.
18
DS692PP2
CS8422
9. Typical base band jitter in accordance with AES-12id-2006 section 3.4.2. Measurements are Time In-
terval Error (TIE) taken with 3rd order 100 Hz to 40 kHz band-pass filter. Measured with Sample Rate
= 48 kHz.
10. OLRCK must remain high for at least 1 OSCLK period and at most 255 OSCLK periods in TDM Mode.
11. In TDM formatted master mode, the OSCLK frequency is fixed at 256*OLRCK.
tlrckh
I/OLRCK
(input)
tlckd
tlcks
tsckh
tsckl
OLRCK
(input)
tfsh
tfss
tsckh
tsckl
I/OSCLK
(input)
OSCLK
tds
tdh
(input)
tds
tdh
SDIN
MSB
MSB-1
MSB-1
(input)
TDM_IN
MSB
MSB-1
MSB-1
(input)
tdpd
tdpd
SDOUT
MSB
(output)
SDOUT
MSB
(output)
Figure 1. Non-TDM Slave Mode Timing
Figure 2. TDM Slave Mode Timing
I/OLRCK
(output)
tlcks
OLRCK
(output)
tfsm
I/OSCLK
(output)
OSCLK
(output)
tds
tdh
tds
tdh
TDM_IN
MSB
MSB
SDIN
MSB-1
MSB-1
MSB
MSB
MSB-1
MSB-1
(input)
(input)
tdpd
tdpd
SDOUT
(output)
SDOUT
(output)
Figure 3. Non-TDM Master Mode Timing
Figure 4. TDM Master Mode Timing
DS692PP2
19
CS8422
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
Inputs: Logic 0 = 0 V, Logic 1 = VL; C = 20 pF.
L
Parameter
CCLK Clock Frequency
Symbol
Min
Max
Unit
f
0
6.0
MHz
sck
t
500
500
1.0
20
66
66
40
15
-
-
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RST Rising Edge to CS Falling
CCLK Edge to CS Falling (Note 12)
CS High Time Between Transmissions
CS Falling to CCLK Edge
srs
t
-
-
spi
t
csh
t
-
css
t
-
CCLK Low Time
scl
t
-
CCLK High Time
sch
t
-
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time (Note 13)
CCLK Falling to CDOUT Valid (Note 14)
Time from CS Rising to CDOUT High-Z
CDOUT Rise Time
dsu
t
-
dh
t
100
100
25
25
100
100
scdov
t
-
cscdo
t
-
r1
t
-
CDOUT Fall Time
f1
t
-
CCLK and CDIN Rise Time (Note 15)
CCLK and CDIN Fall Time (Note 15)
r2
t
-
f2
Notes:
12. t only needed before first falling edge of CS after RST rising edge. t = 0 at all other times.
spi
spi
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. CDOUT should not be sampled during this time.
15. For f < 1 MHz.
sck
RST
CS
t
t
srs
t
t
t
sch
spi css
scl
t
csh
CCLK
t
t
r2
f2
CDIN
t
t
dsu
dh
Hi-Impedance
CDOUT
t
t
t
cscdo
scdov
scdov
Figure 5. SPI Mode Timing
20
DS692PP2
CS8422
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE
Inputs: Logic 0 = 0 V, Logic 1 = VL; C = 20 pF.
L
Parameter
SCL Clock Frequency
Symbol
Min
Max
Unit
f
-
100
kHz
scl
t
500
4.7
4.0
4.7
4.0
4.7
10
-
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
ns
RST Rising Edge to Start
irs
t
-
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
buf
t
-
hdst
t
-
low
t
-
Clock High Time
high
t
-
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 16)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
sust
t
-
-
hdd
t
250
-
sud
t , t
1000
300
-
rc rd
t , t
-
Fall Time SCL and SDA
fc fd
t
4.7
300
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
susp
t
1000
ack
Notes:
16. Data must be held for sufficient time to bridge the transition time, t , of SCL.
fc
R S T
t
irs
R e p e a te d
Stop
S ta rt
Stop
S ta rt
t
t
rd
fd
S D A
S C L
t
t
t
t
t
buf
t
high
hdst
fc
susp
hdst
lo w
t
t
t
t
t
t
sust
sud
ack
rc
hdd
Figure 6. I²C Mode Timing
DS692PP2
21
CS8422
3. TYPICAL CONNECTION DIAGRAMS
3.1
Software Mode
+3.3V
10 µF
0.1 µF
+
+3.3V
+1.8V to +5V
10 µF
0.1 µF
0.1 µF
+
19
3
22
20
VD_FILT
0.1 µF
10 µF
+
1
2
5
5
RX0/RXP0
RX1/RXN0
RX2/RXP1
RX3/RXN1
28
29
27
OSCLK1
OLRCK1
SDOUT1
Serial Audio Input
Device
AES3/SPDIF/IEC60958
Receiver Circuitry
See section 12.3 for details.
TDM Output Device
13
14
15
ILRCK
ISCLK
SDIN
Serial Audio Output
Device
26
31
TDM_IN
RMCK
CS8422
25
24
23
11
12
OLRCK2
OSCLK2
SDOUT2
XTI
Crystal/Clock Source
Serial Audio Input
Device
XTO
+VL
20 kΩ
7
8
AD0/CS
30
18
17
16
GPO3
GPO2
GPO1
GPO0
AD1/CDIN
SCL/CCLK
SDA/CDOUT
RST
Clock Routing,
Interrupt Control,
Channel-Status, and
User Data Output
Microcontroller
9
10
32
4
21
Figure 7. Typical Connection Diagram, Software Mode
22
DS692PP2
CS8422
3.2
Hardware Mode
+3.3V
0.1 µF
10 µF
+
+3.3V
+1.8V to +5V
0.1 µF
10 µF
+
0.1 µF
3
19
22
VD_FILT
20
1
RXP0
10 µF
0.1 µF
+VL
+
2
5
6
AES3/SPDIF/IEC60958
Receiver Circuitry
See section 12.3 for details.
RXN0
RXP1
RXN1
20 kΩ
27
28
29
SDOUT1
OSCLK1
OLRCK1
Serial Audio Input
Device
+VL
20 kΩ
18
9
TX/U
TDM Output Device
26
NV/RERR
V/AUDIO
C
TDM_IN
CS8422
Channel Status, User, and
Validity Data Handling and
TX Passthrough
10
17
16
30
+VL
20 kΩ
RCBL
MCLK_OUT
13
SRC_UNLOCK
25
24
23
OLRCK2
OSCLK2
SDOUT2
20 kΩ
Serial Audio Input
Device
8
MS_SEL
SAOF
+VL
7
20 kΩ
RMCK 31
Hardware Control Circuitry
14
15
32
TX_SEL
RX_SEL
RST
11
XTI
Crystal/Clock
Source
12
XTO
21
4
Figure 8. Typical Connection Diagram, Hardware Mode
DS692PP2
23
CS8422
4. OVERVIEW
The CS8422 is a 24-bit, high performance, monolithic CMOS stereo asynchronous sample rate converter with inte-
grated digital audio interface receiver that decodes audio data according to EIAJ CP1201, IEC-60958, AES3, and
S/PDIF interface standards.
Audio data is input through either a 3-wire serial audio port or the AES3-compatible digital interface receiver. Audio
data is output through one of two 3-wire serial audio output ports. The serial audio ports are capable of 24-, 20-, 18-
, or 16-bit word lengths. Data in to the digital interface receiver can be up to 24-bit. Input and output data can be
completely asynchronous, synchronous to an external data clock through XTI, or synchronous to the master clock
recovered from the incoming S/PDIF or AES3 data.
CS8422 can be controlled either in Software Mode or in a stand-alone Hardware Mode. In Software Mode, the user
can control the device through either a SPI or I²C control port.
Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mix-
ing consoles, high quality D/A, effects processors, computer audio systems, and automotive audio systems.
Figure 7 and Figure 8 show typical connections to the CS8422.
5. THREE-WIRE SERIAL INPUT/OUTPUT AUDIO PORT
The CS8422 provides two independent 3-wire serial audio output ports, and a 3-wire serial audio input (only avail-
able in Software Mode). The interface format should be chosen to suit the attached device either through the control
port in Software Mode, or through the MS_SEL and SAOF pins in Hardware Mode. The following parameters are
adjustable:
Hardware Mode
•
•
•
•
•
Master or slave mode operation
Master-mode MCLK-to-OLRCK (OLRCK1 and OLRCK2) ratios: 128, 256, and 512
Audio data resolution of 16, 20, or 24 bits
Left-justified, I²S, or Right-justified serial data formats
Multi-channel TDM serial audio format (Serial Audio Output 1 only)
Software Mode
•
•
Master or slave mode operation
Master-mode MCLK-to-ILRCK and MCLK-to-OLRCK (OLRCK1 and OLRCK2) ratios: 64, 128, 192, 256,
384, 512, 768, and 1024
•
•
•
•
Audio data resolution of 16, 18, 20, or 24 bits
Left-justified, I²S, or Right-justified serial data formats
Multi-channel TDM serial audio format
AES3 Direct Output format
Figures 9, 10, 11, and 12 show the standard input/output formats available. The TDM serial audio format is de-
scribed in Section 5.1.5 on page 27. For more information about serial audio formats, refer to the Cirrus Logic ap-
plications note AN282, “The 2-Channel Serial Audio Interface: A Tutorial”, available at www.cirrus.com.
24
DS692PP2
CS8422
5.1
Serial Port Clock Operation
5.1.1
Master Mode
When a serial port is set to master mode, its left/right clock (ILRCK, OLRCK1, or OLRCK2), and its serial
bit-clock (ISCLK, OSCLK1, or OSCLK2) are outputs. If a serial output is sourced directly by the AES3 re-
ceiver, then that serial port’s left/right clock and serial bit-clock will be synchronous with RMCK. If a serial
port is routed to or from the sample rate converter (SRC), then that serial port’s left/right clock and serial
bit-clock can be synchronous with either the XTI-XTO or RMCK when it is in master mode.
If a serial output is source directly by the serial input port without the use of the SRC, then all associated
clocks must be synchronous, so both serial ports must use the same master clock source. It is for this
reason that, when in this mode, the serial output clock control is done through the Serial Audio Input Clock
Control (07h) register.
5.1.2
Slave Mode
When a serial port is in slave mode, its left/right clock (ILRCK, OLRCK1, or OLRCK2), and its serial bit-
clock (ISCLK, OSCLK1, or OSCLK2) are inputs. If the serial input or a serial output has the SRC in its
data path, then the serial port’s LRCK and SCLK may be asynchronous to all other serial ports. The
left/right clock should be continuous, but the duty cycle can be less than 50% if enough serial clocks are
present in each associated LRCK phase to clock all of the data bits.
If there are fewer SCLK periods than required to clock all the bits present in one half LRCK period in Left-
Justified and I²S Modes, data will be truncated beginning with the LSB. In Right-Justified Modes, the data
will be invalid.
If a serial audio output is operated in slave mode and sourced directly by the AES3 receiver or the serial
input port without the use of the sample rate converter, then the OLRCK supplied to the serial audio output
should be synchronous to Fsi or ILRCK to avoid skipped or repeated samples. The OSLIP bit (“Interrupt
Status (14h)” on page 59) is provided to indicate when skipped or repeated samples occur.
If the input sample rate, Fsi or ILRCK, is greater than the slave-mode OLRCK frequency, then dropped
samples will occur. If Fsi or ILRCK is less than the slave-mode OLRCK frequency, then samples will be
repeated. In either case the OSLIP bit will be set to 1 and will not be cleared until read through the control
port.
5.1.3
Hardware Mode Control
In Hardware Mode, the serial audio input port is not available. SDOUT1 is the serial data output from the
sample rate converter, and SDOUT2 is the serial audio output directly from the AES3-compatible receiver.
Because there is no serial audio input available in Hardware Mode, all audio data input is done through
the AES3-compatible receiver. In Hardware Mode, the serial output ports are controlled through the SAOF
and MS_SEL pins. See “Hardware Mode Serial Audio Port Control” on page 40 for more details.
In Hardware Mode, there are always 64 SCLK periods per LRCK period when a serial port is set to master
mode.
5.1.4
Software Mode Control
In Software Mode, the CS8422 provides a serial audio input port and two serial audio output ports. Each
serial port’s clocking and data routing options are fully configurable as shown in Serial Audio Input Data
Format (0Bh), Serial Audio Output Data Format - SDOUT1 (0Ch), and Serial Audio Output Data Format
- SDOUT2 (0Dh) registers, found on pages 53, 54, and 55.
DS692PP2
25
CS8422
Channel A
Channel B
I/OLRCK
I/OSCLK
SDIN
SDOUT
M SB
LS B
M SB
LSB
MSB
Figure 9. Serial Audio Interface Format – I²S
I/OLRCK
I/OSCLK
Channel A
Channel B
SDIN
SDOUT
M SB
LS B
M SB
LSB
MSB
Figure 10. Serial Audio Interface Format – Left-Justified
Channel A
Channel B
I/OLRCK
I/OSCLK
SDIN
MSB
MSB
LSB
LSB
MSB
MSB
LSB
LSB
MSB Extended
MSB Extended
SDOUT
Figure 11. Serial Audio Interface Format – Right-Justified (Master Mode only)
OLRCK
OSCLK
SDOUT
Channel A
Channel B
LSB
MSB
V
U
C
Z
LSB
MSB
V
U
C
Z
Figure 12. Serial Audio Interface Format – AES3 Direct Output
26
DS692PP2
CS8422
5.1.5
Time Division Multiplexing (TDM) Mode
TDM Mode allows several TDM-compatible devices to be serially connected together allowing their cor-
responding serial output data to be multiplexed onto one line for input into a DSP or other TDM capable
input device.
In TDM Mode, the TDM_IN pin is used to input TDM-formatted data while the SDOUT1 or SDOUT2 (Soft-
ware Mode only) pin is used to output TDM data. If the CS8422 is the first TDM device in the chain, it
should have its TDM_IN connected to GND. Data is transmitted from SDOUTx (SDOUT1 or SDOUT2)
most significant bit first on the first falling OSCLKx edge after an OLRCKx rising edge and is valid on the
rising edge of OSCLKx.
5.1.5.1 TDM Master Mode
In TDM master mode, OSCLKx frequency is fixed at 256*OLRCKx (where x = 1 or x = 2 depending on
which serial output port is selected as being in TDM Mode). Each sample time slot is 32 bit-clock periods
long; providing 8 channels of digital audio multiplexed together, with the first two channels being supplied
by the CS8422 which has been placed in master mode. An OSCLKx-wide OLRCKx pulse identifies the
start of a new frame, with the valid data sample beginning one OSCLKx after the OLRCKx rising edge. In
TDM master mode, the master clock source for the TDM serial port must be 256, 512, or 1024*Fso. Valid
data lengths are 16, 18, 20, or 24 bits. Figure 13 shows the interface format for TDM master mode.
5.1.5.2 TDM Slave Mode
In TDM slave mode, the number of channels that can by multiplexed to one serial data line depends on
the output sample rate. For slave mode, OSCLKx must operate at N*64*Fso, where N is the number of
CS8422’s in the TDM chain. For example, if Fso = 96 kHz, N = 4 (8 channels of serial audio data),
OSCLKx frequency must be 24.576 MHz. Note that the maximum OSCLKx frequency in slave mode is a
function of the VL supply voltage, as shown in “Switching Specifications” on page 17. Figure 14 shows
the interface format for TDM slave mode.
5.1.5.3 Hardware Mode Control
In Hardware Mode, TDM Mode is selected through the SAOF pin. See Section 8.1 on page 40 for more
details.
5.1.5.4 Software Mode Control
In Software Mode, TDM Mode is selected through the Serial Audio Output Data Format - SDOUT1 (0Ch)
register, found on page 54.
DS692PP2
27
CS8422
OLRCK
OSCLK
SDOUT/
TDM_IN
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
SDOUT 4, ch A
32 OSCLKs
SDOUT 4, ch B
32 OSCLKs
SDOUT 3, ch A
32 OSCLKs
SDOUT 3, ch B
32 OSCLKs
SDOUT 2, ch A
32 OSCLKs
SDOUT 2, ch B
32 OSCLKs
SDOUT 1, ch A
32 OSCLKs
SDOUT 1, ch B
32 OSCLKs
Data
MSB
LSB
Figure 13. TDM Master Mode Timing Diagram
OLRCK
OSCLK
SDOUT/
TDM_IN
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
SDOUT 4, ch A
32 OSCLKs
SDOUT 4, ch B
32 OSCLKs
SDOUT 3, ch A
32 OSCLKs
SDOUT 3, ch B
32 OSCLKs
SDOUT 2, ch A
32 OSCLKs
SDOUT 2, ch B
32 OSCLKs
SDOUT 1, ch A
32 OSCLKs
SDOUT 1, ch B
32 OSCLKs
Data
MSB
LSB
Figure 14. TDM Slave Mode Timing Diagram
CS84221
CS84222
CS84223
CS84224
DSP
OLRCK
OSCLK
SDOUT
OLRCK
OLRCK
OLRCK
LRCK
OSCLK
SDOUT
OSCLK
SDOUT
OSCLK
SDOUT
SCLK
SDIN
TDM_IN
ILRCK
ISCLK
TDM_IN
ILRCK
ISCLK
SDIN
TDM_IN
ILRCK
ISCLK
SDIN
TDM_IN
ILRCK
ISCLK
SDIN
Slave
Slave
Slave
Slave
Master
SDIN
OLRCK OSCLK SDOUT
OLRCK OSCLK SDOUT
OLRCK OSCLK SDOUT
OLRCK OSCLK SDOUT
PCM Source 1
PCM Source 2
PCM Source 3
PCM Source 4
Figure 15. TDM Mode Configuration (All CS8422 outputs are slave)
CS84221
CS84222
CS84223
CS84224
DSP
OLRCK
OLRCK
OLRCK
OLRCK
LRCK
OSCLK
SDOUT
OSCLK
SDOUT
OSCLK
SDOUT
OSCLK
SDOUT
SCLK
SDIN
TDM_IN
ILRCK
ISCLK
SDIN
TDM_IN
ILRCK
ISCLK
SDIN
TDM_IN
ILRCK
ISCLK
SDIN
TDM_IN
ILRCK
ISCLK
SDIN
Master
Slave
Slave
Slave
Slave
OLRCK OSCLK SDOUT
OLRCK OSCLK SDOUT
OLRCK OSCLK SDOUT
OLRCK OSCLK SDOUT
PCM Source 1
PCM Source 2
PCM Source 3
PCM Source 4
Figure 16. TDM Mode Configuration (First CS8422 output is master, all others are slave)
DS692PP2
28
CS8422
6. DIGITAL INTERFACE RECEIVER
The CS8422 includes a digital interface receiver that can receive and decode audio data according to the AES3,
IEC60958, S/PDIF, and EIJ CP1201 interface standards.
The CS8422 uses either a 4:1 single-ended or 2:1 differential input mux to select the input pin(s) that will receive
input data to be decoded. A low-jitter clock (RMCK) is recovered using a PLL, which provides the digital interface
receiver with a master clock. The decoded audio data can either be routed through the SRC for sample rate con-
version, or can be an output on one of two serial audio output ports. The channel status and Q-subcode data portion
of the user data are assembled and buffered in Channel Status Registers (23h - 2Ch) and Q-Channel Subcode (19h
- 22h), and may be accessed through the control port in either SPI or I²C Mode.
6.1
AES3 and S/PDIF Standards
This document assumes that the user is familiar with the AES3 and S/PDIF data formats. It is advisable to
have current copies of the AES3, IEC60958, IEC61937, and EIJ CP1201 specifications on hand for easy
reference.
The latest AES3 standard is available from the Audio Engineering Society at www.aes.org. The latest
IEC60958/61937 standard is available from the International Electrotechnical Commission at www.iec.ch.
The latest EIAJ CP-1201 standard is available from the Japanese Electronics Bureau at www.jei-
ta.or.jp/eiaj/.
Application Note 22: Overview of Digital Audio Interface Data Structures, available at www.cirrus.com, con-
tains a useful tutorial on digital audio specifications, but it should not be considered a substitute for the stan-
dards.
The paper titled An Understanding and Implementation of the SCMS Serial Copy Management System for
Digital Audio Transmission, by Clifton Sanchez, is an excellent tutorial on SCMS. It is available from the
AES as reprint 3518.
6.2
Receiver Input Multiplexer
The CS8422’s receiver input multiplexer allows input of data compatible with AES3, S/PDIF, IEC60958, and
EIAJ CP-1201 standards. For information about recommended receiver input circuits, see “External Receiv-
er Components” on page 64.
6.2.1
Hardware Mode Control
In Hardware Mode, the receiver input multiplexer is limited to a selection between two differential inputs,
RXP0/RXN0 and RXP1/RXN1. The receiver input multiplexer will decode data present at the differential
input selected by the RX_SEL pin. See Section 8. “Hardware Mode Control” on page 39 for more details.
Multiplexer inputs are floating when not selected. Unused inputs should be tied to AGND/DGND
6.2.2
Software Mode Control
In Software Mode, CS8422 offers either a 4:1 single-ended, or a 2:1 differential input multiplexer to ac-
commodate switching between up to four channels of AES3 or S/PDIF-compatible data input. In Single-
Ended Mode, the CS8422 can switch between four single-ended signals present at RX[3:0]. In differential
mode, the CS8422 can switch between two differential signals, present on RXP0/RXN0 and RXP1/RXN1.
Multiplexer inputs are floating when not selected. Unused inputs should be tied to AGND/DGND
In Software Mode, the receiver input multiplexer is controlled through the register described in Section
11.3 “Receiver Input Control (03h)” on page 48.
DS692PP2
29
CS8422
6.2.2.1 Single-Ended Input Mode
When the receiver input multiplexer is set to Single-Ended Mode, the receiver inputs can be switched be-
tween operation as comparator inputs or digital inputs.
Receiver Input Mode 1 (Analog Sensitivity Mode)
If Mode 1 is selected, the inputs are biased at VA/2 and should be coupled through a capacitor. The rec-
ommended value for the AC coupling capacitors is 0.01 µF to 0.1 µF. The recommended dielectrics for
the AC coupling capacitors are C0G or X7R.
When the receiver input multiplexer is in Mode 1, the receiver input pins allow very low amplitude signals
to be decoded reliably. In this mode, the maximum allowable input amplitude is determined by VA, which
is nominally 3.3 volts. If input amplitudes greater than 3.3 Volts to a single pin of the receiver input multi-
plexer are required, then attenuation is necessary prior to the receiver input to avoid damage to the part
(See “Attenuating Input signals” on page 65 for more details). Figure 17 shows the input structure of the
receiver in Single-Ended Mode.
VA
22 kΩ
22 kΩ
(22000/N) Ω
+
RX[3:0]
-
(1500 + 1500/N) Ω
(22000/N) Ω
AGND
Note:
1. If RX[3:0] is selected by either the receiver MUX or the TX pass-through MUX, N=1.
2. If RX[3:0] is selected by both the receiver MUX and the TX pass-through MUX, N=2.
3. If RX[3:0] is not selected at all, N=0 (i.e. high impedance).
Figure 17. Single-Ended Receiver Input Structure, Receiver Mode 1
Receiver Input Mode 2 (Digital Sensitivity Mode)
If Mode 2 is selected, the receiver inputs should be driven by a digital signal referenced to VA. In this
mode, the selected receiver input is not biased, and does not require the use of an AC coupling capacitor
(as with the use of a typical optical receiver output).
When the receiver input multiplexer is in Mode 2 the specifications for V /V apply (see “Switching Spec-
IH IL
ifications” on page 17 for more details).
6.2.2.2 Differential Input Mode
When the receiver input multiplexer is set to differential input mode, the inputs are biased at VA/2, and
require the use of AC coupling capacitors, as mentioned in Section 6.2.2.1. Figure 18 shows the structure
of the receiver in differential mode.
30
DS692PP2
CS8422
VA
(22000/N) Ω
(22000/N) Ω
(1500 + 1500/N) Ω
(1500 + 1500/N) Ω
RXN[1:0]
RXP[1:0]
+
-
(22000/N) Ω
(22000/N) Ω
AGND
Note:
1. If RXP/N[1:0] is selected by either the receiver MUX or the TX pass-through MUX, N=1.
2. If RXP/N[1:0] is selected by both the receiver MUX and the TX pass-through MUX, N=2.
3. If RXP/N[1:0] is not selected at all, N=0 (i.e. high impedance).
Figure 18. Differential Receiver Input Structure
6.3
Recovered Master Clock - RMCK
The CS8422 has an internal PLL which recovers a high-frequency system clock, referred to as the recov-
ered master clock (RMCK). RMCK can be generated by incoming AES3-compatible data or the ISCLK
(slave mode and Software Mode only). This clock is used as the master clock source for the AES3 receiver
and the master-mode serial port that it directly supplies data to, and is available as an output on the RMCK
pin. In addition, the user can set the RMCK as the master clock of either of the two remaining serial ports.
6.3.1
6.3.2
Hardware Mode Control
In Hardware Mode, the RMCK frequency is determined by the incoming AES3 frame rate and the
MS_SEL pin. RMCK can be routed for use as the master clock for the serial audio output associated with
SDOUT1 by connecting a 20 kΩ resistor from the RMCK pin to VL. See “Hardware Mode Control” on
page 39 for more details.
Software Mode Control
In Software Mode, The RMCK frequency is determined by the incoming AES3 frame rate or ISCLK/64
(slave mode only). The RMCK frequency is configured in the register described in Section 11.9 “Recov-
ered Master Clock Ratio Control & Misc. (09h)” on page 52. If the ISCLK is chosen as the source for RM-
CK, then the ratios in the “Recovered Master Clock Ratio Control & Misc. (09h)” register reflect the ratio
of 64*RMCK/ISCLK.
6.4
XTI System Clock Mode
A special clock switching mode is available that allows the clock present at the XTI-XTO clock input to au-
tomatically replace RMCK when the PLL becomes unlocked. This is accomplished without spurious transi-
tions or glitches on RMCK.
When clock switching is enabled, the PLL’s loss of lock will cause the XTI-XTO clock input to be output on
RMCK. If a serial port is set master mode and has RMCK as its master clock source, it’s LRCK and SCLK
DS692PP2
31
CS8422
frequencies will be derived from the XTI-XTO clock when clock switching has taken place and the RMCK-
to-LRCK ratio will be maintained.
When clock switching is not enabled and the PLL has lost lock, RMCK will be derived from the VCO idle
frequency. The frequency of the RMCK output will be still be determined by the ratio selected by the RM-
CK[2:0] bits in register 09h, or the MS_SEL pin in Hardware Mode. When the PLL has lost lock, the VCO
idle frequency is equivalent to AES3 input data with Fs ≅ 54 kHz ± 5% (or ISCLK ≅ 3.456 MHz ± 5%).
6.4.1
6.4.2
Hardware Mode Control
In Hardware Mode, XTI System Clock Mode is always enabled.
Software Mode Control
In Software Mode, XTI System Clock Mode is controlled through the register described in Section 11.2
“Clock Control (02h)” on page 47.
6.5
AES11 Behavior
When an AES3-derived OLRCK is configured as a master, the rising or falling edge of OLRCK (depending
on the serial port interface format setting) will be within -1.5%(1/Fs) to 1.5%(1/Fs) from the start of the pre-
amble X/Z. In master mode, the latency through the receiver depends on the input sample frequency. In
master mode the latency of the audio data will be 3 frames in AES3 direct mode, and 4 frames in all other
cases.
When an AES3-derived OLRCK is configured as a slave, any synchronized input within +/-25% of an AES3
frame from the positive or negative edge of OLRCK (depending on the serial port interface format setting)
will be treated as being sampled at the same time. Since the CS8422 has no control of the OLRCK in slave
mode, the latency of the data through the part will be a multiple of 1/Fs plus the intrinsic delay between OL-
RCK and the preambles also present in master mode.
Both of these conditions are within the tolerance range set forth in the AES11 standard.
6.6
Error and Status Reporting
While decoding the incoming bi-phase encoded data stream, the CS8422 has the ability to identify various
error conditions. Refer to Sections 6.6.1 and 6.6.2 for details.
6.6.1
Software Mode
Software Mode allows the most flexibility in reading errors. When unmasked, bits in the Receiver Error
register (0Ch) indicate the following errors:
1. QCRC – CRC error in Q subcode data.
2. CCRC – CRC error in channel status data.
3. UNLOCK – PLL is not locked to incoming bi-phase data stream, or 2 valid Z preambles have not yet
been detected.
4. V – Data Validity bit is set.
5. CONF – The input data stream may be near error condition due to jitter degradation.
6. BIP – Bi-phase encoding error.
7. PAR – Parity error in incoming data.
32
DS692PP2
CS8422
The error bits are “sticky”, meaning that they are set on the first occurrence of the associated error and
will remain set until the user reads the register through the control port. This enables the register to log all
unmasked errors that occurred since the last time the register was read.
As a result of the bits “stickiness”, it is necessary to perform two reads on these registers to see if the error
condition still exists.
The Receiver Error Mask register (0Eh) allows masking of individual errors. The bits in this register default
to 00h and serve as masks for the corresponding bits of the Receiver Error register. If a mask bit is set to
1, the error is unmasked, which implies the following: its occurrence will be reported in the receiver error
register, induce a pulse on RERR, invoke the occurrence of a RERR interrupt, and affect the current audio
sample according to the status of the HOLD bits. The exceptions are the QCRC and CCRC errors, which
do not affect the current audio sample, even if unmasked.
The HOLD bits allow a choice of:
–
–
–
Holding the previous sample
Replacing the current sample with zero (mute)
Not changing the current audio sample
For more details, refer to “Receiver Error Unmasking (0Eh)” on page 56, “Interrupt Unmasking (0Fh)” on
page 56, “Interrupt Mode (10h)” on page 57, “Receiver Error (13h)” on page 58, and “Interrupt Status
(14h)” on page 59.
6.6.2
Hardware Mode Control
In Hardware Mode, the user may choose to output either the Non-Validity Receiver Error (NVERR) or the
Receiver Error (RERR) on the NV/RERR pin. By default the pin will output the NRERR signal. If upon star-
tup a 20 kΩ resistor is connected between the pin and VL, the NV/RERR pin will output the RERR error
signal. Both RERR and NVERR are updated on AES3 subframe boundaries. See “Hardware Mode Con-
trol” on page 39 for more details.
NVERR – The previous audio sample is held and passed to the serial audio output port if a parity, bi-
phase, confidence or PLL lock error occurs during the current sample.
RERR – The previous audio sample is held and passed to the serial audio output port if the validity bit is
high, or a parity, bi-phase, confidence or PLL lock error occurs during the current sample.
6.7
Non-Audio Detection
An AES3 data stream may be used to convey non-audio data, thus it is important to know whether the in-
coming AES3 data stream is digital audio or not. This information is typically conveyed in channel status bit
®
1, which is extracted automatically by the CS8422. However, certain non-audio sources, such as AC-3 or
MPEG encoders, may not adhere to this convention and the bit may not be properly set. The CS8422 AES3
receiver can detect such non-audio data through the use of an auto-detect module. The auto-detect module
is similar to auto-detect software used in Cirrus Logic DSPs.
®
If the AES3 stream contains sync codes in the proper format for IEC61937 or DTS data transmission, an
internal AUTODETECT signal will be asserted. If the sync codes no longer appear after a certain amount
of time, auto-detection will time-out and AUTODETECT will be de-asserted until another format is detected.
The AUDIO signal is the logical OR of AUTODETECT and the received channel status bit 1.
In Software Mode AUDIO is available through the GPO pins. If non-audio data is detected, the data is still
processed exactly as if it were normal audio. The exception is the use of de-emphasis auto-select feature
which will bypass the de-emphasis filter if the input stream is detected to be non-audio. It is up to the user
to mute the outputs as required.
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33
CS8422
6.7.1
6.7.2
6.8
Hardware Mode Control
In Hardware Mode, AUDIO is output on the V/AUDIO pin when a 20 kΩ resistor is connected from the
V/AUDIO pin to VL.
Software Mode Control
In Software Mode, the AUDIO signal is available through the GPO pins. See “GPO Control 1 (05h)” on
page 50 for more details.
Format Detection (Software Mode Only)
In Software Mode, the CS8422 can automatically detect various serial audio input formats. The Format De-
tect Status register (12h) is used to indicate a detected format. The register will indicate if uncompressed
PCM data, IEC61937 data, DTS_LD data, DTS_CD data, or digital silence was detected. Additionally, the
IEC61937 Pc/Pd burst preambles are available in registers 2Dh-30h. See the register descriptions for more
information.
6.9
Interrupts (Software Mode Only)
The INT signal, available in Software Mode, indicates when an interrupt condition has occurred and may be
output on one of the GPOs. It can be set through bits INT[1:0] in the Control1 register (02h) to be active low,
active high, or open-drain active low. This last mode is used for active low, wired-OR hook-ups, with multiple
peripherals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. Each source
may be masked off through mask register bits. In addition, some sources may be set to rising edge, falling
edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the mi-
crocontroller, many different configurations are possible, depending on the needs of the equipment design-
er. Refer to the register descriptions for the Interrupt Unmasking (0Fh), Interrupt Mode (10h), and Interrupt
Status (14h) registers
6.10 Channel Status and User Data Handling
“Channel Status Buffer Management” on page 66 describes the overall handling of Channel Status and
User data.
6.10.1 Hardware Mode Control
In Hardware Mode, Received Channel Status (C), and User (U) bits are output on the C and TX/U pins
(U data output must be selected on the TX/U pin, see “Hardware Mode Control” on page 39 for details).
OLRCK2 and RCBL are made available to qualify the C and U data output. Figure 19 illustrates timing of
the C and U data and their related signals.
6.10.2 Software Mode Control
In Software Mode, several options are available for accessing the Channel Status and User data that is
encoded in the received AES3 or SPDIF data.
The first option allows access directly through registers. The first 5 bytes of the Channel Status block are
decoded into the “Channel Status Registers (23h - 2Ch)”. Registers 23h-27h contain the A channel status
data. Registers 28h-2Ch contain the B channel status data.
Received Channel Status (C), User (U), and EMPH bits may also be serial outputs to the GPO pins by
appropriately setting the GPOxSEL bits in the “GPO Control 1 (05h)” registers. OLRCK and RCBL can be
34
DS692PP2
CS8422
made available to qualify the C and U data output. In serial port slave mode, VLRCK and RCBL can be
made available to qualify the C and U data output. VLRCK is a virtual word clock, equal to the receiver
recovered sample rate, that can be used to frame the C/U output. VLRCK and RCBL are available through
the GPO pins. Figure 19 illustrates timing of the C and U data, and their related signals. To recover serial
C-data or U-data with either OLRCK1 or OLRCK2, the corresponding serial port must be directly sourced
by the AES3 receiver (not the SRC).
To source an SDOUT signal directly from the RX receiver, the receiver should be set in master mode in
order to recover the received data. In this configuration, the SDOUT signal sourced from the receiver will
toggle at the AES frame rate. If the RX receiver is set to slave mode, the user must ensure that its asso-
ciated input OLRCK signal is externally synchronized to the input S/PDIF stream in order to recover the
received data. In both configurations, VLRCK is equal to the OLRCK signal associated with the serial port
used to clock the recovered receiver data.
When both SDOUTs are sourced from the RX receiver, VLRCK will equal OLRCK1. When both SDOUTs
are sourced from the SRC, then VLRCK will equal the recovered AES frame rate, not OLRCK.
SDOUT1
RX
SDOUT2
RX
VLRCK
OLRCK1
COMMENT
see (Note 4)
see (Note 4)
see (Note 4)
see (Note 6)
RX
SRC
RX
OLRCK1
SRC
SRC
OLRCK2
SRC
AES FRAMES
Table 1. VLRCK Behavior
The user may also access all of the C and U bits directly from the output data stream (SDOUT) by setting
bits SOFSELx[1:0]=11 (AES3 Direct mode) in “Serial Audio Output Data Format - SDOUT1 (0Ch)” or “Se-
rial Audio Output Data Format - SDOUT2 (0Dh)”. The appropriate bits can be stripped from the SDOUT
signal by external control logic such as a DSP or microcontroller. AES3 Direct mode is only valid if the
serial port in question is directly sourced by the AES3 receiver (not the SRC).
If the incoming User data bits have been encoded as Q-channel subcode, the data is decoded, buffered,
and presented in 10 consecutive register locations located in “Q-Channel Subcode (19h - 22h)” register.
An interrupt may be enabled to indicate the decoding of a new Q-channel block, which may be read
through the “Interrupt Status (14h)” register.
The encoded Channel Status bits which indicate sample word length are decoded according to
AES3-2003 or IEC 60958. The number of auxiliary bits are reported in bits 7 through 4 of the “Receiver
Channel Status (11h)”.
DS692PP2
35
CS8422
192 AES3 Frames
RCBL (out)
VLRCK (out)
C/U (out)
C/U[0]
C/U[1]
C/U[383]
t
t
Note:
1. RCBL will go high on the transition of the first output C/U data bit (C/U[0]) and will remain high until the C/U[0] - C/U[1] transition.
2. VLRCK is a virtual word clock that is available through the GPO pins, and can be used to frame the C/U output.
3. VLRCK frequency is always equal to the incoming frame rate of the AES3-compatible data. If there are an even number of OSCLK
periods per OLRCK, then the VLRCK duty cycle is 50%, otherwise it is 50% ± one OSCLK period.
4. If a serial audio output port is sourced directly by the AES3-compatible receiver VLRCK = OLRCK in I²S Mode, and
VLRCK = OLRCK in left-justified and Right-Justified Modes.
5. If a serial port is sourced directly by the AES3-compatible receiver, the data will transition on the fourth OSCLK falling edge after a
VLRCK edge and will be valid on VLRCK edges (t = 4 OSCLK period).
6. If a serial port is not sourced directly by the AES3-compatible receiver (as in a sample rate conversion application), the data will
transition 1/64*Fsi after a VLRCK edge, and will be valid on VLRCK edges (t = 1/64*Fsi).
Figure 19. C/U Data Outputs
36
DS692PP2
CS8422
7. SAMPLE RATE CONVERTER (SRC)
Multirate digital signal processing techniques are used to conceptually upsample the incoming data to a very high
rate and then downsample to the outgoing rate. Internal filtering is designed so that a full input audio bandwidth of
20 kHz is preserved if the input sample and output sample rates are greater than or equal to 44.1 kHz. When the
output sample rate becomes less than the input sample rate, the input is automatically band limited to avoid aliasing
artifacts in the output signal. Any jitter in the incoming signal has little impact on the dynamic performance of the rate
converter and has no influence on the output clock.
7.1
SRC Data Resolution and Dither
When using the serial audio input port in left justified and I²S Modes, all input data is treated as 24-bits wide.
Any truncation that has been done prior to the CS8422 to less than 24-bits should have been done using
an appropriate dithering process. If the serial audio input port is in Right-Justified Mode, the input data will
be truncated to the bit depth set through the “Serial Audio Input Data Format (0Bh)” register. If the bit depth
is set to 16 bits, and the input data is 24-bits wide, then truncation distortion will occur. Similarly, in any serial
audio input port mode, if an inadequate number of bit clocks are entered (i.e. 16 clocks instead of 20 clocks),
then the input words will be truncated, causing truncation distortion at low levels. In summary, there is no
dithering mechanism on the input side of the CS8422, and care must be taken to ensure that no truncation
occurs.
The output side of the SRC can be set to 16, 18, 20, or 24. Dithering is applied and is automatically scaled
to the selected output word length. This dither is not correlated between left and right channel.
7.1.1
7.1.2
Hardware Mode Control
In Hardware Mode, the SRC is the data source for SDOUT1, and its serial output port data resolution is
controlled through the SAOF pin. See Section 8.1 on page 40 for more details.
Software Mode Control
In Software Mode, the serial port data resolution is controlled through the “Serial Audio Input Data Format
(0Bh)”, “Serial Audio Output Data Format - SDOUT1 (0Ch)”, and “Serial Audio Output Data Format -
SDOUT2 (0Dh)” registers.
7.2
SRC Locking
The SRC calculates the ratio between the input sample rate and the output sample rate, and uses this in-
formation to set up various parameters inside the SRC block. The SRC takes some time to make this cal-
culation (approximately ~100 ms when Fso = 48 kHz).
The SRC_UNLOCK signal is used to indicate when the SRC is not locked. When RST is asserted, or if there
is a change in Fsi or Fso, SRC_UNLOCK will be set high. The SRC_UNLOCK pin will continue to be high
until the SRC has reacquired lock and settled, at which point it will transition low. When the SRC_UNLOCK
pin is set low, SDOUT is outputting valid audio data. This can be used to signal a DAC to unmute its output.
The SRC_UNLOCK signal is available through the control port register 15h, or through the SRC_UNLOCK
pin in Hardware Mode.
DS692PP2
37
CS8422
7.3
7.4
SRC Muting
The SDOUT pin sourced by the SRC (SDOUT1 or SDOUT2 in Software Mode, SDOUT1 in Hardware
Mode) is set to all zero output (full mute) immediately after the RST pin is set high. While the output from
the SRC becomes valid, SDOUT will be unmuted over a period of approximately 4096/Fso (soft unmuted).
When the output becomes invalid the SRC’s SDOUT is immediately set to all zero output (hard muted). After
all invalid states have been cleared, the SRC will soft unmute SDOUT.
SRC Master Clock
The CS8422 can use the clock signal supplied through XTI-XTO, the PLL, or an internal ring oscillator as
its master clock (MCLK). If the SRC MCLK source is selected as being XTI-XTO, care must be taken to en-
sure that the SRC MCLK source does not exceed 33 MHz. If the SRC MCLK source exceeds 33 MHz, an
internal clock divider can be enabled to divide the SRC MCLK source by 2, allowing the use of higher fre-
quency clocks. See Section 7.4.1 and Section 7.4.2 for more details.
If the SRC MCLK is applied through XTI then it can be supplied from a digital clock source, a crystal oscil-
lator, or a fundamental mode crystal. If XTO is not used, such as with a digital clock source or crystal oscil-
lator, XTO should be left unconnected or pulled low through a 20 kΩ resistor to GND.
If a crystal in conjunction with the internal oscillator is used to supply the SRC MCLK, the crystal circuit
should be connected as shown in Figure 20. If VL < 2.5 Volts, it is recommended that the crystal attached
across XTI and XTO should be specified as operating with a load capacitance of 10 pF (capacitors in
Figure 20 should be 20 pF). If VL ≥ 2.5 Volts, it is recommended that the crystal attached across XTI and
XTO should be specified as operating with a series capacitance of at 20 pF (capacitors in Figure 20 should
be at 40 pF). Please refer to the crystal manufacturer’s specifications for more information about external
capacitor recommendations.
XTI
XTO
C
C
Figure 20. Typical Connection Diagram for Crystal Circuit
If the PLL clock is selected as the SRC MCLK, the SRC MCLK will be synchronous to incoming AES3-com-
patible data or ISCLK. Unlike RMCK, the user does not control PLL clock’s relationship to the sampling rate
of incoming AES3-compatible data (Fsi), or ISCLK. See Table 2 for the relationship between the Fsi or IS-
CLK/64, and the PLL clock.
Fsi (or ISCLK/64)
PLL/Fsi
Fsi ≤ 49 kHz
512
60 kHz ≤ Fsi ≤ 98 kHz 256
120 kHz ≤ Fsi 128
Table 2. PLL Clock Ratios
The CS8422 has the ability to operate without a master clock input through XTI. This benefits the design by
not requiring extra external clock components (lowering production cost) and not requiring a master clock
to be routed to the CS8422, resulting in lowered noise contribution in the system. In this mode, an internal
oscillator provides the clock to run all of the internal logic. See Section 7.4.1 and Section 7.4.2 for explana-
tion of how the SRC MCLK can be selected.
38
DS692PP2
CS8422
7.4.1
7.4.2
Hardware Mode Control
In Hardware Mode, the default master clock source for the SRC is the internal ring oscillator. Therefore,
it is not necessary to apply an external MCLK source for the SRC. Optionally the user may select the PLL
clock as the SRC MCLK source by connecting a 20 kΩ pull-up resistor between MCLK_OUT and VL.
Software Mode Control
In Software Mode, the SRC master clock source is selected by the SRC_MCLK[1:0] bits in the “SRC Out-
put Serial Port Clock Control (08h)” register. If the XTI clock is selected as the SRC MCLK and XTI is tied
to VL or DGND and XTO is left unconnected, then the internal ring oscillator will take the place of the XTI-
XTO clock source.
If the selected SRC MCLK source is XTI-XTO, and is greater that 33 MHz, the user can enable the internal
clock divide-by-two by setting the SRC_DIV bit in control port register 08h. See “SRC Output Serial Port
Clock Control (08h)” on page 51 for more details.
8. HARDWARE MODE CONTROL
The CS8422 provides a stand-alone hardware control mode in which the part does not require an I²C or SPI control
port. In Hardware Mode, the user is provided with a subset of the features available in Software Mode as shown in
Figure 21. The part will be in Hardware Mode if there is a 20 kΩ pull-up resistor connected between the C pin and
VL upon reset.
Controlling the CS8422 in Hardware Mode is done through dedicated control inputs, 20 kΩ pull-up or pull-down re-
sistors attached to dual-purpose pins, and by attaching a specific resistor values from one of two dedicated control
pins (SAOF and MS_SEL) to either VL or ground. In the case of SAOF and MS_SEL, the resistor should be con-
nected as close to the pin as possible and should have a tolerance no greater than ±1%. Dedicated controls
(TX_SEL and RX_SEL) can be changed during operation whereas pull-up resistor controls are sensed on startup.
Figure 21 shows clock routing options available in Hardware Mode. Control signal names are in italics and are de-
scribed in the table below.
2:1
MUX
TX
(MCLK_OUT Pull-up)
(RMCK Pull-Up)
Sample
Rate
Converter
MS_SEL
SAOF
TX_SEL
Ring Oscillator
2:1
MUX
TDM_IN1
SDOUT1
OSCLK1
OLRCK1
Serial
Audio
Output
1
2:1
MUX
2
2
Receiver
Clock
Recovery
(PLL)
RXP/RXN0
RXP/RXN1
2:1
MUX
MS_SEL
SAOF
RX_SEL
Serial
Audio
Output
2
SDOUT2
OSCLK2
OLRCK2
RMCK
Clock
Generator
MCLK_OUT
XTI XTO
Figure 21. Hardware Mode Clock Routing
DS692PP2
39
CS8422
Pin Name
Description
Pin Configuration
Connected to GND
Connected to VL
Selection
RXP0/RXN0 is active
RXP1/RXN1 is active
RXP0/RXN0 to TX
RXP1/RXN1 to TX
RX_SEL
Selects Active AES3 RX Input
Connected to GND
Connected to VL
Selects RX Input to be output on
TX pin
TX_SEL
SDOUT1
De-emphasis Auto-detect
Enabled
No pull-up on SDOUT1
Enables or Disables De-emphasis
Auto-detect
De-emphasis Auto-detect
Disabled
20 kΩ pull-up on SDOUT1
Selects data format for SDOUT1
& SDOUT2
SAOF
See Table 4 on page 41
Selects master/slave and clock
configuration for SDOUT1&
SDOUT 2
MS_SEL
See Table 5 on page 41
No pull-up on RMCK
Selects master clock source for
SDOUT1 serial port
XTI-XTO
RMCK
RMCK
MCLK_OUT
TX/U
20 kΩ pull-up on RMCK
No pull-up on MCLK_OUT
20 kΩ pull-up on MCLK_OUT
No pull-up on U
Selects master clock source for
the SRC
Ring Oscillator
PLL Clock
Selects TX pass-through output or
incoming U data output
TX Pass-through
U Data Output
Software Mode
Hardware Mode
NVERR
20 kΩ pull-up on U
Selects Software or Hardware
Mode
No pull-up on C
C
20 kΩ pull-up on C
No pull-up on RERR/NVERR
20 kΩ pull-up on RERR/NVERR
20 kΩ pull-down on V/AUDIO
Selects error signal output on
NV/RERR
NV/RERR
RERR
Selects either incoming Validity
data output or AUDIO indicator
output
Validity data output
V/AUDIO
20 kΩ pull-up on V/AUDIO
AUDIO indicator output
Table 3. Hardware Mode Control Settings
8.1
Hardware Mode Serial Audio Port Control
The CS8422 uses the resistors attached to the MS_SEL and SAOF pins to determine the modes of opera-
tion for its serial output ports. After a RST is asserted, the resistor value and condition (VL or GND) are
sensed. This operation will take approximately 4 ms to complete. The SRC_UNLOCK pin will remain high
and both SDOUT pins will be muted until the mode detection sequence has completed. After this, if all clocks
are stable, SRC_UNLOCK will be brought low when audio output is valid and normal operation will begin.
The resistor attached to each mode selection pin should be placed physically close to the CS8422. The end
of the resistor not connected to the mode selection pins should be connected as close as possible to VL and
GND to minimize noise. Table 4 and Table 5 show the pin functions and their corresponding settings.
Table 4 shows the Hardware Mode options for output serial port format and the required SAOF pin config-
urations. In the case of SDOUT2, the output resolution depends on the resolution of the incoming AES3-
compatible data. In Right-Justified Modes, the serial format word-length will be equal to the AES3 input data
resolution. The exception is the case where Right-Justified Mode is selected and the AES3 input word-
length is an odd number of bits. In this case, the SDOUT2 word-length will be zero-stuffed to be 1 bit longer
then the AES3 input word-length (example: a 19-bit AES3 input word will result in an 20-bit right-justified
serial format). For a more detailed description of serial formats, refer to Section 5. on page 24.
Table 5 shows the Hardware Mode master/slave and clock options for both serial ports, and the required
MS_SEL pin configurations. For SDOUT1, when the serial port is set to master mode, the master clock ratio
40
DS692PP2
CS8422
determines what the output sample rate will be based on the MCLK selected for SDOUT1, as shown in the
hardware control pin descriptions shown above. For SDOUT2, the output sample rate is dictated by the in-
coming AES3 data, and the master mode clock ratio determines the frequency of RMCK relative to the in-
coming AES3 sample rate. Note: if TDM Mode is selected for SDOUT1, then SDOUT1 cannot be set to
“Master, Fso = MCLK/128”.
SAOF pin
SDOUT1 Data Format
I²S 24-bit data
SDOUT2 Data Format
32.4 kΩ ± 1% to GND
16.2 kΩ ± 1% to GND
8.06 kΩ ± 1% to GND
4.02 kΩ ± 1% to GND
1.96 kΩ ± 1% to GND
≤1.0 kΩ + 1% to GND
32.4 kΩ ± 1% to VL
I²S
I²S 20-bit data
I²S
I²S 16-bit data
I²S
Left-Justified 24-bit data
Left-Justified 20-bit data
Left-Justified 16-bit data
Left-Justified
Left-Justified
Left-Justified
Right-Justified 24-bit data
(Master mode only)
Right-Justified
(Master mode only)
16.2 kΩ ± 1% to VL
8.06 kΩ ± 1% to VL
Right-Justified 20-bit data
(Master mode only)
Right-Justified
(Master mode only)
Right-Justified 16-bit data
(Master mode only)
Right-Justified
(Master mode only)
4.02 kΩ ± 1% to VL
1.96 kΩ ± 1% to VL
≤1.0 kΩ + 1% to VL
TDM Mode 24-bit data
TDM Mode 20-bit data
TDM Mode 16-bit data
I²S
I²S
I²S
Table 4. Hardware Mode Serial Audio Format Control
MS_SEL pin
SDOUT1
SDOUT2
127.0 kΩ ± 1% to GND
Slave
63.4 kΩ ± 1% to GND Master, Fso = MCLK/128
32.4 kΩ ± 1% to GND Master, Fso = MCLK/256
16.2 kΩ ± 1% to GND Master, Fso = MCLK/512
Slave
RMCK = 256 x Fsi
8.06 kΩ ± 1% to GND
Slave
4.02 kΩ ± 1% to GND Master, Fso = MCLK/128
1.96 kΩ ± 1% to GND Master, Fso = MCLK/256
≤1.0 kΩ + 1% to GND Master, Fso = MCLK/512
Master Mode,
RMCK = 128 x Fsi
127.0 kΩ ± 1% to VL
63.4 kΩ ± 1% to VL
32.4 kΩ ± 1% to VL
16.2 kΩ ± 1% to VL
8.06 kΩ ± 1% to VL
4.02 kΩ ± 1% to VL
1.96 kΩ ± 1% to VL
≤1.0 kΩ + 1% to VL
Slave
Master, Fso = MCLK/128
Master, Fso = MCLK/256
Master, Fso = MCLK/512
Slave
Master Mode,
RMCK = 256 x Fsi
Master, Fso = MCLK/128
Master, Fso = MCLK/256
Master, Fso = MCLK/512
Master Mode,
RMCK = 512 x Fsi
Table 5. Hardware Mode Serial Audio Port Clock Control
DS692PP2
41
CS8422
9. SOFTWARE MODE CONTROL
9.1
Control Port Description
The control port is used to access the registers, allowing the CS8422 to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port has two modes: SPI and I²C, with the CS8422 acting as a slave device. SPI Mode is se-
lected if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I²C
Mode is selected by connecting the AD0/CS pin through a resistor to VL or DGND, thereby permanently
selecting the desired AD0 bit address state.
9.1.1
SPI Mode
In SPI Mode, CS is the CS8422 chip select signal, CCLK is the control port bit clock (input into the CS8422
from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data
line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Figure 22 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 0010000. The eighth bit is a read/write indi-
cator (R/W), which should be low to write. The next eight bits include the 7-bit Memory Address Pointer
(MAP), which is set to the address of the register that is to be updated. The next eight bits are the data
which will be placed into the register designated by the MAP. During writes, the CDOUT output stays in
the Hi-Z state. It may be externally pulled high or low with a 20 kΩ resistor, if desired.
CS
C C L K
C H IP
C H IP
M A P
DATA
A D D R E S S
ADDRESS
0010000
0010000
LSB
MSB
b y te 1
R/W
R/W
C D IN
b y te n
High Impedance
LSB
LSB
MSB
MSB
C D O U T
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 22. Control Port Timing in SPI Mode
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. To begin a read, bring CS low, send out the chip ad-
dress and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the
addressed register (CDOUT will leave the high impedance state). The MAP automatically increments, so
data for successive registers will appear consecutively.
42
DS692PP2
CS8422
9.1.2
I²C Mode
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should
be connected to VL or DGND as desired. The GPO2 pin is used to set the AD2 bit by connecting a 20 kΩ
resistor from the GPO2 pin to VL (a 20 kΩ pull-up sets AD2 = 1, and the absence of a pull-up sets
AD2 = 0). The states of the pins are sensed while the CS8422 is being reset.
The signal timings for a read and write cycle are shown in Figure 23 and Figure 24. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS8422
after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write).
The upper 4 bits of the 7-bit address field are fixed at 0010.
To communicate with a CS8422, the chip address field, which is the first byte sent to the CS8422, should
match 0010 followed by the settings of the AD2, AD1, and AD0 pins. The eighth bit of the address is the
R/W bit. If the operation is a write, the next byte includes the Memory Address Pointer (MAP) which se-
lects the register to be read or written. If the operation is a read, the contents of the register pointed to by
the MAP will be output. Each byte is separated by an acknowledge bit (ACK). The ACK bit is output from
the CS8422 after each input byte is read, and is input to the CS8422 from the microcontroller after each
transmitted byte.
26
27 28
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
24 25
SCL
SDA
DATA +1
DATA +n
CHIP ADDRESS (WRITE)
AD2 AD1 AD0
MAP BYTE
DATA
0
0
1
0
0
7
6
1
0
7
6
1
0
7
6
1
0
6
5
4
3
2
1
0
INC
ACK
ACK
ACK
ACK
STOP
START
Figure 23. Control Port Timing, I²C Slave Mode Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26 27 28
SCL
SDA
STOP
CHIP ADDRESS (WRITE)
AD2 AD1 AD0
MAP BYTE
CHIP ADDRESS (READ)
AD2 AD1 AD0
DATA
DATA +1 DATA + n
0
0
1
0
0
INC
0
0
1
0
1
6
5
4
3
2
1
0
7
0
7
0
7
0
ACK
ACK
START
ACK
ACK
NO
ACK
START
STOP
Figure 24. Control Port Timing, I²C Slave Mode Read
Note that the read operation can not set the MAP so an aborted write operation is used as a preamble.
As shown in Figure 24, the write operation is aborted after the acknowledge for the MAP byte by sending
a stop condition.
9.1.3
Memory Address Pointer (MAP)
The MAP is an 8-bit word containing the control port address to be read or written in both SPI and I²C Modes
and a bit to control an auto-increment feature. MAP[6:0] constitute the address to be read or written, while
bit 7 of the MAP (INC) determines whether or not MAP[6:0] will automatically increment after each control
port read or write. If INC = 0, MAP[6:0] will not automatically increment after each control port read or write.
If INC = 1, MAP[6:0] will automatically increment after each control port read or write. The MAP byte is
shown in Figures 23 and 24.
DS692PP2
43
CS8422
10.REGISTER QUICK REFERENCE
This table shows the register names and default values for read-write registers.
Addr Function
7
6
5
4
ID1
1
3
ID0
0
2
REV2
0
1
0
01h Chip ID &
Version
ID4
ID3
ID2
REV1
REV0
0
0
0
0
0
02h Clock Control
RMCK_
CTL1
RMCK_
CTL0
PDN
FSWCLK
SWCLK
INT1
INT0
Reserved
1
0
0
0
0
TXSEL0
1
0
0
Reserved
0
0
Reserved
0
03h Receiver Input
Control
INPUT_
TYPE
RX_MODE
RXSEL1
RXSEL0
TXSEL1
0
TRUNC
0
0
HOLD1
0
0
HOLD0
0
0
CHS
0
0
04h Receiver Data
Control
EMPH_
CNTL2
EMPH_
CNTL1
EMPH_
CNTL0
DETCI
0
1
0
0
05h GPO Control 1
06h GPO Control 2
GPO0SEL3 GPO0SEL2 GPO0SEL1 GPO0SEL0 GPO1SEL3 GPO1SEL2 GPO1SEL1 GPO1SEL0
0
0
0
0
0
0
0
0
GPO2SEL3 GPO2SEL2 GPO2SEL1 GPO2SEL3 GPO3SEL2 GPO3SEL1 GPO3SEL0 GPO3SEL3
0
SAI_CLK3
0
0
SAI_CLK2
1
0
SAI_CLK1
0
0
SAI_CLK0
0
0
0
Reserved
0
0
Reserved
0
0
07h SAI Clock Con-
trol
SAI_MCLK
0
Reserved
0
08h SRC SAO
Clock Control
SAO_
MCLK
SRC_
MCLK1
SRC_
MCLK2
SAO_CLK3 SAO_CLK2 SAO_CLK1 SAO_CLK0
SRC_DIV
0
RMCK3
0
1
RMCK2
0
1
RMCK1
0
0
RMCK0
0
0
0
Reserved
0
0
0
09h RMCK Cntl.&
Misc.
SRC_
MUTE
Reserved
Reserved
1
0
0
0Ah Data Routing
Control
MUTE_
SAO1
MUTE_
SAO2
SDOUT1_1 SDOUT1_0 SDOUT2_1 SDOUT2_0
SRCD
Reserved
0
0
0
SIFSEL2
0
1
SIFSEL1
0
0
SIFSEL0
0
0
Reserved
0
0
0
0Bh SAI Data
Format
SIMS
SISF
Reserved
Reserved
0
0
0
0
0Ch SAO1 Data For-
mat & TDM
SOMS1
SOSF1
SORES1_1 SORES1_0 SOFSEL1_1 SOFSEL1_0
TDM1
TDM0
0
0
0
0
0
0
0
0
0Dh SAO2 Data For-
mat
SOMS2
SOSF2
SORES2_1 SORES2_0 SOFSEL2_1 SOFSEL2_0
Reserved
Reserved
0
0
0
0
0
0
0
BIPM
0
0
PARM
0
0Eh RERR Unmask-
ing
ACTIVEM
QCRCM
CCRCM
UNLOCKM
VM
CONFM
0
0
0
0
0
RERRM
0
0
QCHM
0
0Fh Interrupt
Unmasking
SRC_
UNLOCKM
PCCHM
OSLIPM
DETCM
CCHM
FCHM
0
0
Reserved
0
0
Reserved
0
0
Reserved
0
0
Reserved
0
0
10h Interrupt Mode
SRC_
UNLOCK1
SRC_
UNLOCK0
RERR1
0
RERR0
0
0
0
Table 6. Summary of Software Register Bits
44
DS692PP2
CS8422
Addr Function
7
6
5
4
3
2
1
0
11h Receiver Chan-
nel
AUX3
AUX2
AUX1
AUX0
PRO
COPY
ORIG
EMPH
Status
12h Format Detect
Status
PCM
ACTIVE
PCCH
IEC61937
QCRC
DTS_LD
CCRC
DETC
DTS_CD
UNLOCK
CCH
HD_CD
V
DGTL_SIL
CONF
Reserved
BIP
Reserved
PAR
13h Receiver Error
14h Interrupt
Status
SRC_
UNLOCK
OSLIP
RERR
QCH
FCH
15h PLL Status
RX_
ACTIVE
ISCLK_
ACTIVE
PLL_LOCK
96KHZ
192KHZ
Reserved
Reserved
Reserved
16h Receiver
Status
CS_
UPDATE
RCVR_
RATE1
RCVR_
RATE0
RX_LOCK
BLK_VERR BLK_CERR BLK_BERR BLK_PERR
0
17h Fs/XTI Ratio
1
FS_XT15
FS_XT14
FS_XT6
FS_XT13
FS_XT5
FS_XT12
FS_XT4
FS_XT11
FS_XT3
FS_XT10
FS_XT2
FS_XT9
FS_XT1
FS_XT8
FS_XT0
18h Fs/XTI Ratio
2
FS_XT7
19h Q Subcode 1
1Ah Q Subcode 2
1Bh Q Subcode 3
1Ch Q Subcode 4
1Dh Q Subcode 5
1Eh Q Subcode 6
1Fh Q Subcode 7
20h Q Subcode 8
CONTROL
TRACK
INDEX
CONTROL
TRACK
INDEX
CONTROL
TRACK
INDEX
CONTROL
TRACK
INDEX
ADDRESS
TRACK
INDEX
ADDRESS
TRACK
INDEX
ADDRESS
TRACK
INDEX
ADDRESS
TRACK
INDEX
MINUTE
SECOND
FRAME
ZERO
MINUTE
SECOND
FRAME
ZERO
MINUTE
SECOND
FRAME
ZERO
MINUTE
SECOND
FRAME
ZERO
MINUTE
SECOND
FRAME
ZERO
MINUTE
SECOND
FRAME
ZERO
MINUTE
SECOND
FRAME
ZERO
MINUTE
SECOND
FRAME
ZERO
ABS
ABS
ABS
ABS
ABS
ABS
ABS
ABS
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
21h Q Subcode 9
ABS
ABS
ABS
ABS
ABS
ABS
ABS
ABS
SECOND
SECOND
SECOND
SECOND
SECOND
SECOND
SECOND
SECOND
22h Q Subcode 10 ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME
23h Channel A Sta-
AC0[7]
AC1[7]
AC2[7]
AC3[7]
AC4[7]
BC0[7]
BC1[7]
BC2[7]
BC3[7]
AC0[6]
AC1[6]
AC2[6]
AC3[6]
AC4[6]
BC0[6]
BC1[6]
BC2[6]
BC3[6]
AC0[5]
AC1[5]
AC2[5]
AC3[5]
AC4[5]
BC0[5]
BC1[5]
BC2[5]
BC3[5]
AC0[4]
AC1[4]
AC2[4]
AC3[4]
AC4[4]
BC0[4]
BC1[4]
BC2[4]
BC3[4]
AC0[3]
AC1[3]
AC2[3]
AC3[3]
AC4[3]
BC0[3]
BC1[3]
BC2[3]
BC3[3]
AC0[2]
AC1[2]
AC2[2]
AC3[2]
AC4[2]
BC0[2]
BC1[2]
BC2[2]
BC3[2]
AC0[1]
AC1[1]
AC2[1]
AC3[1]
AC4[1]
BC0[1]
BC1[1]
BC2[1]
BC3[1]
AC0[0]
AC1[0]
AC2[0]
AC3[0]
AC4[0]
BC0[0]
BC1[0]
BC2[0]
BC3[0]
tus Byte 0
24h Channel A Sta-
tus Byte 1
25h Channel A Sta-
tus Byte 2
26h Channel A Sta-
tus Byte 3
27h Channel A Sta-
tus Byte 4
28h Channel B Sta-
tus Byte 0
29h Channel B Sta-
tus Byte 1
2Ah Channel B Sta-
tus Byte 2
2Bh Channel B Sta-
tus Byte 3
Table 6. Summary of Software Register Bits (Continued)
DS692PP2
45
CS8422
Addr Function
7
6
5
4
3
2
1
0
2Ch Channel B Sta-
tus Byte 4
BC4[7]
BC4[6]
BC4[5]
BC4[4]
BC4[3]
BC4[2]
BC4[1]
BC4[0]
2Dh Burst
Preamble PC
Byte 0
PC0[7]
PC1[7]
PD0[7]
PD1[7]
PC0[6]
PC1[6]
PD0[6]
PD1[6]
PC0[5]
PC1[5]
PD0[5]
PD1[5]
PC0[4]
PC1[4]
PD0[4]
PD1[4]
PC0[3]
PC1[3]
PD0[3]
PD1[3]
PC0[2]
PC1[2]
PD0[2]
PD1[2]
PC0[1]
PC1[1]
PD0[1]
PD1[1]
PC0[0]
PC1[0]
PD0[0]
PD1[0]
2Eh Burst
Preamble PC
Byte 1
2Fh Burst
Preamble Pd
Byte 0
30h Burst
Preamble PD
Byte 1
Table 6. Summary of Software Register Bits (Continued)
46
DS692PP2
CS8422
11.SOFTWARE REGISTER BIT DEFINITIONS
The table row beneath the row that contains the register-bit name shows the register bit default value. Bits labeled
‘Reserved’ must remain at their default value.
11.1 CS8422 I.D. and Version Register (01h)
7
ID4
0
6
ID3
0
5
ID2
0
4
ID1
1
3
ID0
0
2
REV2
0
1
REV1
0
0
REV0
0
ID[4:0] - ID code for the CS8422. Permanently set to 00010
REV[2:0] = 000 (revision A)
REV[2:0] = 010 (revision B1)
11.2 Clock Control (02h)
7
PDN
1
6
FSWCLK
0
5
SWCLK
0
4
3
2
INT1
0
1
INT0
0
0
Reserved
0
RMCK_CTL1 RMCK_CTL0
0
0
PDN - Controls the internal clocks, allowing the CS8422 to be placed in a “powered down”, low current con-
sumption state. This bit must be written to the 0 state to allow the CS8422 to begin operation. All input clocks
should be stable in frequency and phase when PDN is set to 0.
0- Normal part operation.
1- Internal clocks are stopped. Internal state machines are reset. The fully static control port is operational,
allowing registers to be read or changed. Power consumption is low.
FSWCLK – Forces the clock signal on XTI to be output on RMCK regardless of the SWCLK bit functionality
or PLL lock.
0 – Clock signal on XTI is output on RMCK according to the SWCLK bit functionality.
1 – Forces the clock signal on XTI to be output on RMCK regardless of the SWCLK bit functionality.
SWCLK - Outputs XTI clock signal on RMCK pin when PLL loses lock. Any OSCLK or OLRCK derived from
RMCK under normal conditions will be derived from XTI in this case.
0 - Disable automatic clock switching.
1 - Enable automatic clock switching on PLL unlock. Clock signal selected on XTI is automatically output
on RMCK on PLL Unlock.
RMCK_CTL[1:0] - RMCK Control
00 - RMCK is an output and is derived from the frame rate of incoming AES3 data.
01 - RMCK is an output and is derived from the ISCLK input frequency divided by 64. Only valid if serial
audio input port is in slave mode (SIMS = 0 in “Serial Audio Input Data Format (0Bh)” on page 53).
10 - RMCK is high-impedance.
11 - Reserved
INT[1:0] - Interrupt output pin (INT) control
00 - Active high; high output indicates interrupt condition has occurred.
DS692PP2
47
CS8422
01 - Active low, low output indicates an interrupt condition has occurred.
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved.
11.3 Receiver Input Control (03h)
7
6
RXSEL1
0
5
RXSEL0
0
4
TXSEL1
1
3
TXSEL0
0
2
1
0
Reserved
0
RX_MODE
0
INPUT_TYPE Reserved
0
0
RX_MODE - Selects the input mode (single-ended or differential) of the RX pins
0 - Receiver inputs are differential-pair inputs RXP1/RXN1 and RXP0/RXN0.
1 - Receiver inputs are single-ended inputs RX[3:0].
RX_SEL[1:0] – Input multiplexer to the receiver
00 - RX0 or RXP0/RXN0
01 - RX1 (Only valid if RX_MODE = 1)
10 - RX2 or RXP1/RXN1
11 - RX3 (Only valid if RX_MODE = 1)
TX_SEL[1:0] – Selects receiver input for GPO TX source
00 - RX0 or RXP0/RXN0
01 - RX1 (Only valid if RX_MODE = 1)
10 - RX2 or RXP1/RXN1
11 - RX3 (Only valid if RX_MODE = 1)
INPUT_TYPE – Selects receiver input type
0 - Mode 1, receiver multiplexer inputs are comparator inputs biased at VA/2.
1 - Mode 2, receiver multiplexer inputs are digital inputs, referenced to VA. Valid only if RX_MODE = 1.
11.4 Receiver Data Control (04h)
7
TRUNC
0
6
HOLD1
0
5
HOLD0
0
4
CHS
0
3
DETCI
0
2
1
0
EMPH_CNTL2 EMPH_CNTL1 EMPH_CNTL0
1
0
0
TRUNC – Determines if the audio word length is set according to the incoming channel status data as de-
coded by the AUX[3:0] bits. The resulting word length in bits is 24 minus AUX[3:0].
0 – Incoming data is not truncated.
1 – Incoming data is truncated according to the length specified in the channel status data.
Truncation occurs before the de-emphasis filter. TRUNC has no effect on output data is detected as being
non-audio.
HOLD[1:0] – Determine how received AES3 audio sample is affected when a receive error occurs
00 - hold last audio sample.
48
DS692PP2
CS8422
01 - replace the current audio sample with all zeros (mute).
10 - do not change the received audio sample.
11 - reserved
CHS – Sets which channel's C data is decoded in the Receiver Channel Status register (11h) (Default = ‘0’)
0 - A channel
1 - B channel
If CHS = 0 and TRUNC = 1, both channels' audio data will be truncated by the AUX[3:0] bits indicated in
the channel A Channel Status data. If CHS = 1 and TRUNC = 1, both channels' audio data will be trun-
cated by the AUX[3:0] bits indicated in the channel B Channel Status data. This will occur even if the
AUX[3:0] bits indicated in the channel A Channel Status data are not equal to the AUX[3:0] bits indicated
in the channel B Channel Status data.
DETCI - D to E status transfer inhibit
0 -Allow update
1 -Inhibit update
DEM_CNTL[2:0] – De-emphasis filter control. See Figure 25 for De-emphasis filter response.
000 - De-emphasis filter off.
001 - 32 kHz setting
010 - 44.1 kHz setting
011 - 48 kHz setting
100 - Auto-detect Sample Rate. If the PLL estimates that the incoming sample rate is below 49 kHz, de-
emphasis will be applied according to the Channel Status data of the incoming AES3 or S/PDIF data. If
the PLL estimates that the incoming sample rate is not below 49 kHz, de-emphasis will not be enabled. If
the incoming Channel Status data indicates that no de-emphasis should be applied, de-emphasis will not
be enabled. If data is detected as being non-audio, the de-emphasis filter will not be enabled.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
F2
Frequency
3.183 kHz
10.61 kHz
Figure 25. De-Emphasis Filter Response
DS692PP2
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CS8422
11.5 GPO Control 1 (05h)
7
6
5
4
3
2
1
0
GPO0SEL3
0
GPO0SEL2
0
GPO0SEL1
0
GPO0SEL0
0
GPO1SEL3
0
GPO1SEL2
0
GPO1SEL1
0
GPO1SEL0
0
GPOxSEL[3:0] – GPO Source select for GPO0 and GPO1 pins. See Table 7 for available outputs for
GPO[3:0].
11.6 GPO Control 2 (06h)
7
6
5
4
3
2
1
0
GPO2SEL3
0
GPO2SEL2
0
GPO2SEL1
0
GPO2SEL0
0
GPO3SEL3
0
GPO3SEL2
0
GPO3SEL1
0
GPO3SEL0
0
GPOxSEL[3:0] – GPO Source select for GPO2 and GPO3 pins. See Table 7 for available outputs for
GPO[3:0].
Function
GND
Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
Definition
Fixed low level
Fixed VL level.
VL
EMPH
INT
State of EMPH bit in the incoming data stream
CS8422 interrupt output
C
Channel status bit
U
User data bit
RERR
NVERR
RCBL
96KHZ
192KHZ
AUDIO
VLRCK
TX
Receiver Error
Non-Validity Receiver Error
Receiver Channel Status Block
Defined in “PLL Status (15h)” on page 60.
Defined in “PLL Status (15h)” on page 60.
Non-audio indicator for decoded input stream
Virtual LRCK, can be used to frame the C and U output data.
Pass through of AES/SPDIF input selected by TXSEL[2:0] in Section 11.3
“Receiver Input Control (03h)” on page 48.
SRC_UNLOCK
XTI_OUT
1110
1111
SRC unlock indicator
Buffered XTI-XTO output
Table 7. GPO Pin Configurations
11.7 Serial Audio Input Clock Control (07h)
7
SAI_CLK3
0
6
SAI_CLK2
1
5
SAI_CLK1
0
4
SAI_CLK0
0
3
2
1
0
SAI_MCLK
0
Reserved
Reserved
Reserved
SAI_CLK[3:0] – Selects the serial audio input master clock-to-ILRCK ratio when the serial audio input port
is set to master mode (SIMS = 1 as shown in “Serial Audio Input Data Format (0Bh)” on page 53). Note: if
a serial audio output is sourced directly by the serial audio input port, SAI_CLK[3:0] determine the
MCLK/LRCK ratio for both serial ports if they are set to master mode.
0000 - ILRCK = MCLK/64
50
DS692PP2
CS8422
0001 - ILRCK = MCLK/96
0010 - ILRCK = MCLK/128
0011 - ILRCK = MCLK/192
0100 - ILRCK = MCLK/256
0101 - ILRCK = MCLK/384
0110 - ILRCK = MCLK/512
0111 - ILRCK = MCLK/768
1000 - ILRCK = MCLK/1024
SAI_MCLK – Selects the master clock (MCLK) source for the serial audio input when set to master mode
(SIMS = 1, as shown in “Serial Audio Input Data Format (0Bh)” on page 53). When set to master, ILRCK
and ISCLK are derived from the MCLK selected in this register. Note: if either serial audio output port is
sourced directly by the serial audio input port, this bit determines the master clock source for the selected
serial output port when it is in master mode.
0 - XTI-XTO
1 - RMCK
11.8 SRC Output Serial Port Clock Control (08h)
7
6
5
4
3
2
1
0
SRC_DIV
0
SAO_CLK3
0
SAO_CLK2
1
SAO_CLK1
0
SAO_CLK0
0
SAO_MCLK SRC_MCLK1 SRC_MCLK0
0
0
0
SAO_CLK[3:0] – Valid only for the serial port sourced by the SRC. Selects the serial audio input master
clock-to-OLRCK ratio when the serial audio output port is set to master mode (SOMS = 1 as shown in “Serial
Audio Output Data Format - SDOUT1 (0Ch)” on page 54 and “Serial Audio Output Data Format - SDOUT2
(0Dh)” on page 55).
0000 - OLRCK = MCLK/64
0001 - OLRCK = MCLK/96
0010 - OLRCK = MCLK/128
0011 - OLRCK = MCLK/192
0100 - OLRCK = MCLK/256
0101 - OLRCK = MCLK/384
0110 - OLRCK = MCLK/512
0111 - OLRCK = MCLK/768
1000 - OLRCK = MCLK/1024
SAO_MCLK – Selects the master clock (MCLK) source for the serial audio output, sourced by the SRC,
when set to master mode (SOMS1 or SOMS 2 = 1, as shown in “Serial Audio Output Data Format - SDOUT1
(0Ch)” on page 54 and “Serial Audio Output Data Format - SDOUT2 (0Dh)” on page 55). When set to mas-
ter, OLRCK and OSCLK are derived from the MCLK selected in this register.
0 - XTI-XTO
DS692PP2
51
CS8422
1 - RMCK
SRC_MCLK[1:0] - Controls the master clock (MCLK) source for the sample rate converter. See “SRC Mas-
ter Clock” on page 38 for details.
00 - XTI-XTO. If XTI is connected to GND or VL and XTO is left floating, the SRC MCLK will be the internal
ring oscillator.
01 - PLL clock
10 - Internal Ring Oscillator
11 - Reserved
SRC_DIV – Divide-by-two for the SRC MCLK source. Valid only if SRC_MCLK = 00.
0 - SRC MCLK is not divided. Maximum allowable SRC MCLK frequency is 33 MHz.
1 - SRC MCLK is divided. Maximum allowable SRC MCLK frequency is 49.152 MHz.
11.9 Recovered Master Clock Ratio Control & Misc. (09h)
7
RMCK3
0
6
RMCK2
0
5
RMCK1
0
4
RMCK0
0
3
2
1
0
SRC_MUTE
1
Reserved
Reserved
Reserved
RMCK[3:0] – Selects the RMCK/Fsi ratio, where Fsi is the sample rate of the incoming AES3-compatible
data or ISCLK/64. Note: If a serial audio output port is in master mode and sourced directly by the AES3
receiver, then RMCK is the master clock source for the selected serial output port and RMCK[3:0] determine
the MCLK/OLRCK ratio for the selected serial output port.
0000 - RMCK = 64 x Fsi
0001 - RMCK = 96 x Fsi
0010 - RMCK = 128 x Fsi
0011 - RMCK = 192 x Fsi
0100 - RMCK = 256 x Fsi
0101 - RMCK = 384 x Fsi
0110 - RMCK = 512 x Fsi
0111 - RMCK = 768 x Fsi
1000 - RMCK = 1024 x Fsi
SRC_MUTE – When SRC_MUTE is set to ‘1’, the SRC will soft-mute when it loses lock and soft unmute
when it regains lock.
0 - Soft mute disabled
1 - Soft mute enabled
11.10 Data Routing Control(0Ah)
7
6
5
4
3
2
1
SRCD
0
0
SDOUT1(1)
0
SDOUT1(0)
0
SDOUT2(1)
0
SDOUT2(0)
1
MUTESAO1
0
MUTESAO2
0
Reserved
SDOUT1[1:0] - Controls the data source for SDOUT1
52
DS692PP2
CS8422
00 - Sample Rate Converter
01 - AES3 Receiver Output
10 - SDIN (SDIN and SDOUT should be synchronous)
11 - Reserved
SDOUT2[1:0] - Controls the data source for SDOUT2
00 - Sample Rate Converter
01 - AES3 Receiver Output
10 - SDIN (SDIN and SDOUT should be synchronous)
11 - Reserved
MUTESAO1 - Mute control for the serial audio output port 1
0 - SDOUT1 not muted
1 - SDOUT1 muted (set to all zeros)
MUTESAO2 - Mute control for the serial audio output port 2
0 - SDOUT2 not muted.
1 - SDOUT2 muted (set to all zeros).
SRCD - Controls the data source of the sample rate converter
0 - Serial Audio Input Port (SDIN)
1 - AES3 Receiver Output
11.11 Serial Audio Input Data Format (0Bh)
7
SIMS
0
6
SISF
0
5
SIFSEL2
0
4
SIFSEL1
0
3
SIFSEL0
0
2
1
0
Reserved
Reserved
Reserved
SIMS - Master/Slave Mode Selector
0 - Serial audio input port is in slave mode. ISCLK and ILRCK are inputs.
1 - Serial audio input port is in master mode. ISCLK and ILRCK are outputs.
SISF - ISCLK Frequency. Valid only in master mode (SIMS = 1). Should be changed when PDN = 1. See
Table 8 for details.
ISCLK/ILRCK Ratio
SAI_CLK[3:0]
MCLK/ILRCK Ratio
SISF = 0
SISF = 1
INVALID
96
0000
0001
0010
0011
0100
64
96
64
48
64
48
64
128
192
256
128
96
128
Table 8. ISCLK/ILRCK Ratios and SISF Settings
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0101
0110
0111
1000
384
512
48
64
48
64
96
128
96
768
1024
128
Table 8. ISCLK/ILRCK Ratios and SISF Settings
SIFSEL[2:0] - Serial audio input data format
000 - Left-Justified, up to 24-bit data
001 - I²S, up to 24-bit data
010 - Right-Justified, 24-bit data
011 - Right-Justified, 20-bit data
100 - Right-Justified, 18-bit data
101 - Right-Justified, 16-bit data
110, 111 - Reserved
11.12 Serial Audio Output Data Format - SDOUT1 (0Ch)
7
SOMS1
0
6
SOSF1
0
5
4
3
2
1
0
TDM0
0
SORES1_1
0
SORES1_0
0
SOFSEL1_1 SOFSEL1_0
TDM1
0
0
0
SOMS1 - Master/Slave Mode Selector
0 - Serial audio output port is in slave mode. OSCLK and OLRCK are inputs.
1 - Serial audio output port is in master mode. OSCLK and OLRCK are outputs.
SOSF1 - OSCLK1 Frequency. Valid only in master mode (SOMS1 = 1). If the SRC is selected as the source
for SDOUT1 (SDOUT1[1:0] = 00 in register 0Ah), then the master clock (MCLK) is the SAO MCLK (as se-
lected by the SAO_MCLK bit in register 08h). If the AES3 receiver is selected as the source for SDOUT1
(SDOUT1[1:0] = 01 in register 0Ah), then the MCLK is RMCK. Should be changed when PDN = 1. See
Table 9 for details. Note: If serial output 1 is in master mode and sourced directly by the serial input port,
SAI_CLK[3:0] determines the MCLK/OLRCK1 ratio.
SAO_CLK[3:0],
SAI_CLK[3:0], or
RMCK[3:0]
OSCLK1/OLRCK1 Ratio
MCLK/OLRCK1 Ratio
SOSF1 = 0
SOSF1 = 1
0000
0001
0010
0011
0100
0101
0110
0111
1000
64
96
64
48
64
48
64
48
64
48
64
INVALID
96
128
192
256
384
512
768
1024
128
96
128
96
128
96
128
Table 9. OSCLK1/OLRCK1 Ratios and SOSF1 Settings
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SORES1[1:0] - Resolution of the output data on SDOUT
00 - 24-bit resolution.
01 - 20-bit resolution.
10 - 18-bit resolution.
11 - 16-bit resolution
SOFSEL1[1:0] - Format of the output data on SDOUT
00 - Left-Justified
01 - I²S
10 - Right-Justified (Master mode only)
11 - AES3 Direct. Direct copy of the received NRZ data from the AES3 receiver including C, U, and V bits.
The time slot occupied by the Z bit is used to indicate the location of the block start. Only valid if serial port
sourced directly by the AES3-compatible receiver.
TDM[1:0] - Enable the time-division multiplexing (TDM) through TDM_IN and either SDOUT1 or SDOUT2.
See “Time Division Multiplexing (TDM) Mode” on page 27 for more details.
00 - TDM Mode not enabled. Serial audio format selected by SOFSEL1[1:0]
01 - TDM Mode enabled through TDM_IN and SDOUT1. SOFSEL1[1:0] has no effect in this mode.
10 - TDM Mode enabled through TDM_IN and SDOUT2. SOFSEL2[1:0] has no effect in this mode.
11 - Reserved
11.13 Serial Audio Output Data Format - SDOUT2 (0Dh)
7
SOMS2
0
6
SOSF2
0
5
4
3
2
1
0
SORES2_1
0
SORES2_0
0
SOFSEL2_1 SOFSEL2_0
Reserved
Reserved
0
0
SOMS2 - Master/Slave Mode Selector
0 - Serial audio output port is in slave mode. OSCLK and OLRCK are inputs.
1 - Serial audio output port is in master mode. OSCLK and OLRCK are outputs.
SOSF2 - OSCLK2 Frequency. Valid only in master mode (SOMS2 = 1). If the SRC is selected as the source
for SDOUT2 (SDOUT2[1:0] = 00 in register 0Ah), then the master clock (MCLK) is the SAO MCLK (as se-
lected by the SAO_MCLK bit in register 08h). If the AES3 receiver is selected as the source for SDOUT2
(SDOUT2[1:0] = 01 in register 0Ah), then the MCLK is RMCK. Should be changed when PDN = 1. See
Table 10 for details. Note: If serial output 2 is in master mode and sourced directly by the serial input port,
then SAI_CLK[3:0] determine the MCLK/OLRCK1 ratio.
SAO_CLK[3:0],
SAI_CLK[3:0], or
RMCK[3:0]
OSCLK2/OLRCK2 Ratio
MCLK/OLRCK2 Ratio
SOSF2 = 0
SOSF2 = 1
0000
0001
64
96
64
48
INVALID
96
Table 10. OSCLK2/OLRCK2 Ratios and SOSF1 Settings
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0010
0011
0100
0101
0110
0111
1000
128
192
256
384
512
768
1024
64
48
64
48
64
48
64
128
96
128
96
128
96
128
Table 10. OSCLK2/OLRCK2 Ratios and SOSF1 Settings
SORES2[1:0] - Resolution of the output data on SDOUT
00 - 24-bit resolution.
01 - 20-bit resolution.
10 - 18-bit resolution.
11 - 16-bit resolution
SOFSEL2[1:0] - Format of the output data on SDOUT
00 - Left-Justified
01 - I²S
10 - Right-Justified (Master mode only)
11 - AES3 Direct. Direct copy of the received NRZ data from the AES3 receiver including C, U, and V bits.
The time slot occupied by the Z bit is used to indicate the location of the block start. Only valid if serial port
source is the AES3-compatible receiver.
11.14 Receiver Error Unmasking (0Eh)
7
6
QCRCM
0
5
CCRCM
0
4
3
VM
0
2
CONFM
0
1
BIPM
0
0
PARM
0
ACTIVEM
UNLOCKM
0
RECEIVER ERROR MASK[7:0]
The bits[7:0] in this register serve as masks for the corresponding bits of the Receiver Error Register. If a
mask bit is set to 1, the error is unmasked, meaning that its occurrence will appear in the receiver error reg-
ister, will affect RERR[6:0], will affect the RERR interrupt, and will affect the current audio sample according
to the status of the HOLD bit. If a mask bit is set to 0, the error is masked, meaning that its occurrence will
not appear in the receiver error register, will not affect the RERR pin, will not affect the RERR interrupt, and
will not affect the current audio sample. The ACTIVE, CCRC, and QCRC bits behave differently from the
other bits: they do not affect the current audio sample even when unmasked. If QCRC, CCRC, CONF, BIP,
or PARM are unmasked, and RERRM in register 0Fh is unmasked, then RERR[1:0] should be set to “Rising
Edge Active” in the Interrupt Mode register (register 10h). This register defaults to 00h.
11.15 Interrupt Unmasking (0Fh)
7
PCCHM
0
6
OSLIPM
0
5
DETCM
0
4
CCHM
0
3
RERRM
0
2
QCHM
0
1
FCHM
0
0
SRC_UNLOCKM
0
The bits of this register serve as a mask for the Interrupt Status register. If a mask bit is set to 1, the error
is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set
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to 0, the error is masked, meaning that its occurrence will not affect the internal INT signal or the status reg-
ister. The bit positions align with the corresponding bits in Interrupt Status register. This register defaults to
00h.
The INT signal may be selected to output on the GPO pins. See Section 11.5 on page 50 for more details.
11.16 Interrupt Mode (10h)
7
6
5
4
3
RERR1
0
2
RERR0
0
1
0
Reserved
Reserved
Reserved
Reserved
SRC_UNLOCK1 SRC_UNLOCK0
0
0
The interrupt mode control in the behavior of the INT pin to RERR and SRC_UNLOCK interrupts. There are
three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active
mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode,
the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt
pin becomes active during the interrupt condition. Be aware that the active level (Active High or Low) only
depends on the INT[1:0] bits. These registers default to 00h. The interrupts in the Interrupt Status register
not represented here are all rising edge active.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
11.17 Receiver Channel Status (11h)
7
6
5
4
3
2
1
0
AUX3
AUX2
AUX1
AUX0
PRO
COPY
ORIG
EMPH
The bits in this register can be associated with either channel A or B of the received data. The desired chan-
nel is selected with the CHS bit of “Receiver Data Control (04h)” on page 48.
AUX3:0 - Incoming auxiliary data field width, as indicated by the incoming channel status bits, decoded ac-
cording to IEC60958 and AES3.
0000 - Auxiliary data is not present.
0001 - Auxiliary data is 1 bit long.
0010 - Auxiliary data is 2 bits long.
0011 - Auxiliary data is 3 bits long.
0100 - Auxiliary data is 4 bits long.
0101 - Auxiliary data is 5 bits long.
0110 - Auxiliary data is 6 bits long.
0111 - Auxiliary data is 7 bits long.
1000 - Auxiliary data is 8 bits long.
1001 - 1111 Reserved
PRO - Channel status block format indicator
0 - Received channel status block is in the consumer format.
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1 - Received channel status block is in the professional format.
COPY - SCMS copyright indicator
0 - Copyright asserted.
1 - Copyright not asserted. If the category code is set to General in the incoming AES3 stream, copyright
will always be indicated by COPY, even when the stream indicates no copyright.
ORIG - SCMS generation indicator, decoded from the category code and the L bit.
0 - Received data is 1st generation or higher.
1 - Received data is original.
Note: COPY and ORIG will both be set to 1 if incoming data is flagged as professional or if the receiver
is not in use.
EMPH – Indicates if the input channel status data indicates that the incoming audio data has been pre-em-
phasized.
0 – 50 μs/15 μs pre-emphasis indicated.
1 – 50 μs/15 μs pre-emphasis not indicated.
11.18 Format Detect Status (12h)
7
6
5
4
3
2
1
0
PCM
IEC61937
DTS_LD
DTS_CD
HD_CD
DGTL_SIL
Reserved
Reserved
Note: PCM, DTS_LD, DTS_CD and IEC61937 are mutually exclusive. A ‘1’ indicated the condition
was detected.
PCM – Un-compressed PCM data was detected.
IEC61937 – IEC61937 data was detected.
DTS_LD – DTS_LD data was detected.
DTS_CD – DTS_CD data was detected.
HD_CD – HD_CD data was detected.
DGTL_SIL – Digital Silence was detected: at least 2047 consecutive constant samples of the same 24-bit
audio data on both channels.
11.19 Receiver Error (13h)
7
6
5
4
3
2
1
0
Reserved
QCRC
CCRC
UNLOCK
V
CONF
BIP
PAR
This register contains the AES3 receiver status bits. Unmasked bits will go high on occurrence of the error,
and will stay high until the register is read. Reading the register resets all bits to 0, unless the error source
is still true. Bits that are masked off in the receiver error mask register will always be 0 in this register.
QCRC - Q-subcode data CRC error indicator. Updated on Q-subcode block boundaries
0 - No error.
1 - Error.
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CCRC - Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries, valid only
in Pro mode.
0 - No error.
1 - Error.
UNLOCK - Receiver lock status when sourced by incoming AES3-compatible data. Updated on CS block
boundaries.
0 - Receiver locked.
1 - Receiver out of lock.
V - Received AES3 Validity bit status. Updated on sub-frame boundaries.
0 - Data is valid and is normally linear coded PCM audio.
1 - Data is invalid, or may be valid compressed audio.
CONF - Confidence bit. Updated on sub-frame boundaries.
0 - No error.
1 - Confidence error. The input data stream may be near error condition due to jitter degradation.
BIP - Bi-phase error bit. Updated on sub-frame boundaries.
0 - No error.
1 - Bi-phase error. This indicates an error in the received bi-phase coding.
PAR - Parity bit. Updated on sub-frame boundaries.
0 - No error.
1 - Parity error.
11.20 Interrupt Status (14h)
7
6
5
4
3
2
1
0
PCCH
OSLIP
DETC
CCH
RERR
QCH
FCH
SRC_UNLOCK
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since
the register was last read. A “0” means the associated interrupt condition has NOT occurred since the last
reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and
the interrupt source is still true. Status bits that are masked off in the associated mask register will always
be “0” in this register.
PCCH – PC burst preamble change.
Indicates that the PC byte has changed from its previous value. If the IEC61937 bit in the Format Detect
Status register goes high, it will cause a PCCH interrupt even if the PC byte hasn’t changed since the last
time the IEC61937 bit went high.
OSLIP - Serial audio output port data slip interrupt
When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port data source,
this bit will go high every time a data sample is dropped or repeated. See “Serial Port Clock Operation”
on page 25 for more information.
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DETC - D to E C-buffer transfer interrupt.
Indicates the completion of a D to E C-buffer transfer. See “Channel Status Buffer Management” on page
53.
CCH - C-Data change.
Indicates that the current 10 bytes of channel status is different from the previous 10 bytes. (5 bytes per
channel)
RERR - A receiver error has occurred.
The Receiver Error register may be read to determine the nature of the error which caused the interrupt.
QCH – A new block of Q-subcode is available for reading.
The data must be read within 588 AES3 frames after the interrupt occurs to avoid corruption of the data
by the next block.
FCH – Format Change
Goes high when the PCM, IEC61937, DTS_LD, DTS_CD, or DGTL_SIL bits in the Format Detect Status
register transition from 0 to 1. When these bits in the Format Detect Status register transition from 1 to 0,
an interrupt will not be generated.
SRC_UNLOCK - SRC Unlock condition.
Indicates that the SRC has lost the ability to output valid data
11.21 PLL Status (15h)
7
6
5
4
3
2
1
0
ISCLK
ACTIVE
RX_ACTIVE
PLL_LOCK
96KHZ
192KHZ
Reserved
Reserved
Reserved
RX_ACTIVE - Receiver Active
This bit is a level-signal version of the ACTIVE bit in register 13h.
ISCLK_ACTIVE- ISCLK Active
0 - There is no toggling on the ISCLK pin, or the frequency of toggling is less than 36 kHz on the ISCLK
pin.
1 - There is toggling at a frequency of at least 1.536 MHz on the ISCLK pin.
PLL_LOCK -
0 - The PLL has not achieved lock.
1 - The PLL, driven by either an AES3 or ISCLK input, has achieved lock.
96KHZ – Indicates the frequency range of the sample rate of incoming AES3 data (Fsi). If Fsi ≤ 49 kHz or
Fsi ≥ 120 kHz, this bit will output a “0”. If 60 kHz ≤ Fsi ≤ 98 kHz, this bit will output a “1”. Otherwise the output
is indeterminate.
192KHZ – Indicates the frequency range of the sample rate of incoming AES3 data (Fsi). If Fsi ≤ 98 kHz,
this bit will output a “0”. If Fsi ≥120 kHz, this bit will output a “1”. Otherwise the output is indeterminate.
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11.22 Receiver Status (16h)
7
6
5
4
3
2
1
0
CS_UPDATE RCVR_RATE1 RCVR_RATE0 RX_LOCK
BLK_VERR
-
BLK_CERR
-
BLK_BERR
-
BLK_PERR
-
0
-
-
-
CS_UPDATE - Determines whether channel status registers and RCVR_RATE are updated in the presence
of a receiver error (register 14h).
0 - The receiver channel status registers and RCVR_RATE are updated on each AES3 block boundary.
1 - The receiver channel status registers and RCVR_RATE are updated on each AES3 block boundary if
no biphase, confidence, parity, or CRCC error has occurred during the reception of the channel status
block.
RCVR_RATE - Input sample rate represented in the channel status data of incoming AES3 data.
00 - Reserved
01 - 32 kHz
10 - 44.1 kHz
11 - 48 kHz
RX_LOCK - AES3 Receiver PLL Lock
0 - The PLL has not achieved lock for more than 2 Z preambles or AES3 input is not driving PLL.
1 - Goes high 2 Z preambles after the PLL has achieved lock when an AES3 input has been selected to
drive the PLL.
BLK_VERR - Block Validity Error. Updated on DETC boundaries
0 - The Validity bit of the incoming AES3 data has remained low during the input of the last AES3 data
block.
1 - The Validity bit of incoming AES3 data has gone high at some point during the input of the last AES3
data block.
BLK_CERR - Block Confidence Error. Updated on DETC boundaries
0 - The Confidence bit associated with incoming AES3 data has remained high during the input of the last
AES3 data block.
1 - The Confidence bit associated with incoming AES3 data has gone low at least once during the input
of the last AES3 data block.
BLK_BERR - Block Biphase Error. Updated on DETC boundaries
0 - There has been no biphase error associated with incoming AES3 data during the input of the last AES3
data block.
1 - There has been at least one biphase error associated with incoming AES3 data during the input of the
last AES3 data block.
BLK_PERR - Block Parity Error. Updated on DETC boundaries
0 - There has been no parity error associated with incoming AES3 data during the input of the last AES3
data block.
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1 - There has been at least one parity error associated with incoming AES3 data during the input of the
last AES3 data block.
11.23 Fs/XTI Ratio (17h - 18h)
7
6
5
4
3
2
1
0
FS_XT15
FS_XT7
FS_XT14
FS_XT6
FS_XT13
FS_XT5
FS_XT12
FS_XT4
FS_XT11
FS_XT3
FS_XT10
FS_XT2
FS_XT9
FS_XT1
FS_XT8
FS_XT0
FS_XTI[15:0] - 256*Fs/XTI, where Fs is the sample rate of incoming AES3-compatible data.
The integer part of FS_XT[15:0] is represented in bits [15:10] in register 17h, and the fractional part is rep-
resented in bits [9:0] of registers 17h and 18h; with a precision of 300 Hz in Fs and is updated approxi-
mately every 2048/(XTI frequency). Reading register 17h will cause the value of 18h to freeze until
register 18h is read.
11.24 Q-Channel Subcode (19h - 22h)
7
6
5
4
3
2
1
0
CONTROL
TRACK
INDEX
CONTROL
TRACK
INDEX
CONTROL
TRACK
INDEX
CONTROL
TRACK
INDEX
ADDRESS
TRACK
INDEX
ADDRESS
TRACK
INDEX
ADDRESS
TRACK
INDEX
ADDRESS
TRACK
INDEX
MINUTE
SECOND
FRAME
ZERO
MINUTE
SECOND
FRAME
ZERO
MINUTE
SECOND
FRAME
ZERO
MINUTE
SECOND
FRAME
ZERO
MINUTE
SECOND
FRAME
ZERO
MINUTE
SECOND
FRAME
ZERO
MINUTE
SECOND
FRAME
ZERO
MINUTE
SECOND
FRAME
ZERO
ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE
ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND
ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME
Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus bit 7 of address 19h is Q[0] while
bit 0 of address 19h is Q[7]. Similarly bit 0 of address 22h corresponds to Q[79].
11.25 Channel Status Registers (23h - 2Ch)
Address
23h
Channel Status Byte
Channel A Status Byte 0
Channel A Status Byte 1
Channel A Status Byte 2
Channel A Status Byte 3
Channel A Status Byte 4
Channel B Status Byte 0
Channel B Status Byte 1
Channel B Status Byte 2
Channel B Status Byte 3
Channel B Status Byte 4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AC0[7]
AC1[7]
AC2[7]
AC3[7]
AC4[7]
BC0[7]
BC1[7]
BC2[7]
BC3[7]
BC4[7]
AC0[6]
AC1[6]
AC2[6]
AC3[6]
AC4[6]
BC0[6]
BC1[6]
BC2[6]
BC3[6]
BC4[6]
AC0[5]
AC1[5]
AC2[5]
AC3[5]
AC4[5]
BC0[5]
BC1[5]
BC2[5]
BC3[5]
BC4[5]
AC0[4]
AC1[4]
AC2[4]
AC3[4]
AC4[4]
BC0[4]
BC1[4]
BC2[4]
BC3[4]
BC4[4]
AC0[3]
AC1[3]
AC2[3]
AC3[3]
AC4[3]
BC0[3]
BC1[3]
BC2[3]
BC3[3]
BC4[3]
AC0[2]
AC1[2]
AC2[2]
AC3[2]
AC4[2]
BC0[2]
BC1[2]
BC2[2]
BC3[2]
BC4[2]
AC0[1]
AC1[1]
AC2[1]
AC3[1]
AC4[1]
BC0[1]
BC1[1]
BC2[1]
BC3[1]
BC4[1]
AC0[0]
AC1[0]
AC2[0]
AC3[0]
AC4[0]
BC0[0]
BC1[0]
BC2[0]
BC3[0]
BC4[0]
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
Each byte is MSB first with respect to the 80 Channel Status bits. Thus bit 0 of address 23h, AC0[0], is the
location of the Pro bit. For N = 0-79, Channel Status bit N (per AES specification) is mapped to bit N mod 8
(remainder of N divided by 8) at address 23h+floor(N/8) (23h + integer result of N divided by 8 rounded
down). For example, Channel Status bit 35 is mapped to bit 3 (35/8 = 4 remainder 3) of address 27h (23h
+ 4h).
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11.26 IEC61937 PC/PD Burst preamble (2Dh - 30h)
Address
2Dh
Burst Preamble Byte
Burst Preamble PC Byte 0
Burst Preamble PC Byte 1
Burst Preamble PD Byte 0
Burst Preamble PD Byte 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PC0[7]
PC1[7]
PD0[7]
PD1[7]
PC0[6]
PC1[6]
PD0[6]
PD1[6]
PC0[5]
PC1[5]
PD0[5]
PD1[5]
PC0[4]
PC0[4]
PC0[4]
PD1[4]
PC0[3]
PC1[3]
PD0[3]
PD1[3]
PC0[2]
PC1[2]
PD0[2]
PD1[2]
PC0[1]
PC1[1]
PD0[1]
PD1[1]
PC0[0]
PC1[0]
PD0[0]
PD1[0]
2Eh
2Fh
30h
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12.APPLICATIONS
12.1 Reset, Power Down, and Start-Up
When RST is low the CS8422 enters a low power mode, all internal states are reset, and the outputs are
disabled. After RST transitions from low to high the part senses the resistor value on the configuration pins
(MS_SEL and SAOF) and sets the appropriate mode of operation. After the mode has been set (approxi-
mately 4 μs) the part is set to normal operation and all outputs are functional.
12.2 Power Supply, Grounding, and PCB layout
The CS8422 operates from a VA = +3.3 V and VL = +1.8 V to +5.0 V supply. These supplies may be set
independently. Follow normal supply decoupling practices, see Figure 7 and 8 for details.
Extensive use of power and ground planes, ground plane fill in unused areas, and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be mounted on the same side of the board as
the CS8422 to minimize inductance effects and all decoupling capacitors should be as close to the CS8422
as possible. The pin of the configuration resistors not connected to MS_SEL and SAOF should be connect-
ed as close as possible to VL or DGND.
12.3 External Receiver Components
The CS8422 AES3 receiver is designed to accept both the professional and consumer interfaces. The dig-
ital audio specifications for professional use call for a balanced receiver, using XLR connectors, with
110 Ω ± 20% impedance. The XLR connector on the receiver should have female pins with a male shell.
Since the receiver has a very high input impedance, a 110 Ω resistor should be placed across the receiver
terminals to match the line impedance, as shown in Figure 26 and Figure 27. Although transformers are not
required by the AES specification, they are strongly recommended.
If some isolation is desired without the use of transformers, a 0.01 μF capacitor should be placed in series
with each input pin (RXP[3:0] and RXN[3:0]) as shown in Figure 27. However, if a transformer is not used,
high frequency energy could be coupled into the receiver, causing degradation in analog performance.
Figure 26 and Figure 27 show an optional (recommended) DC blocking capacitor (0.1 μF to 0.47 μF) in se-
ries with the cable input. This improves the robustness of the receiver, preventing the saturation of the trans-
former, or any DC current flow, if a DC voltage is present on the cable.
The circuit in Figure 28 shows the input circuit for switching between up to four single-ended signals in re-
ceiver input Mode 1 (analog sensitivity mode). If the application requires switching between a single-ended
consumer interface and a differential interface, the CS8422 must be in differential mode and the input circuit
in Figure 28 should be used for the single ended source. Standards for the consumer interface call for an
unbalanced circuit having a receiver impedance of 75 Ω ±5%. The connector for the consumer interface is
an RCA phono socket.
The circuit in Figure 29 shows the input circuit for switching between up to four single-ended TTL or CMOS
signals, and should be used when the S/PDIF receiver is in Receiver Input Mode 2. If the application re-
quires switching between a CMOS or TTL source and a differential source, the CS8422 must be in differ-
ential mode and the input circuit in Figure 30 should be used for the single-ended digital source. If the
application requires switching between a single ended source in Mode 1, and a TTL or CMOS source, the
circuit in Figure 30 should be used for the CMOS/TTL source (no RXN connection is present in this case).
When designing systems, it is important to avoid ground loops and DC current flowing down the shield of
the cable that could result when boxes with different ground potentials are connected. Generally, it is good
practice to ground the shield to the chassis of the transmitting unit, and connect the shield through a capac-
itor to chassis ground at the receiver. However, in some cases it is advantageous to have the ground of two
64
DS692PP2
CS8422
boxes held to the same potential, and the cable shield might be depended upon to make that electrical con-
nection. Generally, it is a good idea to provide the option of grounding or capacitively coupling the shield to
the chassis.
CS8422
CS8422
* See Text
0.01 μF
0.01 μF
XLR
* See Text
XLR
RXP
RXP0
RXN0
110 Ω
Twisted
Pair
110 Ω
Twisted
Pair
110 Ω
110 Ω
RXN
1
1
Figure 26. Professional Input Circuit – Differential
Mode
Figure 27. Transformerless Professional Input Cir-
cuit – Differential Mode
.01μF
.01μF
CS8422
RX3
75 Ω
CS8422
75 Ω
Coax
0.01 μF
RCA Phono
RXP
RX2
75 Ω
75 Ω
Coax
75 Ω
Coax
.
.
.
75 Ω
75 Ω
.01μF
RXN
0.01 μF
RX0
75 Ω
Coax
Figure 28. S/PDIF MUX Input Circuit – Single-Ended
Receiver Mode 1 Single-Ended Input Circuit –
Differential Mode
TTL/CMOS
CS8422
TTL/CMOS
CS8422
0.01 μF
RX3
RXP
RXN
RX0
0.01μF
Figure 29. S/PDIF MUX Input Circuit – Digital Mode
Figure 30. TTL/CMOS Input Circuit – Differential
Mode
12.3.1 Attenuating Input signals
The input signals to the RX, RXP, and RXN pins in all modes of operation are limited to amplitudes equal
to, or less than +3.3 V. In some cases it may be necessary to attenuate the input signal so the input to the
device is within the valid operating range. Figures 31 and 32 illustrate how this should be done for both sin-
gle-ended and differential inputs. In both cases, equations (1) and (2) must be satisfied simultaneously.
DS692PP2
65
CS8422
.01μF
CS8422
RX
R1
+
Vin
-
75 Ω
R2
Coax
AGND
247.5
Vin
(1)
R2 =
(2) R1 = 75 – R2
Figure 31. Receiver Input Attenuation – Single-ended Input
CS8422
Rin
Vin+
Vin-
RXP
110 Ω
Twisted
Pair
R
Rin
RXN
AGND
726
Vin+ - Vin-
(1)
(2)
R =
R
2
Rin = 55 -
Figure 32. Receiver Input Attenuation – Differential Input
12.3.2 Isolating Transformer Requirements
Please refer to the application note AN134: AES and SPDIF Recommended Transformers for resources on
transformer selection
12.4 Channel Status Buffer Management
12.4.1 AES3 Channel Status (C) Bit Management
The CS8422 contains sufficient RAM to store the first 5 bytes of C data for both A and B channels (5 x 2 x 8
= 80 bits). The user may read from this buffer’s RAM through the control port.
The buffering scheme involves two buffers, named D and E, as shown in Figure 33. The MSB of each byte
represents the first bit in the serial C data stream. For example, the MSB of byte 0 (which is at control port
address 23h) is the consumer/professional bit for channel status block A.
The first buffer (D) accepts incoming C data from the AES receiver. The 2nd buffer (E) accepts entire blocks
of data from the D buffer. The E buffer is also accessible from the control port, allowing reading of the first
five bytes of C data.
The complete C data may be obtained through the C pin in Hardware Mode and through one of the GPO
pins in Software Mode. The C data is serially shifted out of the CS8422 clocked by the rising and falling
edges of OLRCK or VLRCK.
66
DS692PP2
CS8422
There are a number of conditions that will inhibit the buffer update. If the CS_UPDATE bit in “Receiver Sta-
tus (16h)” is set to ‘0’, the only condition that will inhibit the update is PLL phase unlock. If the CS_UPDATE
bit in “Receiver Status (16h)” is set to ‘1’, a biphase, confidence, parity, or CRC error will also inhibit the
update.
A
B
8-bits 8-bits
Control
Port
Registers
Received
Data
Buffer
From
AES3
Receiver
5 words
E
24 words
D
C Data Serial Output
Figure 33. Channel Status Data Buffer Structure
12.4.2 Accessing the E buffer
The user can monitor the incoming data by reading the E buffer, which is mapped into the register space of
the CS8422, through the control port.
The user can configure the interrupt enable register to cause interrupts to occur whenever D to E buffer
transfers occur. This allows determination of the allowable time periods to interact with the E buffer.
Also provided is a D to E inhibit bit in the “Receiver Data Control (04h)” register. This may be used whenever
“long” control port interactions are occurring or for debugging purposes.
A flowchart for reading the E buffer is shown in Figure 34. Since a D to E interrupt occurs just after reading,
there is a substantial time interval until the next D to E transfer (approximately 192 frames worth of time).
This is usually enough time to access the E data without having to inhibit the next transfer.
D to E interrupt occurs
Optionally set D to E inhibit
Read E data
If set, clear D to E inhibit
Return
Figure 34. Flowchart for Reading the E Buffer
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67
CS8422
12.4.3 Serial Copy Management System (SCMS)
In Software Mode, the CS8422 allows read access to all the channel status bits. For consumer mode SCMS
compliance, the host microcontroller needs to read and interpret the Category Code, Copy bit and L bit ap-
propriately.
In Hardware Mode, the SCMS protocol can be followed by using the C bit serial output pin. See “Channel
Status and User Data Handling” on page 34 for more details.
12.5 Jitter Attenuation
Figure 35 shows the jitter attenuation characteristics of the CS8422 PLL. The AES3 and IEC60958-4 spec-
ifications state a maximum of 2 dB jitter gain.
2
0
−2
−4
−6
−8
−10
−12
−14
−16
−18
102
103
104
105
106
107
Jitter Frequency (Hz)
Figure 35. CS8422 PLL Jitter Attenuation Characteristics
68
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CS8422
12.6 Jitter Tolerance
Figure 36 shows the Receiver Jitter Tolerance template as illustrated in the AES3 and IEC60958-4 specifi-
cation. CS8422 devices have been tested to pass this template.
Figure 36. Jitter Tolerance Template
12.7 Group Delay
The group delay introduced by the CS8422 depends on the type of interface selected, and input and output sample
rates of the sample rate converter. The expression for the group delay through the CS8422 with the use of the sam-
ple rate converter is shown below, where the interface delay is 3 OLRCK periods in all modes except AES3 direct
mode, in which it is 2 OLRCK periods. If the sample rate converter is not being used, then the approximate group
delay will be equal to the interface delay.
8.7
Fsi Fso
5
TotalGroupDelay = ------- + --------- + InterfaceDelay
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69
CS8422
13.PERFORMANCE PLOTS
Test conditions (unless otherwise specified): Measurement bandwidth is 20 Hz to Fso/2 Hz (unweighted);
VA = VL = V_REG = 3.3 V; XTI - XTO = 24.576 MHz; Input signal is a 0 dBFS 1 kHz sine wave; data resolution is
24 bits; Serial Audio Input and Output ports set to slave; Input and output clocks and data are asynchronous.
+0
-10
-20
-30
+0
-10
-20
-30
-40
-50
-40
-50
-60
-60
-70
-70
-80
-80
-90
-90
d
B
F
S
d
B
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
-200
10k
20k
30k
40k
50k
Hz
60k
70k
80k
90k
2.5k
5k
7.5k
10k
12.5k
Hz
15k
17.5k
20k
22.5k
Figure 37. Wideband FFT –
Figure 38. Wideband FFT –
0 dBFS 1 kHz Tone, 48 kHz:48 kHz
0 dBFS 1 kHz Tone, 44.1 kHz:192 kHz
+0
-10
-20
-30
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-40
-50
-60
-70
-80
-90
d
d
B
F
S
B
F
S
-100
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
-200
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
22k
2.5k
5k
7.5k
10k
12.5k
Hz
15k
17.5k
20k
22.5k
Hz
Figure 39. Wideband FFT –
0 dBFS 1 kHz Tone, 44.1 kHz:48 kHz
Figure 40. Wideband FFT –
0 dBFS 1 kHz Tone, 48 kHz:44.1 kHz
+0
+0
-10
-20
-30
-10
-20
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
d
d
B
F
S
B
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
-200
5k
10k
15k
20k
25k
Hz
30k
35k
40k
45k
2.5k
5k
7.5k
10k
12.5k
Hz
15k
17.5k
20k
22.5k
Figure 41. Wideband FFT –
0 dBFS 1 kHz Tone, 48 kHz:96 kHz
Figure 42. Wideband FFT –
0 dBFS 1 kHz Tone, 96 kHz:48 kHz
70
DS692PP2
CS8422
+0
-10
-20
+ 0
-10
-20
-30
-40
-30
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
d
B
F
S
d
B
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
-200
5k
10k
15k
20k
25k
Hz
30k
35k
40k
45k
2.5k
5k
7.5k
10k
12.5k
Hz
15k
17.5k
20k
22.5k
Figure 43. Wideband FFT –
0 dBFS 1 kHz Tone, 192 kHz:48 kHz
Figure 44. Wideband FFT –
-60 dBFS 1 kHz Tone, 48 kHz:96 kHz
+ 0
-10
-20
+ 0
-10
-20
-30
-40
-30
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
d
d
B
F
S
B
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
-200
2.5k
5k
7.5k
10k
12.5k
Hz
15k
17.5k
20k
22.5k
10k
20k
30k
40k
50k
Hz
60k
70k
80k
90k
Figure 45. Wideband FFT –
-60 dBFS 1 kHz Tone, 48 kHz:48 kHz
Figure 46. Wideband FFT –
-60 dBFS 1 kHz Tone, 44.1 kHz:192 kHz
+ 0
-10
-20
+ 0
-10
-20
-30
-40
-30
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
d
d
B
F
S
B
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
-200
2.5k
5k
7.5k
10k
12.5k
Hz
15k
17.5k
20k
22.5k
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
22k
Hz
Figure 47. Wideband FFT –
-60 dBFS 1 kHz Tone, 44.1 kHz:48 kHz
Figure 48. Wideband FFT –
-60 dBFS 1 kHz Tone, 48 kHz:44.1 kHz
DS692PP2
71
CS8422
+ 0
-10
-20
+ 0
-10
-20
-30
-40
-30
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
d
B
F
S
d
B
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
-200
2.5k
5k
7.5k
10k
12.5k
Hz
15k
17.5k
20k
22.5k
2.5k
5k
7.5k
10k
12.5k
Hz
15k
17.5k
20k
22.5k
Figure 49. Wideband FFT –
-60 dBFS 1 kHz Tone, 96 kHz:48 kHz
Figure 50. IMD –
10 kHz and 11 kHz -7 dBFS, 96 kHz:48 kHz
+ 0
-10
-20
+ 0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-30
-40
-50
-60
-70
-80
-90
d
B
F
S
d
B
F
S
-100
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
-200
2.5k
5k
7.5k
10k
12.5k
Hz
15k
17.5k
20k
22.5k
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
22k
Hz
Figure 51. Wideband FFT –
-60 dBFS 1 kHz Tone, 192 kHz:48 kHz
Figure 52. IMD –
10 kHz and 11 kHz -7 dBFS, 48 kHz:44.1 kHz
+ 0
+ 0
-10
-20
-10
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
d
d
B
F
S
B
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
-200
2.5k
5k
7.5k
10k
12.5k
Hz
15k
17.5k
20k
22.5k
2.5k
5k
7.5k
10k
12.5k
Hz
15k
17.5k
20k
22.5k
Figure 53. IMD –
10 kHz and 11 kHz -7 dBFS, 44.1 kHz:48 kHz
Figure 54. Wideband FFT –
0 dBFS 20 kHz Tone, 44.1 kHz:48 kHz
72
DS692PP2
CS8422
+ 0
-10
-20
+ 0
-10
-20
-30
-40
-30
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
d
B
F
S
d
B
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
-200
10k
20k
30k
40k
50k
Hz
60k
70k
80k
90k
5k
10k
15k
20k
25k
Hz
30k
35k
40k
45k
Figure 55. Wideband FFT –
0 dBFS 80 kHz Tone, 192 kHz:192 kHz
Figure 56. Wideband FFT –
0 dBFS 20 kHz Tone, 48 kHz:96 kHz
+ 0
-10
-20
+ 0
-10
-20
-30
-40
-30
-40
-50
-60
-70
-80
-90
-50
-60
-70
-80
-90
d
B
F
S
d
B
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
-200
2.5k
5k
7.5k
10k
12.5k
Hz
15k
17.5k
20k
22.5k
2.5k
5k
7.5k
10k
12.5k
Hz
15k
17.5k
20k
22.5k
Figure 57. Wideband FFT –
0 dBFS 20 kHz Tone, 48 kHz:48 kHz
Figure 58. Wideband FFT –
0 dBFS 20 kHz Tone, 96 kHz:48 kHz
+ 0
T
+ 0
-10
-20
-10
-20
-30
-30
-40
-50
-60
-70
-80
-90
-40
-50
-60
-70
-80
-90
d
B
F
S
d
B
F
S
-1 00
-1 10
-1 20
-1 30
-1 40
-1 50
-1 60
-1 70
-1 80
-1 90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-2 00
-200
40 k
6 0k
80 k
10 0k
12 0k
1 40 k
1 60 k
1 80 k
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
22k
H z
Hz
Figure 59. Wideband FFT –
0 dBFS 20 kHz Tone, 48 kHz:44.1 kHz
Figure 60. THD+N vs. Output Sample Rate –
0 dBFS 1 kHz Tone, Fsi = 192 kHz
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CS8422
+ 0
+ 0
-10
-10
-20
-30
-20
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
d
B
F
S
d
B
F
S
-1 00
-1 10
-1 20
-1 30
-1 40
-1 50
-1 60
-1 70
-1 80
-1 90
-1 00
-1 10
-1 20
-1 30
-1 40
-1 50
-1 60
-1 70
-1 80
-1 90
-2 00
-2 00
40 k
6 0k
8 0k
1 00 k
1 20 k
1 40 k
1 60 k
1 80 k
40 k
6 0k
80 k
10 0k
12 0k
1 40 k
1 60 k
1 80 k
H z
H z
Figure 61. THD+N vs. Output Sample Rate –
0 dBFS 1 kHz Tone, Fsi = 48 kHz
Figure 62. THD+N vs. Output Sample Rate –
0 dBFS 1 kHz Tone, Fsi = 96 kHz
+ 0
+ 0
-10
-10
-20
-30
-20
-30
-40
-50
-60
-70
-80
-90
-40
-50
-60
-70
-80
-90
d
B
F
S
d
B
F
S
-1 00
-1 10
-1 20
-1 30
-1 40
-1 50
-1 60
-1 70
-1 80
-1 90
-1 00
-1 10
-1 20
-1 30
-1 40
-1 50
-1 60
-1 70
-1 80
-1 90
-2 00
-2 00
40 k
6 0k
8 0k
1 00 k
1 20 k
1 40 k
1 60 k
1 80 k
40 k
6 0k
80 k
10 0k
12 0k
1 40 k
1 60 k
1 80 k
H z
H z
Figure 63. THD+N vs. Output Sample Rate –
0 dBFS 1 kHz Tone, Fsi = 44.1 kHz
Figure 64. Dynamic Range vs. Output Sample Rate –
-60 dBFS 1 kHz Tone, Fsi = 192 kHz
+ 0
+ 0
-10
-10
-20
-30
-40
-50
-60
-70
-80
-20
-30
-40
-50
-60
-70
-80
-90
-90
d
d
B
F
S
B
F
S
-1 00
-1 00
-1 10
-1 10
-1 20
-1 30
-1 40
-1 50
-1 60
-1 70
-1 80
-1 90
-1 20
-1 30
-1 40
-1 50
-1 60
-1 70
-1 80
-1 90
-2 00
-2 00
40 k
6 0k
80 k
10 0k
12 0k
1 40 k
1 60 k
1 80 k
40 k
6 0k
80 k
10 0k
12 0k
1 40 k
1 60 k
1 80 k
H z
H z
Figure 65. THD+N vs. Output Sample Rate –
0 dBFS 1 kHz Tone, Fsi = 32 kHz
Figure 66. Dynamic Range vs. Output Sample Rate –
-60 dBFS 1 kHz Tone, Fsi = 32 kHz
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+ 0
+ 0
-10
-10
-20
-30
-20
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
d
B
F
S
d
B
F
S
-1 00
-1 10
-1 20
-1 30
-1 40
-1 50
-1 60
-1 70
-1 80
-1 90
-1 00
-1 10
-1 20
-1 30
-1 40
-1 50
-1 60
-1 70
-1 80
-1 90
-2 00
-2 00
40 k
6 0k
80 k
10 0k
12 0k
1 40 k
1 60 k
1 80 k
40 k
6 0k
80 k
10 0k
12 0k
1 40 k
1 60 k
1 80 k
H z
H z
Figure 67. Dynamic Range vs. Output Sample Rate –
Figure 68. Dynamic Range vs. Output Sample Rate –
-60 dBFS 1 kHz Tone, Fsi = 44.1 kHz
-60 dBFS 1 kHz Tone, Fsi = 96 kHz
+ 5
+ 0
-0.01
-0.02
T
T
T
+ 0
-5
-10
-15
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
-0.09
-20
-25
-30
-35
-40
192 kHz : 48 kHz
-45
-50
-55
-60
d
B
F
S
d
-65
B
F
S
-0 .1
-0.11
-0.12
-0.13
-0.14
-0.15
-0.16
-0.17
-0.18
-0.19
-70
-75
-80
-85
192 kHz : 32 kHz
-90
192 kHz : 96 kHz
-95
-1 00
-1 05
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 40
-0 .2
1 0k
20 k
3 0k
H z
40 k
50 k
6 0k
0
5 k
10 k
1 5k
2 0k
2 5k
H z
Figure 69. Frequency Response – 0 dBFS Input
Figure 70. Passband Ripple – 192 kHz:48 kHz
+ 0
+ 0
-5
-10
-10
-20
-30
-15
-20
-25
-40
-30
-50
-35
-40
-60
-45
-70
-50
-55
-80
-60
-90
d
B
F
S
-65
d
B
F
S
-1 00
-1 10
-1 20
-1 30
-1 40
-1 50
-1 60
-1 70
-1 80
-1 90
-70
-75
-80
-85
-90
-95
-1 00
-1 05
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-2 00
-1 40
-14 0
40 k
6 0k
8 0k
1 00 k
1 20 k
1 40 k
1 60 k
1 80 k
-12 0
-10 0
-80
-6 0
-40
-2 0
+ 0
H z
d B F S
Figure 71. Dynamic Range vs. Output Sample Rate –
-60 dBFS 1 kHz Tone, Fsi = 48 kHz
Figure 72. Linearity Error –
0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:48 kHz
DS692PP2
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CS8422
+ 0
-5
+ 0
-5
-10
-15
-10
-15
-20
-20
-25
-25
-30
-30
-35
-35
-40
-40
-45
-45
-50
-50
-55
-55
-60
-60
-65
d
B
F
S
-65
d
B
F
S
-70
-70
-75
-75
-80
-80
-85
-85
-90
-90
-95
-95
-1 00
-1 05
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 00
-1 05
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 40
-14 0
-1 40
-14 0
-12 0
-10 0
-80
-6 0
-40
-2 0
+ 0
-12 0
-1 00
-8 0
-60
-40
-20
+ 0
d B F S
dB F S
Figure 73. Linearity Error –
Figure 74. Linearity Error –
0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:44.1 kHz
0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:96 kHz
+ 0
+ 0
-5
-5
-10
-15
-10
-15
-20
-20
-25
-25
-30
-30
-35
-35
-40
-40
-45
-45
-50
-50
-55
-55
-60
-60
-65
-65
d
d
B
F
S
B
F
S
-70
-70
-75
-75
-80
-80
-85
-85
-90
-90
-95
-95
-1 00
-1 05
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 00
-1 05
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 40
-14 0
-1 40
-14 0
-12 0
-1 00
-8 0
-60
-40
-20
+ 0
-12 0
-10 0
-80
-6 0
-40
-2 0
+ 0
dB F S
d B F S
Figure 75. Linearity Error –
Figure 76. Linearity Error –
0 to -140 dBFS Input, 200 Hz Tone, 96 kHz:48 kHz
0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:192 kHz
+ 0
+ 0
-5
-5
-10
-15
-10
-15
-20
-20
-25
-25
-30
-30
-35
-35
-40
-40
-45
-45
-50
-50
-55
-55
-60
-60
-65
d
-65
d
B
F
S
B
F
S
-70
-70
-75
-75
-80
-80
-85
-85
-90
-90
-95
-95
-1 00
-1 05
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 00
-1 05
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 40
-14 0
-1 40
-14 0
-12 0
-10 0
-80
-6 0
-40
-2 0
+ 0
-12 0
-10 0
-80
-6 0
-40
-2 0
+ 0
d B F S
d B F S
Figure 77. Linearity Error –
0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:48 kHz
Figure 78. Linearity Error –
0 to -140 dBFS Input, 200 Hz Tone, 192 kHz:44.1 kHz
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-1 00
-1 05
-1 00
-1 05
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 40
-1 45
-1 50
-1 55
-1 60
-1 65
-1 70
-1 75
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 40
-1 45
-1 50
-1 55
-1 60
-1 65
-1 70
-1 75
d
B
F
S
d
B
F
S
-1 80
-14 0
-1 80
-14 0
-12 0
-10 0
-80
-6 0
-40
-2 0
+ 0
-12 0
-10 0
-80
-6 0
-40
-2 0
+ 0
d B F S
d B F S
Figure 79. THD+N vs. Input Amplitude –
1 kHz Tone, 48 kHz:44.1 kHz
Figure 80. THD+N vs. Input Amplitude –
1 kHz Tone, 48 kHz:96 kHz
-1 00
-1 05
-1 00
-1 05
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 40
-1 45
-1 50
-1 55
-1 60
-1 65
-1 70
-1 75
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 40
-1 45
-1 50
-1 55
-1 60
-1 65
-1 70
-1 75
d
d
B
F
S
B
F
S
-1 80
-14 0
-1 80
-14 0
-12 0
-10 0
-80
-6 0
-40
-2 0
+ 0
-12 0
-10 0
-80
-6 0
-40
-2 0
+ 0
d B F S
d B F S
Figure 81. THD+N vs. Input Amplitude –
1 kHz Tone, 96 kHz:48 kHz
Figure 82. THD+N vs. Input Amplitude –
1 kHz Tone, 44.1 kHz:192 kHz
-1 00
-1 05
-1 00
-1 05
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 40
-1 45
-1 50
-1 55
-1 60
-1 65
-1 70
-1 75
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 40
-1 45
-1 50
-1 55
-1 60
-1 65
-1 70
-1 75
d
d
B
F
S
B
F
S
-1 80
-14 0
-1 80
-14 0
-12 0
-1 00
-8 0
-60
-40
-20
+ 0
-12 0
-1 00
-8 0
-60
-40
-20
+ 0
dB F S
dB F S
Figure 83. THD+N vs. Input Amplitude –
1 kHz Tone, 44.1 kHz:48 kHz
Figure 84. THD+N vs. Input Amplitude –
1 kHz Tone, 192 kHz:48 kHz
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-1 00
-1 05
-1 00
-1 05
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 40
-1 45
-1 50
-1 55
-1 60
-1 65
-1 70
-1 75
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 40
-1 45
-1 50
-1 55
-1 60
-1 65
-1 70
-1 75
d
B
F
S
d
B
F
S
-1 80
-1 80
0
2 k
4 k
6k
8k
10 k
H z
12 k
1 4 k
16 k
18 k
2 0k
0
0
0
2 k
4 k
6 k
8 k
1 0k
H z
1 2k
14 k
1 6k
18 k
2 0k
Figure 85. THD+N vs. Input Frequency –
0 dBFS, 48 kHz:44.1 kHz
Figure 86. THD+N vs. Input Frequency –
0 dBFS, 48 kHz:96 kHz
-1 00
-1 05
-1 00
-1 05
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 40
-1 45
-1 50
-1 55
-1 60
-1 65
-1 70
-1 75
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 40
-1 45
-1 50
-1 55
-1 60
-1 65
-1 70
-1 75
d
B
F
S
d
B
F
S
-1 80
-1 80
2 k
4 k
6 k
8 k
1 0k
H z
1 2k
14 k
1 6k
18 k
2 0k
0
2 k
4 k
6 k
8 k
1 0k
H z
1 2k
14 k
1 6k
18 k
2 0k
Figure 87. THD+N vs. Input Frequency –
0 dBFS, 44.1 kHz:48 kHz
Figure 88. THD+N vs. Input Frequency –
0 dBFS, 96 kHz:48 kHz
-1 00
-1 05
-1 10
-1 15
-1 20
-1 25
-1 30
-1 35
-1 40
-1 45
-1 50
-1 55
-1 60
-1 65
-1 70
-1 75
d
B
F
S
-1 80
2 k
4 k
6 k
8 k
1 0k
H z
1 2k
14 k
1 6k
18 k
2 0k
Figure 89. Total Power Supply Current vs. Differential
Mode Receiver Input Sample Frequency
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14.PACKAGE DIMENSIONS
32L QFN (5 X 5 mm BODY) PACKAGE DRAWING
b
e
Pin #1 Corner
D
Pin #1 Corner
E2
E
A1
A
L
D2
Bottom View
Top View
Side View
INCHES
MILLIMETERS
NOTE
DIM
A
A1
b
D
D2
E
E2
e
L
MIN
--
0.0000
0.0079
NOM
--
--
MAX
MIN
--
0.00
0.20
NOM
--
--
0.25
5.00 BSC
3.70
5.00 BSC
3.70
0.50 BSC
0.40
MAX
1.00
0.05
0.30
0.0394
0.0020
0.0118
1
1
1,2
1
1
1
1
1
1
0.0098
0.1969 BSC
0.1457
0.1969 BSC
0.1457
0.0197 BSC
0.0157
0.1437
0.1437
0.0118
0.1476
0.1476
0.0197
3.65
3.65
0.30
3.75
3.75
0.50
JEDEC #: MO-220
Controlling Dimension is Millimeters.
Notes:
1. Dimensioning and tolerance per ASME Y 14.5M-1995.
2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm
from the terminal tip
15.THERMAL CHARACTERISTICS AND SPECIFICATIONS
Parameters
Package Thermal Resistance (Note 1)
Allowable Junction Temperature
Symbol
Min
Typ
38
-
Max
-
Units
°C/Watt
°C
θ
-
-
JA
125
Notes:
1.
θ
is specified according to JEDEC specifications for multi-layer PCBs.
JA
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16.ORDERING INFORMATION
Temp
Range
Pb-Free
YES
Order#
Product
Description
Package
Grade
Container
Rail
CS8422-CNZ
-40° to
+85°C
24-bit, Asynchronous
Sample Rate Converter with
Integrated Digital Interface
Receiver
Commercial
Tape and Reel CS8422-CNZR
Rail CS8422-DNZ
Tape and Reel CS8422-DNZR
CS8422
QFN
-40° to
+105°C
Automotive
-
Evaluation Board for
CS8422
CDB8422
-
YES
-
-
CDB8422
17.REFERENCES
1. Audio Engineering Society AES3-2003: “AES standard for digital audio - Digital input-output interfacing -
Serial transmission format for two-channel linearly represented digital audio data,” September 2003.
2. Audio Engineering Society AES-12id-2006: “AES Information Document for digital audio measurements -
Jitter performance specifications,” May 2007.
3. Philips Semiconductor, “The I²C-Bus Specification: Version 2,” Dec. 1998.
http://www.semiconductors.philips.com
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18.REVISION HISTORY
Release
Changes
PP1
Added interchannel phase deviation to Performance Specifications - Sample Rate Converter table
Added gain error to Performance Specifications - Sample Rate Converter table
Added 32 kHz:48 kHz dynamic range to Performance Specifications - Sample Rate Converter table
Updated (Note 2) in Performance Specifications - Sample Rate Converter table
Updated values in DC Electrical Characteristics table
Changed (Note 3) and (Note 4) in DC Electrical Characteristics table
Updated RMCK jitter specification in Switching Specifications table
Changed (Note 9) in Switching Specifications table
Moved SDIN/TDM_IN setup and hold times in Switching Specifications table
Changed master mode non-TDM I/OSCLK minimum frequency in Switching Specifications table
Changed tsrs value in Switching Characteristics - Control Port - SPI mode
Changed tirs value in Switching Characteristics - Control Port - I²C mode
Fixed calculation error in Section 5.1.5.2 TDM Slave Mode
Added note to Section 11.9 Recovered Master Clock Ratio Control & Misc. (09h)
Added Section 12.6 Jitter Tolerance
Added Section 13. Performance Plots
Added Section 17. References
Updated VIH minimum specification in Digital Interface Specifications table
Updated VIL maximum specification in Digital Interface Specifications table
Updated Input Hysteresis specification in Digital Interface Specifications table
Added (Note 6) to Digital Interface Specifications table
Removed VIH maximum specification in Digital Interface Specifications table
Removed VIL minimum specification in Digital Interface Specifications table
PP2
Updated package dimensions in Section 14. Package Dimensions
DS692PP2
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CS8422
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
“Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its sub-
sidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and
is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before
placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order
acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this informa-
tion, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document
is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks,
trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be
made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to
other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT-
ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIR-
RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM-
ER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY
INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT-
TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
AC-3 is a registered trademark of Dolby Laboratories, Inc.
DTS is a registered trademark of Digital Theater Systems, Inc.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
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DS692PP2
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