EP7311-IR-C [CIRRUS]
HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE; 高性能,低功耗的系统级芯片, SDRAM和增强数字音频接口型号: | EP7311-IR-C |
厂家: | CIRRUS LOGIC |
描述: | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
文件: | 总54页 (文件大小:1540K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EP7311 Data Sheet
High-Performance,
FEATURES
I ARM720T Processor
Low-Power System on Chip with
SDRAM and Enhanced Digital
Audio Interface
— ARM7TDMI CPU
— 8 KB of four-way set-associative cache
— MMU with 64-entry TLB
— Thumb code support enabled
I Ultra low power
OVERVIEW
— 90 mW at 74 MHz typical
— 30 mW at 18 MHz typical
— 10 mW in the Idle State
— <1 mW in the Standby State
I 48 KB of on-chip SRAM
The Maverick™ EP7311 is designed for ultra-low-power
applications such as PDAs, smart cellular phones, and
industrial hand held information appliances. The core-
logic functionality of the device is built around an
ARM720T processor with 8 KB of four-way set-
associative unified cache and a write buffer. Incorporated
into the ARM720T is an enhanced memory management
unit (MMU) which allows for support of sophisticated
™
I MaverickKey IDs
— 32-bit unique ID can be used for SDMI compliance
— 128-bit random ID
®
operating systems like Linux .
I Dynamically programmable clock speeds of
18, 36, 49, and 74 MHz
(cont.)
(cont.)
BLOCK DIAGRAM
EPB Bus
Multimedia
Codec Port
Clocks &
Timers
ARM720T
ICE-JTAG
Power
Management
Serial
Interrupts,
Interface
PWM & GPIO
ARM7TDMI CPU Core
8 KB
Cache
Write
Buffer
Keypad&
Touch
Screen I/F
(2) UARTs
w/ IrDA
Boot
ROM
Bus
Bridge
MMU
Internal Data Bus
Memory Controller
SRAM I/F SDRAM I/F
On-chip SRAM
48 KB
LCD
Controller
TM
MaverickKey
MEMORY AND STORAGE
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
Nov ’03
DS506PP1
http://www.cirrus.com
EP7311
High-Performance, Low-Power System on Chip
FEATURES (cont)
I LCD controller
— Interrupt Controller
— Boot ROM
— Interfaces directly to a single-scan panel
monochrome STN LCD
I Package
— Interfaces to a single-scan panel color STN LCD
with minimal external glue logic
— 208-Pin LQFP
— 256-Ball PBGA
— 204-Ball TFBGA
I Full JTAG boundary scan and Embedded ICE
support
I The fully static EP7311 is optimized for low power
dissipation and is fabricated on a 0.25 micron CMOS
process
I Integrated Peripheral Interfaces
— 32-bit SDRAM Interface up to 2 external banks
— 8/ 32/ 16-bit SRAM/ FLASH/ ROM Interface
— Multimedia Codec Port
I Development Kits
— EDB7312: Development Kit with color STN LCD
on board.
— Two Synchronous Serial Interfaces (SSI1, SSI2)
— CODEC Sound Interface
— EDB7312-LW: EDB7312 with Lynuxworks’
BlueCat Linux Tools and software for Windows
host (free 30 day BlueCat support from
Lynuxworks).
— 8×8 Keypad Scanner
— 27 General Purpose Input/ Output pins
— Dedicated LED flasher pin from the RTC
I Internal Peripherals
— EDB7312-LL: EDB7312 with Lynuxworks’ BlueCat
Linux Tools and software for Linux host (free 30
day BlueCat support from Lynuxworks).
— Two 16550 compatible UARTs
— IrDA Interface
Note: * BlueCat available separately through Lynuxworks
— Two PWM Interfaces
only.
* Use the EDB7312 Development Kit for all the EP73xx
devices.
— Real-time Clock
— Two general purpose 16-bit timers
OVERVIEW (cont.)
The EP7311 is designed for low-power operation. Its core
operates at only 2.5 V, while its I/ O has an operation
range of 2.5 V–3.3 V. The device has three basic power
states: operating, idle and standby.
Simply by adding desired memory and peripherals to the
highly integrated EP7311 completes a low-power system
solution. All necessary interface logic is integrated on-
chip.
One of its notable features is MaverickKey unique IDs.
These are factory programmed IDs in response to the
growing concern over secure web content and commerce.
With Internet security playing an important role in the
delivery of digital media such as books or music,
traditional software methods are quickly becoming
unreliable. The MaverickKey unique IDs consist of two
registers, one 32-bit series register and one random 128-
bit register that may be used by an OEM for an
authentication mechanism.
2
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Digital Music Initiative) or any other authentication
mechanism.
Processor Core - ARM720T
The EP7311 incorporates an ARM 32-bit RISC
microcontroller that controls a wide range of on-chip
peripherals. The processor utilizes a three-stage pipeline
consisting of fetch, decode and execute stages. Key
features include:
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP7311 through the use of laser
probing technology. These IDs can then be used to match
secure copyrighted content with the ID of the target
device the EP7311 is powering, and then deliver the
copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today’s
Internet appliances.
•
•
ARM (32-bit) and Thumb (16-bit compressed)
instruction sets
Enhanced MMU for Microsoft Windows CE and other
operating systems
•
•
8 KB of 4-way set-associative cache.
Translation Look Aside Buffers with 64 Translated
Entries
Memory Interfaces
There are two main external memory interfaces. The first
one is the ROM/ SRAM/ FLASH-style interface that has
programmable wait-state timings and includes burst-
mode capability, with six chip selects decoding six
256 MB sections of addressable space. For maximum
flexibility, each bank can be specified to be 8-, 16-, or 32-
bits wide. This allows the use of 8-bit-wide boot ROM
options to minimize overall system cost. The on-chip
boot ROM can be used in product manufacturing to
serially download system code into system FLASH
memory. To further minimize system memory
requirements and cost, the ARM Thumb instruction set is
supported, providing for the use of high-speed 32-bit
operations in 16-bit op-codes and yielding industry-
leading code density.
Power Management
The EP7311 is designed for ultra-low-power operation.
Its core operates at only 2.5 V, while its I/ O has an
operation range of 2.5 V–3.3 V allowing the device to
achieve a performance level equivalent to 60 MIPS. The
device has three basic power states:
• Operating — This state is the full performance
state. All the clocks and peripheral logic are
enabled.
• Idle — This state is the same as the Operating
State, except the CPU clock is halted while
waiting for an event such as a key press.
• Standby — This state is equivalent to the
computer being switched off (no display), and
the main oscillator shut down. An event such as
a key press can wake-up the processor.
Pin Mnemonic
nCS[5:0]
I/O
Pin Description
Chip select out
Address output
O
O
A[27:0]
D[31:0]
I/O Data I/O
Pin Mnemonic
BATOK
I/O
Pin Description
Battery ok input
nMOE/nSDCAS
nMWE/nSDWE
(Note)
(Note)
O
O
ROM expansion OP enable
I
ROM expansion write enable
External power supply sense
input
nEXTPWR
I
Halfword access select
output
HALFWORD
O
nPWRFL
I
I
Power fail sense input
WORD
O
O
Word access select output
Transfer direction
nBATCHG
Battery changed sense input
WRITE/nSDRAS
(Note)
Table A. Power Management Pin Assignments
Table B. Static Memory Interface Pin Assignments
MaverickKey™ Unique ID
Note: Pins are multiplexed. See Table S on page 8 for more
information.
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
3
EP7311
High-Performance, Low-Power System on Chip
The second is the programmable 16- or 32-bit-wide
SDRAM interface that allows direct connection of up to
two banks of SDRAM, totaling 512 Mb. To assure the
lowest possible power consumption, the EP7311
supports self-refresh SDRAMs, which are placed in a
low-power state by the device when it enters the low-
power Standby State.
RX/ TX signals to/ from UART 1 to enable these signals
to drive an infrared communication interface directly.
Pin Mnemonic
TXD[1]
I/O
Pin Description
UART 1 transmit
O
I
RXD[1]
CTS
UART 1 receive
I
UART 1 clear to send
UART 1 data carrier detect
UART 1 data set ready
UART 2 transmit
Pin Mnemonic
SDCLK
I/O
Pin Description
DCD
I
O
O
O
O
O
SDRAM clock output
DSR
I
SDCKE
SDRAM clock enable output
SDRAM chip select out
SDRAM RAS signal output
SDRAM CAS control signal
TXD[2]
RXD[2]
LEDDRV
PHDIN
O
I
nSDCS[1:0]
UART 2 receive
WRITE/nSDRAS
nMOE/nSDCAS
(Note 2)
(Note 2)
O
I
Infrared LED drive output
Photo diode input
SDRAM write enable control
signal
nMWE/nSDWE
(Note 2)
O
Table D. Universal Asynchronous Receiver/Transmitters Pin
Assignments
A[27:15]/DRA[0:12] (Note 1)
A[14:13]/DRA[12:14]
PD[7:6]/SDQM[1:0] (Note 2)
SDQM[3:2]
O
O
SDRAM address
SDRAM internal bank select
Multimedia Codec Port (MCP)
I/O SDRAM byte lane mask
SDRAM byte lane mask
I/O Data I/O
The Multimedia Codec Port provides access to an audio
codec, a telecom codec, a touchscreen interface, four
general purpose analog-to-digital converter inputs, and
ten programmable digital I/ O lines.
O
D[31:0]
Table C. SDRAM Interface Pin Assignments
Pin Mnemonic
SIBCLK
I/O
Pin Description
Serial bit clock
Note: 1. Pins A[27:13] map to DRA[0:14] respectively.
(i.e. A[27}/DRA[0}, A[26}/DRA[1], etc.) This is to
balance the load for large memory systems.
2. Pins are multiplexed. See Table S on page 8 for
more information.
O
O
I
SIBDOUT
SIBDIN
Serial data out
Serial data in
Sample clock
SIBSYNC
O
Digital Audio Capability
Table E. MCP Interface Pin Assignments
The EP7311 uses its powerful 32-bit RISC processing
engine to implement audio decompression algorithms in
software. The nature of the on-board RISC processor, and
the availability of efficient C-compilers and other
software development tools, ensures that a wide range of
audio decompression algorithms can easily be ported to
and run on the EP7311
Note: See Table R on page 8 for information on pin
multiplexes.
Universal Asynchronous
Receiver/Transmitters (UARTs)
The EP7311 includes two 16550-type UARTs for RS-232
serial communications, both of which have two 16-byte
FIFOs for receiving and transmitting data. The UARTs
support bit rates up to 115.2 kbps. An IrDA SIR protocol
encoder/ decoder can be optionally switched into the
4
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
CODEC Interface
Synchronous Serial Interface
The EP7311 includes an interface to telephony-type
CODECs for easy integration into voice-over-IP and
other voice communications systems. The CODEC
interface is multiplexed to the same pins as the MCP and
SSI2.
•
ADC (SSI) Interface: Master mode only; SPI and
Microwire1-compatible (128 kbps operation)
•
Selectable serial clock polarity
Pin Mnemonic
ADCLK
I/O
Pin Description
Pin Mnemonic
PCMCLK
I/O
Pin Description
Serial bit clock
O
I
SSI1 ADC serial clock
SSI1 ADC serial input
SSI1 ADC serial output
SSI1 ADC chip select
SSI1 ADC sample clock
O
O
I
ADCIN
PCMOUT
PCMIN
Serial data out
Serial data in
Frame sync
ADCOUT
nADCCS
SMPCLK
O
O
O
PCMSYNC
O
Table F. CODEC Interface Pin Assignments
Table H. Serial Interface Pin Assignments
Note: See Table R on page 8 for information on pin
multiplexes.
LCD Controller
A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The
display frame buffer start address is programmable,
allowing the LCD frame buffer to be in SDRAM, internal
SRAM or external SRAM.
SSI2 Interface
An additional SPI/ Microwire1-compatible interface is
available for both
communications. The SSI2 unit shares the same pins as
the MCP and CODEC interfaces through a multiplexer.
master
and
slave mode
•
•
•
•
•
Interfaces directly to a single-scan panel monochrome
STN LCD
•
•
•
•
Synchronous clock speeds of up to 512 kHz
Separate 16 entry TX and RX half-word wide FIFOs
Half empty/ full interrupts for FIFOs
Interfaces to a single-scan panel color STN LCD with
minimal external glue logic
Panel width size is programmable from 32 to 1024
pixels in 16-pixel increments
Separate RX and TX frame sync signals for
asymmetric traffic
Video frame buffer size programmable up to
128 KB
Pin Mnemonic
SSICLK
I/O
Pin Description
Serial bit clock
Bits per pixel of 1, 2, or 4 bits
I/O
O
SSITXDA
SSIRXDA
SSITXFR
SSIRXFR
Serial data out
Pin Mnemonic
CL1
I/O
Pin Description
LCD line clock
I
Serial data in
O
O
O
O
O
I/O
I/O
Transmit frame sync
Receive frame sync
CL2
LCD pixel clock out
DD[3:0]
FRM
M
LCD serial display data bus
LCD frame synchronization pulse
LCD AC bias drive
Table G. SSI2 Interface Pin Assignments
Note: See Table R on page 8 for information on pin
multiplexes.
Table I. LCD Interface Pin Assignments
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
5
EP7311
High-Performance, Low-Power System on Chip
.
64-Keypad Interface
Pin Mnemonic
nEINT[2:1]
I/O
Pin Description
External interrupt
Matrix keyboards and keypads can be easily read by the
I
I
I
I
EP7311.
A
dedicated 8-bit column driver output
EINT[3]
External interrupt
generates strobes for each keyboard column signal. The
pins of Port A, when configured as inputs, can be
nEXTFIQ
External Fast Interrupt input
Media change interrupt input
selectively OR'ed together to provide
a keyboard
nMEDCHG/nBROM
(Note)
interrupt that is capable of waking the system from a
STANDBY or IDLE state.
Table K. Interrupt Controller Pin Assignments
•
•
•
•
•
Column outputs can be individually set high with the
remaining bits left at high-impedance
Note: Pins are multiplexed. See Table S on page 8 for more
information.
Column outputs can be driven all-low, all-high, or all-
high-impedance
Real-Time Clock
Keyboard interrupt driven by OR'ing together all Port
A bits
The EP7311 contains a 32-bit Real Time Clock (RTC) that
can be written to and read from in the same manner as
the timer counters. It also contains a 32-bit output match
register which can be programmed to generate an
interrupt.
Keyboard interrupt can be used to wake up the
system
8×8 keyboard matrix usable with no external logic,
extra keys can be added with minimal glue logic
•
Driven by an external 32.768 kHz crystal oscillator
Pin Mnemonic
COL[7:0]
I/O
Pin Description
Pin Mnemonic
RTCIN
Pin Description
O
Keyboard scanner column drive
Real-Time Clock Oscillator Input
Real-Time Clock Oscillator Output
Real-Time Clock Oscillator Power
Real-Time Clock Oscillator Ground
Table J. Keypad Interface Pin Assignments
RTCOUT
VDDRTC
VSSRTC
Interrupt Controller
When unexpected events arise during the execution of a
program (i.e., interrupt or memory fault) an exception is
usually generated. When these exceptions occur at the
same time, a fixed priority system determines the order
in which they are handled. The EP7311 interrupt
controller has two interrupt types: interrupt request
(IRQ) and fast interrupt request (FIQ). The interrupt
controller has the ability to control interrupts from 22
different FIQ and IRQ sources.
Table L. Real-Time Clock Pin Assignments
PLL and Clocking
•
Processor and Peripheral Clocks operate from a single
3.6864 MHz crystal or external 13 MHz clock
•
Programmable clock speeds allow the peripheral bus
to run at 18 MHz when the processor is set to 18 MHz
and at 36 MHz when the processor is set to 36, 49 or
74 MHz
•
•
•
Supports 22 interrupts from a variety of sources (such
as UARTs, SSI1, and key matrix.)
Routes interrupt sources to the ARM720T’s IRQ or
FIQ (Fast IRQ) inputs
Pin Mnemonic
MOSCIN
Pin Description
Main Oscillator Input
Five dedicated off-chip interrupt lines operate as level
sensitive interrupts
MOSCOUT
VDDOSC
VSSOSC
Main Oscillator Output
Main Oscillator Power
Main Oscillator Ground
Table M. PLL and Clocking Pin Assignments
6
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
DC-to-DC converter interface (PWM)
Hardware debug Interface
•
Provides two 96 kHz clock outputs with
programmable duty ratio (from 1-in-16 to 15-in-16)
that can be used to drive a positive or negative DC to
DC converter
•
Full JTAG boundary scan and Embedded ICE
support
Pin Mnemonic
TCLK
I/O
Pin Description
JTAG clock
I
I
Pin Mnemonic
DRIVE[1:0]
FB[1:0]
I/O
Pin Description
PWM drive output
PWM feedback input
TDI
JTAG data input
I/O
I
TDO
nTRST
TMS
O
I
JTAG data output
JTAG async reset input
JTAG mode select
Table N. DC-to-DC Converter Interface Pin Assignments
I
Table P. Hardware Debug Interface Pin Assignments
Timers
•
•
Internal (RTC) timer
LED Flasher
Two internal 16-bit programmable hardware count-
down timers
A dedicated LED flasher module can be used to generate
a low frequency signal on Port D pin 0 for the purpose of
blinking an LED without CPU intervention. The LED
flasher feature is ideal as a visual annunciator in battery
powered applications, such as a voice mail indicator on a
portable phone or an appointment reminder on a PDA.
General Purpose Input/Output (GPIO)
•
•
Three 8-bit and one 3-bit GPIO ports
Supports scanning keyboard matrix
•
•
•
•
Software adjustable flash period and duty cycle
Operates from 32 kHz RTC clock
Pin Mnemonic
PA[7:0]
I/O
Pin Description
GPIO port A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Will continue to flash in IDLE and STANDBY states
4 mA drive current
PB[7:0]
GPIO port B
GPIO port D
GPIO port D
GPIO port D
GPIO port E
GPIO port E
PD[0]/LEDFLSH
PD[5:1]
(Note)
(Note)
Pin Mnemonic
PD[0]/LEDFLSH (Note)
I/O
Pin Description
LED flasher driver
PD[7:6]/SDQM[1:0]
O
PE[1:0]/BOOTSEL[1:0] (Note)
PE[2]/CLKSEL (Note)
Table Q. LED Flasher Pin Assignments
Note: Pins are multiplexed. See Table S on page 8 for more
information.
Table O. General Purpose Input/Output Pin Assignments
Note: Pins are multiplexed. See Table S on page 8 for more
information.
Internal Boot ROM
The internal 128 byte Boot ROM facilitates download of
saved code to the on-board SRAM/ FLASH.
Packaging
The EP7311 is available in a 208-pin LQFP package, 256-
ball PBGA package or a 204-ball TFBGA package.
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
7
EP7311
High-Performance, Low-Power System on Chip
The following table shows the pins that have been
multiplexed in the EP7311.
Pin Multiplexing
The following table shows the pin multiplexing of the
MCP, SSI2 and the CODEC. The selection between SSI2
and the CODEC is controlled by the state of the SERSEL
bit in SYSCON2. The choice between the SSI2, CODEC,
and the MCP is controlled by the MCPSEL bit in
SYSCON3 (see the EP73xx User ’s Manual for more
information).
Signal
nMOE
Block
Signal
nSDCAS
Block
SDRAM
Static Memory
Static Memory
Static Memory
Static Memory
Static Memory
GPIO
nMWE
nSDWE
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
WRITE
A[27:15]
A[14:13]
PD[7:6]
nSDRAS
DRA[0:12]
DRA[13:14]
SDQM[1:0]
Pin
Mnemonic
I/O
MCP
SSI2
CODEC
SSICLK
I/O
O
I
SIBCLK
SIBDOUT
SIBDIN
SIBSYNC
p/u
SSICLK
SSITXDA
SSIRXDA
PCMCLK
PCMOUT
PCMIN
System
Configuration
System
Configuration
RUN
CLKEN
SSITXDA
SSIRXDA
SSITXFR
SSIRXFR
Interrupt
Controller
Boot ROM
select
nMEDCHG
PD[0]
nBROM
I/O
I
SSITXFR PCMSYNC
SSIRXFR p/u
GPIO
GPIO
LEDFLSH
BOOTSEL[1:0]
LED Flasher
System
Configuration
PE[1:0]
BUZ
O
System
Configuration
Table R. MCP/SSI2/CODEC Pin Multiplexing
PE[2]
GPIO
CLKSEL
Table S. Pin Multiplexing
8
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
System Design
As shown in system block diagram, simply adding
desired memory and peripherals to the highly integrated
EP7311 completes a low-power system solution. All
necessary interface logic is integrated on-chip.
CRYSTAL
CRYSTAL
MOSCIN
RTCIN
DD[0-3]
CL1
LCD
CL2
FRM
nCS[4]
PB0
EXPCLK
M
COL[0-7]
KEYBOARD
D[0-31]
A[0-27]
PA[0-7]
PC CARD
CONTROLLER
PC CARD
SOCKET
PB[0-7]
nMOE
WRITE
PD[0-7]
DC
INPUT
PE[0-2]
POWER
SUPPLY UNIT
SDRAS/
SDCAS
AND
COMPARATORS
nPOR
nPWRFL
BATOK
nEXTPWR
nBATCHG
RUN
×16
SDRAM
×16
SDRAM
SDCS[0]
BATTERY
SDQM[0-3]
WAKEUP
SDCS[1]
×16
×16
SDRAM
SDRAM
SDQM[0-3]
DRIVE[0-1]
FB[0-1]
DC-TO-DC
CONVERTERS
nCS[0]
nCS[1]
SSICLK
SSITXFR
SSITXDA
SSIRXDA
SSIRXFR
CODEC/SSI2/
MCP
×16
FLASH
×16
FLASH
×16
FLASH
×16
FLASH
IR LED AND
PHOTODIODE
LEDDRV
PHDIN
CS[n]
WORD
RXD1/2
TXD1/2
DSR
2× RS-232
TRANSCEIVERS
EXTERNAL MEMORY-
MAPPED EXPANSION
BUFFERS
CTS
DCD
ADCCLK
nADCCS
ADCOUT
ADCIN
nCS[2]
nCS[3]
ADC
DIGITIZER
BUFFERS
AND
LATCHES
LEDFLSH
ADDITIONAL I/O
SMPCLK
Figure 1. A Maximum EP7311 Based System
Note: A system can only use one of the following peripheral
interfaces at any given time: SSI2,CODEC or MCP.
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
9
EP7311
High-Performance, Low-Power System on Chip
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
DC Core, PLL, and RTC Supply Voltage
DC I/O Supply Voltage (Pad Ring)
DC Pad Input Current
2.9 V
3.6 V
10 mA/pin; 100 mA cumulative
–40°C to +125°C
Storage Temperature, No Power
Recommended Operating Conditions
DC core, PLL, and RTC Supply Voltage
DC I/O Supply Voltage (Pad Ring)
DC Input / Output Voltage
2.5 V 0.2 V
2.3 V - 3.5 V
O–I/O supply voltage
Extended -20°C to +70°C; Commercial 0°C to +70°C;
Industrial -40°C to +85°C
Operating Temperature
DC Characteristics
All characteristics are specified at V
= 2.5 V, V
= 3.3 V and V = 0 V over an operating temperature of 0°C
DDCORE
DDIO SS
to +70°C for all frequencies of operation. The current consumption figures have test conditions specified per
parameter.”
Symbol
VIH
Parameter
Min
Typ
Max
Unit
Conditions
VDDIO = 2.5 V
VDDIO = 2.5 V
0.65 × VDDIO
VSS − 0.3
VDDIO + 0.3
0.25 × VDDIO
CMOS input high voltage
CMOS input low voltage
-
-
V
V
VIL
Schmitt trigger positive going
threshold
VT+
-
-
2.1
V
Schmitt trigger negative going
threshold
VT-
0.8
-
-
-
V
V
Vhst
Schmitt trigger hysteresis
0.1
0.4
VIL to VIH
CMOS output high voltagea
Output drive 1a
Output drive 2a
VDD – 0.2
-
-
-
-
-
-
V
V
V
IOH = 0.1 mA
IOH = 4 mA
IOH = 12 mA
VOH
VOL
2.5
2.5
CMOS output low voltagea
Output drive 1a
Output drive 2a
-
-
-
-
-
-
0.3
0.5
0.5
V
V
V
IOL = –0.1 mA
IOL = –4 mA
IOL = –12 mA
VIN = VDD or GND
IIN
Input leakage current
-
25
8
-
-
-
1.0
100
10.0
µA
µA
pF
Bidirectional 3-state leakage
currentb c
VOUT = VDD or GND
IOZ
CIN
Input capacitance
10
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Symbol
Parameter
Output capacitance
Min
Typ
Max
Unit
Conditions
COUT
CI/O
8
8
-
-
10.0
10.0
pF
pF
Transceiver capacitance
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD 0.1 V,
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
IDDSTANDBY
@ 25 C
-
-
77
41
-
-
µA
µA
µA
VIL = GND 0.1 V
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD 0.1 V,
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
IDDSTANDBY
@ 70 C
-
-
-
-
570
111
VIL = GND 0.1 V
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD 0.1 V,
Standby current consumption1
IDDSTANDBY
@ 85 C
-
-
-
-
1693
163
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
VIL = GND 0.1 V
Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = VDD 0.1 V, VIL
Idle current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
IDDidle
-
-
6
10
-
-
mA
V
at 74 MHz
= GND 0.1 V
Minimum standby voltage for
state retention, internal SRAM
cache, and RTC operation only
VDDSTANDBY
Standby supply voltage
2.0
-
-
a.
b.
c.
Refer to the strength column in the pin assignment tables for all package types.
Assumes buffer has no pull-up or pull-down resistors.
The leakage value given assumes that the pin is configured as an input pin but is not currently being driven.
Note: 1) Total power consumption = IDDCORE x 2.5 V + IDDIO x 3.3 V
2) A typical design will provide 3.3 V to the I/O supply (i.e., VDDIO), and 2.5 V to the remaining logic. This is to allow the I/O to be
compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs).
2) Pull-up current = 50 µA typical at VDD = 3.3 V.
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
11
EP7311
High-Performance, Low-Power System on Chip
Timings
Timing Diagram Conventions
This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any
variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless
specifically stated.
C l o c k
H i g h t o L o w
H i g h / L o w t o H i g h
B u s C h a n g e
B u s V a l i d
U n d e f i n e d / I n v a l i d
V a l i d B u s t o T r i s t a t e
B u s / S i g n a l O m i s s i o n
Figure 2. Legend for Timing Diagrams
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are
specified at V
= 3.1 - 3.5 V and V = 0 V over an operating temperature of -40°C to +85°C. Pin loadings is 50 pF.
DDIO
SS
The timing values are referenced to 1/ 2 V
.
DD
12
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
SDRAM Interface
Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the
values for the timings of each of the SDRAM modes.
Parameter
Symbol
tCSa
Min
Typ
Max
Unit
SDCLK rising edge to SDCS assert delay time
SDCLK rising edge to SDCS deassert delay time
SDCLK rising edge to SDRAS assert delay time
SDCLK rising edge to SDRAS deassert delay time
SDCLK rising edge to SDRAS invalid delay time
SDCLK rising edge to SDCAS assert delay time
SDCLK rising edge to SDCAS deassert delay time
SDCLK rising edge to ADDR transition time
SDCLK rising edge to ADDR invalid delay time
SDCLK rising edge to SDMWE assert delay time
SDCLK rising edge to SDMWE deassert delay time
DATA transition to SDCLK rising edge time
0
− 3
1
2
2
3
1
4
2
0
1
2
1
0
-
4
10
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCSd
tRAa
tRAd
− 3
2
10
7
tRAnv
tCAa
− 2
− 5
− 3
− 2
− 2
− 4
-
5
tCAd
3
tADv
5
tADx
5
tMWa
tMWd
tDAs
5
4
2
tDAh
SDCLK rising edge to DATA transition hold time
SDCLK rising edge to DATA transition delay time
-
-
1
tDAd
0
-
15
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
13
EP7311
High-Performance, Low-Power System on Chip
SDRAM Load Mode Register Cycle
SDCLK
tCSa
tCSd
tRAd
tCAd
SDCS
tRAa
SDRAS
tCAa
SDCAS
tADv
tADx
ADDR
DATA
SDQM
tMWa
tMWd
SDMWE
Figure 3. SDRAM Load Mode Register Cycle Timing Measurement
Note:
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
14
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
SDRAM Burst Read Cycle
SDCLK
tCSa
tCSa
tCSd
tCSd
SDCS
SDRAS
SDCAS
ADDR
tRAa
tRAd
tRAnv
tCAa
tCAd
tADv
tADv
ADRAS
ADCAS
tDAs
tDAs
tDAs
tDAs
DATA
D1
D2
D3
D4
tDAh
tDAh
tDAh
tDAh
SDQM
[0:3]
SDMWE
Figure 4. SDRAM Burst Read Cycle Timing Measurement
Note: 1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal.
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
15
EP7311
High-Performance, Low-Power System on Chip
SDRAM Burst Write Cycle
SDCLK
tCSa
tCSa
tCSd
tCSd
SDCS
tRAa
tRAd
SDRAS
SDCAS
tCAa
tCAd
tADv
tADv
ADDR
ADCAS
ADRAS
tDAd
tDAd
tDAd
tDAd
DATA
D1
D2
D3
D4
SDQM
0
tMWa
tMWd
SDMWE
Figure 5. SDRAM Burst Write Cycle Timing Measurement
Note:
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
16
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
SDRAM Refresh Cycle
SDCLK
tCSa
tCSd
SDCS
tRAa
tRAd
SDRAS
SDCAS
SDATA
ADDR
tCAd
tCAa
SDQM
[3:0]
SDMWE
Figure 6. SDRAM Refresh Cycle Timing Measurement
Note:
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
17
EP7311
High-Performance, Low-Power System on Chip
Static Memory
Figure 7 through Figure 10 define the timings associated with all phases of the Static Memory. The following table
contains the values for the timings of each of the Static Memory modes.
Parameter
Symbol
tCSd
tCSh
tAd
Min
Typ
Max
Unit
EXPCLK rising edge to nCS assert delay time
EXPCLK falling edge to nCS deassert hold time
EXPCLK rising edge to A assert delay time
EXPCLK falling edge to A deassert hold time
EXPCLK rising edge to nMWE assert delay time
EXPCLK rising edge to nMWE deassert hold time
EXPCLK falling edge to nMOE assert delay time
EXPCLK falling edge to nMOE deassert hold time
EXPCLK falling edge to HALFWORD deassert delay time
EXPCLK falling edge to WORD assert delay time
EXPCLK rising edge to data valid delay time
EXPCLK falling edge to data invalid delay time
Data setup to EXPCLK falling edge time
2
2
4
3
3
3
3
2
2
2
8
6
-
8
7
20
20
16
19
10
10
10
10
20
16
21
30
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
tAh
10
6
tMWd
tMWh
tMOEd
tMOEh
tHWd
tWDd
tDv
6
7
7
8
8
13
15
-
tDnv
tDs
tDh
EXPCLK falling edge to data hold time
-
-
3
tWRd
tEXs
EXPCLK rising edge to WRITE assert delay time
EXPREADY setup to EXPCLK falling edge time
EXPCLK falling edge to EXPREADY hold time
5
-
11
-
23
0
tEXh
-
-
0
18
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Static Memory Single Read Cycle
EXPCLK
tCSd
tCSh
nCS
tAd
A
nMWE
tMOEd
tMOEh
nMOE
tHWd
HALF-
WORD
tWDd
WORD
tDs
tDh
D
tEXs
tEXh
EXPRDY
tWRd
WRITE
Figure 7. Static Memory Single Read Cycle Timing Measurement
Note: 1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Address, Halfword, Word, and Write hold state until next cycle.
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
19
EP7311
High-Performance, Low-Power System on Chip
Static Memory Single Write Cycle
EXPCLK
tCSd
tCSh
nCS
tAd
A
tMWd
tMWh
nMWE
nMOE
tHWd
HALF-
WORD
tWDd
WORD
tDv
D
tEXs
tEXh
EXPRDY
WRITE
Figure 8. Static Memory Single Write Cycle Timing Measurement
Note: 1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
3. Address, Data, Halfword, Word, and Write hold state until next cycle.
20
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
EXPCLK
tCSd
tCSh
nCS
tAh
tAd
tAh
tAh
A
nMWE
tMOEd
tMOEh
nMOE
tHWd
HALF
WORD
tWDd
WORD
D
tDs tDh
tDs tDh
tDs tDh
tDs tDh
tEXs
tEXh
EXPRDY
WRITE
tWRd
Figure 9. Static Memory Burst Read Cycle Timing Measurement
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.
4. Address, Halfword, Word, and Write hold state until next cycle.
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
21
EP7311
High-Performance, Low-Power System on Chip
Static Memory Burst Write Cycle
EXPCLK
tCSd
tCSh
nCS
tAh
tAh
tAh
tAd
A
nMWE
nMOE
tMWd
tMWd
tMWd
tMWd
tMWh
tMWh
tMWh
tMWh
tHWd
HALF
WORD
tWDd
WORD
D
tDv
tDnv
tDv
tDnv
tDv tDnv
tDv
tEXs
tEXh
EXPRDY
WRITE
Figure 10. Static Memory Burst Write Cycle Timing Measurement
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
4. Address, Data, Halfword, Word, and Write hold state until next cycle.
22
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
SSI1 Interface
Parameter
Symbol
tCd
Min
Max
Unit
ADCCLK falling edge to nADCCSS deassert delay time
ADCIN data setup to ADCCLK rising edge time
ADCIN data hold from ADCCLK rising edge time
ADCCLK falling edge to data valid delay time
ADCCLK falling edge to data invalid delay time
9
-
10
15
14
13
3
ms
ns
ns
ns
ns
tINs
tINh
-
tOvd
tOd
− 7
− 2
ADC
CLK
tCd
nADC
CSS
tINs
tINh
ADCIN
tOvd
tOd
ADC
OUT
Figure 11. SSI1 Interface Timing Measurement
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
23
EP7311
High-Performance, Low-Power System on Chip
SSI2 Interface
Parameter
Symbol
tclk_per
tclk_high
tclk_low
tclkrf
Min
Max
Unit
SSICLK period (slave mode)
185
925
925
3
2050
1025
1025
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SSICLK high time
SSICLK low time
SSICLK rise/fall time
tFRd
SSICLK rising edge to RX and/or TX frame sync high time
SSICLK rising edge to RX and/or TX frame sync low time
SSIRXFR and/or SSITXFR period
SSIRXDA setup to SSICLK falling edge time
SSIRXDA hold from SSICLK falling edge time
SSICLK rising edge to SSITXDA data valid delay time
SSITXDA valid time
-
3
tFRa
-
8
tFR_per
tRXs
960
3
990
7
tRXh
3
7
tTXd
-
2
tTXv
960
990
tclk_per
tclk_high
tclk_low
SSI
CLK
tclkrf
tFR_per
tFRd
tFRa
SSIRXFR/
SSITXFR
tRXh
tRXs
SSI
RXDA
D7
D2
D2
D1
D1
D0
D0
tTXd
SSI
TXDA
D7
tTXv
Figure 12. SSI2 Interface Timing Measurement
24
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
LCD Interface
Parameter
Symbol
tCL1d
tCL2d
tFRMd
tMd
Min
Max
Unit
CL[2] falling to CL[1] rising delay time
CL[1] falling to CL[2] rising delay time
CL[1] falling to FRM transition time
CL[1] falling to M transition time
− 10
80
25
3,475
10,425
20
ns
ns
ns
ns
ns
300
− 10
− 10
tDDd
CL[2] rising to DD (display data) transition time
20
CL[2]
tCL2d
tCL1d
CL[1]
FRM
tFRMd
tMd
M
tDDd
DD [3:0]
Figure 13. LCD Controller Timing Measurement
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
25
EP7311
High-Performance, Low-Power System on Chip
JTAG Interface
Parameter
Symbol
tclk_per
tclk_high
tclk_low
tJPs
Min
Max
Units
TCK clock period
2
1
1
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock high time
TCK clock low time
-
JTAG port setup time
0
tJPh
JTAG port hold time
-
3
tJPco
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
-
10
12
19
tJPzx
-
tJPxz
-
tclk_per
tclk_high
tclk_low
TCK
tJPh
tJPs
TMS
TDI
tJPzx
tJPco
tJPxz
TDO
Figure 14. JTAG Timing Measurement
26
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Packages
208-Pin LQFP Package Characteristics
208-Pin LQFP Package Specifications
29.60 (1.165)
30.40 (1.197)
27.80 (1.094)
28.20 (1.110)
0.17 (0.007)
0.27 (0.011)
27.80 (1.094)
28.20 (1.110)
29.60 (1.165)
30.40 (1.197)
EP7311
208-Pin LQFP
0.50
(0.0197)
BSC
Pin 1 Indicator
Pin 208
Pin 1
1.35 (0.053)
1.45 (0.057)
1.00 (0.039) BSC
0.45 (0.018)
0.75 (0.030)
0.09 (0.004)
0.20 (0.008)
0° MIN
7° MAX
0.05 (0.002)
0.15 (0.006)
1.40 (0.055)
1.60 (0.063)
Figure 15. 208-Pin LQFP Package Outline Drawing
Note: 1) Dimensions are in millimeters (inches), and controlling dimension is millimeter.
2) Drawing above does not reflect exact package pin count.
3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information.
4) For pin locations, please see Figure 16. For pin descriptions see the EP7311 User’s Manual.
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
27
EP7311
High-Performance, Low-Power System on Chip
208-Pin LQFP Pin Diagram
D[25]
A[25]/DRA[2]
D[26]
A[26]/DRA[1]
D[27]
A[27]/DRA[0]
VSSIO
D[28]
D[29]
D[30]
D[31]
BUZ
COL[0]
COL[1]
TCLK
VDDIO
COL[2]
COL[3]
COL[4]
COL[5]
COL[6]
COL[7]
FB[0]
VSSIO
FB[1]
SMPCLK
ADCOUT
ADCCLK
DRIVE[0]
DRIVE[1]
VDDIO
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
157
158
159
160
161
162
163
VDDOSC
MOSCIN
MOSCOUT
VSSOSC
WAKEUP
nPWRFL
A[6]
164
D[6]
165
A[5]
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
D[5]
VDDIO
VSSIO
A[4]
D[4]
A[3]
D[3]
A[2]
VSSIO
D[2]
A[1]
D[1]
A[0]
D[0]
EP7311
VSSCORE
VDDCORE
VSSIO
VDDIO
CL[2]
CL[1]
FRM
208-Pin LQFP
(Top View)
M
VSSIO
DD[3]
DD[2]
VSSIO
DD[1]
DD[0]
VDDCORE
VSSCORE
nADCCS
ADCIN
SSIRXFR
SSIRXDA
SSITXDA
SSITXFR
VSSIO
SSICLK
PD[0]/LEDFLSH
PD[1]
PD[2]
PD[3]
TMS
VDDIO
PD[4]
PD[5]
PD[6]/SDQM[0]
PD[7]/SDQM[1]
nSDCS[1]
nSDCS[0
]
SDQM[3]
SDQM[2]
VDDIO
VSSIO
SDCKE
SDCLK
nMWE/nSDWE
nMOE/nSDCAS
VSSIO
nCS[0]
nCS[1]
nCS[2]
nCS[3]
nCS[4]
Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram
Note: 1. N/C should not be grounded but left as no connects.
2. Pin differences between the EP7211 and the EP7311 are bolded.
28
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
208-Pin LQFP Numeric Pin Listing
Table T. 208-Pin LQFP Numeric Pin Listing (Continued)
Reset
Table T. 208-Pin LQFP Numeric Pin Listing
Pin
Pin
No.
Signal
Type
Strength
Reset
State
State
Signal
Type
Strength
No.
38
39
40
41
42
43
44
45
DSR
nTEST[1]
nTEST[0]
EINT[3]
I
1
nCS[5]
VDDIO
VSSIO
EXPCLK
WORD
WRITE/nSDRAS
RUN/CLKEN
EXPRDY
TXD[2]
RXD[2]
TDI
O
1
Low
I
With p/u*
With p/u*
2
Pad Pwr
I
3
Pad Gnd
I
4
I/O
1
1
1
1
1
1
nEINT[2]
I
I
5
Out
Low
Low
Low
nEINT[1]
6
Out
nEXTFIQ
PE[2]/CLKSEL
I
7
O
I/O
1
1
Input
Input
8
I
PE[1]/
BOOTSEL[1]
46
47
I/O
I/O
9
O
High
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
I
PE[0]/
BOOTSEL[0]
1
Input
I
with p/u*
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
VSSRTC
RTCOUT
RTCIN
RTC Gnd
VSSIO
PB[7]
Pad Gnd
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pad Pwr
O
1
1
1
1
1
1
1
1
Input
Input
Input
Input
Input
Input
Input
Input
I
PB[6]
VDDRTC
N/C
RTC power
PB[5]
PB[4]
PD[7]/SDQM[1]
PD[6]/SDQM[0]
PD[5]
I/O
1
1
1
1
Low
Low
Low
Low
PB[3]
I/O
PB[2]
I/O
PB[1]/PRDY2
PB[0]/PRDY1
VDDIO
TDO
PD[4]
I/O
VDDIO
Pad Pwr
TMS
I
with p/u*
1
1
1
1
1
1
1
1
1
1
1
1
Three state
Input
Input
Input
Input
Input
Input
Input
Input
Low
PD[3]
I/O
1
1
1
1
1
Low
Low
Low
Low
Input
PA[7]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
PD[2]
I/O
PA[6]
PD[1]
I/O
PA[5]
PD[0]/LEDFLSH
SSICLK
VSSIO
I/O
PA[4]
I/O
PA[3]
Pad Gnd
PA[2]
SSITXFR
SSITXDA
SSIRXDA
SSIRXFR
ADCIN
I/O
1
1
Low
Low
PA[1]
O
PA[0]
I
LEDDRV
TXD[1]
VSSIO
PHDIN
CTS
I/O
I
Input
High
O
High
Pad Gnd
I
High
nADCCS
VSSCORE
VDDCORE
VSSIO
O
1
Core Gnd
Core Pwr
Pad Gnd
I
RXD[1]
DCD
I
I
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
29
EP7311
High-Performance, Low-Power System on Chip
Table T. 208-Pin LQFP Numeric Pin Listing (Continued)
Table T. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Reset
State
Pin
No.
Reset
State
Signal
Type
Strength
Signal
Type
Strength
74
75
VDDIO
Pad Pwr
I/O
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
D[23]
A[22]/DRA[5]
D[22]
I/O
1
1
1
1
1
Low
Low
Low
Low
Low
High /
Low
O
DRIVE[1]
2
2
I/O
High /
Low
76
DRIVE[0]
I/O
A[21]/DRA[6]
D[21]
O
I/O
77
78
ADCCLK
ADCOUT
SMPCLK
FB[1]
O
1
1
1
Low
Low
Low
VSSIO
Pad Gnd
O
A[20]/DRA[7]
D[20]
O
1
1
1
1
1
1
Low
Low
Low
Low
Low
Low
79
O
I/O
80
I
A[19]/DRA[8]
D[19]
O
81
VSSIO
Pad Gnd
I/O
82
FB[0]
I
A[18]/DRA[9]
D[18]
O
83
COL[7]
COL[6]
COL[5]
COL[4]
COL[3]
COL[2]
VDDIO
TCLK
O
1
1
1
1
1
1
High
High
High
High
High
High
I/O
84
O
VDDIO
VSSIO
Pad Pwr
85
O
Pad Gnd
86
O
nTRST
A[17]/DRA[10]
D[17]
I
O
87
O
1
1
1
1
1
1
1
1
1
1
1
1
1
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
88
O
I/O
O
89
Pad Pwr
A[16]/DRA[11]
D[16]
90
I
I/O
O
91
COL[1]
COL[0]
BUZ
O
1
1
1
1
1
1
1
High
High
Low
Low
Low
Low
Low
A[15]/DRA[12]
D[15]
92
O
I/O
O
93
O
I/O
A[14]/DRA[13]
D[14]
94
D[31]
I/O
O
95
D[30]
I/O
A[13]/DRA[14]
D[13]
96
D[29]
I/O
I/O
O
97
D[28]
I/O
A[12]
98
VSSIO
Pad Gnd
O
D[12]
I/O
O
99
A[27]/DRA[0]
D[27]
2
1
2
1
2
1
1
1
Low
Low
Low
Low
Low
Low
Low
Low
—
A[11]
100
101
102
103
104
105
106
107
108
109
110
I/O
VDDIO
VSSIO
Pad Pwr
Pad Gnd
I/O
O
A[26]/DRA[1]
D[26]
O
I/O
D[11]
1
1
1
1
1
1
1
1
Low
Low
Low
Low
Low
Low
Low
Low
A[25]/DRA[2]
D[25]
O
A[10]
I/O
D[10]
I/O
O
HALFWORD
A[24]/DRA[3]
VDDIO
VSSIO
O
A[9]
O
D[9]
I/O
O
Pad Pwr
Pad Gnd
I/O
A[8]
—
D[8]
I/O
O
D[24]
1
1
Low
Low
A[7]
A[23]/DRA[4]
O
30
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table T. 208-Pin LQFP Numeric Pin Listing (Continued)
Table T. 208-Pin LQFP Numeric Pin Listing (Continued)
Reset
Pin
No.
Reset
State
Pin
No.
Signal
Type
Strength
Signal
Type
Strength
State
149
150
151
152
153
154
VSSIO
D[7]
Pad Gnd
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
M
DD[3]
O
1
1
1
Low
Low
Low
I/O
1
Low
I/O
nBATCHG
nEXTPWR
BATOK
nPOR
I
I
I
I
DD[2]
I/O
VSSIO
Pad Gnd
DD[1]
I/O
1
1
1
1
2
2
Low
Low
High
High
Low
Low
Schmitt
Schmitt
DD[0]
I/O
nMEDCHG/
nBROM
nSDCS[1]
nSDCS[0]
SDQM[3]
SDQM[2]
VDDIO
O
155
I
O
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
nURESET
VDDOSC
MOSCIN
MOSCOUT
VSSOSC
WAKEUP
nPWRFL
A[6]
I
I/O
Osc Pwr
I/O
Osc
Pad Pwr
Osc
VSSIO
Pad Gnd
Osc Gnd
SDCKE
SDCLK
nMWE/nSDWE
nMOE/nSDCAS
VSSIO
I/O
2
2
1
1
Low
Low
High
High
I
Schmitt
I/O
I
O
O
1
1
1
1
Low
Low
Low
Low
O
D[6]
I/O
Pad Gnd
A[5]
Out
nCS[0]
O
O
O
O
O
1
1
1
1
1
High
High
High
High
High
D[5]
I/O
nCS[1]
VDDIO
VSSIO
A[4]
Pad Pwr
nCS[2]
Pad Gnd
nCS[3]
O
1
1
2
1
2
Low
Low
Low
Low
Low
nCS[4]
D[4]
I/O
A[3]
O
*With p/u’ means with internal pull-up on the pin.
D[3]
I/O
A[2]
O
VSSIO
D[2]
Pad Gnd
I/O
1
2
1
2
1
Low
Low
Low
Low
Low
A[1]
O
D[1]
I/O
O
A[0]
D[0]
I/O
VSS CORE
VDD CORE
VSSIO
VDDIO
CL[2]
Core Gnd
Core Pwr
Pad Gnd
Pad Pwr
O
1
1
1
Low
Low
Low
CL[1]
O
FRM
O
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
31
EP7311
High-Performance, Low-Power System on Chip
204-Ball TFBGA Package Characteristics
204-Ball TFBGA Package Specifications
TOP VIEW
BOTTOM VIEW
0.08 M
Ø
C
Ø0.15 M C A B
Ø0.25~0.35(204X)
A1 CORNER
A1 CORNER
1
2 3 4 5 6 7 8 9 10 1112 13 14 15 16 17 18 19 20
20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
T
M
N
P
R
T
U
V
W
Y
U
V
W
Y
A
0.65
12.35
B
13 0.05
0.15(4X)
C
Substrate Thickness :
0.36
Ball Pitch :
0.65
0.3
Ball Diameter :
Mold Thickness :
SEATING PLANE
C
0.53
Figure 17. 204-Ball TFBGA Package
32
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
204-Ball TFBGA Pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
nMWE/
nSDWE
GNDCOR
E
A
B
C
D
E
F
VDDIO EXPCLK nCS3 nCS1
SDQM2 nSDCS1
SDCKE nSDCS0
DD2
FRM
CL1
D1
A2
D4
A5 nPWRFLMOSCOUT GNDIO
GNDIO
GNDIO A
nMOE/
nSDCAS
WORD VDDIO nCS5 nCS2
RUN/
DD1
DD0
M
CL2
D0
A0
A1
D2
D3
A3
A4
D5
D6 WAKEUP MOSCIN GNDIO
GNDOS
GNDIO nURESET B
VDDCO
RE
EXPRDY VDDIO nCS4 nCS0 SDCLK SDQM3
RXD2 VDDIO
DD3
A6
VDDOSC GNDIO
BATOK
nPOR
A7
C
D
E
F
CLKEN
C
PB7
GNDIO nBATCHG
WRITE/
TXD2
nMEDCHG
nEXTPWR
/nBROM
PB4
PB3
D9
nSDRAS
PB6
PB2
TDO
PA5
PA2
TDI
D7
D8
A8
A9
D10
D11
A12
PB1/
PRDY2
G
H
J
PB5
G
H
J
PB0/
PRDY1
PA7
PA4
PA1
A10
D12
D13
A13/
DRA14
PA6
A11
A14/
DRA13
K
L
VDDIO
D14
VDDIO
D15
K
L
A16/
DRA11
TXD1 LEDDRV PA3
D16
A15/
DRA12
A17/
DRA10
M
N
P
RXD1
CTS
PA0
nTRST
M
N
P
R
A18/
DRA9
DSR nTEST1 PHDIN
D17
D18
D19
A20/
DRA7
EINT3 nEINT2 DCD
PE2/
D20
A19/
DRA8
A21/
DRA6
R nEXTFIQ
nTEST0
D22
D23
CLKSEL
PE1/
PE0/
A22/
DRA5
T
BOOT BOOT nEINT1
SEL1 SEL0
D21
T
HALF
WORD
A23/
DRA4
U GNDRTCRTCOUT RTCIN
V VDDRTC GNDIO GNDIO
D24
U
V
PD7/
SDQM1
A26/
DRA1
A24/
DRA3
PD4
TMS
PD2
SSICLK SSIRXDAnADCCS VDDIO ADCCLK COL7 COL4 TCLK BUZ
GNDCO
D29
D30
VDDIO
D26
VDDIO
VDDIO
PD6/SD
QM0
A27/
DRA0
W
Y
GNDIO GNDIO GNDIO
PD1 SSITXFR SSIRXFR
DRIVE1 ADCOUT FB0 COL5 COL2 COL0
D25
W
RE
PD0/
VDDCO
RE
A25/
DRA2
GNDIO GNDIO GNDIO PD5
PD3
LED SSITXDA ADCIN
FLSH
DRIVE0 SMPLCK FB1 COL6 COL3 COL1
D31
D28
D27
VDDIO
Y
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
33
EP7311
High-Performance, Low-Power System on Chip
204-Ball TFBGA Ball Listing
The list is ordered by ball location.
Table 21. 204-Ball TFBGA Ball Listing
Reset
State
†
Ball Location
Name
Type
Description
Strength
Digital I/O power,
3.3 V
A1
VDDIO
Pad power
I
Expansion clock
input
A2
EXPCLK
1
A3
A4
nCS[3]
nCS[1]
1
1
High
High
O
O
Chip select 3
Chip select 1
ROM, expansion
write enable/
SDRAM write enable
control signal
A5
nMWE/nSDWE
1
High
O
SDRAM byte lane
mask
A6
A7
A8
SDQM[2]
nSDCS[1]
DD[2]
2
1
1
Low
High
Low
O
O
O
SDRAM chip select
2
LCD serial display
data
LCD frame
synchronization
pulse
A9
FRM
1
1
Low
Low
O
A10
A11
A12
A13
A14
A15
CL[1]
VSSCORE
D[1]
O
LCD line clock
Core ground
Core ground
1
2
1
1
Low
Low
Low
Low
I/O
O
Data I/O
A[2]
System byte address
Data I/O
D[4]
I/O
O
A[5]
System byte address
Power fail sense
input
A16
nPWRFL
I
A17
A18
A19
A20
MOSCOUT
VSSIO
O
Main oscillator out
I/O ground
Pad ground
Pad ground
Pad ground
VSSIO
I/O ground
VSSIO
I/O ground
Word access select
output
B1
B2
WORD
VDDIO
1
Low
O
Digital I/O power, 3.3
V
Pad power
B3
B4
nCS[5]
nCS[2]
1
1
Low
O
O
Chip select 5
Chip select 2
High
ROM, expansion OP
enable/SDRAM CAS
control signal
B5
nMOE/nSDCAS
1
High
O
SDRAM clock
enable output
B6
B7
SDCKE
2
1
Low
O
O
SDRAM chip select
0
nSDCS[0]
High
34
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
LCD serial display
data
B8
DD[1]
1
Low
O
B9
M
1
1
1
2
2
1
1
Low
Low
Low
Low
Low
Low
Low
O
0
LCD AC bias drive
LCD pixel clock out
Data I/O
B10
B11
B12
B13
B14
B15
CL[2]
D[0]
A[1]
D[3]
A[4]
D[6]
I/O
O
System byte address
Data I/O
I/O
O
System byte address
Data I/O
I/O
System wake up
input
B16
WAKEUP
Schmitt
I
B17
B18
B19
B20
MOSCIN
VSSIO
I
Main oscillator input
I/O ground
Pad ground
Pad ground
I
VSSIO
I/O ground
nURESET
Schmitt
1
User reset input
Run output / clock
enable output
C1
C2
C3
RUN/CLKEN
EXPRDY
VDDIO
Low
0
Expansion port
ready input
1
I
Digital I/O power,
3.3 V
Pad power
C4
C5
C6
nCS[4]
nCS[0]
SDCLK
1
1
2
High
High
Low
O
O
O
Chip select 4
Chip select 0
SDRAM clock out
SDRAM byte lane
mask
C7
SDQM[3]
DD[0]
2
1
1
Low
Low
Low
O
LCD serial display
data
C8
O
O
LCD serial display
data
C9
DD[3]
Digital core power,
2.5 V
C10
VDDCORE
Core power
C11
C12
C13
C14
C15
C16
A[0]
2
1
2
1
1
Low
Low
Low
Low
Low
O
System byte address
Data I/O
D[2]
I/O
A[3]
O
System byte address
Data I/O
D[5]
I/O
O
A[6]
System byte address
PLL ground
VSSOSC
Oscillator ground
Oscillator power in,
2.5V
C17
VDDOSC
Oscillator power
C18
C19
VSSIO
BATOK
Pad ground
I
I/O ground
Battery ok input
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
35
EP7311
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
C20
nPOR
PB[7]
Schmitt
1
I
I
Power-on reset input
GPIO port B
‡
D1
D2
Input
UART 2 receive data
input
RXD[2]
I
Digital I/O power,
3.3V
D3
VDDIO
VSSIO
Pad power
D18
D19
D20
E1
Pad ground
I/O ground
Battery changed
sense input
nBATCHG
A[7]
I
O
I
1
1
Low
System byte address
GPIO port B
‡
PB[4]
Input
UART 2 transmit
data output
E2
E3
TXD[2]
1
1
High
Low
O
O
Transfer direction /
SDRAM RAS signal
output
WRITE/nSDRAS
Media change
interrupt input /
internal ROM boot
enable
E18
E19
nMEDCHG/nBROM
nEXTPWR
I
I
External power
supply sense input
E20
F1
D[9]
1
1
Low
I/O
I/O
Data I/O
‡
PB[3]
GPIO port B
GPIO port B
Input
‡
F2
PB[6]
1
I/O
Input
F3
TDI
with p/u*
I
JTAG data input
Data I/O
F18
F19
F20
D[7]
A[8]
D[10]
1
1
1
Low
Low
Low
I/O
O
System byte address
Data I/O
I/O
‡
G1
PB[1]
PB[2]
PB[5]
D[8]
1
1
1
1
I/O
I/O
I/O
I/O
Input
‡
G2
GPIO port B
GPIO port B
Data I/O
Input
‡
G3
Input
‡
G18
Input
G19
G20
A[9]
1
1
Low
Low
O
System byte address
Data I/O
D[11]
I/O
‡
H1
PA[7]
TDO
1
1
I/O
O
GPIO port A
Input
‡
H[2]
JTAG data out
Input
‡
H[3]
PB[0]
A[10]
1
1
I/O
O
GPIO port B
Input
H[18]
Low
System byte address
36
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
H19
D[12]
A[12]
1
1
Low
Low
I/O
O
Data I/O
H20
J1
System byte address
‡
PA[4]
PA[5]
PA[6]
1
1
1
I/O
I/O
I/O
GPIO port A
GPIO port A
GPIO port A
Input
Input
Input
‡
‡
J2
J3
J18
J19
A[11]
D[13]
1
1
Low
Low
O
System byte address
Data I/O
I/O
Systembyte address
/ SDRAM address
J20
K1
A[13]/DRA[14]
PA[1]
1
1
1
Low
O
I/O
I/O
‡
GPIO port A
GPIO port A
Input
Input
‡
K2
PA[2]
Digital I/O power,
3.3V
K3
VDDIO
Pad power
K18
K19
K20
D[14]
1
1
1
Low
Low
Low
High
Low
I/O
O
Data I/O
Systembyte address
/ SDRAM address
A[14]/DRA[13]
D[15]
I/O
Data I/O
UART 1 transmit
data out
L1
L2
L3
TXD[1]
LEDDRV
PA[3]
1
1
1
O
O
IR LED drive
GPIO port A
‡
I/O
Input
Digital I/O power,
3.3V
L18
L19
L20
VDDIO
Pad power
D[16]
1
1
Low
Low
I/O
O
Data I/O
Systembyte address
/ SDRAM address
A[16]/DRA[11]
UART 1 receive data
input
M1
RXD[1]
I
UART 1 clear to
send input
M2
CTS
I
‡
M3
PA[0]
1
1
I/O
O
GPIO port A
Input
Systembyte address
/ SDRAM address
M18
A[15]/DRA[12]
Low
Systembyte address
/ SDRAM address
M19
M20
N1
A[17]/DRA[10]
nTRST
1
Low
O
I
JTAG async reset
input
UART 1 data set
ready input
DSR
I
Test mode select
input
N2
N3
nTEST[1]
PHDIN
With p/u*
I
I
Photodiode input
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
37
EP7311
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
N18
D[17]
D[19]
1
1
Low
Low
I/O
I/O
Data I/O
N19
N20
P1
Data I/O
Systembyte address
/ SDRAM address
A[18]/DRA[9]
EINT[3]
1
Low
O
I
External interrupt
External interrupt
input
P2
nEINT[2]
I
UART 1 data carrier
detect
P3
DCD
I
P18
P19
P20
R1
D[18]
1
1
1
Low
Low
Low
I/O
O
Data I/O
Systembyte address
/ SDRAM address
A[20]/DRA[7]
D[20]
I/O
I
Data I/O
External fast
interrupt input
nEXTFIQ
GPIO port E / clock
input mode select
‡
R2
R3
PE[2]/CLKSEL
nTEST[0]
1
I/O
I
Input
Test mode select
input
With p/u*
Systembyte address
/ SDRAM address
R18
R19
R20
A[19]/DRA[8]
D[22]
1
1
1
Low
Low
Low
O
I/O
O
Data I/O
Systembyte address
/ SDRAM address
A[21]/DRA[6]
GPIO port E / boot
mode select
‡
T1
T2
T3
PE[1]/BOOTSEL[1]
PE[0]/BOOTSEL[0]
nEINT[1]
1
1
I/O
I/O
I
Input
GPIO port E / boot
mode select
‡
Input
External interrupt
input
T18
T19
D[21]
D[23]
1
1
Low
Low
I/O
I/O
Data I/O
Data I/O
Systembyte address
/ SDRAM address
T20
U1
U2
U3
A[22]/DRA[5]
VSSRTC
RTCOUT
RTCIN
1
Low
O
Real time clock
ground
RTC ground
Real time clock
oscillator output
O
Real time clock
oscillator input
I/O
Halfword access
select output
U18
U19
U20
HALFWORD
D[24]
1
1
1
Low
Low
Low
O
I/O
O
Data I/O
Systembyte address
/ SDRAM address
A[23]/DRA[4]
Real time clock
power, 2.5V
V1
VDDRTC
RTC power
38
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
V2
VSSIO
VSSIO
Pad ground
Pad ground
I/O ground
I/O ground
V3
V4
GPIO port D /
SDRAM byte lane
mask
PD[7]/SDQM[1]
1
Low
I/O
V5
V6
PD[4]
PD[2]
1
1
Low
Low
I/O
I/O
GPIO port D
GPIO port D
DAI/CODEC/SSI2
serial clock
‡
V7
SSICLK
SSIRXDA
nADCCS
VDDIO
1
I/O
Input
DAI/CODEC/SSI2
serial data input
V8
I/O
SSI1 ADC chip
select
V9
1
High
O
Digital I/O power,
3.3V
V10
V11
V12
V13
Pad power
SSI1 ADC serial
clock
ADCCLK
COL[7]
1
1
1
Low
High
High
O
O
O
Keyboard scanner
column drive
Keyboard scanner
column drive
COL[4]
V14
V15
V16
TCLK
BUZ
I
JTAG clock
1
1
Low
Low
O
Buzzer drive output
Data I/O
D[29]
I/O
Systembyte address
/ SDRAM address
V17
V18
V19
V20
A[26]/DRA[1]
VDDIO
2
Low
O
Digital I/O power,
3.3 V
Pad power
Pad power
O
Digital I/O power,
3.3 V
VDDIO
Systembyte address
/ SDRAM address
A[24]/DRA[3]
‘
Low
W1
W2
W3
VSSIO
VSSIO
VSSIO
Pad ground
Pad ground
Pad ground
I/O ground
I/O ground
I/O ground
GPIO port D /
SDRAM byte lane
mask
W4
PD[6]/SDQM[0]
1
Low
I/O
W5
W6
TMS
with p/u*
1
I
JTAG mode select
GPIO port D
PD[1]
Low
Low
I/O
DAI/CODEC/SSI2
frame sync
W7
SSITXFR
1
1
I/O
DAI/CODEC/SSI2
frame sync
‡
W8
SSIRXFR
VSSCORE
DRIVE[1]
I/O
Core Ground
I/O
Input
W9
Core Ground
High /
Low
W10
2
PWM drive output
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
39
EP7311
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
SSI1 ADC serial
data output
W11
ADCOUT
1
Low
O
I
W12
W13
FB[0]
PWM feedback input
Keyboard scanner
column drive
COL[5]
1
1
High
High
O
Keyboard scanner
column drive
W14
COL[2]
O
Keyboard scanner
column drive
W15
W16
W17
W18
W19
COL[0]
D[30]
1
1
2
1
High
Low
Low
Low
O
I/O
O
Data I/O
Systembyte address
/ SDRAM address
A[27]/DRA[0]
D[26]
I/O
Data I/O
Digital I/O power,
3.3V
VDDIO
Pad power
W20
Y1
D[25]
1
Low
I/O
Pad ground
Pad ground
Pad ground
I/O
Data I/O
VSSIO
VSSIO
VSSIO
PD[5]
PD[3]
I/O ground
I/O ground
I/O ground
GPIO port D
GPIO port D
Y2
Y3
Y4
1
1
Low
Low
Y5
I/O
GPIO port D / LED
blinker output
Y6
Y7
Y8
PD[0]/LEDFLSH
SSITXDA
1
1
Low
Low
I/O
O
I
DAI/CODEC/SSI2
serial data output
SSI1 ADC serial
input
ADCIN
Digital core power,
2.5V
Y9
VDDCORE
DRIVE[0]
Core power
I/O
‡
Y10
2
1
PWM drive output
Input
SSI1 ADC sample
clock
Y11
Y12
Y13
SMPCLK
FB[1]
Low
O
I
PWM feedback input
Keyboard scanner
column drive
COL[6]
1
1
1
High
High
High
O
Keyboard scanner
column drive
Y14
Y15
COL[3]
COL[1]
O
O
Keyboard scanner
column drive
Y16
Y17
Y18
D[31]
D[28]
D[27]
1
1
1
Low
Low
Low
I/O
I/O
I/O
Data I/O
Data I/O
Data I/O
Systembyte address
/ SDRAM address
Y19
A[25]/DRA[2]
2
Low
O
40
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
Digital I/O power,
3.3V
Y20
VDDIO
Pad power
*
“With p/u” means with internal pull-up of 100 KOhms on the pin.
† Strength 1 = 4 ma
Strength 2 = 12 ma
‡
Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
256-Ball PBGA Package Characteristics
256-Ball PBGA Package Specifications
Figure 18. 256-Ball PBGA Package
Note: 1) For pin locations see Table V.
2) Dimensions are in millimeters (inches), and controlling dimension is millimeter
3) Before beginning any new EP7311 design, contact Cirrus Logic for the latest package information.
256-Ball PBGA Pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
F
VDDIO
nCS[4]
nCS[1]
SDCLK
SDQM[3]
DD[1]
M
VDDIO
D[0]
D[2]
A[3]
VDDIO
A[6]
MOSCOUT VDDOSC VSSIO
WAKEUP VDDIO nURESET
A
B
nMOE/
nSDCAS
nCS[5]
VDDIO
VDDIO
EXPCLK
EXPRDY
PB[7]
nCS[3]
VSSIO
VSSIO
TDI
VDDIO nSDCS[1]
DD[2]
VSSIO
CL[1]
VDDIO
CL[2]
FRM
VDDCORE
VSSIO
VSSRTC
A[0]
D[1]
VSSIO
D[4]
A[2]
A[4]
A[5]
VDDIO
VDDIO
WORD
TXD[2]
PB[4]
VSSIO
nCS[2]
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
nTRST
VSSIO
VSSIO
VDDIO
nPOR nEXTPWR C
WRITE/
nSDRAS
nMWE/
nSDWE
nSDCS[0]
SDQM[2]
SDCKE
nPWRFL MOSCIN
D[7]
D[9]
D[8]
D[10]
D
E
F
nMEDCHG/
nBROM
RXD[2]
PB[5]
nCS[0]
VSSIO
D[5]
VSSOSC
VSSRTC
A[7]
VSSIO
BATOK
A[8]
RUN/
CLKEN
PB[3]
VSSIO
TDO
DD[3]
DD[0]
A[1]
D[6]
nBATCHG
A[9]
D[11]
D[12]
D[14]
D[16]
VDDIO
VDDIO
D[13]
G
H
J
PB[1]
VDDIO
PA[5]
PB[6]
PA[6]
PA[0]
VSSRTC VSSRTC
D[3]
VSSRTC
G
H
J
A[13]/
DRA[14]
PA[7]
VSSIO
VSSIO
VSSIO
VDDIO
VDDIO
VSSIO
VSSIO
PA[4]
PB[0]
PB[2]
CTS
VSSRTC VSSRTC
VSSRTC VSSRTC
A[10]
A[11]
A[12]
D[15]
A[17]/
A[16]/
A[15]/
A[14]/
DRA[13]
PA[3]
PA[1]
PA[2]
TXD[1]
D[17]
DRA[10] DRA[11] DRA[12]
K
L
LEDDRV
RXD[1]
PHDIN
DSR
DCD
nTEST[1] EINT[3]
VSSRTC
ADCIN
COL[4]
COL[6]
FB[0]
TCLK
D[31]
D[20]
VSSRTC
D[27]
D[19]
D[18]
VDDIO
K
L
PE[2]/
PD[0]/
LEDFLSH
A[22]/
DRA[5]
A[21]/
DRA[6]
A[18]/
A[19]/
nEINT[1]
VSSRTC
CLKSEL
VSSRTC
DRA[9]
DRA[8]
PE[0]/
BOOTSEL[0]
A[23]/
DRA[4]
A[20]/
DRA[7]
M
N
P
R
T
nTEST[0] nEINT[2]
TMS
PD[5]
VDDIO
PD[2]
SSITXFR DRIVE[1]
COL[0]
COL[2]
VDDIO
COL[3]
COL[5]
VSSIO
D[21]
D[23]
M
N
P
R
T
PE[1]/
nEXTFIQ
VDDIO
VSSIO
PD[1]
SSIRXDA ADCCLK SMPCLK
D[29]
D[26] HALFWORD VSSIO
D[22]
D[24]
BOOTSEL[1]
VSSRTC RTCOUT
VDDIO
VSSIO
VSSIO
VDDIO
VDDIO
VSSIO
COL[7]
FB[1]
VSSIO
COL[1]
VDDIO
VSSIO
D[30]
BUZ
VDDIO
VSSIO
VDDIO
A[27]/
DRA[0]
A[25]/
DRA[2]
A[24]\
DRA[3]
RTCIN
VDDIO
PD[7]/
PD[4]
PD[6]/
SSITXDA nADCCS
ADCOUT
VDDIO
D[25]
A[26]/
DRA[1]
VDDRTC
PD[3]
SSICLK SSIRXFR VDDCORE DRIVE[0]
D[28]
VSSIO
SDQM[1] SDQM[0]
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
41
EP7311
High-Performance, Low-Power System on Chip
0.85 (0.034)
0.05 (.002)
17.00 (0.669)
0.20 (.008)
0.40 (0.016)
0.05 (.002)
Pin 1 Corner
15.00 (0.590)
0.20 (.008)
D1
30° TYP
Pin 1 Indicator
17.00 (0.669)
0.20 (.008)
E1
15.00 (0.590)
0.20 (.008)
2 Layer
0.36 (0.014)
0.09 (0.004)
TOP VIEW
SIDE VIEW
D
17.00 (0.669)
Pin 1 Corner
1.00 (0.040)
E
1.00 (0.040)
REF
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
1.00 (0.040)
REF
A
B
C
D
E
F
G
H
J
1.00 (0.040)
17.00 (0.669)
K
L
M
N
P
R
T
0.50
R
BOTTOM VIEW
3 Places
JEDEC #: MO-151
Ball Diameter: 0.50 mm 0.10 mm
17 ¥ 17 ¥ 1.61 mm body
42
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
256-Ball PBGA Ball Listing
The list is ordered by ball location.
Table V. 256-Ball PBGA Ball Listing (Continued)
Table V. 256-Ball PBGA Ball Listing
Ball Location
Name
Type
Description
Ball Location
Name
VDDIO
Type
Description
C12
C13
C14
C15
C16
VDDIO
VSSIO
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
A1
A2
Pad power Digital I/O power, 3.3V
nCS[4]
nCS[1]
SDCLK
SDQM[3]
DD[1]
O
O
O
O
O
O
Chip select out
VSSIO
Pad ground I/O ground
A3
Chip select out
nPOR
I
I
Power-on reset input
A4
SDRAM clock out
nEXTPWR
External power supply sense input
A5
SDRAM byte lane mask
LCD serial display data
LCD AC bias drive
Transfer direction / SDRAM RAS signal
output
D1
WRITE/nSDRAS
O
I
A6
A7
M
D2
D3
D4
D5
EXPRDY
VSSIO
VDDIO
nCS[2]
Expansion port ready input
A8
VDDIO
D[0]
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
A9
I/O
I/O
O
Data I/O
Pad power Digital I/O power, 3.3V
A10
A11
A12
A13
A14
D[2]
Data I/O
O
O
Chip select out
A[3]
System byte address
ROM, expansion write enable/ SDRAM
write enable control signal
D6
nMWE/nSDWE
VDDIO
A[6]
Pad power Digital I/O power, 3.3V
D7
D8
nSDCS[0]
CL[2]
O
O
SDRAM chip select out
LCD pixel clock out
O
O
System byte address
Main oscillator out
MOSCOUT
D9
VSSRTC
D[4]
Core ground Real time clock ground
Oscillator
power
A15
VDDOSC
Oscillator power in, 2.5V
D10
D11
D12
D13
D14
D15
D16
E1
I/O
Data I/O
A16
B1
VSSIO
nCS[5]
VDDIO
nCS[3]
Pad ground I/O ground
nPWRFL
MOSCIN
VDDIO
VSSIO
D[7]
I
I
Power fail sense input
Main oscillator input
O
Chip select out
B2
Pad power I/O ground
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
B3
O
O
Chip select out
ROM, expansion OP enable/SDRAM
CAS control signal
I/O
Data I/O
B4
nMOE/nSDCAS
D[8]
I/O
Data I/O
B5
B6
VDDIO
nSDCS[1]
DD[2]
Pad power Digital I/O power, 3.3V
RXD[2]
PB[7]
I
I
UART 2 receive data input
GPIO port B
O
O
O
SDRAM chip select out
LCD serial display data
LCD line clock
E2
B7
E3
TDI
I
JTAG data input
Word access select output
B8
CL[1]
E4
WORD
VSSIO
nCS[0]
SDQM[2]
FRM
O
B9
VDDCORE
D[1]
Core power Digital core power, 2.5V
E5
Pad ground I/O ground
B10
B11
B12
B13
B14
B15
B16
C1
I/O
O
O
O
I
Data I/O
E6
O
O
Chip select out
A[2]
System byte address
System byte address
System byte address
System wake up input
E7
SDRAM byte lane mask
LCD frame synchronization pulse
System byte address
Data I/O
A[4]
E8
O
A[5]
E9
A[0]
O
WAKEUP
VDDIO
nURESET
VDDIO
EXPCLK
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
E10
D[5]
I/O
Pad power Digital I/O power, 3.3V
User reset input
Pad power Digital I/O power, 3.3V
Expansion clock input
Oscillator
ground
E11
E12
E13
VSSOSC
VSSIO
PLL ground
I
Pad ground I/O ground
C2
I
Media change interrupt input / internal
ROM boot enable
nMEDCHG/nBROM
I
C3
Pad ground I/O ground
E14
E15
E16
F1
VDDIO
D[9]
Pad power Digital I/O power, 3.3V
C4
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
I/O
Data I/O
C5
D[10]
I/O
Data I/O
C6
Pad ground I/O ground
PB[5]
I
I
GPIO port B
GPIO port B
C7
Pad ground I/O ground
F2
PB[3]
C8
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
F3
VSSIO
TXD[2]
RUN/CLKEN
VSSIO
Pad ground I/O ground
C9
F4
O
O
UART 2 transmit data output
Run output / clock enable output
C10
C11
Pad ground I/O ground
F5
Pad ground I/O ground
F6
Pad ground I/O ground
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
43
EP7311
High-Performance, Low-Power System on Chip
Table V. 256-Ball PBGA Ball Listing (Continued)
Table V. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Type
Description
Ball Location
Name
Type
Description
F7
F8
SDCKE
DD[3]
O
O
SDRAM clock enable output
LCD serial display data
System byte address
Data I/O
J7
J8
CTS
VSSRTC
VSSRTC
A[17]/DRA[10]
A[16]/DRA[11]
A[15]/DRA[12]
A[14]/DRA[13]
nTRST
I
UART 1 clear to send input
RTC ground Real time clock ground
RTC ground Real time clock ground
F9
A[1]
O
J9
F10
F11
F12
F13
F14
F15
F16
G1
D[6]
I/O
J10
J11
J12
J13
J14
J15
J16
K1
O
O
O
O
I
System byte address / SDRAM address
VSSRTC
BATOK
nBATCHG
VSSIO
D[11]
RTC ground Real time clock ground
System byte address / SDRAM address
System byte address / SDRAM address
System byte address / SDRAM address
JTAG async reset input
Data I/O
I
I
Battery ok input
Battery changed sense input
Pad ground I/O ground
I/O Data I/O
Pad power Digital I/O power, 3.3V
GPIO port B
Pad power Digital I/O power, 3.3V
D[16]
I/O
I/O
O
I
VDDIO
PB[1]
D[17]
Data I/O
I
LEDDRV
PHDIN
IR LED drivet
G2
VDDIO
TDO
K2
Photodiode input
G3
O
I
JTAG data out
GPIO port B
GPIO port B
K3
VSSIO
Pad ground I/O ground
G4
PB[4]
K4
DCD
I
I
I
UART 1 data carrier detect
G5
PB[6]
I
K5
nTEST[1]
EINT[3]
Test mode select input
External interrupt
G6
VSSRTC
VSSRTC
DD[0]
Core ground Real time clock ground
RTC ground Real time clock ground
K6
G7
K7
VSSRTC
ADCIN
RTC ground Real time clock ground
G8
O
LCD serial display data
Data I/O
K8
I
SSI1 ADC serial input
Keyboard scanner column drive
JTAG clock
G9
D[3]
I/O
K9
COL[4]
O
G10
G11
G12
G13
G14
G15
G16
H1
VSSRTC
A[7]
RTC ground Real time clock ground
K10
K11
K12
K13
K14
K15
K16
L1
TCLK
I
O
O
O
System byte address
System byte address
System byte address
D[20]
I/O
I/O
I/O
Data I/O
A[8]
D[19]
Data I/O
A[9]
D[18]
Data I/O
VSSIO
D[12]
Pad ground I/O ground
VSSIO
Pad ground I/O ground
I/O
Data I/O
VDDIO
Pad power Digital I/O power, 3.3V
Pad power Digital I/O power, 3.3V
D[13]
I/O
Data I/O
VDDIO
PA[7]
I
I
GPIO port A
GPIO port A
RXD[1]
I
I
UART 1 receive data input
UART 1 data set ready input
H2
PA[5]
L2
DSR
H3
VSSIO
PA[4]
Pad ground I/O ground
L3
VDDIO
Pad power Digital I/O power, 3.3V
H4
I
I
I
I
GPIO port A
GPIO port A
GPIO port B
GPIO port B
L4
nEINT[1]
PE[2]/CLKSEL
VSSRTC
PD[0]/LEDFLSH
VSSRTC
COL[6]
I
I
External interrupt input
H5
PA[6]
L5
GPIO port E / clock input mode select
H6
PB[0]
L6
RTC ground Real time clock ground
H7
PB[2]
L7
I/O
GPIO port D / LED blinker output
H8
VSSRTC
VSSRTC
A[10]
RTC ground Real time clock ground
RTC ground Real time clock ground
L8
Core ground Real time clock ground
H9
L9
O
Keyboard scanner column drive
Data I/O
H10
H11
H12
H13
H14
H15
H16
J1
O
O
O
O
System byte address
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
M4
M5
M6
D[31]
I/O
A[11]
System byte address
VSSRTC
A[22]/DRA[5]
A[21]/DRA[6]
VSSIO
RTC ground Real time clock ground
A[12]
System byte address
O
O
System byte address / SDRAM address
System byte address / SDRAM address
A[13]/DRA[14]
VSSIO
D[14]
System byte address / SDRAM address
Pad ground I/O ground
Pad ground I/O ground
I/O
Data I/O
A[18]/DRA[9]
A[19]/DRA[8]
nTEST[0]
nEINT[2]
VDDIO
O
O
I
System byte address / SDRAM address
D[15]
I/O
Data I/O
System byte address / SDRAM address
Test mode select input
PA[3]
I
I
GPIO port A
GPIO port A
J2
PA[1]
I
External interrupt input
J3
VSSIO
PA[2]
Pad ground I/O ground
Pad power Digital I/O power, 3.3V
GPIO port E / Boot mode select
JTAG mode select
Pad power Digital I/O power, 3.3V
J4
I
I
GPIO port A
PE[0]/BOOTSEL[0]
TMS
I
J5
PA[0]
GPIO port A
I
J6
TXD[1]
O
UART 1 transmit data out
VDDIO
44
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table V. 256-Ball PBGA Ball Listing (Continued)
Table V. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Type
Description
Ball Location
Name
Type
Description
M7
M8
SSITXFR
DRIVE[1]
FB[0]
I/O
I/O
I
MCP/CODEC/SSI2 frame sync
PWM drive output
R7
R8
VDDIO
ADCOUT
COL[7]
Pad power Digital I/O power, 3.3V
O
O
SSI1 ADC serial data output
Keyboard scanner column drive
Keyboard scanner column drive
Keyboard scanner column drive
Data I/O
M9
PWM feedback input
Keyboard scanner column drive
Data I/O
R9
M10
M11
M12
M13
M14
M15
M16
N1
COL[0]
D[27]
O
R10
R11
R12
R13
R14
R15
R16
T1
COL[3]
O
I/O
COL[1]
O
VSSIO
Pad ground I/O ground
D[30]
I/O
O
A[23]/DRA[4]
VDDIO
A[20]/DRA[7]
D[21]
O
System byte address / SDRAM address
A[27]/DRA[0]
A[25]/DRA[2]
VDDIO
System byte address / SDRAM address
System byte address / SDRAM address
Pad power Digital I/O power, 3.3V
O
O
I/O
I
System byte address / SDRAM address
Pad power Digital I/O power, 3.3V
Data I/O
A[24]/DRA[3]
VDDRTC
PD[7]/SDQM[1]
PD[6]/SDQM[0]
PD[3]
O
System byte address / SDRAM address
nEXTFIQ
PE[1]/BOOTSEL[1]
VSSIO
External fast interrupt input
GPIO port E / boot mode select
RTC power Real time clock power, 2.5V
N2
I
T2
I/O
I/O
I/O
I/O
–
GPIO port D / SDRAM byte lane mask
N3
Pad ground I/O ground
T3
GPIO port D / SDRAM byte lane mask
GPIO port D
N4
VDDIO
PD[5]
Pad power Digital I/O power, 3.3V
T4
N5
I/O
I/O
I/O
O
GPIO port D
T5
SSICLK
MCP/CODEC/SSI2 serial clock
MCP/CODEC/SSI2 frame sync
N6
PD[2]
GPIO port D
T6
SSIRXFR
VDDCORE
DRIVE[0]
FB[1]
N7
SSIRXDA
ADCCLK
SMPCLK
COL[2]
D[29]
MCP/CODEC/SSI2 serial data input
SSI1 ADC serial clock
SSI1 ADC sample clock
Keyboard scanner column drive
Data I/O
T7
Core power Core power, 2.5V
N8
T8
I/O
I
PWM drive output
N9
O
T9
PWM feedback input
N10
N11
N12
N13
N14
N15
N16
P1
O
T10
T11
T12
T13
T14
T15
T16
COL[5]
O
Keyboard scanner column drive
I/O
I/O
O
VDDIO
Pad power Digital I/O power, 3.3V
D[26]
Data I/O
BUZ
O
I/O
O
Buzzer drive output
HALFWORD
VSSIO
Halfword access select output
D[28]
Data I/O
Pad ground I/O ground
A[26]/DRA[1]
D[25]
System byte address / SDRAM address
Data I/O
D[22]
I/O
I/O
Data I/O
Data I/O
I/O
D[23]
VSSIO
Pad ground I/O ground
VSSRTC
RTCOUT
VSSIO
RTC ground Real time clock ground
P2
O
Real time clock oscillator output
P3
Pad ground I/O ground
Pad ground I/O ground
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
Pad ground I/O ground
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
Pad ground I/O ground
Pad power Digital I/O power
Pad ground I/O ground
P4
VSSIO
P5
VDDIO
VSSIO
P6
P7
VSSIO
P8
VDDIO
VSSIO
P9
P10
P11
P12
P13
P14
P15
P16
R1
VDDIO
VSSIO
VSSIO
VDDIO
VSSIO
D[24]
I/O
Data I/O
VDDIO
RTCIN
Pad power Digital I/O power, 3.3V
I/O
Real time clock oscillator input
R2
VDDIO
PD[4]
Pad power Digital I/O power, 3.3V
R3
I/O
I/O
O
GPIO port D
R4
PD[1]
GPIO port D
R5
SSITXDA
nADCCS
MCP/CODEC/SSI2 serial data output
SSI1 ADC chip select
R6
O
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
45
EP7311
High-Performance, Low-Power System on Chip
JTAG Boundary Scan Signal Ordering
Table W. JTAG Boundary Scan Signal Ordering
LQFP
Pin No.
TFBGA PBGA
Signal
Type
Position
Ball
Ball
1
B3
A2
B1
E3
C1
C2
E2
D2
F3
D1
F2
G3
E1
F1
G2
G1
H3
H1
J3
B1
C2
E4
D1
F5
D2
F4
E1
E2
G5
F1
G4
F2
H7
G1
H6
H1
H5
H2
H4
J1
nCS[5]
EXPCLK
WORD
WRITE/nSDRAS
RUN/CLKEN
EXPRDY
TXD2
O
I/O
O
1
4
3
5
6
6
O
8
7
O
10
13
14
16
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
65
67
69
70
71
72
73
74
75
76
77
78
8
I
9
O
10
13
14
15
16
17
18
19
20
23
24
25
26
27
28
29
30
31
32
34
35
36
37
38
39
40
41
42
43
RXD2
I
PB[7]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
PB[6]
PB[5]
PB[4]
PB[3]
PB[2]
PB[1]/PRDY2
PB[0]/PRDY1
PA[7]
PA[6]
PA[5]
J2
PA[4]
J1
PA[3]
L3
K2
K1
M3
L2
L1
N3
M2
M1
P3
N1
N2
R3
P1
P2
J4
PA[2]
J2
PA[1]
J5
PA[0]
K1
J6
LEDDRV
TXD1
O
K2
J7
PHDIN
CTS
I
I
L1
K4
L2
K5
M1
K6
M2
L4
RXD1
I
DCD
I
DSR
I
nTEST1
nTEST0
EINT3
I
I
I
nEINT2
nEINT1
I
I
46
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table W. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA PBGA
Signal
Type
Position
Ball
Ball
44
45
46
47
53
54
55
56
59
60
61
62
68
69
70
75
76
77
78
79
80
82
83
84
85
86
87
88
91
92
93
94
95
96
97
99
100
101
T3
R1
N1
L5
nEXTFIQ
PE[2]/CLKSEL
PE[1]/BOOTSEL1
PE[0]/BOOTSEL0
PD[7]/SDQM[1]
PD[6/SDQM[0]]
PD[5]
I
79
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
80
R2
N2
83
T1
M4
T2
86
T2
89
V4
T3
92
W4
Y4
N5
95
R3
PD[4]
98
V5
T4
PD[3]
101
104
107
110
122
125
126
128
131
134
136
138
140
141
142
144
146
148
150
152
154
156
158
160
163
166
169
172
174
177
W5
Y5
N6
PD[2]
R4
PD[1]
V6
L7
PD[0]/LEDFLSH
SSIRXFR
ADCIN
W6
Y6
T6
I/O
I
K8
W8
Y8
R6
nADCCS
DRIVE1
DRIVE0
ADCCLK
ADCOUT
SMPCLK
FB1
O
M8
T8
I/O
I/O
O
V9
W10
Y10
V11
W11
Y11
Y12
W12
V12
Y13
W13
V13
Y14
W14
A1
N8
R8
O
N9
O
T9
I
M9
R9
FB0
I
COL7
O
L9
COL6
O
T10
K9
COL5
O
COL4
O
R10
N10
R11
M10
T12
L10
R12
N11
T13
R13
M11
T14
COL3
O
COL2
O
COL1
O
COL0
O
BUZ
O
V14
Y15
W15
V15
Y16
W16
V16
D[31]
I/O
I/O
I/O
I/O
Out
I/O
O
D[30]
D[29]
D[28]
A[27]/DRA[0]
D[27]
A[26]/DRA[1]
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
47
EP7311
High-Performance, Low-Power System on Chip
Table W. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA PBGA
Signal
Type
Position
Ball
Ball
102
103
104
105
106
109
110
111
112
113
114
115
117
118
119
120
121
122
126
127
128
129
130
131
132
133
134
135
136
137
138
141
142
143
144
145
146
147
Y17
W17
Y18
V17
W18
Y19
W20
U18
V20
U19
U20
T19
T20
R19
R20
T18
P19
P20
R18
N19
N20
P18
M19
N18
L20
L19
M18
K20
K19
K18
J20
N12
R14
T15
N13
R16
P15
M13
N16
L12
N15
L13
M16
M15
K11
L16
K12
L15
K13
J10
D[26]
A[25]/DRA[2]
D[25]
I/O
O
179
182
184
187
189
191
194
196
199
201
204
206
209
211
214
216
219
221
224
226
229
231
234
236
239
241
244
246
249
251
254
256
259
261
264
266
269
271
I/O
O
HALFWORD
A[24]/DRA[3]
D[24]
O
I/O
O
A[23]/DRA[4]
D[23]
I/O
O
A[22]/DRA[5]
D[22]
I/O
O
A[21]/DRA[6]
D[21]
I/O
O
A[20]/DRA[7]
D[20]
I/O
O
A[19]/DRA[8]
D[19]
I/O
O
A[18]/DRA[9]
D[18]
I/O
O
A[17]/DRA[10]
D[17]
J16
I/O
O
J11
A[16]/DRA[11]
D[16]
J15
I/O
O
J12
A[15]/DRA[12]
D[15]
H16
J13
I/O
O
A[14]/DRA[13]
D[14]
H15
H13
G16
H12
G15
H11
F15
H10
E16
G13
E15
G12
D16
I/O
O
A[13]/DRA[14]
D[13]
I/O
O
A[12]
D[12]
I/O
O
A[11]
J19
D[11]
I/O
O
H20
H19
J18
A[10]
D[10]
I/O
O
A[9]
K3
D[9]
I/O
O
Y3
A[8]
G20
D[8]
I/O
48
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table W. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA PBGA
Signal
Type
Position
Ball
Ball
148
150
151
152
153
154
155
156
161
162
163
164
165
166
169
170
171
172
173
175
176
177
178
179
184
185
186
187
188
189
191
192
193
194
195
196
199
200
H18
F20
G19
E20
F19
G18
D20
F18
D19
E19
C19
C20
E18
B20
B16
A16
C15
B15
A15
C14
B14
A14
C13
B13
A13
C12
B12
A12
C11
B11
B10
A10
A9
G11
D15
F13
C16
F12
C15
E13
B16
B14
D11
A13
F10
B13
E10
B12
D10
A11
G9
A[7]
D[7]
O
I/O
I
274
276
279
280
281
282
283
284
285
286
287
289
292
294
297
299
302
304
307
309
312
314
317
319
322
324
326
328
330
333
336
339
342
344
346
349
352
355
nBATCHG
nEXTPWR
BATOK
nPOR
nMEDCHG/nBROM
nURESET
WAKEUP
nPWRFL
A[6]
I
I
I
I
I
I
I
O
D[6]
I/O
O
A[5]
D[5]
I/O
O
A[4]
D[4]
I/O
O
A[3]
D[3]
I/O
O
B11
A10
F9
A[2]
D[2]
I/O
O
A[1]
B10
E9
D[1]
I/O
O
A[0]
A9
D[0]
I/O
O
D8
CL2
B8
CL1
O
E8
FRM
O
A7
M
O
F8
DD[3]
I/O
I/O
I/O
I/O
O
B7
DD[2]
A6
DD[1]
G8
DD[0]
B6
nSDCS[1]
nSDCS[0]
SDQM[3]
SDQM[2]
SDCKE
SDCLK
B9
D7
O
C9
A5
I/O
I/O
I/O
I/O
A8
E7
B8
F7
C8
A4
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
49
EP7311
High-Performance, Low-Power System on Chip
Table W. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA PBGA
Signal
Type
Position
Ball
Ball
201
202
204
205
206
207
208
A7
B7
C7
A6
B6
C6
A5
D6
B4
E6
A3
D5
B3
A2
nMWE/nSDWE
nMOE/nSDCAS
nCS[0]
O
O
O
O
O
O
O
358
360
362
364
366
368
370
nCS[1]
nCS[2]
nCS[3]
nCS[4]
1) See EP7311 Users’ Manual for pin naming / functionality.
2) For each pad, the JTAG connection ordering is input,
output, then enable as applicable.
50
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Table X. Acronyms and Abbreviations (Continued)
CONVENTIONS
Acronym/
Definition
This section presents acronyms, abbreviations, units of
measurement, and conventions used in this data sheet.
Abbreviation
TAP
test access port
Acronyms and Abbreviations
TLB
translation lookaside buffer
universal asynchronous receiver
Table X lists abbreviations and acronyms used in this
data sheet.
UART
Table X. Acronyms and Abbreviations
Units of Measurement
Acronym/
Definition
Table Y. Unit of Measurement
Abbreviation
Symbol
Unit of Measure
A/D
analog-to-digital
degree Celsius
°C
fs
ADC
CODEC
D/A
analog-to-digital converter
coder / decoder
sample frequency
hertz (cycle per second)
kilobits per second
kilobyte (1,024 bytes)
kilohertz
Hz
digital-to-analog
kbps
KB
DMA
EPB
FCS
FIFO
FIQ
direct-memory access
embedded peripheral bus
frame check sequence
first in / first out
kHz
kΩ
kilohm
Mbps
MB
MBps
MHz
µA
megabits (1,048,576 bits) per second
megabyte (1,048,576 bytes)
megabytes per second
megahertz (1,000 kilohertz)
microampere
fast interrupt request
general purpose I/O
in circuit test
GPIO
ICT
IR
infrared
IRQ
standard interrupt request
Infrared Data Association
Joint Test Action Group
liquid crystal display
light-emitting diode
µF
microfarad
IrDA
JTAG
LCD
LED
LQFP
LSB
MIPS
MMU
MSB
PBGA
PCB
PDA
PLL
µW
µs
microwatt
microsecond (1,000 nanoseconds)
milliampere
mA
mW
ms
milliwatt
low profile quad flat pack
least significant bit
millisecond (1,000 microseconds)
nanosecond
ns
millions of instructions per second
memory management unit
most significant bit
V
volt
W
watt
plastic ball grid array
printed circuit board
personal digital assistant
phase locked loop
p/u
pull-up resistor
RISC
RTC
SIR
reduced instruction set computer
Real-Time Clock
slow (9600–115.2 kbps) infrared
static random access memory
synchronous serial interface
SRAM
SSI
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
51
EP7311
High-Performance, Low-Power System on Chip
General Conventions
Pin Description Conventions
Hexadecimal numbers are presented with all letters in
uppercase and a lowercase “h” appended or with a 0x at
the beginning. For example, 0x14 and 03CAh are
hexadecimal numbers. Binary numbers are enclosed in
single quotation marks when in text (for example, ‘11’
designates a binary number). Numbers not indicated by
an “h”, 0x or quotation marks are decimal.
Abbreviations used for signal directions are listed in
Table Z.
Table Z. Pin Description Conventions
Abbreviation
Direction
I
Input
O
I/O
Output
Registers are referred to by acronym, with bits listed in
Input or Output
brackets separated by
a
colon (:) (for example,
CODR[7:0]), and are described in the EP7311 User ’s
Manual. The use of “TBD” indicates values that are “to
be determined,” “n/ a” designates “not available,” and
“n/ c” indicates a pin that is a “no connect.”
52
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
ORDERING INFORMATION
The order number for the device is:
EP7311 — CV — C
Revision †
Package Type:
V = Low Profile Quad Flat Pack
B = Plastic Ball Grid Array (17 mm x 17 mm)
R = Reduced Ball Grid Array (13 mm x 13 mm)
Temperature Range:
Part Number C = Commercial
E = Extended Operating Version
I = Industrial Operating Version
Product Line:
Embedded Processor
Note: Contact Cirrus Logic for up-to-date information on revisions. Go to the Cirrus Logic Internet site at
http://cirrus.com/corporate/contacts to find contact information for your local sales representative.
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
53
EP7311
High-Performance, Low-Power System on Chip
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
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without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify,
before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order
acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information,
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
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LINUX is a registered trademark of Linus Torvalds.
54
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
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