EP9307_技术文档

EP9307 Data Sheet

FEATURES

ARM9 SOC with Ethernet, USB,

Display and Touchscreen

•

200 MHz ARM920T Processor

•

16 Kbyte Instruction Cache

16 Kbyte Data Cache

®

•

Linux , Microsoft Windows CE enabled MMU

•

Touchscreen Interface with ADC

8 x 8 Keypad Scanner

100 MHz System Bus

™

One Serial Peripheral Interface (SPI) Port

•

MaverickCrunch Math Engine

2

•

Floating point, integer and signal processing

instructions

•

6-channel or 2-channel Serial Audio Interface (I S)

2-channel low-cost Serial Audio Interface (AC'97)

Optimized for digital music compression and

decompression algorithms

•

Internal Peripherals

•

12 Direct Memory Access (DMA) Channels

Real-time Clock with software Trim

Dual PLL controls all clock domains

Watchdog Timer

Hardware interlocks allow in-line coding

™

•

MaverickKey IDs

•

32-bit unique ID can be used for DRM compliance

128-bit random ID

Two general purpose 16-bit timers

One general purpose 32-bit timer

One 40-bit Debug Timer

Integrated Peripheral Interfaces

•

32-bit SDRAM Interface up to 4 banks

32/16-bit SRAM/FLASH/ROM

Serial EEPROM Interface

1/10/100 Mbps Ethernet MAC

Three UARTs

Interrupt Controller

Boot ROM

•

Package

272 pin TFBGA

•

Three-port USB 2.0 Full Speed Host (OHCI)

(12 Mbits per second)

•

IrDA Interface

LCD and Raster Interface with Graphics

Accelerator

Serial

Audio

Interface

Peripheral Bus

Clocks &

Timers

MaverickCrunch^TM

ARM920T

12 Channel DMA

Interrupts

& GPIO

(3) UARTs

w/

MaverickKey^TM

IrDA

D-Cache

16KB

I-Cache

16KB

Keypad &

Touch

Screen I/F

(3) USB

Hosts

Boot

ROM

Bus

Bridge

MMU

Processor Bus

Unified

SDRAM I/F

Graphic

Accelerator

SRAM &

Flash I/F

Video/LCD

Controller

Ethernet MAC

MEMORY AND STORAGE

AUG ‘04

DS667PP3

http://www.cirrus.com

1

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

OVERVIEW

The EP9307 is an ARM920T-based system-on-a-chip

(SOC) design with a large peripheral set targeted to a

variety of applications:

and commerce. With Internet security playing an

important role in the delivery of digital media such as

books or music, traditional software methods are quickly

becoming unreliable. The MaverickKey unique IDs

provide OEMs with a method of utilizing specific

hardware IDs such as those assigned for SDMI (Secure

Digital Music Initiative) or any other authentication

mechanism.

•

Thin client computers for business and home

Internet radio

Internet access devices

Industrial computers

A high-performance 1/10/100 Mbps Ethernet Media

Access Controller (MAC) is included along with external

Specialized terminals

2

interfaces to SPI, I S audio, Raster/LCD, keypad and

Point of sale terminals

touchscreen. A three-port USB 2.0 Full Speed Host

(OHCI) (12 Mbits per second) and three UARTs are

included as well.

Test and measurement equipment

The EP9307 is one of a series of ARM920T-based

devices.

The EP9307 is a high-performance, low-power RISC-

based single-chip computer built around an ARM920T

microprocessor core with a maximum operating clock

rate of 200 MHz (184 MHz for industrial conditions). The

ARM core operates from a 1.8 V supply, while the I/O

operates at 3.3 V with power usage between 100 mW

and 750 mW (dependent on speed).

The ARM920T microprocessor core with separate

16 Kbyte, 64-way set-associative instruction and data

caches is augmented by the MaverickCrunch™ co-

processor

enabling

high-speed

floating

point

calculations.

™

MaverickKey unique hardware programmed IDs are a

solution to the growing concern over secure web content

Table A. Change History

Revision

Date

Changes

1

2

July 2004

Initial Release.

August 2004

Correct error in pin out table, pages 42 & 43.

2

DS667PP3

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Table of Contents

FEATURES .........................................................................................................1

OVERVIEW .........................................................................................................2

Processor Core - ARM920T ......................................................................................... 6

MaverickCrunch™ Math Engine .................................................................................. 6

MaverickKey™ Unique ID ............................................................................................ 6

General Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH) ........................ 6

Ethernet Media Access Controller (MAC) .................................................................... 7

Serial Interfaces (SPI, I2S and AC ’97) ........................................................................ 7

Raster/LCD Interface ................................................................................................... 7

Graphics Accelerator ................................................................................................... 8

Touch Screen Interface with 12-bit Analog-to-Digital Converter (ADC) ....................... 8

64-Keypad Interface ..................................................................................................... 8

Universal Asynchronous Receiver/Transmitters (UARTs) ............................................ 9

Internal Boot ROM ....................................................................................................... 9

Triple Port USB Host .................................................................................................... 9

Two-Wire Interface With EEPROM Support ................................................................ 9

Real-Time Clock with Software Trim .......................................................................... 10

PLL and Clocking ....................................................................................................... 10

Timers ........................................................................................................................ 10

Interrupt Controller ..................................................................................................... 10

Dual LED Drivers ....................................................................................................... 10

General Purpose Input/Output (GPIO) ....................................................................... 10

Reset and Power Management ..................................................................................11

Hardware Debug Interface ..........................................................................................11

12-Channel DMA Controller ........................................................................................11

Electrical Specifications .................................................................................12

Absolute Maximum Ratings ....................................................................................... 12

Recommended Operating Conditions ........................................................................ 12

DC Characteristics ..................................................................................................... 13

Timings .............................................................................................................14

Memory Interface ....................................................................................................... 15

Ethernet MAC Interface ............................................................................................ 29

Audio Interface ........................................................................................................... 31

AC’97 ...................................................................................................................... 35

LCD Interface .......................................................................................................... 36

ADC ........................................................................................................................... 37

JTAG .......................................................................................................................... 38

272 Pin TFBGA Package Outline ...................................................................39

272 TFBGA Diagram ................................................................................................. 39

272 Pin TFBGA Pinout (Bottom View) ....................................................................... 40

Acronyms and Abbreviations ........................................................................47

Units of Measurement .....................................................................................47

ORDERING INFORMATION ............................................................................48

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EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

List of Figures

Figure 1. Timing Diagram Drawing Key .................................................................................14

Figure 2. SDRAM Load Mode Register Cycle Timing Measurement .....................................15

Figure 3. SDRAM Burst Read Cycle Timing Measurement ...................................................16

Figure 4. SDRAM Burst Write Cycle Timing Measurement ...................................................17

Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................18

Figure 6. Static Memory Single Word Read Cycle Timing Measurement ..............................19

Figure 7. Static Memory Single Word Write Cycle Timing Measurement ..............................20

Figure 8. Static Memory Multiple Word Read 8 Bit Cycle Timing Measurement ...................21

Figure 9. Static Memory Multiple Word Write 8 bit Cycle Timing Measurement ....................22

Figure 10. Static Memory Multiple Word Read 16 Bit Cycle Timing Measurement ...............23

Figure 11. Static Memory Multiple Word Write 16 bit Cycle Timing Measurement ................24

Figure 12. Static Memory Burst Read Cycle Timing Measurement .......................................25

Figure 13. Static Memory Single Read Wait Cycle Timing Measurement .............................26

Figure 14. Static Memory Single Write Wait Cycle Timing Measurement ..............................27

Figure 15. Static Memory Turnaround Cycle Timing Measurement .......................................28

Figure 16. Ethernet MAC Timing Measurement .....................................................................30

Figure 17. SPI Single Transfer Timing Measurement ............................................................32

Figure 18. Microwire Frame Format, Single Transfer ............................................................32

Figure 19. SPI Format with SPH=1 Timing Measurement .....................................................33

Figure 20. Inter-IC Sound (I2S) Timing Measurement ...........................................................34

Figure 21. AC ‘97 Configuration Timing Measurement ..........................................................35

Figure 22. LCD Timing Measurement ....................................................................................36

Figure 23. ADC Transfer Function .........................................................................................37

Figure 24. JTAG Timing Measurement ..................................................................................38

Figure 25. 272 Pin TFBGA Diagram ......................................................................................39

Figure 26. 272 Pin TFBGA Pinout

....................................................................................41

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EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

List of Tables

Table A. Change History .......................................................................................................... 2

Table B. General Purpose Memory Interface Pin Assignments .............................................. 6

Table C. Ethernet Media Access Controller Pin Assignments ................................................. 7

Table D. Audio Interfaces Pin Assignment .............................................................................. 7

Table E. LCD Interface Pin Assignments ................................................................................ 8

Table F. Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments ... 8

Table G.64-Key Keypad Interface Pin Assignments ............................................................... 8

Table H. Universal Asynchronous Receiver / Transmitters Pin Assignments .......................... 9

Table I. Triple Port USB Host Pin Assignments ..................................................................... 9

Table J. Two-Wire Port with EEPROM Support Pin Assignments .......................................... 9

Table K. Real-Time Clock with Pin Assignments ................................................................... 10

Table L. PLL and Clocking Pin Assignments ........................................................................ 10

Table M.Interrupt Controller Pin Assignment ........................................................................ 10

Table N. Dual LED Pin Assignments ..................................................................................... 10

Table O.General Purpose Input/Output Pin Assignment ...................................................... 11

Table P. Reset and Power Management Pin Assignments ................................................... 11

Table Q.Hardware Debug Interface ...................................................................................... 11

Table R. 272 Pin Diagram Dimensions .................................................................................. 40

Table S. Pin Descriptions ..................................................................................................... 44

Table T. Pin Multiplex Usage Information ............................................................................. 46

DS667PP3

5

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

provide OEMs with a method of utilizing specific

hardware IDs such as those assigned for SDMI (Secure

Digital Music Initiative) or any other authentication

mechanism.

Processor Core - ARM920T

The ARM920T is a Harvard architecture processor with

separate 16 Kbyte instruction and data caches with an 8-

word line length but a unified memory. The processor

utilizes a five-stage pipeline consisting of fetch, decode,

execute, memory and write stages. Key features include:

Both a specific 32-bit ID as well as a 128-bit random ID is

programmed into the EP9307 through the use of laser

probing technology. These IDs can then be used to

match secure copyrighted content with the ID of the

target device the EP9307 is powering, and then deliver

the copyrighted information over a secure connection. In

addition, secure transactions can benefit by also

matching device IDs to server IDs. MaverickKey IDs

provide a level of hardware security required for today’s

Internet appliances.

•

ARM (32-bit) and Thumb (16-bit compressed)

instruction sets

32-bit Advanced Micro-Controller Bus Architecture

(AMBA)

•

16 Kbyte Instruction Cache with lockdown

16 Kbyte Data Cache (programmable write-through or

write-back) with lockdown

®

•

MMU for Linux , Microsoft Windows CE and other

operating systems

General Purpose Memory Interface (SDRAM,

SRAM, ROM, FLASH)

Translation Look Aside Buffers with 64 Data and 64

Instruction Entries

The EP9307 features a unified memory address model

where all memory devices are accessed over a common

address/data bus. A separate internal port is dedicated to

the read-only Raster/LCD refresh engine, while the rest

of the memory accesses are performed via the Processor

bus. The SRAM memory controller supports 8, 16 and

32-bit devices and accommodates an internal boot ROM

concurrently with 32-bit SDRAM memory.

Programmable Page Sizes of 64 Kbyte, 4 Kbyte, and

1 Kbyte

Independent lockdown of TLB Entries

™

MaverickCrunch Math Engine

The MaverickCrunch Engine is

a

mixed-mode

coprocessor designed primarily to accelerate the math

processing required to rapidly encode digital audio

formats. It accelerates single and double precision

integer and floating point operations plus an integer

•

1-4 banks of 32-bit, 100 MHz SDRAM

One internal port dedicated to the Raster/LCD

Refresh Engine (Read Only)

multiply-accumulate

(MAC)

instruction

that

is

•

One internal port dedicated to the rest of the chip via

the Processor bus

considerably faster than the ARM920T's native MAC

instruction. The ARM920T coprocessor interface is

utilized thereby sharing its memory interface and

instruction stream. Hardware forwarding and interlock

allows the ARM to handle looping and addressing while

MaverickCrunch handles computation. Features include:

Address and data bus shared between SDRAM,

SRAM, ROM, and FLASH memory

Both NAND and NOR FLASH memory supported

Table B. General Purpose Memory Interface Pin Assignments

•

IEEE-754 single and double precision floating point

32/64-bit integer

Pin Mnemonic

Pin Description

SDCLK

SDRAM Clock

Add/multiply/compare

SDCLKEN

SDCSn[3:0]

RASn

SDRAM Clock Enable

SDRAM Chip Selects 3-0

SDRAM RAS

Integer MAC 32-bit input with 72-bit accumulate

Integer Shifts

Floating point to/from integer conversion

Sixteen 64-bit register files

CASn

SDRAM CAS

SDWEn

SDRAM Write Enable

Chip Selects 7, 6, 3, 2, 1, 0

Address Bus 25-0

Four 72-bit accumulators

CSn[7:6] and CSn[3:0]

AD[25:0]

DA[31:0]

DQMn[3:0]

WRn

™

MaverickKey Unique ID

Data Bus 31-0

MaverickKey unique hardware programmed IDs are a

solution to the growing concern over secure web content

and commerce. With Internet security playing an

important role in the delivery of digital media such as

books or music, traditional software methods are quickly

becoming unreliable. The MaverickKey unique IDs

SDRAM Output Enables / Data Masks

SRAM Write Strobe

SRAM Read/OE Strobe

SRAM Wait Input

RDn

WAITn

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EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Ethernet Media Access Controller (MAC)

Table D. Audio Interfaces Pin Assignment

The MAC subsystem is compliant with the ISO/TEC

802.3 topology for a single shared medium with several

stations. Multiple MII-compliant PHYs are supported.

Features include:

I2S on SSP

Mode

I2S on AC'97

Mode

Normal Mode

Name

Description

Pin Description Pin Description

SCLK1

SFRM1

SPI Bit Clock

I2S Serial Clock

SPI Bit Clock

•

Supports 1/10/100 Mbps transfer rates for

home/small-business/large-business applications

SPI Frame Clock I2S Frame Clock

SPI Frame Clock

SPI Serial Input

SSPRX1 SPI Serial Input I2S Serial Input

SPI Serial

Interfaces to an off-chip PHY through industry

standard Media Independent Interface (MII)

SSPTX1

I2S Serial Output SPI Serial Output

Output

(No I2S Master

Clock)

Table C. Ethernet Media Access Controller Pin Assignments

ARSTn

AC'97 Reset

I2S Master Clock

I2S Serial Clock

Pin Mnemonic

Pin Description

ABITCLK AC'97 Bit Clock AC'97 Bit Clock

MDC

Management Data Clock

AC'97 Frame

Clock

AC'97 Frame

Clock

MDIO

Management Data I/O

Receive Clock

ASYNC

ASDI

I2S Frame Clock

RXCLK

MIIRXD[3:0]

RXDVAL

RXERR

TXCLK

MIITXD[3:0]

TXEN

AC'97 Serial

Input

AC'97 Serial Input I2S Serial Input

Receive Data

Receive Data Valid

Receive Data Error

Transmit Clock

Transmit Data

AC'97 Serial

Output

AC'97 Serial

I2S Serial Output

Output

ASDO

Raster/LCD Interface

The Raster/LCD interface provides data and interface

signals for a variety of display types. It features fully

programmable video interface timing for non-interlaced

flat panel or dual scan displays. Resolutions up to

1280 x 1024 are supported from a unified SDRAM based

frame buffer. A 16-bit PWM provides control for LCD

panel contrast. LCD specific features include:

Transmit Enable

Transmit Error

TXERR

CRS

Carrier Sense

CLD

Collision Detect

2

Serial Interfaces (SPI, I S and AC ’97)

•

Timing and interface signals for digital LCD and TFT

displays

The SPI port can be configured as a master or a slave,

®

supporting the National Semiconductor , Motorola and

Full programmability for either non-interlaced or dual-

scan color and grayscale flat panel displays

®

Texas Instruments signaling protocols.

Dedicated data path to SDRAM controller for

improved system performance

The AC'97 port supports multiple codecs for multichannel

2

audio output with a single stereo input. The I S port can

be configured to support two channel, 24 bit audio.

Pixel depths of 4, 8, 16, or 18-bits per pixel or 256

levels of grayscale

2

•

Hardware Cursor up to 64 x 64 pixels

256 x 18 Color Lookup Table

Hardware Blinking

These ports are multiplexed so that I S port 0 will take

over either the AC'97 pins or the SPI pins. The second

and third I2S ports' serial input and serial output pins are

multiplexed with EGPIO[4,5,6,13]. The clocks supplied in

the first I2S port are also used for the second and third

I2S ports.

8-bit interface to low end panel

•

Normal Mode: One SPI Port and one AC’97 Port

2

I S on SSP Mode: One AC’97 Port and up to three I S

Ports

2

•

I S on AC’97 Mode: One SPI Port and up to three I S

Ports

Note: I²S may not be output on AC’97 and SSP ports at the

same time.

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EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Table E. LCD Interface Pin Assignments

Table F. Touch Screen Interface with 12-bit Analog-to-Digital

Converter Pin Assignments

Pin Mnemonic

Pin Description

Pin Mnemonic

Pin Description

SPCLK

Pixel Clock

Xp, Xm

Touch screen ADC X Axis

Touch screen ADC Y Axis

P[17:0]

Pixel Data Bus [17:0]

Yp, Ym

Horizontal

Synchronization/Line Pulse

HSYNC/LP

Touch screen ADC X Axis

Voltage Feedback

SXp, SXm

Vertical or Composite

Synchronization / Frame Pulse

VCSYNC/FP

Touch screen ADC Y Axis

Voltage Feedback

SYp, SYm

BLANK

Composite Blank

BRIGHT

Pulse Width Modulated Brightness

64-Keypad Interface

Graphics Accelerator

The keypad circuitry scans an 8 x 8 array of 64 normally

open, single pole switches. Any one or two keys

depressed will be de-bounced and decoded. An interrupt

is generated whenever a stable set of depressed keys is

detected. If the keypad is not utilized, the 16 column/row

pins may be used as general purpose I/O. The Keypad

interface:

The EP9307 contains a hardware graphics acceleration

engine that improves graphic performance by handling

block copy, block fill and hardware line draw operations.

The Graphics Accelerator is used in the system to off-

load graphics operations from the processor.

Pixel depths supported by the Graphics Accelerator are

4, 8, 16 or 24 bits per pixel (bpp). The 24 bits per pixel

mode can be operated as packed (4 pixels every 3

words) or unpacked (1 pixel per word with the high byte

unused.)

•

Provides scanning, debounce and decoding for a 64-

key array.

•

Scans an 8-row by 8-column matrix.

May decode 2 keys at once.

Generates an interrupt when a new stable key is

determined.

The block copy operations of the Graphics Accelerator

are similar to a DMA (Direct Memory Access) transfer

that understands pixel organization, block width,

transparency, and transformation from 1bpp to higher 4,

8, 16 or 24 bpp.

•

Also generates a 3-key reset interrupt.

Table G. 64-Key Keypad Interface Pin Assignments

Pin Mnemonic

Alternative Usage

The line draw operations also allow for solid lines or

dashed lines. The colors for line drawing can be either

foreground color and background color or foreground

color with the background being transparent.

Description

Key Matrix Column

Inputs

COL[7:0]

ROW[7:0]

General Purpose I/O

Key Matrix Row

Inputs

Touch Screen Interface with 12-bit Analog-

to-Digital Converter (ADC)

The touch screen interface performs all sampling,

averaging, ADC range checking, and control for a wide

variety of analog resistive touch screens. This controller

only interrupts the processor when a meaningful change

occurs. The touch screen hardware may be disabled and

the switch matrix and ADC controlled directly if desired.

Features include:

•

Support for 4, 5, 7, or 8-wire analog resistive touch

screens.

Flexibility - unused lines may be used for temperature

sensing or other functions.

Touch screen interrupt function.

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EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Universal Asynchronous

Triple Port USB Host

Receiver/Transmitters (UARTs)

The USB Open Host Controller Interface (Open HCI)

provides full speed serial communications ports at a

baud rate of 12 Mbits/sec. Up to 127 USB devices

(printer, mouse, camera, keyboard, etc.) and USB hubs

can be connected to the USB host in the USB “tiered-

start” topology.

Three 16550-compatible UARTs are supplied. Two

provide asynchronous HDLC (High-level Data Link

Control) protocol support for full duplex transmit and

receive. The HDLC receiver handles framing, address

matching, CRC checking, control-octet transparency, and

optionally passes the CRC to the host at the end of the

packet. The HDLC transmitter handles framing, CRC

generation, and control-octet transparency. The host

must assemble the frame in memory before

transmission. The HDLC receiver and transmitter use the

This includes the following features:

•

Compliance with the USB 2.0 specification

Compliance with the Open HCI Rev 1.0 specification

Supports both low speed (1.5 Mbps) and full speed

(12 Mbps) USB device connections

®

UART FIFOs to buffer the data streams. A third IrDA

compatible UART is also supplied.

•

Root HUB integrated with 3 downstream USB ports

Transceiver buffers integrated, over-current protection

on ports

•

UART1 supports modem bit rates up to 115.2 Kbps,

supports HDLC and includes a 16 byte FIFO for

receive and a 16 byte FIFO for transmit. Interrupts are

generated on Rx, Tx and modem status change.

•

Supports power management

Operates as a master on the bus

UART2 contains an IrDA encoder operating at either

the slow (up to 115 Kbps), medium (0.576 or 1.152

Mbps), or fast (4 Mbps) IR data rates. It also has a 16

byte FIFO for receive and a 16 byte FIFO for transmit.

The Open HCI host controller initializes the master DMA

transfer with the AHB bus:

•

Fetches endpoint descriptors and transfer descriptors

Accesses endpoint data from system memory

Accesses the HC communication area

UART3 supports HDLC and includes a 16 byte FIFO

for receive and a 16 byte FIFO for transmit. Interrupts

are generated on Rx and Tx.

Writes status and retire transfer descriptor

Table H. Universal Asynchronous Receiver / Transmitters Pin

Assignments

Table I. Triple Port USB Host Pin Assignments

Pin Mnemonic

Pin Name - Description

Pin Mnemonic

Pin Name - Description

USBp[2:0]

USBm[2:0]

USB Positive signals

USB Negative Signals

TXD0

UART1 Transmit

RXD0

UART1 Receive

UART1 Clear To

Send / Transmit Enable

CTSn

Two-Wire Interface With EEPROM Support

UART1 Data Set

Ready / Data Carrier Detect

The two-wire interface provides communication and

control for EEPROM devices.

DSRn/DCDn

DTRn

UART1 Data Terminal Ready

UART1 Ready To Send

UART1 Ring Indicator

RTSn

Table J. Two-Wire Port with EEPROM Support Pin Assignments

EGPIO[0]/RI

Alternative

Pin Mnemonic Pin Name - Description

Usage

UART2 Transmit / IrDA

Output

TXD1/SIROUT

EEPROM / Two-Wire

Interface Clock

General

Purpose I/O

RXD1/SIRIN

TXD2

UART2 Receive / IrDA Input

UART3 Transmit

EECLK

EEPROM / Two-Wire

Interface Data

General

Purpose I/O

EEDATA

RXD2

UART3 Receive

TENn

HDLC3 Transmit Enable

Internal Boot ROM

The Internal 16 Kbyte ROM allows booting from FLASH

memory, SPI or UART.

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EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

sensitive, active low level sensitive, rising edge triggered,

falling edge triggered, or combined rising/falling edge

triggered.

Real-Time Clock with Software Trim

The software trim feature on the real time clock (RTC)

provides software controlled digital compensation of the

32.768 KHz crystal oscillator. This compensation is

accurate to 1.24 sec/month.

•

Supports 64 interrupts from a variety of sources (such

as UARTs, GPIO, and key matrix)

Routes interrupt sources to either the ARM920T’s

IRQ or FIQ (Fast IRQ) inputs

Table K. Real-Time Clock with Pin Assignments

Three dedicated off-chip interrupt lines operate as

active high level sensitive interrupts

Pin Mnemonic

Pin Name - Description

RTCXTALI

Real-Time Clock Oscillator Input

Real-Time Clock Oscillator Output

Any of the 16 GPIO lines maybe configured to

generate interrupts

RTCXTALO

Software supported priority mask for all FIQs and

IRQs

PLL and Clocking

The Processor and the Peripheral Clocks operate from a

single 14.7456 MHz crystal.

Table M. Interrupt Controller Pin Assignment

Pin Mnemonic

Pin Name - Description

The Real Time Clock operates from a 32.768 KHz crystal

oscillator.

INT[2:0]

External Interrupts 2, 1, 0

Table L. PLL and Clocking Pin Assignments

Dual LED Drivers

Pin Mnemonic

Pin Name - Description

Two pins are assigned specifically to drive external

LEDs.

XTALI

Main Oscillator Input

XTALO

Main Oscillator Output

Main Oscillator Power

Main Oscillator Ground

Table N. Dual LED Pin Assignments

Pin Name -

VDD_PLL

GND_PLL

Pin Mnemonic

Alternative Usage

Description

GRLED

Green LED

Red LED

General Purpose I/O

Timers

REDLED

The Watchdog Timer insures proper operation by

requiring periodic attention to prevent a reset-on-time-

out.

General Purpose Input/Output (GPIO)

The 14 EGPIO pins may each be configured individually

as an output, an input, or an interrupt input.

Two 16-bit timers operate as free running down-counters

or as periodic timers for fixed interval interrupts and have

a range of 0.03 ms to 4.27 seconds.

There are 22 pins that may alternatively be used as input,

output, or open-drain pins, but do not support interrupts.

These pins are:

One 32-bit timer, plus a 6-bit prescale counter, has a

range of 0.03 µs to 73.3 hours.

• Key Matrix ROW[7:0], COL[7:0]

• Ethernet MDIO

• Both LED Outputs

• EEPROM Clock and Data

• GGPIO[2]

One 40-bit debug timer, plus a 6-bit prescale counter, has

a range of 1.0 µs to 12.7 days.

Interrupt Controller

• HGPIO[7:2]

The interrupt controller allows up to 62 interrupts to

generate an Interrupt Request (IRQ) or Fast Interrupt

Request (FIQ) signal to the processor core. Thirty-two

hardware priority assignments are provided for assisting

IRQ vectoring, and two levels are provided for FIQ

vectoring. This allows time critical interrupts to be

processed in the shortest time possible. Internal

interrupts may be programmed as active high or active

low level sensitive inputs. GPIO pins programmed as

interrupts may be programmed as active high level

6 pins may alternatively be used as inputs only:

• CTSn, DSRn/DCDn

• 4 Interrupt Lines

2 pins may alternatively be used as outputs only:

• RTSn

• ARSTn

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EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

decrement, or stay at the same value. All DMA

addresses are physical, not virtual addresses.

Table O. General Purpose Input/Output Pin Assignment

Pin Mnemonic

Pin Name - Description

EGPIO[15]

EGPIO[13:0]

Expanded General Purpose Input / Output

Pins with Interrupts

FGPIO[7]

FGPIO[5]

FGPIO[0]

Expanded General Purpose Input / Output

Pins with Interrupts

Reset and Power Management

The chip may be reset through the PRSTn pin or through

the open drain common reset pin, RSTOn.

Clocks are managed on a peripheral-by-peripheral basis

and may be turned off to conserve power.

The processor clock is dynamically adjustable from 0 to

200 MHz (184 MHz for industrial conditions).

Table P. Reset and Power Management Pin Assignments

Pin Mnemonic

Pin Name - Description

PRSTn

RSTOn

Power On Reset

User Reset In/Out – Open Drain –

Preserves Real Time Clock value

Hardware Debug Interface

The JTAG interface allows use of ARM’s Multi-ICE or

other in-circuit emulators.

Table Q. Hardware Debug Interface

Pin Mnemonic

Pin Name - Description

TCK

JTAG Clock

TDI

JTAG Data In

TDO

TMS

TRSTn

JTAG Data Out

JTAG Test Mode Select

JTAG Port Reset

12-Channel DMA Controller

The DMA module contains 12 separate DMA channels.

These may be used for peripheral-to-memory or

memory-to-peripheral access. Two of these are

dedicated to memory-to-memory transfers. Each DMA

channel is connected to the 16-bit DMA request bus.

The request bus is a collection of requests, Serial Audio

and UARTs. Each DMA channel can be used

independently or dedicated to any request signal. For

each DMA channel, source and destination addressing

can be independently programmed to increment,

DS667PP3

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ARM9 SOC with Ethernet, USB, Display and Touchscreen

Electrical Specifications

Absolute Maximum Ratings

(All grounds = 0 V, all voltages with respect to 0 V)

Parameter

Symbol

Min

Max

Unit

RVDD

CVDD

VDD_PLL

VDD_ADC

-

3.96

2.16

3.96

V

Power Supplies

Total Power Dissipation

(Note 1)

(Note 2)

-

2

10

W

mA

V

Input Current per Pin, DC (Except supply pins)

Output current per pin, DC

Digital Input voltage

-

50

-0.3

-40

RVDD+0.3

+125

Storage temperature

°C

Note: 1. Includes all power generated due to AC and/or DC output loading.

2. The power supply pins are at maximum values listed in “Recommended Operating Conditions”, below.

3. At ambient temperatures above 70° C, total power dissipation must be limited to less than 2.5 Watts.

WARNING: Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Recommended Operating Conditions

(All grounds = 0 V, all voltages with respect to 0 V)

Parameter

Symbol

Min

Typ

Max

Unit

RVDD

CVDD

VDD_PLL

VDD_ADC

3.0

1.65

3.0

3.3

1.80

3.3

3.6

1.94

3.6

V

Power Supplies

T_A

Operating Ambient Temperature - Commercial

0

+25

+70

°C

Operating Ambient Temperature - Industrial

Processor Clock Speed - Commercial

Processor Clock Speed - Industrial

System Clock Speed - Commercial

System Clock Speed - Industrial

-40

+25

+85

200

184

100

92

°C

FCLK

HCLK

-

MHz

12

DS667PP3

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ARM9 SOC with Ethernet, USB, Display and Touchscreen

DC Characteristics

(T = 0 to 70° C; CVDD = VDD_PLL = 1.8; RVDD = 3.3 V;

A

All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted)

Parameter

Symbol

Min

Max

Unit

V_oh

V_ol

V_ih

V_il

I_ih

High level output voltage

Low level output voltage

High level input voltage

Low level input voltage

High level leakage current

Low level leakage current

Iout = -4 mA

Iout = 4 mA

(Note 4)

0.85 × RVDD

-

V

-

0.15 × RVDD

VDD + 0.3

0.35 × RVDD

10

(Note 5)

0.65 × RVDD

V

−0.3

V

Vin = 3.3 V

Vin = 0

-

µA

I_il

-10

Parameter

Min

Typ

Max

Unit

Power Supply Pins (Outputs Unloaded)

Power Supply Current:

CVDD/VDD_PLL Total

RVDD

-

200

20

-

mA

Low-Power Mode Supply Current

CVDD/VDD_PLL Total

RVDD

-

2.5

1.0

-

mA

Note: 4. For open drain pins, high level output voltage is dependent on the external load.

5. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation (See Table S on

page 44). If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not

driven and programmed as an input, it should be tied to power or ground through its own resistor.

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ARM9 SOC with Ethernet, USB, Display and Touchscreen

Timings

Timing Diagram Conventions

This data sheet contains one or more timing diagrams. The following key explains the components used in these

diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached

unless specifically stated.

Clock

High to Low

High/Low to High

Bus Change

Bus Valid

Undefined/Invalid

Valid Bus to High Impedance State

Bus/Signal Omission

Figure 1. Timing Diagram Drawing Key

Timing Conditions

Unless specified otherwise, the following conditions are true for all timing measurements.

• T = 0 to 70° C

A

• CVDD = VDD_PLL = 1.8V

• RVDD = 3.3 V

• All grounds = 0 V

• Logic 0 = 0 V, Logic 1 = 3.3 V

• Output loading = 50 pF

• Timing reference levels = 1.5 V

• The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between

33 MHz and 100 MHz (92 MHz for industrial conditions).

14

DS667PP3

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ARM9 SOC with Ethernet, USB, Display and Touchscreen

Memory Interface

Figure 2 through Figure 5 define the timings associated with all phases of the SDRAM. The following table contains the

values for the timings of each of the SDRAM modes.

Parameter

Symbol

t_{clk_high}

t_{clk_low}

t_clkrf

Min

Typ

Max

Unit

(t_HCLK)/2

SDCLK high time

SDCLK low time

SDCLK rise/fall time

-

ns

(t_HCLK)/2

3

8

4

6

2

t_d

Signal delay from SDCLK rising edge time

Signal hold from SDCLK rising edge time

DQMn delay from SDCLK rising edge time

DQMn hold from SDCLK rising edge time

DA valid setup to SDCLK rising edge time

DA valid hold from SDCLK rising edge time

t_h

t_DQd

t_DQh

t_DAs

t_DAh

SDRAM Load Mode Register Cycle

t_{clk_low}

t_{clk_high}

t_clkrf

SDCLK

t_d

t_h

SDCSn

RASn

CASn

SDWEn

DQMn

AD

OP-Code

DA

Figure 2. SDRAM Load Mode Register Cycle Timing Measurement

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EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

SDRAM Burst Read Cycle

t_{clk_low}

t_{clk_high}

SDCLK

t_clkrf

t_d

t_h

SDCSn

RASn

CASn

SDWEn

DQMn

AD

t_DQd

t_DQh

t_d

t_DAs

t_DAh

DA

Figure 3. SDRAM Burst Read Cycle Timing Measurement

16

DS667PP3

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ARM9 SOC with Ethernet, USB, Display and Touchscreen

SDRAM Burst Write Cycle

t_{clk_high}

t_{clk_low}

SDCLK

t_clkrf

t_d

t_h

SDCSn

RASn

CASn

SDWEn

DQMn

AD

DA

Figure 4. SDRAM Burst Write Cycle Timing Measurement

DS667PP3

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EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

SDRAM Auto Refresh Cycle

t_{clk_high}

t_{clk_low}

SDCLK

t_clkrf

t_d

t_h

7

b

d

e

SDCSn

RASn

CASn

SDWEn

Note: Chip select shown as bus to illustrate multiple devices being put into auto refresh in one access

Figure 5. SDRAM Auto Refresh Cycle Timing Measurement

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DS667PP3

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ARM9 SOC with Ethernet, USB, Display and Touchscreen

Static Memory Single Word Read Cycle

Parameter

Symbol

t_ADs

Min

Typ

5

Max

Unit

AD setup to RDn assert time

-

ns

t_ADh

t_HCLK× 2

AD hold from RDn deassert time

RDn assert time

-

t_RDpw

t_RDd

t_HCLK× (WST1 + 2)

t_HCLK× 33

-

CSn assert to RDn assert delay time

CSn deassert to RDn deassert delay time

CSn assert to DQMn assert delay time

CSn deassert to DQMn deassert delay time

DA setup to RDn deassert time

DA hold from RDn deassert time

-

0

-

t_RDh

-

0

t_DQMd

t_DQMh

t_DAs

-

0

-

t_HCLK+ 6

-

t_DAh

0

See “Timing Conditions” on page 14 for definition of HCLK.

t_ADs

t_ADh

AD

CSn

WRn

t_RDd1

t_RDd2

h

t_RDpw

RDn

t_DQMd1

t_DQMd2

h

DQMn

t_DAh

t_DAs

DA

WAIT

Figure 6. Static Memory Single Word Read Cycle Timing Measurement

DS667PP3

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EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Static Memory Single Word Write Cycle

Parameter

Symbol

t_ADs

Min

Typ

t_HCLK

Max

Unit

AD setup to WRn assert time

AD hold from WRn deassert time

WRn deassert to CSn deassert time

CSn to WRn assert delay time

WRn assert time

-

ns

t_ADh

t_HCLK× 3

t_HCLK

t_CSh

t_WRd

0

t_WRpw

t_DQMd

t_DQMh

t_DAh

t_HCLK× (WST1 + 1)

CSn to DQMn assert delay time

WRn deassert to DQMn deassert time

WRn deassert to DA transition time

0

t_HCLK

t_ADs

t_ADh

AD

t_CSh

CSn

t_WRd

t_WRpw

WRn

RDn

t_DQMd

t_DQMh

DQMn

t_DAh

DA

WAIT

Figure 7. Static Memory Single Word Write Cycle Timing Measurement

20

DS667PP3

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ARM9 SOC with Ethernet, USB, Display and Touchscreen

Static Memory 32-bit Read on 8-bit External Bus

Parameter

Symbol

t_ADs

Min

Typ

Max

Unit

t_HCLK

AD setup to RDn assert time

-

ns

t_AD1

t_HCLK× (WST1 + 1)

t_HCLK× (WST1 + 2)

t_HCLK× 2

RDn assert to Address 1 transition time

Address 2 assert time

t_AD2

t_AD3

Address 3 assert time

t_AD4

AD transition to RDn deassert time

AD hold from RDn deassert time

RDn assert time

t_ADh

t_RDpwL

t_RDd

t_HCLK× (4 × WST1 + 5)

CSn assert to RDn assert delay time

CSn deassert to RDn deassert delay time

CSn assert to DQMn assert delay time

CSn deassert to DQMn deassert delay time

DA setup to AD transition time

DA to RDn setup time

0

t_RDh

0

t_DQMd

t_DQMh

t_DAs1

t_DAs2

t_DAh1

t_DAh2

0

6

t_HCLK+ 6

AD transition to DA transition hold time

RDn deassert to DA transition hold time

0

t_ADs

t_AD1

t_AD2

t_AD3

t_AD4

t_ADh

AD

CSn

WRn

RDn

t_RDd

t_RDh

t_RDPwL

t_DQMd

t_DQMh

DQMn

DA

t_DAh

1

t_DAh1

t_DAh2

1

t_DAs1

t_DAs2

WAIT

Figure 8. Static Memory Multiple Word Read 8 Bit Cycle Timing Measurement

DS667PP3

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EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Static Memory 32-bit Write on 8-bit External Bus

Parameter

Symbol

t_ADs

Min

Typ

t_HCLK

Max

Unit

AD setup to WRn assert time

WRn deassert to AD transition time

AD hold from WRn deassert time

CSn hold from WRn deassert time

CSn to WRn assert delay time

WRn assert time

-

ns

t_ADd

t_HCLK

t_ADh

t_HCLK× 3

t_HCLK

t_CSh

t_WRd

0

t_WRpwL

t_WRpwH

t_DQMd

t_DQMpwL

t_DQMpwH

t_DAh

t_HCLK× (WST1 + 1)

t_HCLK× 2

WRn deassert time

CSn to DQMn assert delay time

DQMn assert time

0

t_HCLK× (WST1 + 1)

t_HCLK× 2

DQMn deassert time

t_HCLK

WRn/DQMn deassert to DA transition time

t_ADs

t_ADd

t_ADh

AD

CSn

t_CSh

t_{W Rd}

t_{W RpwL}

WRn

t_{W RpwH}

RDn

t_DQMd

t_DQMpwL

DQMn

t_DQMpwH

DA

t_DAh

WAIT

Figure 9. Static Memory Multiple Word Write 8 bit Cycle Timing Measurement

22

DS667PP3

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ARM9 SOC with Ethernet, USB, Display and Touchscreen

Static Memory 32-bit Read on 16-bit External Bus

Parameter

Symbol

t_ADs

Min

Typ

t_HCLK

Max

Unit

AD setup to RDn assert time

RDn assert to AD transition time

AD transition to RDn deassert time

AD hold from RDn deassert time

RDn assert time

-

ns

t_ADd1

t_ADd2

t_ADh

t_HCLK× (WST1 + 1)

t_HCLK× (WST1 + 2)

t_HCLK× 2

t_RDpwL

t_RDd

t_HCLK× (2 × WST1 + 3)

CSn to RDn assert delay time

CSn to RDn deassert delay time

CSn to DQMn assert delay time

CSn to DQMn deassert delay time

DA to ADsetup time

0

t_RDh

0

t_DQMd

t_DQMh

t_DAs1

t_DAs2

t_DAh1

t_DAh2

0

6

t_HCLK+ 6

DA to RDn setup time

AD transition to DA transition hold time

RDn deassert to DA transition hold time

0

t_ADs

t_ADd1

t_ADd2

t_ADh

AD

CSn

WRn

t_RDd

t_RDh

t_RDpwl

RDn

t_DQMh

t_DQMd

DQMn

t_DAh2

t_DAs1

t_DAh1

t_DAs2

DA

WAIT

Figure 10. Static Memory Multiple Word Read 16 Bit Cycle Timing Measurement

DS667PP3

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EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Static Memory 32-bit Write on 16-bit External Bus

Parameter

Symbol

t_ADs

Min

Typ

t_HCLK

Max

Unit

AD setup to WRn assert time

WRn deassert to AD transition time

AD hold from WRn deassert time

CSn hold from WRn deassert time

CSn to WRn assert delay time

WRn assert time

-

ns

t_ADd

t_HCLK

t_ADh

2 × t_HCLK

t_HCLK

t_CSh

t_WRd

0

t_WRpwL

t_WRpwH

t_DQMd

t_DQMpwL

t_DQMpwH

t_DAh1

t_HCLK× (WST1 + 1)

t_HCLK× 2

WRn deassert time

CSn to DQMn assert delay time

DQMn assert time

0

t_HCLK× (WST1 + 1)

t_HCLK× 2

t_HCLK

DQMn deassert time

WRn/DQMn deassert to DA transition time

t_DAh2

t_HCLK

t_ADs

t_ADd

t_ADh

AD

CSn

t_CSh

t_WRd

t_WRpwL

WRn

t_WRpwH

RDn

t_DQMd

t_DQpwL

DQMn

t_DQpwH

t_DAh1

t_DAh2

DA

WAIT

Figure 11. Static Memory Multiple Word Write 16 bit Cycle Timing Measurement

24

DS667PP3

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Static Memory Burst Read Cycle

Parameter

Symbol

t_ADd1

t_ADd2

t_ADh

Min

Typ

t_HCLK× (WST1 + 1)

t_HCLK× (WST2 + 1)

t_HCLK× 2

Max Unit

CSn assert to Address 1 transition time

Address 2 assert time

-

0

-

ns

AD hold from CSn deassert time

CSn assert time

t_CSpw

t_RDd

t_HCLK× ((WST1 + 1) + 4(WST2 + 1))

CSn to RDn assert delay time

RDn assert time

0

t_RDpw

t_DQMd

t_DQMpw

t_DAs1

t_HCLK× ((WST1 + 1) + 4(WST2 + 1))

CSn to DQMn assert delay time

DQMn assert time

4

t_HCLK× ((WST1 + 1) + 4(WST2 + 1))

DA to AD setup time

6

t_DAs2

t_HCLK+ 6

DA to CSn setup time

t_DAh1

t_DAh2

AD transition to DA transition hold time

CSn deassert to DA transition hold time

0

Note: These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details.

t_ADd1

t_ADd2

t_ADh

AD

CSn

t_CSpw

WRn

RDn

t_RDd

t_RDpw

t_DQMd

t_DQMpw

DQMn

t_DAh1

t_DAh2

DA

t_DAs1

t_DAs2

WAIT

Figure 12. Static Memory Burst Read Cycle Timing Measurement

DS667PP3

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EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Static Memory Single Read Wait Cycle

Parameter

Symbol

t_WAITd

Min

Typ

Max

t_HCLK× (WST1 - 2)

t_HCLK× 510

Unit

CSn assert to WAIT time

-

ns

t_WAITpw

t_CSnd

t_HCLK× 2

t_HCLK× 3

WAIT assert time

t_HCLK× 5

WAIT to CSn deassert delay time

AD

CSn

WRn

RDn

DQMn

DA

t_WAITd

t_CSnd

t_WAITpw

WAIT

Figure 13. Static Memory Single Read Wait Cycle Timing Measurement

26

DS667PP3

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ARM9 SOC with Ethernet, USB, Display and Touchscreen

Static Memory Single Write Wait Cycle

Parameter

Symbol

t_WRd

Min

Typ

Max

t_HCLK× 4

Unit

t_HCLK× 2

WAIT to WRn deassert delay time

CSn assert to WAIT time

-

ns

t_WAITd

t_WAITpw

t_CSnd

t_HCLK× (WST1 - 2)

t_HCLK× 510

t_HCLK× 5

-

t_HCLK× 2

t_HCLK× 3

WAIT assert time

WAIT to CSn deassert delay time

AD

CSn

t_WRd

WRn

RDn

DQMn

DA

t_WAITd

t_CSnd

t_WAITpw

WAIT

Figure 14. Static Memory Single Write Wait Cycle Timing Measurement

DS667PP3

27

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Static Memory Turnaround Cycle

Parameter

Symbol

Min

Typ

Max

Unit

t_BTcyc

t_HCLK× (IDCY+1)

CSnX deassert to CSnY assert time

-

ns

Note: X and Y represent any two chip select numbers.

t_BTcyc

AD

X

CSn0

Y

CSn1

WRn

RDn

DQMn

DA

WAIT

Figure 15. Static Memory Turnaround Cycle Timing Measurement

28

DS667PP3

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Ethernet MAC Interface

Min

Typ

Max

Parameter

Symbol

Unit

10 Mbit 100 Mbit 10 Mbit 100 Mbit 10 Mbit 100 Mbit

mode

t_{TX_per}

t_{TX_high}

t_{TX_low}

t_TXd

TXCLK cycle time

-

14

0

400

200

10

-

40

20

10

-

26

25

5

ns

TXCLK high time

140

0

260

TXCLK low time

260

TXCLK to signal transition delay time

TXCLK rise/fall time

RXCLK cycle time

25

t_TXrf

-

5

t_{RX_per}

t_{RX_high}

t_{RX_low}

t_RXs

-

400

200

-

40

20

-

RXCLK high time

140

10

-

14

10

-

260

26

-

RXCLK low time

260

RXDVAL/RXERR setup time

RXDVAL/RXERR hold time

RXCLK rise/fall time

MDC cycle time

-

t_RXh

-

t_RXrf

-

5

-

5

t_{MDC_per}

t_{MDC_high}

t_{MDC_low}

t_MDCrf

t_MDIOs

t_MDIOh

400

160

-

400

160

-

MDC high time

-

MDC low time

-

MDC rise/fall time

-

5

-

5

MDIO setup time (STA sourced)

MDIO hold time (STA sourced)

10

15

-

MDC to MDIO signal transition delay time

(PHY sourced)

t_MDIOd

-

300

ns

STA - Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer

(PHY) interface to the wireless medium.

PHY - Ethernet physical layer interface.

DS667PP3

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EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

t_{TX_high}

t_{TX_low}

t_TXrf

TXCLK

t_TXd

t_{TX_per}

MII_TXD[3:0]/

TXEN/

TXERR

t_{RX_low}

t_{RX_high}

t_RXrf

RXCLK

t_RXh

t_{RX_per}

MII_RXD[3:0]/

RXDVAL/

RXERR

t_RXs

t_MDCrf

MDC

t_{MDC_high}

t_{MDC_low}

t_MDIOs

t_MDIOh

MDIO

(Sourced

by STA)

t_{MDC_per}

MDC

MDIO

(Sourced

by PHY)

t_MDIOd

Figure 16. Ethernet MAC Timing Measurement

30

DS667PP3

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ARM9 SOC with Ethernet, USB, Display and Touchscreen

Audio Interface

The following table contains the values for the timings of each of the SPI modes.

Parameter

Symbol

t_{clk_per}

t_{clk_high}

t_{clk_low}

t_clkrf

Min

Typ

Max

Unit

SCLK cycle time

SCLK high time

SCLK low time

-

tspix_clk

-

ns

(tspix_clk)/2

SCLK rise/fall time

4.5 / 1.5

t_DMd

Data from master valid delay time

Data from master setup time

Data from master hold time

Data from slave valid delay time

Data from slave setup time

Data from slave hold time

2

t_DMs

20

40

2

t_DMh

t_DSd

t_DSs

20

40

t_DSh

Note:

tspix_clk is programmable by the user.

DS667PP3

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EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Texas Instruments’ Synchronous Serial Format

t_{clk_per}

t_{clk_high}

t_clkrf

SCLK

t_{clk_low}

SFRM

SSPTXD/

MSB

LSB

SSPRXD

4 to 16 bits

Figure 17. SPI Single Transfer Timing Measurement

Microwire

t_{clk_high}

t_{clk_per}

t_clkrf

SCLK

SFRM

t_{clk_low}

LSB

MSB

SSPTXD

SSPRXD

8-bit control

0

MSB

LSB

4 to 16 bits output data

Figure 18. Microwire Frame Format, Single Transfer

32

DS667PP3

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Motorola SPI

t_{clk_per}

t_{clk_high}

t_clkrf

SCLK

(SPO=0)

t_{clk_low}

SCLK

(SPO=1)

t_DMs

t_DMh

SSPTXD

from master

MSB

LSB

t_DMd

t_DSdt_DSs

t_DSd

SSPRXD

from slave

MSB

LSB

SFRM

Figure 19. SPI Format with SPH=1 Timing Measurement

DS667PP3

33

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

2

Inter-IC Sound - I S

Parameter

Symbol

Min

Typ

Max

Unit

t_{clk_per}

t_{clk_high}

t_{clk_low}

t_clkrf

t_{i2s_clk}

SCLK cycle time

SCLK high time

SCLK low time

-

ns

(t_{i2s_clk}) / 2

SCLK rise/fall time

4

1.5

20

10

4

t_LRs

SCLK to LRCLK assert delay time

LRCLK from SCLK assert hold time

SDI to SCLK deassert setup time

SDI from SCLK deassert hold time

SCLK to SDO assert delay time

SDO from SCLK assert hold time

t_LRh

t_SDIs

t_SDIh

t_SDOd

t_SDOh

4

Note:

t_{i2s_clk}is programmable by the user.

t_{clk_per}

t_clkrf

t_{clk_high}

t_{clk_low}

SCLK

t_LRh

t_LRs

LRCLK

t_SDOs

t_SDOh

SDO/SDI

t_SDIs

t_SDIh

Figure 20. Inter-IC Sound (I²S) Timing Measurement

34

DS667PP3

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ARM9 SOC with Ethernet, USB, Display and Touchscreen

AC’97

Parameter

Symbol

t_{clk_per}

t_{clk_high}

t_{clk_low}

t_clkr

Min

Typ

Max

Unit

ABITCLK input cycle time

ABITCLK input high time

ABITCLK input low time

ABITCLK input rise time

ABITCLK input fall time

-

36

2

81.4

-

45

6

ns

-

t_clkf

2

-

6

t_s

ASDI setup to ABITCLK falling

ASDI hold after ABITCLK falling

ASDI input rise/fall time

10

2

23

53

-

t_h

-

t_rfin

6

ABITCLK rising to ASDO/ASYNC valid, C_L= 55 pF

ASYNC/ASDO rise time, C_L= 55 pF

t_co

2

-

15

6

t_rout

2

-

ASYNC/ASDO fall time, C_L= 55 pF

t_fout

2

-

6

t_{clk_per}

t_{clk_high}

t_{clk_low}

ABITCLK

t_clkrf

f

r

t_h

t_s

t_rfin

ASDI

ASDO

t

/t

_foutt_rf_f_o_o_u_u_t_t

t_co

ASYNC

t

t_rout

t_rf_f_o_o_u_u_t_t

rfout

Figure 21. AC ‘97 Configuration Timing Measurement

DS667PP3

35

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

LCD Interface

Parameter

Symbol

t_clkr

Min

Typ

Max

Unit

SPCLK rising time

-

5

-

ns

t_clkf

SPCLK falling time

5

1

t_CD

SPCLK rising edge to control signal transition time

SPCLK rising edge to data transition time

SPCLK falling edge to control signal transition time

SPCLK falling edge to data transition time

Data valid time

t_DD

0

t_CDi

(t_SPCLK)/2

t_SPCLK

t_DDi

t_Dv

t_clkr

t_clkf

SPCLK

HSYNC/

V_CSYNC/

BLANK/

t_CD

BRIGHT

t_DD

P [17:0]

t_Dv

t_clkr

t_clkf

SPLCK

t_CDi

HSYNC/

V_CSYNC/

BLANK/

BRIGHT

t_DDi

P [17:0]

t_Dv

Figure 22. LCD Timing Measurement

36

DS667PP3

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

ADC

Parameter

Comment

Value

Units

No missing codes

Range of 0 to 3.3 V

Resolution

50K counts (approximate)

Integral non-linearity

Offset error

0.01%

15

mV

Full scale error

0.2%

ADIV = 0

ADIV = 1

3750

925

Samples per second

Maximum sample rate

ADIV = 0

ADIV = 1

500

2

µs

ms

Channel switch settling time

Noise (RMS) - typical

120

µV

Note:

ADIV refers to bit 16 in the KeyTchClkDiv register.

ADIV = 0 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 4.

ADIV = 1 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 16.

61A8

0000

FFFF

9E58

0

Vref/2

Vref

A/D Converter Transfer Function

(approximately 25,000 counts)

Figure 23. ADC Transfer Function

Using the ADC:

This ADC has a state-machine based conversion engine that automates the conversion process. The initiator for a

conversion is the read access of the TSXYResult register by the CPU. The data returned from reading this register

contains the result as well as the status bit indicating the state of the ADC. However, this peripheral requires a delay

between each successful conversion and the issue of the next conversion command, or else the returned value of

successive samples may not reflect the analog input. Since the state of the ADC state machine is returned through the

same channel used to initiate the conversion process, there must be a delay inserted after every complete conversion.

Note that reading TSXYResult during a conversion will not affect the result of the ongoing process.

The following is a recommended procedure for safely polling the ADC from software:

1. Read the TSXYResult register into a local variable to initiate a conversion.

2. If the value of bit 31 of the local variable is '0', repeat step 1.

3. Delay long enough to meet the maximum sample rate as shown above.

4. Mask the local variable with 0xFFFF to remove extraneous data.

5. If signed mode is used, do a sign extend of the lower halfword.

6. Return the sampled value.

DS667PP3

37

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

JTAG

Parameter

Symbol

t_{clk_per}

t_{clk_high}

t_{clk_low}

t_JPs

Min

Max

Units

TCK clock period

100

50

20

45

-

ns

TCK clock high time

TCK clock low time

-

TMS/TDI to clock rising setup time

Clock rising to TMS/TDI hold time

JTAG port clock to output

-

t_JPh

-

t_JPco

30

t_JPzx

JTAG port high impedance to valid output

JTAG port valid output to high impedance

-

t_JPxz

-

TMS

TDI

t_{clk_per}

t_JPs

t_JPh

t_{clk_high}

t_{clk_low}

TCK

TDO

t_JPzx

t_JPco

t_JPxz

Figure 24. JTAG Timing Measurement

38

DS667PP3

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

272 Pin TFBGA Package Outline

272 TFBGA Diagram

Figure 25. 272 Pin TFBGA Diagram

D

0.600 REF

E1

e

ddd

Øb

ddd

DS667PP3

39

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Table R. 272 Pin Diagram Dimensions

dimension in mm

NOM

dimension in inches

Symbol

MIN

MAX

MIN

NOM

MAX

A

A1

A2

b

1.35

0.23

1.40

0.28

1.45

0.33

0.053

0.009

0.026

0.014

0.0083

0.549

0.502

0.549

0.502

0.030

0.055

0.011

0.028

0.016

0.0102

0.551

0.504

0.551

0.504

0.031

0.057

0.013

0.030

0.018

0.0122

0.553

0.506

0.553

0.506

0.033

0.004

0.65

0.70

0.75

0.35

0.40

0.45

c

0.21

0.26

0.31

D

13.95

12.75

13.95

12.75

0.75

14.00

12.80

14.00

12.80

0.80

14.05

12.85

14.05

12.85

0.85

D3

E

E3

e

ddd

0.10

Note: 1. Controlling Dimension: Millimeter.

2. Primary Datum C and seating plane are defined by the spherical crowns of the solder balls.

3. Dimension b is measured at the maximum solder ball diameter, parallel to Primary Datum C.

4. There shall be a minimum clearance of 0.25 mm between the edge of the solder ball and the body edge.

5. Reference Document: JEDEC MO-151, BAL-2

272 Pin TFBGA Pinout (Bottom View)

The following table shows the 272 pin TFBGA pinout. (For better understanding, compare the coordinates on the x and

y axis on Figure 26, "272 Pin TFBGA Pinout", on page 41 with Figure 25, "272 Pin TFBGA Diagram", on page 39.

• VDD_core is vddc.

• VDD_ring is vddr.

• GND_core is gndc.

• GND_ring is gndr.

40

DS667PP3

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Pin List

The following Thin-profile Fine-pitch Ball Grid Array (TFBGA) ball assignment table is sorted in order of ball.

Ball

Signal

Ball

Signal

Ball

Signal

Ball

Signal

A1

A2

CSn[1]

CSn[7]

E1

E2

SDCSn[2]

SDWEN

DA[22]

AD[3]

J10

J12

J13

J14

J15

J16

J17

K1

gndc

vddc

P1

P2

SPCLK

P[10]

A3

SDCLKEN

DA[31]

E3

vddr

P3

P[11]

A4

E4

COL[5]

COL[6]

CSn[0]

COL[3]

AD[4]

P4

P[3]

A5

DA[29]

E5

DA[15]

AD[21]

DA[17]

vddr

P5

AD[15]

AD[13]

AD[12]

DA[2]

A6

DA[27]

E6

P6

A7

HGPIO[2]

RDn

E7

P7

A8

E8

P8

A9

MIIRXD[3]

RXDVAL

MIITXD[1]

CRS

E9

vddr

K2

DA[12]

DA[10]

DA[11]

vddr

P9

AD[8]

A10

A11

A12

A13

A14

A15

A16

A17

B1

E10

E11

E12

E13

E14

E15

E16

E17

F1

vddr

K3

P10

P11

P12

P13

P14

P15

P16

P17

R1

TCK

MIIRXD[0]

TXERR

EGPIO[2]

EGPIO[4]

EGPIO[3]

sXp

K4

BOOT[1]

EEDAT

GRLED

RDLED

GGPIO[2]

RXD[1]

RXD[2]

P[9]

K5

FGPIO[7]

FGPIO[0]

WAITn

K6

gndr

K8

gndc

K9

gndc

USBm[2]

ASDI

K10

K12

K13

K14

K15

K16

K17

L1

gndc

sXm

vddc

AD[25]

RASn

COL[4]

PLL_VDD

COL[2]

COL[1]

COL[0]

DA[9]

B2

CSn[2]

F2

SDCSn[1]

SDCSn[0]

DQMn[3]

AD[5]

R2

HSYNC

P[6]

B3

CSn[6]

F3

R3

B4

AD[20]

F4

R4

P[5]

B5

DA[30]

F5

R5

P[0]

B6

AD[18]

F6

gndr

R6

AD[14]

DA[4]

B7

HGPIO[3]

AD[17]

F7

gndr

L2

AD[2]

R7

B8

F8

gndr

L3

AD[1]

R8

DA[1]

B9

RXCLK

MIIRXD[1]

MIITXD[2]

TXEN

F9

vddc

L4

DA[8]

R9

DTRn

B10

B11

B12

B13

B14

B15

B16

B17

C1

F10

F11

F12

F13

F14

F15

F16

F17

G1

G2

G3

G4

G5

G6

G12

G13

vddc

L5

BLANK

gndr

R10

R11

R12

R13

R14

R15

R16

R17

T1

TDI

gndr

L6

BOOT[0]

ASYNC

SSPTX[1]

PWMOUT

USBm[0]

ABITCLK

USBp[0]

NC

EGPIO[7]

EGPIO[5]

ADC_GND

EGPIO[6]

sYm

L12

L13

L14

L15

L16

L17

M1

M2

M3

M4

M5

M6

M7

M8

gndr

FGPIO[5]

EGPIO[15]

USBp[2]

ARSTn

ADC_VDD

AD[23]

ROW[7]

ROW[5]

PLL_GND

XTALI

XTALO

BRIGHT

AD[0]

sYp

DQMn[0]

CASn

C2

DA[26]

T2

NC

C3

CSn[3]

DA[21]

AD[22]

vddr

DQMn[1]

DQMn[2]

P[17]

T3

V_CSYNC

P[7]

C4

DA[25]

T4

C5

AD[24]

T5

P[2]

C6

AD[19]

gndr

T6

DA[7]

C7

HGPIO[5]

WRn

gndr

T7

AD[11]

AD[9]

C8

EGPIO[9]

vddc

T8

42

DS667PP3

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Ball

Signal

Ball

Signal

Ball

Signal

Ball

Signal

C9

C10

C11

C12

C13

C14

C15

C16

C17

D1

MDIO

MIIRXD[2]

TXCLK

MIITXD[0]

CLD

G14

G15

G16

G17

H1

EGPIO[10]

EGPIO[11]

RTCXTALO

RTCXTALI

DA[18]

DA[20]

DA[19]

DA[16]

vddr

M9

M10

M11

M12

M13

M14

M15

M16

M17

N1

vddc

gndr

T9

T10

T11

T12

T13

T14

T15

T16

T17

U1

DSRn

TMS

gndr

ROW[6]

ROW[4]

ROW[1]

ROW[0]

ROW[3]

ROW[2]

P[14]

SFRM[1]

INT[2]

INT[0]

USBp[1]

NC

EGPIO[13]

TRSTn

Xp

H2

H3

H4

Xm

H5

NC

SDCSn[3]

DA[23]

H6

vddc

NC

D2

H8

gndc

N2

P[16]

U2

NC

D3

SDCLK

DA[24]

H9

gndc

N3

P[15]

U3

P[8]

D4

H10

H12

H13

H14

H15

H16

H17

J1

gndc

N4

P[13]

U4

P[4]

D5

HGPIO[7]

HGPIO[6]

DA[28]

gndr

N5

P[12]

U5

P[1]

D6

vddr

N6

DA[5]

vddr

U6

DA[6]

DA[3]

AD[10]

DA[0]

TDO

D7

EGPIO[8]

PRSTn

COL[7]

RSTOn

AD[6]

N7

U7

D8

HGPIO[4]

AD[16]

N8

vddr

U8

D9

N9

vddr

U9

D10

D11

D12

D13

D14

D15

D16

D17

MDC

N10

N11

N12

N13

N14

N15

N16

N17

vddr

U10

U11

U12

U13

U14

U15

U16

U17

RXERR

MIITXD[3]

EGPIO[12]

EGPIO[1]

EGPIO[0]

Ym

EECLK

ASDO

CTSn

RXD[0]

TXD[0]

TXD[1]

TXD[2]

NC

J2

DA[14]

AD[7]

SCLK[1]

SSPRX[1]

INT[1]

RTSn

USBm[1]

NC

J3

J4

DA[13]

vddr

J5

J6

vddc

Yp

J8

gndc

DS667PP3

43

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

The following section focuses on the EP9307 pin signals

•

P - Power pad

G - Ground pad

I - Pin is an input only

from two viewpoints

- the pin usage and pad

characteristics, and the pin multiplexing usage. The first

table (Table S) is a summary of all the EP9307 pin

signals. The second table (Table T) illustrates the pin

signal multiplexing and configuration options.

I/O - Pin is input/output

4mA - Pin is a 4mA output driver

8mA - Pin is an 8mA output driver

12mA - Pin is an 12mA output driver

Table S is a summary of the EP9307 pin signals, which

illustrates the pad type and pad pull type (if any). The

symbols used in the table are defined as follows. (Note: A

blank box means Not Applicable (NA) or, for Pull Type,

No Pull (NP).)

See the text description for additional information about

bi-directional pins.

Under the Pull Type Column:

Under the Pad Type column:

•

PU - Resistor is a pull up to the RVDD supply

PD - Resistor is a pull down to the RGND supply

•

A - Analog pad

.

Table S. Pin Descriptions (Continued)

Table S. Pin Descriptions

Pad

Type

Pull

Type

Pin Name

Block

Description

Pad

Type

Pull

Type

Pin Name

TCK

Block

Description

Vertical or composite synchronization/frame

pulse out

V_CSYNC

Raster

8ma

PU

JTAG

I

PD JTAG clock in

PD JTAG data in

TDI

BLANK

BRIGHT

PWMOUT

Xp, Xm

Yp, Ym

sXp, sXm

sYp, sYm

VDD_ADC

GND_ADC

COL[7:0]

ROW[7:0]

USBp[2:0]

USBm[2:0]

TXD0

Raster

PWM

8ma

PU Composite blanking signal out

TDO

JTAG

4ma

I

-

JTAG data out

4ma

-

PWM brightness control out

Pulse width modulator output

Touchscreen ADC X axis

TMS

JTAG

PD JTAG test mode select

PD JTAG reset

8ma

TRSTn

JTAG

I

ADC

A

-

BOOT[1:0]

XTALI

System

PLL

I

PD Boot mode select in

ADC

A

Touchscreen ADC Y axis

A

-

Main oscillator input

ADC

A

Touchscreen ADC X axis feedback

Touchscreen ADC Y axis feedback

Touchscreen ADC power, 3.3V

Touchscreen ADC ground

XTALO

VDD_PLL

GND_PLL

RTCXTALI

RTCXTALO

WRn

PLL

A

Main oscillator output

Main oscillator power, 1.8V

Main oscillator ground

RTC oscillator input

ADC

A

PLL

P

ADC

P

PLL

G

ADC

G

RTC

A

Key

8ma

PU Key matrix column inputs

PU Key matrix row outputs

RTC

A

RTC oscillator output

SRAM Write strobe out

SRAM Read/OE strobe out

Key

8ma

EBUS

SDRAM

Raster

4ma

I

USB

A

-

USB positive signals

USB negative signals

Transmit out

RDn

USB

A

WAITn

PU SRAM Wait in

UART1

UART2

UART3

EMAC

4ma

AD[25:0]

DA[31:0]

CSn[3:0]

CSn[7:6]

DQMn[3:0]

SDCLK

SDCLKEN

SDCSn[3:0]

RASn

8ma

4ma

8ma

4ma

8ma

4ma

12ma

8ma

-

Shared Address bus out

RXD0

I

PU Receive in

PU Shared Data bus in/out

PU Chip select out

CTSn

I

PU Clear to send/transmit enable

PU Data set ready/Data Carrier Detect

DSRn

I

DTRn

4ma

-

Data Terminal Ready output

Ready to send

-

Shared data mask out

SDRAM clock out

RTSn

4ma

TXD1

4ma

Transmit/IrDA output

SDRAM clock enable out

SDRAM chip selects out

SDRAM RAS out

RXD1

I

PU Receive/IrDA input

Transmit

PU Receive

Management data clock

TXD2

4ma

-

RXD2

I

CASn

SDRAM CAS out

MDC

4ma

SDWEn

P[17:0]

SDRAM write enable out

MDIO

4ma

PU Management data input/output

PD Receive clock in

PU Pixel data bus out

RXCLK

MIIRXD[3:0]

RXDVAL

I

SPCLK

HSYNC

PU Pixel clock in/out

PD Receive data in

PU Horizontal synchronization/ line pulse out

PD Receive data valid

44

DS667PP3

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Table S. Pin Descriptions (Continued)

Pad

Type

Pull

Type

Pin Name

RXERR

Block

Description

EMAC

LED

I

4ma

I

PD Receive data error

PU Transmit clock in

PD Transmit data out

PD Transmit enable

PD Transmit error

PD Carrier sense

TXCLK

MIITXD[3:0]

TXEN

4ma

I

TXERR

CRS

CLD

I

PU Collision detect

GRLED

RDLED

EECLK

EEDAT

ABITCLK

ASYNC

ASDI

12ma

4ma

8ma

I

-

Green LED

Red LED

LED

EEPROM

AC97

SPI1

PU EEPROM/Two-wire Interface clock

PU EEPROM/Two-wire Interface data

PD AC97 bit clock

PD AC97 frame sync

PD AC97 Primary input

PU AC97 output

ASDO

8ma

I

ARSTn

SCLK1

SFRM1

SSPRX1

SSPTX1

INT[2:0]

PRSTn

RSTOn

EGPIO[15]

EGPIO[13:0]

FGPIO[7, 5, 0]

GGPIO[2]

HGPIO[7:2]

vddc

-

AC97 reset

PD SPI bit clock

PD SPI Frame Clock

PD SPI input

SPI1

8ma

I

-

SPI output

INT

PD External interrupts

PU Power on reset

Syscon

GPIO

I

4ma

-

User Reset in out - open drain

I/O, 4ma PU Enhanced GPIO

I/O, 8ma PU GPIO

GPIO

I/O, 8ma PU GPIO

GPIO

I/O, 8ma PU GPIO

Power

Ground

P

G

-

Digital power, 1.8V

Digital power, 3.3V

Digital ground

vddr

gndc

gndr

Digital ground

DS667PP3

45

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Table T illustrates the pin signal multiplexing and configuration options.

Table T. Pin Multiplex Usage Information

Physical

Pin Name

Description

Multiplex signal name

COL[7:0]

ROW[7:0]

EGPIO[0]

EGPIO[1]

EGPIO[2]

EGPIO[3]

EGPIO[4]

EGPIO[5]

EGPIO[6]

EGPIO[7]

EGPIO[8]

EGPIO[9]

EGPIO[10]

EGPIO[11]

EGPIO[12]

EGPIO[13]

EGPIO[15]

ABITCLK

ASYNC

GPIO

GPIO Port D[7:0]

GPIO Port C[7:0]

RI

GPIO

Ring Indicator Input

1Hz clock monitor

DMA request

CLK1HZ

DMARQ

HDLCCLK1

SDO1

HDLC Clock

I2S Transmit Data 1

I2S Receive Data 1

I2S Transmit Data 2

DMA Request 0

DMA Acknowledge 0

DMA EOT 0

SDI1

SDO2

DREQ0

DACK0

DEOT0

DREQ1

DACK1

DEOT1

SDI2

DMA Request 1

DMA Acknowledge 1

DMA EOT 1

I2S Receive Data 2

Device active / present

I2S Serial clock

I2S Frame Clock

I2S Transmit Data 0

I2S Receive Data 0

I2S Master clock

I2S Serial clock

I2S Frame Clock

I2S Transmit Data 0

I2S Receive Data 0

DASP

SCLK

LRCK

ASDO

SDO0

ASDI

SDI0

ARSTn

MCLK

SCLK1

SCLK

SFRM1

LRCK

SSPTX1

SSPRX1

SDO0

SDI0

46

DS667PP3

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

Acronyms and Abbreviations

Term

Definition

The following tables list abbreviations and acronyms

used in this data sheet.

OHCI

Open Host Controller Interface

PHY

PIO

Ethernet PHYsical layer interface

Programmed I/O

Term

Definition

ADC

Analog-to-Digital Converter

RISC

SDMI

Reduced Instruction Set Computer

Secure Digital Music Initiative

ALT

Alternative

AMBA

ATAPI

Advanced Micro-controller Bus Architecture

ATA Packet Interface

SDRAM Synchronous Dynamic RAM

SPI

Serial Peripheral Interface

CODEC COder/DECoder

SRAM

Static Random Access Memory

CRC

DAC

DMA

Cyclic Redundancy Check

Station - Any device that contains an IEEE 802.11

conforming Medium Access Control (MAC) and physical

layer (PHY) interface to the wireless medium

STA

Digital-to-Analog Converter

Direct-Memory Access

TFT

TLB

USB

Thin Film Transistor

EEPROM Electronically Erasable Programmable Read Only Memory

Translation Lookaside Buffer

Universal Serial Bus

EMAC

EBUS

FIFO

FIQ

Ethernet Media Access Controller

External Bus

Units of Measurement

First In/First Out

Fast Interrupt Request

Flash memory

Symbol

Unit of Measure

FLASH

GPIO

HDLC

I/F

degree Celsius

°C

General Purpose I/O

High-level Data Link Control

Interface

Hz

Hertz = cycle per second

Kilobits per second

Kilobyte

Kbps

Kbyte

KHz

Mbps

MHz

µA

I²S

KiloHertz = 1000 Hz

Megabits per second

MegaHertz = 1,000 KiloHertz

Inter-IC Sound

IC

Integrated Circuit

ICE

In-Circuit Emulator

microAmpere = 10^-6Ampere

IDE

Integrated Drive Electronics

Institute of Electronics and Electrical Engineers

Infrared Data Association

microsecond = 1,000 nanoseconds = 10^-6seconds

milliAmpere = 10^-3Ampere

µs

IEEE

IrDA

IRQ

ISO

JTAG

LFSR

MII

mA

ms

mW

ns

millisecond = 1,000 microseconds = 10^-3seconds

milliWatt = 10^-3Watts

Standard Interrupt Request

International Standards Organization

Joint Test Action Group

nanosecond = 10^-9seconds

picoFarad = 10^-12Farads

pF

V

Linear Feedback Shift Register

Media Independent Interface

Memory Management Unit

Volt

W

Watt

MMU

DS667PP3

47

EP9307

ARM9 SOC with Ethernet, USB, Display and Touchscreen

ORDERING INFORMATION

The order numbers for the device are:

EP9307-CR

EP9307-CRZ

EP9307-IR

0°C to +70°C

-40°C to +85°C

272 pin TFBGA

Lead Free

EP9307-IRZ

EP9307 — CRZ

Lead Material:

Z = Lead Free

Part Number

Package Type:

R = 272 pin TFBGA

Product Line:

Embedded Processor

Temperature Range:

C = Commercial

E = Extended Operating Version

I = Industrial Operating Version

Note: Go to the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative.

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find one nearest you go to www.cirrus.com

IMPORTANT NOTICE

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries

("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS

IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that infor-

mation being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including

those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this infor-

mation as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by

furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual

property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within

your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribu-

tion, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY

OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIR-

CRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL AP-

PLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES).

INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND

MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICU-

LAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR

PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS,

DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY

RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this doc-

ument may be trademarks or service marks of their respective owners.

Microsoft and Windows are registered trademarks of Microsoft Corporation.

Microwire is a trademark of National Semiconductor Corp. National Semiconductor is a registered trademark of National Semiconductor Corp.

Texas Instruments is a registered trademark of Texas Instruments, Inc.

Motorola is a registered trademark of Motorola, Inc.

LINUX is a registered trademark of Linus Torvalds.

48

DS667PP3


型号：	EP9307
厂家：	CIRRUS LOGIC
描述：	ARM9 SOC WITH ETHERNET USB DISPLAY AND TOUCHSCREEN 与以太网USB显示和触摸屏ARM9 SOC 微控制器和处理器微处理器以太网以太网：16GBASE-T
文件：	总48页 (文件大小：716K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EP9307 [CIRRUS]

相关型号：

EP9307-CBZ

EP9307-CR

EP9307-CRZ

EP9307-ERZ

EP9307-IB

EP9307-IBZ

EP9307-IR

EP9307-IRZ

EP9308

EP9309

EP9310

EP9311