SA53 [CIRRUS]
Switching Amplifier; 开关放大器
| 型号： | SA53 |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | Switching Amplifier |
| 文件： | 总14页 (文件大小：727K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P r o d u c t I n n o v a t i o n F r o m
SA53
Switching Amplifier
FEATURESꢀ
DESCRIPTION
The SA53 is a fully integrated switching amplifier de-
signed primarily to drive DC brush motors. Two inde-
pendent half bridges provide over 10 amperes peak
output current under microcontroller or DSC control.
Thermal and short circuit monitoring is provided, which
generates fault signals for the microcontroller to take
appropriate action. A block diagram is provided in Fig-
ure 1.
♦ Low Cost Intelligent Switching Amplifier
♦ Directly Connects to Most Embedded Micro-
controllers and Digital Signal Controllers
♦ Integrated Gate Driver Logic with Dead-time
Generation and Shoot-through Prevention
♦ Wide Power Supply Range (8.5 V To 60 V)
♦ Over 10A Peak Output Current per Phase
♦ 3A Continuous Output Current per Phase
♦ Independent Current Sensing for each Output
♦ User Programmable Cycle-by-cycle Current
Limit Protection
Additionally, cycle-by-cycle current limit offers user
programmable hardware protection independent of the
microcontroller. Output current is measured using an
innovative low loss technique. The SA53 is built using
a multi-technology process allowing CMOS logic con-
trol and complementary DMOS output power devices
on the same IC. Use of P-channel high side FETs en-
ables 60V operation without bootstrap or charge pump
circuitry.
♦ Over-Current and Over-Temperature Warning
Signals
APPLICATIONS
♦ Bidirectional DC Brush Motors
♦ 2 Unidirectional DC Brush Motors
♦ 2 Independent Solenoid Actuators
♦ Stepper Motors
The Power Quad surface mount package balances ex-
cellent thermal performance with the advantages of a
low profile surface mount package.
FIgUREꢀꢁ.ꢀBLOCKꢀDIAgRAm
VS
+
VDD
Vs 1
Vs 2
SC
TEMP
VDD
VDD
I1'
I2'
Fault
Logic
ILIM/DIS1
I1
I2
I1'
I2'
Gate
Control
DIS2
1t
Out 1
Out 2
Phase 1
1b
PWM
Signals
Control
Logic
2t
Phase 2
2b
SGND
SA53 Switching Amplifier
PGND 1
PGND 2
GND
Copyright © Cirrus Logic, Inc. 2009
mAYꢀ2009
ꢀ
APEX − SA53UREVA
(All Rights Reserved)
http://www.cirrus.com
P r o d u c t I n n o v a t i o n F r o m
SA53
ꢁ.ꢀChARACTERISTICSꢀANDꢀSPECIFICATIONS
ABSOLUTEꢀmAxImUmꢀRATINgS
Paraꢂeter
Syꢂbol
VS
min
maꢃ
60
Units
V
SUPPLY VOLTAGE
SUPPLY VOLTAGE
VDD
5.5
V
LOGIC INPUT VOLTAGE
(-0.5)
(VDD+0.5)
10
V
OUTPUT CURRENT, peak, 10ms
POWER DISSIPATION, avg, 25ºC
TEMPERATURE, solder, 10sec
TEMPERATURE, junction
(NOTE 2)
(NOTE 2)
IOUT
PD
A
100
W
TS
260
°C
°C
°C
°C
(NOTE 2)
TJ
150
TEMPERATURE RANGE, storage
OPERATING TEMPERATURE, case
TSTG
TA
−55
−40
125
125
SPECIFICATIONS
PARAmETER
LOgIC
TESTꢀCONDITIONS (Note 1)
UNITS
mIN
TYP
mAx
INPUT LOW
1
V
V
V
V
INPUT HIGH
1.8
OUTPUT LOW
OUTPUT HIGH
0.3
3.7
OUTPUT CURRENT
(SC, Temp, ILIM/DIS1)
50
mA
POWERꢀSUPPLY
VS
UVLO
4.5
50
60
V
V
V
VS UNDERVOLTAGE LOCKOUT, (UVLO)
8.3
VDD
5.5
30
20 kHz (One phase switching at
50% duty cycle) , VS=50V, VDD=5V
SUPPLY CURRENT, VS
SUPPLY CURRENT, VDD
25
mA
mA
20 kHz (One phase switching at
50% duty cycle) , VS=50V, VDD=5V
5
6
CURRENTꢀLImIT
CURRENT LIMIT THRESHOLD (Vth)
Vth HYSTERESIS
3.75
100
V
mV
OUTPUT
CURRENT, CONTINUOUS
RISING DELAY, TD (RISE)
FALLING DELAY, TD (FALL)
DISABLE DELAY, TD (DIS)
ENABLE DELAY, TD (DIS)
RISE TIME, T (RISE)
25ºC Case Temperature
See Figure 10
See Figure 10
See Figure 10
See Figure 10
See Figure 11
3
A
270
270
200
200
50
ns
ns
ns
ns
ns
ns
FALL TIME, T (FALL)
See Figure 11
50
ON RESISTANCE SOURCING
(P-CHANNEL)
3A Load
3A Load
400
400
mΩ
mΩ
ON RESISTANCE
SINKING (N-CHANNEL)
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P r o d u c t I n n o v a t i o n F r o m
SA53
SPECIFICATIONS,ꢀcontinued
PARAmETER
ThERmAL
TESTꢀCONDITIONS (Note 1)
UNITS
mIN
TYP
mAx
THERMAL WARNING
135
40
ºC
ºC
THERMAL WARNING HYSTERESIS
RESISTANCE, junction to case
TEMPERATURE RANGE, case
Full temperature range
1.25
1.5
ºC/W
ºC
Meets Specifications
-40
85
NOTES:
1. (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Condi-
tions. Typical performance characteristics and specifications are derived from measurements taken
at typical supply voltages and TC = 25°C).
2. Long term operation at elevated temperature will result in reduced product life. De-rate internal power
dissipation to achieve high MTBF.
3. Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specified current rating or a junction temperature of 150°C.
FIgUREꢀ2.ꢀ64-pinꢀQFP,ꢀPackaꢄeꢀStyleꢀhQ
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P r o d u c t I n n o v a t i o n F r o m
SA53
VS SUPPLY CURRENT
CURRENT SENSE
VS SUPPLY CURRENT
10
25
20
15
10
5
180
160
140
120
100
80
125°C
25°C
1
60
ONE PHASE SWITCHING
FREQUENCY = 20kHz
50% DUTY CYCLE
40
ONE PHASE SWITCHING @
50% DUTY CYCLE; VS=50V
20
0
0
0.1
0.01
0
50 100 150 200 250 300
FREQUENCY (kHz)
10
20
30
40
50
60
0.1
1
10
VS SUPPLY VOLTAGE (V)
SENSE CURRENT (mA)
POWER DERATING
VDD SUPPLY CURRENT
VDD SUPPLY CURRENT
8
7.5
7
5
4.9
4.8
4.7
4.6
4.5
120
100
80
60
40
20
0
ONE PHASE SWITCHING
FREQUENCY = 20kHz
50% DUTY CYCLE
6.5
6
125°C
5.5
5
25°C
ONE PHASE SWITCHING @
50% DUTY CYCLE; VS=50V
4.5
4
10
20
VS SUPPLY VOLTAGE (V)
ON RESISTANCE - BOTTOM FET
0.8
30
40
50
60
0
50 100 150 200 250 300
FREQUENCY (kHz)
-40
0
40
80
120
CASE TEMPERATURE, TC
ON RESISTANCE - TOP FET
0.8
0.75 (P-Channel)
0.75 (N-Channel)
0.7
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.7
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
VS=11
VS=13
VS=15
VS=11
VS=13
VS=15
VS=17
VS>17
0.25
0.2
0.25
0.2
0.15
VS>22
0.15
0
1
2
3
4
5
6
7
8
9 10
0
1
2
3
4
5
6
7
8
9 10
IOUT,(A)
IOUT,(A)
DIODE FORWARD VOLTAGE - TOP FET
DIODE FORWARD VOLTAGE - BOTTOM FET
5
5
4
3
2
1
0
(P-Channel)
(N-Channel)
4
3
2
1
0
0.5
0.7
0.9
1.1
1.3
1.5
0.5
0.7
0.9
1.1
1.3
1.5
FORWARD VOLTAGE (V)
FORWARD VOLTAGE (V)
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P r o d u c t I n n o v a t i o n F r o m
SA53
FIgUREꢀ3.ꢀExTERNALꢀCONNECTIONS
OUT 2
NC
32
31
30
29
28
27
53
54
55
56
57
58
NC
VS
VS
VS
1
PGND 2
PGND 2
PGND 2
HS
1
1
NC
HS
HS
NC
2b
26
25
24
23
22
21
59
60
61
62
63
64
HS
TEMP
NC
NC
2t
DIS2
NC
NC
I1
TABLEꢀꢁ.ꢀPINꢀDESCRIPTIONS
Pinꢀ#
PinꢀNaꢂe
SiꢄnalꢀType
Simplified Pin Description
High Voltage Supply (8.5-60V) supplies phase 1 only
Half Bridge 2 Power Output
29,30,31
VS (phase 1)
Power
51,52,53
OUT 2
Power Output
Power
55,56,57
PGND (phase 2)
High Current GND Return Path for Power Output 2
3
SC
2b
2t
Logic Output
Logic Input
Logic Input
Analog Output
Indication of a short of an output to supply, GND or another phase
Logic high commands 2 phase lower FET to turn on
Logic high commands 2 phase upper FET to turn on
Phase 2 current sense output
61
63
1
I2
As an output, logic high indicates cycle-by-cycle current limit, and
logic low indicates normal operation. As an input, logic high places
all outputs in a high impedance state and logic low disables the
cycle-by-cycle current limit function.
7
ILIM/DIS1
Logic Input/Output
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P r o d u c t I n n o v a t i o n F r o m
SA53
TABLEꢀꢁ.ꢀPINꢀDESCRIPTIONS
Pinꢀ#
PinꢀNaꢂe
SiꢄnalꢀType
Simplified Pin Description
5,9,11,13
SGND
Power
Analog and digital GND – internally connected to PGND
Logic high commands 1 phase lower FET to turn on
Logic high commands 1 phase upper FET to turn on
Logic Supply (5V)
15
17
19
21
23
25
1b
Logic Input
Logic Input
Power
1t
VDD
I1
Analog Output
Logic Input
Logic Output
Power
Phase 1 current sense output
DIS2
TEMP
Logic high places all outputs in a high impedance state
Thermal indication of die temperature above 135ºC
High Voltage Supply phase 2
46,47,48,49 VS (phase 2)
33,34,35 OUT 1
Power Output
Power
Half Bridge 1 Power Output
37,38,39,40 PGND (phase 1)
High Current GND Return Path for Power Outputs 1&2
Pins connected to the package heat slug
26,27,58,59 HS
2,4,6,8,10,
Mechanical
12,14,16,18,
20,22,24,28,
32,36,41,42,
NC
---
Do Not Connect
43,44,45,50,
54,60,62,64
ꢁ.2ꢀPinꢀDescriptions
VS:ꢀ Supply voltage for the output transistors. These pins require decoupling (1μF capacitor with good high fre-
quency characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as
close to the VS and PGND pins as possible. Additional capacitance will be required at the VS pins to handle load
current peaks and potential motor regeneration. Refer to the applications section of this datasheet for additional
discussion regarding bypass capacitor selection. Note that VS pins 29-31 carry only the phase 1 supply current.
Pins 46-49 carry supply current for phase 2. Phase 1 may be operated at a different supply voltage from phase
2. Both VS voltages are monitored for undervoltage conditions.
OUTꢀꢁ,ꢀOUTꢀ2:ꢀThese pins are the power output connections to the load. NOTE: When driving an inductive load, it
is recommended that two Schottky diodes with good switching characteristics (fast tRR specs) be connected to
each pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See Section 2.6)
PgND:ꢀPower Ground. This is the ground return connection for the output FETs. Return current from the load flows
through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section
2.1 of this datasheet for more details.
SC:ꢀShort Circuit output. If a condition is detected on any output which is not in accordance with the input com-
mands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approxi-
mately 200ns during switching transitions but in high current applications, short glitches may appear on the
SC pin. A high state on the SC output will not automatically disable the device. The SC pin includes an internal
12kΩ series resistor.
ꢁb,ꢀ2b:ꢀThese Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower N-
channel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low
side N-channel FET off. If 2b or 2b is high at the same time that a corresponding 1t or 2t input is high, protection
circuitry will turn off both FETs in order to prevent shoot-through on that output phase. Protection circuitry also
includes a dead-time generator, which inserts dead time in the outputs in the case of simultaneous switching of
the top and bottom input signals.
ꢁt,ꢀ2t:ꢀThese Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper P-
channel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top P-
channel FET off.
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P r o d u c t I n n o v a t i o n F r o m
SA53
Iꢁ,ꢀI2:ꢀCurrent sense pins. The SA53 supplies a positive current to these pins which is proportional to the current
flowing through the top side P-channel FET for that phase. Commutating currents flowing through the backbody
diode of the P-channel FET or through external Schottky diodes are not registered on the current sense pins.
Nor do currents flowing through the low side N-channel FET, in either direction, register at the current sense
pins. A resistor connected from a current sense pin to SGND creates a voltage signal representation of the
phase current that can be monitored with ADC inputs of a processor or external circuitry.
The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If
the voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of
this functionality are described in the applications section of this datasheet.
ILIm/DISꢁ:ꢀThis pin is directly connected to the disable circuitry of the SA53. Pulling this pin to logic high places OUT
1 and OUT 2 in a high impedance state. This pin is also connected internally to the output of the current limit
latch through a 12kΩ resistor and can be monitored to observe the function of the cycle-by-cycle current limit
feature. Pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature.
SgND:ꢀThis is the ground return connection for the VDD logic power supply pin. All internal analog and logic circuitry
is referenced to this pin. PGND is internally connected to GND through a resistance of a few ohms,. However, it
is highly recommended to connect the GND pin to the PGND pins externally as close to the device as possible.
Failure do to this may result in oscillations on the output pins during rising or falling edges.
VDD:ꢀThis is the connection for the 5V power supply, and provides power for the logic and analog circuitry in the
SA53. This pin requires decoupling (at least 0.1μF capacitor with good high frequency characteristics is recom-
mended) to the SGND pin.
DIS2:ꢀThe DIS2 pin is a Schmitt triggered logic level input that places OUT 1 and OUT 2 in a high impedance state
when pulled high. DIS2 has an internal 12kΩ pull-down resistor and may therefore be left unconnected.
TEmP:ꢀThis logic level output goes high when the die temperature of the SA53 reaches approximately 135ºC. This
pin WILL NOT automatically disable the device. The TEMP pin includes a 12kΩ series resistor.
hS:ꢀThese pins are internally connected to the thermal slug on the reverse of the package. They should be con-
nected to GND. Neither the heat slug nor these pins should be used to carry high current.
NC:ꢀThese “no-connect” pins should be left unconnected.
2.ꢀSA53ꢀOPERATION
The SA53 is designed primarily to drive DC brush motors. However, it can be used for any application requiring two
high current outputs. The signal set of the SA53 is designed specifically to interface with a DSP or microcontroller.
A typical system block diagram is shown in the figure below. Over-temperature, Short-Circuit and Current Limit fault
signals provide important feedback to the system controller which can safely disable the output drivers in the pres-
ence of a fault condition. High side current monitors for both phases provide performance information which can be
used to regulate or limit torque.
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SA53
FIgUREꢀ4.ꢀSYSTEmꢀDIAgRAm
Vs +
VDD
Vs 1
Vs 2
SC
TEMP
Fault
Logic
ILIM/DIS1
Current
monitor
Signals
I1
I2
GND
DC BRUSH
MOTOR
DIS2
1t
Control
Logic
Gate
Control
OUT 1
OUT 2
1
1b
PWM
Signals
2
2t
2b
SGND
SA53 Switching Amplifier
Microcontroller
or DSC
PGND 1
PGND 2
SGND
GND
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P r o d u c t I n n o v a t i o n F r o m
SA53
The block diagram in Figure 5 illustrates the features of the input and output structures of the SA53. For simplicity,
a single phase is shown.
FIgUREꢀ5.ꢀINPUTꢀANDꢀOUTPUTꢀSTRUCTURESꢀFORꢀAꢀSINgLEꢀPhASE
12k
12k
Current
Sense
SC
Logic
SC
Vdd
I1'
_
+
Vth
Temp
Sense
+
_
TEMP
Ref
12k
Lim 1
Lim 2
ILIM/DIS1
I1
UVLO
12k
DIS2
1t
Vs
Gate
Control
OUT 1
PGND
1b
SGND
TABLEꢀ2.ꢀTRUThꢀTABLE
Comments
0
0
1
1
0
X
X
0
0
X
X
0
0
X
High-Z
PGND
VS
Top and Bottom output FETs for that phase are turned off.
Bottom output FET for that phase is turned on.
Top output FET for that phase is turned on.
1 <Vth
0 <Vth
1
X
High-Z
Both output FETs for that phase are turned off.
Voltage on I1 or I2 has exceeded Vth, which causes ILIM/DIS1 to go high.
This internally disables Top and Bottom output FETs for ALL phases.
DIS2 pin pulled high, which disables all outputs.
Pulling the ILIM/DIS1 pin high externally acts as a second disable input,
which disables ALL output FETs.
X X >Vth
1
X
1
High-Z
High-Z
High-Z
X X
X X
X
X
X
Pulled
High
X
Determined Pulling the DIS2 pin low externally disables the cycle-by-cycle current limit
Pulled
Low
X X
X X
X
X
0
by PWM
inputs
function. The state of the outputs is strictly a function of the PWM inputs.
X
X
High-Z
If VS is below the UVLO threshold all output FETs will be disabled.
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SA53
2.ꢁꢀLAYOUTꢀCONSIDERATIONS
Output traces carry signals with very high dV/dt and dI/dt. Proper routing and adequate power supply bypassing
ensures normal operation. Poor routing and bypassing can cause erratic and low efficiency operation as well as
ringing at the outputs.
The VS supply should be bypassed with a surface mount ceramic capacitor mounted as close as possible to the VS
pins. Total inductance of the routing from the capacitor to the VS and GND pins must be kept to a minimum to pre-
vent noise from contaminating the logic control signals. A low ESR capacitor of at least 25μF per ampere of output
current should be placed near the SA53 as well. Capacitor types rated for switching applications are the only types
that should be considered.
The bypassing requirements of the VDD supply are less stringent, but still necessary. A 0.1μF to 0.47μF surface
mount ceramic capacitor (X7R or NPO) connected directly to the VDD pin is sufficient.
SGND and PGND pins are connected internally. However, these pins must be connected externally in such a way
that there is no motor current flowing in the logic and signal ground traces as parasitic resistances in the small
signal routing can develop sufficient voltage drops to erroneously trigger input transitions. Alternatively, a ground
plane may be separated into power and logic sections connected by a pair of back to back Schottky diodes. This
isolates noise between signal and power ground traces and prevents high currents from passing between the plane
sections.
Unused area on the top and bottom PCB planes should be filled with solid or hatched copper to minimize inductive
coupling between signals. The copper fill may be left unconnected, although a ground plane is recommended.
2.2ꢀFAULTꢀINDICATIONSꢀ
In the case of either an over-temperature or short circuit fault, the SA53 will take no action to disable the outputs.
Instead, the SC and TEMP signals are provided to an external controller, where a determination can be made re-
garding the appropriate course of action. In most cases, the SC pin would be connected to a FAULT input on the
processor, which would immediately disable its PWM outputs. The TEMP fault does not require such an immediate
response, and would typically be connected to a GPIO, or Keyboard Interrupt pin of the processor. In this case,
the processor would recognize the condition as an external interrupt, which could be processed in software via an
Interrupt Service Routine. The processor could optionally bring all inputs low, or assert a high level to either of the
disable inputs on the SA53.
Figure 6 shows an external SR flip-flop which provides a hard wired shutdown of all outputs in response to a fault in-
dication. An SC or TEMP fault sets the latch, pulling the disable pin high. The processor clears the latched condition
with a GPIO. This circuit can be used in safety critical
FIgUREꢀ6.ꢀExTERNALꢀFAULTꢀLATChꢀCIRCUIT
applications to remove software from the fault-shut-
down loop, or simply to reduce processor overhead.
In applications which may not have available GPIO,
PWM
the TEMP pin may be externally connected to the
adjacent DIS1 pin. If the device temperature reach-
SC
SA53
DIS2
TEMP
es ~135ºC all outputs will be disabled, de-energizing
the motor. The SA53 will re-energize the motor when
the device temperature falls below approximately
95ºC. The TEMP pin hysteresis is wide to reduce the
likelihood of thermal oscillations which can greatly
reduce the life of the device.
PROCESSOR
FAULT RESET
LATCHED FAULT
GPIO
INTERRUPT
2.3 UNDER-VOLTAGE LOCKOUT
The undervoltage lockout condition results in the SA53 unilaterally disabling all output FETs until VS is above the
UVLO threshold indicated in the spec table. There is no external signal indicating that an undervoltage lock- out
condition is in progress. The SA53 has two VS connections: one for phase 1 and another for phase 2. The supply
voltages on these pins need not be the same, but the UVLO will engage if either is below the threshold. Hysteresis
on the UVLO circuit prevents oscillations with typical power supply variations.
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P r o d u c t I n n o v a t i o n F r o m
SA53
2.4ꢀCURRENTꢀSENSE
FꢀGURE 7. START-UP VOLTAGE AND CURRENT
External power shunt resistors are not required
with the SA53. Forward current in each top,
Pchannel output FET is measured and mirrored to
the respective current sense output pin, Ia, Ib and
Ic. By connecting a resistor between each cur-
rent sense pin and a reference, such as ground,
a voltage develops across the resistor that is pro-
portional to the output current for that phase. An
ADC can monitor the voltages on these resistors
for protection or for closed loop torque control
in some application configurations. The current
sense pins source current from the VDD supply.
Headroom required for the current sense circuit is
approximately 0.5V. The nominal scale factor for
each proportional output current is shown in the
typical performance plot on page 4 of this data-
sheet.
NON-LIMITED MOTOR CURRENT
NON-LIMITED BACK EMF
LIMITED BACK EMF
LIMITED MOTOR CURRENT
TIME
2.5ꢀCYCLE-BY-CYCLEꢀCURRENTꢀ
LImIT
In applications where the current in the motor is not directly controlled, both the average current rating of the mo-
tor and the inrush current must be considered when selecting a proper amplifier. For example, a 1A continuous
motor might require a drive amplifier that can deliver well over 10A peak in order to survive the inrush condition at
startup.
Because the output current of each upper output FET is measured, the SA53 is able to provide a very robust current
limit scheme. This enables the SA53 to safely and easily drive virtually any DC brush motor through a startup inrush
condition. With limited current, the starting torque and acceleration are also limited. The plot in Figure 7 shows start-
ing current and back EMF with and without current limit enabled.
If the voltage of any of the two current sense pins exceeds the current limit threshold voltage (Vth), all outputs are
disabled. After all current sense pins fall below the Vth threshold voltage AND the offending phase’s top side input
goes low, the output stage will return to an active state on the rising edge of ANY top side input command signal
(1t or 2t). With most commutation schemes, the current limit will reset each pwm cycle. This scheme regulates the
peak current in each phase during each pwm cycle as illustrated in the timing diagram below. The ratio of average
to peak current depends on the inductance of the motor winding, the back EMF developed in the motor, and the
width of the pulse.
Figure 8 illustrates the current limit trigger and reset sequence. Current limit engages and ILIM/DIS1 goes high when
any current sense pin exceeds Vth. Notice that the moment at which the current sense signal exceeds the Vth
threshold is asynchronous with respect to the input PWM signal. The difference between the PWM period and the
motor winding L/R time constant will often result in an audible beat frequency sometimes called a sub-cycle oscil-
lation.
This oscillation can be seen on the ILIM/DIS1 pin waveform in Figure 8. Input signals commanding 0% or 100% duty
cycle may be incompatible with the current limit feature due to the absence of rising edges of 1t and 2t except when
commutating phases. At high RPM, this may result in poor performance. At low RPM, the motor may stall if the cur-
rent limit trips and the motor current reaches zero without a commutation edge which will typically reset the current
limit latch.
The current limit feature may be disabled by tying the ILIM/Dis1 pin to GND. The current sense pins will continue to
provide top FET output current information.
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P r o d u c t I n n o v a t i o n F r o m
SA53
Typically, the current sense pins source
current into grounded resistors which pro-
vide voltages to the current limit compara-
tors. If instead the current limit resistors are
connected to a voltage output DAC, the
current limit can be controlled dynamically
from the system controller. This technique
essentially reduces the current limit thresh-
old voltage to (Vth-VDAC). During expect-
ed conditions of high torque demand, such
as start-up or reversal, the DAC can adjust
the current limit dynamically to allow pe-
riods of high current. In normal operation
when low current is expected, the DAC
output voltage can increase, reducing the
current limit setting to provide more con-
servative fault protection.
FꢀGURE 8. CURRENT LꢀꢁꢀT WAVEFORꢁS
It INPUT
Vth
I1
OUT 1
2.6ꢀExTERNALꢀFLYBACKꢀ
DIODES
External fly-back diodes will offer superior
reverse recovery characteristics and low-
er forward voltage drop than the internal
back-body diodes. In high current applica-
ILIM/DIS1
tions, external flyback diodes can reduce power dissipation and heat-
ing during commutation of the motor current. Reverse recovery time
and capacitance are the most important parameters to consider when
selecting these diodes. Ultra-fast rectifiers offer better reverse recovery
time and Schottky diodes typically have low capacitance. Individual ap-
plication requirements will be the guide when determining the need for
these diodes and for selecting the component which is most suitable.
FIgUREꢀ9.ꢀSChOTTKYꢀDIODES
VS VS
OUT 1
SA53
OUT 2
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P r o d u c t I n n o v a t i o n F r o m
SA53
FIgUREꢀꢁ0.ꢀTImINgꢀDIAgRAmS
TOP INPUT
BOTTOM INPUT
DISABLE
OUTPUT
td(fall)
td(rise)
td(dis)
td(dis)
DELAY TIMING
td(dis)
td(dis)
3.ꢀPOWERꢀDISSIPATION
FIgUREꢀꢁꢁ.ꢀOUTPUTꢀRESPONSE
The thermally enhanced package of the SA53 al-
lows several options for managing the power dissi-
pated in the three output stages. Power dissipation
in traditional PWM applications is a combination
of output power dissipation and switching losses.
Output power dissipation depends on the quadrant
of operation and whether external flyback diodes
are used to carry the reverse or commutating cur-
rents. Switching losses are dependent on the fre-
quency of the PWM cycle as described in the typi-
cal performance graphs.
80%
OUTPUT
20%
The size and orientation of the heatsink must be
selected to manage the average power dissipation
of the SA53. Applications vary widely and various
thermal techniques are available to match the re-
quired performance. The patent pending mounting
technique shown in Figure 12, with the SA53 in-
verted and suspended through a cutout in the PCB
is adequate for power dissipation up to 17W with
the HS33, a 1.5 inch long aluminum extrusion with
four fins. In free air, mounting the PCB perpendicu-
t(rise)
t(fall)
TOP INPUT
BOTTOM INPUT
lar to the ground, such that the heated air flows upward along the channels of the fins can provide a total ΘJA of less
than 14 ºC/W (9W max average PD). Mounting the PCB parallel to the ground impedes the flow of heated air and
provides a ΘJA of 16.66 ºC/W (7.5W max average PD). In applications in which higher power dissipation is expected
or lower junction or case temperatures are required, a larger heatsink or circulated air can significantly improve the
performance.
4.ꢀORDERINgꢀANDꢀPRODUCTꢀSTATUSꢀINFORmATION
mODEL
TEmPERATURE
PACKAgE
PRODUCTIONꢀSTATUS
SA53-IHZ
-25 to 85ºC
64 pin Power QFP (HQ package drawing)
Samples Available 1Q09
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P r o d u c t I n n o v a t i o n F r o m
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FIgUREꢀꢁ2.ꢀhEATSINKꢀTEChNIQUE
PATENTꢀPENDINgꢀ
CONTACTINgꢀCIRRUSꢀLOgICꢀSUPPORT
For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America.
For inquiries via email, please contact tucson.support@cirrus.com.
International customers can also request support by contacting their local Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
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supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
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copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-
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does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED TO BE
SUITABLE FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PROD-
UCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUS-
TOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE
CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES,
BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, Apex and Apex Precision Power are trademarks of Cirrus Logic, Inc. All other brand and product names in
this document may be trademarks or service marks of their respective owners.
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