WM8742_技术文档

WM8742

24-bit 192 kHz DAC with Advanced Digital Filtering

DESCRIPTION

FEATURES



Advanced Ultra High Performance Multi-bit Sigma-Delta

Architecture

The WM8742 is a very high performance stereo DAC

designed for audio applications such as professional

recording systems, A/V receivers and high specification CD,

DVD and home theatre systems. The device supports PCM

data input word lengths from 16 to 32-bits and sampling

rates up to 192kHz. The WM8742 also supports DSD bit-

stream data format, in both direct DSD and PCM-converted

DSD modes.



126dB SNR (‘A’-weighted mono @ 48kHz)

123dB SNR (‘A’-weighted stereo @ 48kHz)

121dB SNR (non-weighted stereo @ 48kHz)

-100dB THD @ 48kHz

Differential analogue voltage outputs

High tolerance to clock jitter



PCM Mode

The WM8742 includes fine resolution volume and soft mute

control, digital de-emphasis and a range of advanced digital

filter responses, followed by a digital interpolation filter,

multi-bit sigma delta modulator and stereo DAC. The

architecture optimises the linearity of the DAC and provides

maximum insensitivity to clock jitter.



Sampling frequency: 32kHz to 192kHz

Input data word length support: 16 to 32-bit

Supports all standard audio interface formats

Selectable advanced digital filter responses



Includes linear/minimum phase and range of

tailored characteristics



Enables low pre-ringing, minimal latency

The digital filters include several selectable roll-off and

performance characteristics. The user can select between

standard sharp or slow roll-off responses. In addition, the

WM8742 includes a selection of advanced digital filter

characteristics including non-half band filters and minimum

phase filters.



Optional interface to industry standard external filters

Digital volume control in 0.125dB steps with soft ramp

and soft mute

Anti-clipping mode to prevent distortion even with input

signals recorded up to 0dB



Selectable de-emphasis support

Zero Flag output

This flexibility provides

a range of benefits, such as

significantly reduced pre-ringing and minimal group delay.

The internal digital filters can also be by-passed and the

WM8742 used with an external digital filter.



DSD Mode



DSD bit-stream support for SACD applications

Support for normal or phase modulated bit-streams

Direct or PCM converted DSD paths (DSD Plus)

DSD mute

The WM8742 supports two connection schemes for audio

DAC control. The 2/3 wire serial control interface provides

access to all features. A range of features can also be

accessed by hardware control interface.

Hardware or software control modes:

2 and 3 wire serial control interface support





Pin compatible with WM8740 and WM8741

The WM8742 is available in

package, and is pin compatible with the WM8740 and

WM8741.

a convenient 28-SSOP

4.5V to 5.5V analogue, 3.15V to 3.6V digital supply

operation



28-lead SSOP Package

APPLICATIONS



Professional audio systems

CD, DVD, SACD audio

Home theatre systems

A/V receivers

Rev 4.4

JAN 2020

Copyright  Cirrus Logic, Inc., 2009–2020

http://www.cirrus.com

WM8742

BLOCK DIAGRAM

CONTROL INTERFACE

PCM

ATTENUATION /

MUT E

SIGMA DELTA

MO DULATOR

VMIDL

PCM

PCM DIGIT AL FILT ERS

BCLK/DSD64CLK

FSEL/DINR

PCM

ATTENUATION /

MUT E

SIGMA DELTA

MO DULATOR

VOUTLP

DAC

LEFT

AUDIO

INTERFACE

DIN/DINL

LRCLK/DSDL

IW O/DOUT

OSR/DSDR

VOUTLN

DSD

ATTENUATION /

MUT E

DSD TO PCM

CONVERTOR

VOUTRP

VOUTRN

DAC

RIGHT

DSD

VMIDR

WM8742

2

Rev 4.4

WM8742

TABLE OF CONTENTS

DESCRIPTION................................................................................................................ 1

FEATURES..................................................................................................................... 1

APPLICATIONS.............................................................................................................. 1

BLOCK DIAGRAM ......................................................................................................... 2

TABLE OF CONTENTS.................................................................................................. 3

PIN CONFIGURATION................................................................................................... 4

ORDERING INFORMATION........................................................................................... 4

PIN DESCRIPTION (SOFTWARE CONTROL MODE)................................................... 5

PIN DESCRIPTION (HARDWARE CONTROL MODE).................................................. 7

ABSOLUTE MAXIMUM RATINGS................................................................................. 9

THERMAL PERFORMANCE.......................................................................................... 9

RECOMMENDED OPERATING CONDITIONS............................................................ 10

ELECTRICAL CHARACTERISTICS ............................................................................ 10

MASTER CLOCK TIMING.......................................................................................................11

PCM DIGITAL AUDIO INTERFACE TIMING...........................................................................12

DSD AUDIO INTERFACE TIMING..........................................................................................13

CONTROL INTERFACE TIMING – 3-WIRE MODE................................................................14

CONTROL INTERFACE TIMING – 2-WIRE MODE................................................................15

INTERNAL POWER ON RESET CIRCUIT..............................................................................16

DEVICE DESCRIPTION ............................................................................................... 18

INTRODUCTION .....................................................................................................................18

CLOCKING SCHEMES ...........................................................................................................18

CONTROL INTERFACE..........................................................................................................18

SOFTWARE CONTROL INTERFACE.....................................................................................19

DIGITAL AUDIO INTERFACE.................................................................................................21

DSD MODE .............................................................................................................................27

SOFTWARE CONTROL MODE..............................................................................................29

HARDWARE CONTROL MODE..............................................................................................40

OVERVIEW OF FUNCTIONS....................................................................................... 44

REGISTER MAP........................................................................................................... 45

DIGITAL FILTER CHARACTERISTICS ....................................................................... 50

PCM MODE FILTER CHARACTERISTICS.............................................................................50

8FS MODE FILTER CHARACTERISTICS ..............................................................................52

DSD PLUS MODE FILTER CHARACTERISTICS...................................................................53

PCM MODE FILTER RESPONSE...........................................................................................54

8FS MODE FILTER RESPONSE............................................................................................59

DSD PLUS MODE FILTER RESPONSE.................................................................................59

DSD DIRECT MODE FILTER RESPONSE.............................................................................60

DE-EMPHASIS FILTER RESPONSE......................................................................................62

APPLICATIONS INFORMATION ................................................................................. 63

PACKAGE DIMENSIONS............................................................................................. 64

IMPORTANT NOTICE .................................................................................................. 65

REVISION HISTORY .................................................................................................... 66

Rev 4.4

3

WM8742

PIN CONFIGURATION

LRCLK/DSDL

DIN/DINL

BCLK/DSD64CLK

FSEL/DINR

MCLK

CSB/SADDR/I2S

SCLK/DSD

SDIN/DEEMPH

MUTEB/SDOUT

MODE/LRSEL

IWO/DOUT

OSR/DSDR

ZFLAG

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

2

3

4

5

DIFFHW

DGND

6

7

DVDD

8

AVDDR

AVDDL

9

AGNDR

AGNDL

10

VMIDR

VMIDL

11

12

13

14

VOUTRP

VOUTRN

AGND

VOUTLP

VOUTLN

AVDD

ORDERING INFORMATION

PEAK SOLDERING

TEMPERATURE

DEVICE

RANGE

PACKAGE

28-lead SSOP

(Pb-free)

WM8742GEDS/V

WM8742GEDS/RV

-0 to +70C

260˚C

28-lead SSOP

(Pb-free, tape and reel)

Note:

Reel Quantity = 2,000

4

Rev 4.4

WM8742

PIN DESCRIPTION (SOFTWARE CONTROL MODE)

NAME

TYPE

DESCRIPTION

PCM MODE

8FS PCM MODE

DSD MODES

Audio interface left/right

clock input

Audio interface left/right

clock input

DSD left audio data in

1

2

3

4

LRCLK /

DSDL

Digital input

Audio interface data input Audio interface left data

input

Unused

DIN /

DINL

Audio interface bit clock

input

Audio interface bit clock

input

64fs system clock input

Unused

BCLK /

DSD64CLK

FSEL /

DINR

Unused

Audio interface right data

input

Digital input

Tri-level

Master clock input

Unused

5

6

MCLK

Digital input

Differential mono mode

selection

Differential mono mode

selection

Differential mono mode

selection

DIFFHW

Digital input

Internal pull-

down

0 = normal operation

1 = differential mono

mode

1 = differential mono

mode

1 = differential mono

mode

Digital ground

7

8

DGND

DVDD

Supply

Digital supply

Right analogue positive

reference

Right analogue positive

reference

Right analogue positive

reference

9

AVDDR

AGNDR

VMIDR

Analogue Input

Right analogue negative

reference

Right analogue negative

reference

Right analogue negative

reference

10

11

Right analogue midrail

decoupling pin

Right analogue midrail

decoupling pin

Right analogue midrail

decoupling pin

Analogue

Output

Right DAC positive

output

Right DAC positive

output

Right DAC positive

output

12

13

VOUTRP

VOUTRN

Analogue

Output

Right DAC negative

output

Right DAC negative

output

Right DAC negative

output

Analogue

Output

Analogue ground

14

15

16

AGND

AVDD

Supply

Analogue supply

Supply

Left DAC negative output

VOUTLN

Analogue

Output

Left DAC positive output

17

18

VOUTLP

VMIDL

Analogue

Output

Left analogue midrail

decoupling pin

Left analogue midrail

decoupling pin

Left analogue midrail

decoupling pin

Analogue

Output

Left analogue negative

reference

Left analogue negative

reference

Left analogue negative

reference

19

20

21

22

AGNDL

AVDDL

Analogue Input

Left analogue positive

reference

Left analogue positive

reference

Left analogue positive

reference

Analogue Input

Digital Output

Zero flag output

ZFLAG

Unused

DSD right audio data in

OSR/DSDR

Digital input

Tri-level

Buffered audio interface

data output

Unused

23

IWO /

Digital

input/output

DOUT

Rev 4.4

5

WM8742

NAME

TYPE

DESCRIPTION

PCM MODE

8FS PCM MODE

DSD MODES

When DIFFHW=0:

0 = hardware mode

When DIFFHW=0:

0 = hardware mode

When DIFFHW=0:

0 = hardware mode

24

MODE /

LRSEL

Digital input,

tri-level

1 = 3-wire software mode 1 = 3-wire software mode 1 = 3-wire software mode

Z = 2-wire software mode Z = 2-wire software mode Z = 2-wire software mode

When DIFFHW=1:

0 = left channel mono

1 = right channel mono

Softmute Control

When DIFFHW=1:

0 = left channel mono

1 = right channel mono

Softmute Control

When DIFFHW=1:

0 = left channel mono

1 = right channel mono

Softute Control

25

MUTEB /

SDOUT

Digital input or

output:

0 = mute active

Internal pull-up

1 = normal operation

NOTE: In 3-wire mode

only, this pin may be

used as a buffered

control interface data

output

NOTE: In DSD Direct

mode this is an analogue

mute

Serial control interface

data input

Serial control interface

data input

Serial control interface

data input

26

27

28

SDIN /

DEEMPH

SCLK /

DSD

Digital input

Tri-level

Serial control interface

clock input

Serial control interface

clock input

Serial control interface

clock input

Digital input

3-wire mode: serial

CSB /

Digital input

control interface latch

SADDR /

I²S

2-wire mode: device

address select

2-wire mode: device

address select

2-wire mode: device

address select

Notes:

1. Undefined inputs should be connected to DVDD or DGND

2. Tri-level pins which require the ‘Z’ state to be selected should be left floating (open)

6

Rev 4.4

WM8742

PIN DESCRIPTION (HARDWARE CONTROL MODE)

NAME

TYPE

DESCRIPTION

PCM MODE

DSD DIRECT MODE

Audio interface left/right clock input

Audio interface data input

DSD left audio data in

1

2

3

4

LRCLK /

DSDL

Digital input

Unused

DIN /

DINL

Audio interface bit clock input

64fs system clock input

Unused

BCLK /

DSD64CLK

FSEL /

DINR

Selects between one of three digital

filters – see Table 50

Digital input

Tri-level

Master clock input

Unused

5

6

MCLK

Digital input

Differential mono mode selection

0 = normal operation

Differential mono mode selection

0 = normal operation

DIFFHW

Digital input

Internal pull-

down

1 = differential mono mode

Digital ground

1 = differential mono mode

Digital ground

7

8

DGND

DVDD

Supply

Digital supply

Supply

Right analogue positive reference

Right analogue negative reference

Right analogue midrail decoupling pin

Right analogue positive reference

Right analogue negative reference

Right analogue midrail decoupling pin

9

AVDDR

AGNDR

VMIDR

Analogue Input

10

11

Analogue

Output

Right DAC positive output

Right DAC negative output

Right DAC positive output

Right DAC negative output

12

13

VOUTRP

VOUTRN

Analogue

Output

Analogue

Output

Analogue ground

14

15

16

AGND

AVDD

Supply

Analogue supply

Supply

Left DAC negative output

VOUTLN

Analogue

Output

Left DAC positive output

17

18

VOUTLP

VMIDL

Analogue

Output

Left analogue midrail decoupling pin

Analogue

Output

Left analogue negative reference

Left analogue positive reference

Zero flag output

Left analogue negative reference

Left analogue positive reference

Unused

19

20

21

22

AGNDL

AVDDL

Analogue Input

Digital Output

ZFLAG

Controls internal oversampling rate:

0 = low rate

DSD right audio data in

OSR/DSDR

Digital input

Tri-level

Z = medium rate

1 = high rate

Controls audio interface wordlength –

Unused

23

IWO /

Digital

see Table 46

input/output

DOUT

Rev 4.4

7

WM8742

NAME

TYPE

DESCRIPTION

PCM MODE

When DIFFHW=0:

DSD DIRECT MODE

When DIFFHW=0:

0 = hardware mode

24

MODE /

LRSEL

Digital input,

tri-level

0 = hardware mode

1 = 3-wire software mode

Z = 2-wire software mode

When DIFFHW=1:

1 = 3-wire software mode

Z = 2-wire software mode

When DIFFHW=1:

0 = left channel mono

1 = right channel mono

Softmute Control

0 = left channel mono

1 = right channel mono

Analogue Mute Control

0 = mute active

25

26

MUTEB /

SDOUT

Digital input or

output:

0 = mute active

Internal pull-up

1 = normal operation

De-emphasis Control

0 = normal operation

1 = de-emphasis applied

Z = anti-clipping digital filter mode

HW Mode Select:

Unused

SDIN /

Digital input

Tri-level

DEEMPH

HW Mode Select:

0 = PCM

27

28

SCLK /

DSD

Digital input

0 = PCM

1 = DSD Direct

Unused

Controls audio interface format – see

Table 46

CSB /

SADDR /

I²S

Notes:

1. Undefined inputs should be connected to DVDD or DGND

2. Tri-level pins who require the ‘Z’ state to be selected should be left floating (open)

8

Rev 4.4

WM8742

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at

or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical

Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible

to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage

of this device.

CONDITION

MIN

-0.3V

MAX

+4.5V

Digital supply voltage, DVDD

Analogue supply voltage, AVDD

Voltage range digital inputs

-0.3V

+7V

DGND - 0.3V

AGND - 0.3V

DVDD + 0.3V

AVDD + 0.3V

38.462MHz

+70°C

Voltage range analogue inputs

Master Clock Frequency

Operating temperature range, T_A

Storage temperature

-0°C

-65°C

-55°C

+150°C

Ambient temperature (supplies applied)

Pb free package body temperature (soldering 10 seconds)

Pb free package body temperature (soldering 2 minutes)

+125°C

+260°C

+183°C

Notes:

1. Analogue and digital grounds must always be within 0.3V of each other.

THERMAL PERFORMANCE

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Thermal resistance –

θ_JC

23.9

°C/W

junction to case

Thermal resistance –

θ_JA

67.1

°C/W

junction to ambient

Rev 4.4

9

WM8742

RECOMMENDED OPERATING CONDITIONS

PARAMETER

Digital supply range

SYMBOL

DVDD

TEST CONDITIONS

MIN

3.15

4.5

TYP

3.3

5

MAX

3.6

UNIT

V

Analogue supply range

Ground

AVDD

5.5

V

AGND, DGND

0

V

Difference DGND to AGND

Analogue operating current

Digital operating current

Analogue standby current

-0.3

0

+0.3

V

I_AVDD

I_DVDD

AVDD = 5V

DVDD = 3.3V

AVDD = 5V

55

40

45

mA

I_{AVDD (Standby)}

Clocks stopped

DVDD = 3.3V

Clocks stopped

Digital standby current

I_{DVDD (Standby)}

1.5

mA

ELECTRICAL CHARACTERISTICS

TEST CONDITIONS

AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, T_A= +25^oC, 1kHz test signal, fs = 48kHz, MCLK = 512fs unless otherwise

stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Digital Logic Levels

Input LOW level

V_IL

V_IH

0.3 x DVDD

0.1 x DVDD

V

Input HIGH level

0.7 x DVDD

0.9 x DVDD

Output LOW level

Output HIGH level

DSD Input Characteristics

DSD reference level

V_OL

V_OH

I_OL= 2mA

I_OH= 2mA

DSD Direct or DSD Plus Mode

0

dB_DSD

%

50

DAC Performance

Signal to Noise Ratio

(Note 1)

SNR

A-weighted mono

@ fs = 48kHz

126

123

121

118

120

125

dB

A-weighted stereo

@ fs = 48kHz

118

A-weighted stereo

@ fs = 96kHz

A-weighted stereo

@ fs = 192kHz

Non-weighted stereo

@ fs = 48kHz

Dynamic Range

(Note 2)

DNR

THD

A=weighted,

-60dB full scale input

Mono 0dB @ fs = 48kHz

Stereo 0dB @ fs = 48kHz

Stereo 0dB @ fs = 96kHz

Stereo 0dB @ fs = 192kHz

1kHz

Total Harmonic Distortion

(Note 2)

-100

130

0.1

dB

Channel Separation

dB

Channel Level Matching

Channel Phase Deviation

dB

0.01

-80

Degree

dB

Power Supply Rejection

Ratio

PSRR

100mVpp at 1kHz

20Hz to 20kHz 100mVpp

-67

dB

10

Rev 4.4

WM8742

TEST CONDITIONS

AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, T_A= +25^oC, 1kHz test signal, fs = 48kHz, MCLK = 512fs unless otherwise

stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Internal Analogue Filter

Bandwidth

-3dB

474

kHz

dB

Passband edge response

Analogue Output Levels

20kHz

-0.0077

PCM full scale differential

output level

V_RMS

kΩ

Into 10kΩ load, 0dBFS input

Into 10kΩ load, 0dB_DSDinput

To midrail or AC coupled

2

DSD Direct differential

output level

0.948

0.991

2

DSD Plus differential output

level

Minimum resistance load

Maximum capacitance load

Output DC level

1

nF

V

AVDD/2

Reference Levels

Potential divider resistance

10

kΩ

AVDD to VMIDL/VMIDR and

VMIDL/VMIDR to AGND

Voltage at VMIDL/VMIDR

AVDD/2

V

Notes:

1.

Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted

over a 20Hz to 20kHz bandwidth.

2. All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher THD and lower

SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band

noise; although it is not audible it may affect dynamic specification values.

MASTER CLOCK TIMING

t_MCLKL

V_IH

V_IL

MCLK

t_MCLKH

t_MCLKY

Figure 1 Master Clock Timing Requirements

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, T_A= +25^oC

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Master Clock Timing Information

MCLK Master clock pulse width high

MCLK Master clock pulse width low

MCLK Master clock cycle time

MCLK Duty cycle

t_MCLKH

t_MCLKL

t_MCLKY

10

ns

27

40:60

60:40

Table 1 MCLK Timing Requirements

Rev 4.4

11

WM8742

PCM DIGITAL AUDIO INTERFACE TIMING

t_BCH

t_BCL

V_IH

V_IL

BCLK

LRCLK

DIN

t_BCY

V_IH

V_IL

t_LRSU

t_DS

t_LRH

V_IH

V_IL

t_DH

Figure 2 Digital Audio Data Timing

Test Conditions

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, T_A= +25^oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

t_BCY

t_BCH

t_BCL

40

16

8

ns

BCLK pulse width high

BCLK pulse width low

LRCLK set-up time to BCLK

rising edge

t_LRSU

LRCLK hold time from

BCLK rising edge

t_LRH

t_DS

8

ns

DIN set-up time to BCLK

rising edge

DIN hold time from BCLK

rising edge

t_DH

Table 2 Digital Audio Interface Timing Requirements

12

Rev 4.4

WM8742

DSD AUDIO INTERFACE TIMING

t_DH

D[n-1]

D[n]

D[n+1]

DSD[0:1]

t_64CY

t_DC

t_64L

DSDCLK64

t_64H

t_DS

Figure 3 DSD Audio Timing - Normal Mode

D[n-1]

D[n]

D[n+1]

DSD[0:1]

t_64CY

t_DC

t_64L

DSDCLK64

Figure 4 DSD Audio Timing - Phase Modulated Mode

Test Conditions

DVDD = 3.3V, GND = 0V, T_A= +25^oC, fs = 44.1kHz, DSDCLK64 = 64fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

DSDCLK64 cycle time

t_64CY

t_64H

t_64L

354.3

ns

DSDCLK64 pulse width high

DSDCLK64 pulse width low

140

20

DSD[0:1] set-up time to

DSDCLK64 rising edge

t_DSN

DSD[0:1] hold time from

DSDCLK64 rising edge

t_DHN

t_DC

20

ns

Difference in edge timing of

DSD[0:1] to DSDCLK64

-10

10

Table 3 DSD Audio Interface Timing Requirements

Rev 4.4

13

WM8742

CONTROL INTERFACE TIMING – 3-WIRE MODE

t_CSL

t_CSH

V_IH

V_IL

CSB

t_SCY

t_SCL

t_CSS

t_SCH

t_SCS

V_IH

V_IL

SCLK

SDIN

V_IH

V_IL

LSB

t_DSU

t_DHO

Figure 5 Control Interface Timing - 3-Wire Serial Control Mode

Test Conditions

DVDD = 3.3V, GND = 0V, T_A= +25^oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SCLK rising edge to LATCH

rising edge

t_SCS

40

ns

SCLK pulse cycle time

SCLK pulse width low

t_SCY

t_SCL

t_SCH

t_DSU

t_DHO

t_CSL

t_CSH

t_CSS

80

32

20

ns

SCLK pulse width high

SDIN to SCLK set-up time

SCLK to SDIN hold time

LATCH pulse width low

LATCH pulse width high

LATCH rising to SCLK rising

Table 4 Control Interface Timing – 3-Wire Serial Control Mode

14

Rev 4.4

WM8742

CONTROL INTERFACE TIMING – 2-WIRE MODE

t_RIS

t_FAL

t_CSS

t_DHO

t_SCH

t_SCL

t_CSE

V_IH

V_IL

SCLK

SDIN

t_HOL

V_IH

V_IL

LSB

t_DSU

Figure 6 Control Interface Timing - 2-Wire Serial Control Mode

Test Conditions

DVDD = 3.3V, DGND = 0V, T_A= +25^oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

MIN

0

TYP

MAX

UNIT

MHz

ns

SCLK Frequency

5

SCLK Low Pulse-Width

SCLK High Pulse-Width

Hold Time (Start Condition)

Setup Time (Start Condition)

Data Setup Time

t_SCL

t_SCH

t_HOL

t_CSE

t_DSU

t_RIS

80

us

600

100

ns

SDIN, SCLK Rise Time

SDIN, SCLK Fall Time

Setup Time (Stop Condition)

300

ns

t_FAL

t_CSS

t_DHO

t_PS

ns

600

4

ns

Data Hold Time

900

6

ns

Max Pulse width of spikes that will be suppressed

Table 5 Control Interface Timing – 2-wire Serial Control Mode

Rev 4.4

15

WM8742

INTERNAL POWER ON RESET CIRCUIT

The WM8742 includes two internal Power On Reset (POR) circuits which are used to reset the digital

logic into a default state after power up and to allow the analogue circuits to power-up silently.

The digital POR circuit is powered from DVDD. This circuit monitors DVDD and asserts the internal

digital reset if DVDD are below the minimum DVDD threshold which will allow the digital logic to

function.

The analogue POR circuit is powered from AVDD. The circuit monitors AVDD, tri-stating the DAC

outputs and isolating the internal reference resistor strings from AVDDL and AVDDR until there is

sufficient AVDD voltage to allow the analogue DAC stages to function correctly.

V_{por_hi}

AVDD

V_{por_lo}

V_pord

AGND

VMIDL

AGND

HI

INTERNAL

ANALOGUE

PORB

LO

POR

Undefined

Internal

POR active

No Power

Device Ready

Internal POR active

Figure 7 AVDD Power up Sequence

Test Conditions

AVDD = 5V, AGND = 0V, T_A= +25^oC, T_{A_max}= +125^oC, T_{A_min}= -25^oC, AVDD_max= 5.5V, AVDD_min= 4.5V

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power Supply Input Timing Information

AVDD level to POR rising

edge (AVDD rising)

V_{por_hi}

V_{por_lo}

Measured from AGND

2.00

1.84

V

AVDD level to POR falling

edge (AVDD falling)

Table 6 Analogue POR Timing

16

Rev 4.4

WM8742

V_{por_lo}

V_{por_hi}

DVDD

DGND

HI

V_pord

INTERNAL

DIGITAL PORB

LO

No Power

POR

Undefined

Internal

POR active

Internal POR active

Device Ready

Figure 8 DVDD Power up Sequence

Test Conditions

DVDD = 3.3V, DGND = 0V, T_A= +25^oC, T_{A_max}= +125^oC, T_{A_min}= -25^oC, DVDD_max= 3.6V, DVDD_min= 3.0V

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power Supply Input Timing Information

DVDD level to POR rising

edge (DVDD rising)

V_{por_hi}

V_{por_lo}

Measured from DGND

1.86

1.83

V

DVDD level to POR falling

edge (DVDD falling)

Table 7 Digital POR Timing

In a real application the designer is unlikely to have control of the relative power up sequence of

AVDD and DVDD. The POR circuit ensures a reasonable delay between applying power to the

device and Device Ready.

Figure 7 and Figure 8 show typical power up scenarios in a real system. DVDD must be established

before the device can be written to. Any writes to the device before device ready will be ignored.

Note: DVDD must be established before the MCLK is started. This will ensure all synchronisation

circuitry within the device is fully initialised and ready.

AVDD must be established before the device will output any signal. Whilst the device will output

signal as soon as the Internal Analogue PORB indicates device ready, normal operation is not

possible until the VMID pin has reached the midrail voltage.

Rev 4.4

17

WM8742

DEVICE DESCRIPTION

INTRODUCTION

The WM8742 is an ultra high performance DAC designed for digital audio applications. Its range of

features makes it ideally suited for use in professional recording environments, CD/DVD players, AV

receivers and other high-end consumer audio equipment.

The WM8742 is a complete differential stereo audio digital-to-analogue converter. The system

includes a dithered digital interpolation filter, fine resolution volume control and digital de-emphasis,

followed by a multi-bit sigma delta modulator and switched capacitor multi-bit stage with differential

voltage outputs. The device supports both PCM and DSD digital audio input formats.

The WM8742 includes a configurable digital audio interface support for a 3-wire and 2-wire serial

control interface, and a hardware control interface. The software control interface may be

asynchronous to the audio data interface; in which case control data will be re-synchronised to the

audio processing internally. It is fully compatible with, and an ideal partner for, a range of industry

standard microprocessors, controllers and DSPs.

Uniquely, the WM8742 has a large range of high performance low latency advanced digital filters.

The full range of filters is selectable in software mode, and a limited range of filters are available under

hardware control. The filters allow users the flexibility to choose characteristics to match their group

delay, phase and latency requirements.

Operation using a master clock of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is supported. Sample

rates (fs) from 32kHz to 192kHz are allowed, provided the appropriate master clock is input (see

Table 11 for details).

In normal PCM mode, the audio data interface supports right justified, left justified and I²S interface

formats along with a highly flexible DSP serial port interface.

There are two DSD modes. In DSD Direct mode, the datastream is subjected to the minimum

possible processing steps between input and output. In DSD Plus mode, the datastream is converted

to PCM and filtered to allow reduction of out of band components. This step also provides additional

benefits in allowing access to other PCM features such as volume control and advanced digital

filtering.

The device is packaged in a small 28-lead SSOP.

CLOCKING SCHEMES

In a typical digital audio system there is only one central clock source producing a reference clock to

which all audio data processing is synchronised. This clock is often referred to as the audio system’s

Master Clock. The external master system clock can be applied directly through the MCLK input pin

with no software configuration necessary for sample rate selection.

MCLK is used to derive clocks for the DAC path in PCM mode. The DAC path consists of DAC

sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a system where

there are a number of possible sources for the reference clock it is recommended that the clock

source with the lowest jitter be used to optimise the performance of the DAC.

CONTROL INTERFACE

The WM8742 supports 2-wire and 3-wire serial control, and hardware control. Selection of control

mode is made by controlling the state of the MODE pin.

NAME

MODE/

LRSEL

DESCRIPTION

24

0 = Hardware control mode

1 = 3-wire serial control mode

Z = 2-wire serial control mode

Table 8 Control Mode Configuration

18

Rev 4.4

WM8742

SOFTWARE CONTROL INTERFACE

The software control interface may be operated using a 2-wire or 3-wire (SPI-compatible) serial

interface. When operating under serial control, hardware configuration pins are ignored.

Note: DIFFHW will override all other pins, forcing the device into hardware control mode and

differential mono mode.

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

Every rising edge of SCLK clocks in one bit of data on SDIN. A rising edge on CSB latches a

complete control word consisting of 16 bits. The 3-wire interface protocol is shown in Figure 9.

Figure 9 3-wire Serial Interface Protocol

Notes:

1. A[6:0] are Control Address Bits

2. D[7:0] are Control Data Bits

3. D[8] is always set to zero

3-WIRE CONTROL INTERFACE DAISY CHAINING

In daisy chaining mode, SDOUT (pin 25) outputs control data sampled on SDIN with a delay of 16

SCLK cycles. This data signal can be used to control another WM8742 in a daisy chain circuit as

shown in Figure 10.

DAC #1

DAC #2

DAC #3

Figure 10 Control Interface Daisy Chaining Setup

To configure devices into daisy chain mode the CSB signal should be driven low while there is a

register write to set register bit SDOUT=1. CSB should then be driven high, this sets the first device in

daisy chain mode. CSB should then be driven low again while register bit SDOUT is set high. Setting

CSB high again will cause the first register write to be output to the second device from the SDOUT

pin, this sets the second device into daisy chain mode. This method must be repeated for the number

Rev 4.4

19

WM8742

of devices in the chain until they are all set into daisy chain mode. Figure 11 shows the protocol for

configuring the first two devices in the daisy chain.

CSB

SCLK

ADDR=0x08, DATA=0x022

ADDR=0x7F, DATA=0x1FF

ADDR=0x08, DATA=0x022

DAC1 SDIN

DAC1 SDOUT/

DAC2 SDIN

DAC1 configured into daisy chain mode

DAC1 receives 16-bits of control data ready to

echo on SDOUT. DAC1 does not act on control

data as no rising CSB to latch data in

DAC1 outputs previous 16-bits of control data on

SDOUT and receives dummy write on SDIN

DAC2 configured into daisy chain mode

Figure 11 Initial Setup of Two WM8742 Devices into Control Interface Daisy Chain Mode

To write to a single device in the chain a complete sequence needs to be written to all the devices.

Devices that do not require a register change must also be written to. The user can choose to write

either the same data as the previous write, or write all 1s for the register address and data. All 1s will

result in writing to a non-existent register, address 7Fh, preserving the current register settings.

Figure 12 shows an example of how to access three WM8742 devices (the devices have all previously

been configured in daisy chain mode):

CSB

SCLK

A6

A5

D1

D0

A6

A5

D1

D0

A6

A5

D1

D0

DAC1 SDIN

DAC1 SDOUT/

DAC2 SDIN

DAC2 SDOUT/

DAC3 SDIN

CSB goes high

DAC1 processes blue data

DAC2 processes yellow data

DAC3 processes pink data

Figure 12 Daisy Chain Control Interface Example for Three WM8742 Devices

To ensure that only valid data is written to the devices in daisy chain mode, a pull up resistor is used

in SDOUT. When connected to the SDIN pin of the next device in the chain, this results in all ones

being written to the control interface of that device until the correct daisy chain data is written and

latched.

Serial daisy chaining is available only when using 3-wire serial control mode. It is not available in 2-

wire serial control mode or hardware control mode.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

3 wire Serial Interface Daisy Chaining

0 = No Output

R8

Mode Control 2

08h

5

SDOUT

0

1 = Output on pin 25.

Table 9 Control Interface Daisy Chaining Selection

20

Rev 4.4

WM8742

2-WIRE SERIAL CONTROL MODE

The WM8742 supports software control via a 2-wire serial bus. Many devices can be controlled by the

same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address of

each register in the WM8742).

The WM8742 operates as a slave device on the 2-wire control bus. The controller indicates the start

of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a

device address and data will follow. All devices on the 2-wire bus respond to the start condition and

shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address

received matches the address of the WM8742 and the R/W bit is ‘0’, indicating a write, then the

WM8742 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not

recognised or the R/W bit is ‘1’, the WM8742 returns to the idle condition and wait for a new start

condition and valid address.

Once the WM8742 has acknowledged a correct address, the controller sends the first byte of control

data (B15 to B8, i.e. the WM8742 register address plus the first bit of register data). The WM8742

then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then

sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the

WM8742 acknowledges again by pulling SDIN low.

The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.

After receiving a complete address and data sequence the WM8742 returns to the idle state and waits

for another start condition. If a start or stop condition is detected out of sequence at any point during

data transfer (i.e. SDIN changes while SCLK is high), the device reverts to the idle condition.

SDI

N

DEVICE ADDRESS RD / WR

(7 BITS) BIT

ACK

(LOW)

CONTROL BYTE 1

(BITS 15 TO 8)

ACK

(LOW)

ACK

(LOW)

CONTROL BYTE 2

(BITS 7 TO 0)

SCLK

remaining 8 bits of

register data

START

STOP

register address and

1st register data bit

Figure 13 2-wire Serial Control Interface

The WM8742 device address can be configured between two options. This is selected by the SADDR

pin.

NAME

DESCRIPTION

28

CSB/

0 = 2-wire address 0011010

SADDR/I²S 1 = 2-wire address 0011011

Table 10 2-wire Serial Control Mode Address Selection

DIGITAL AUDIO INTERFACE

PCM MODE

There are a number of valid PCM data input modes. Two channel and one channel differential mono

modes can be selected by serial or hardware control. It is also possible to bypass the WM8742 digital

filters and apply a signal at a rate 8fs (where fs is the sampling rate) directly to the switched capacitor

stage.

Rev 4.4

21

WM8742

PCM DIGITAL AUDIO INTERFACE

Audio data is applied to the DAC system via the Digital Audio Interface. Five popular interface

formats are supported:



Left Justified mode

Right Justified mode

I²S mode

DSP mode A

DSP mode B

All five formats require the MSB to be transmitted first, and support word lengths of 16, 20, 24 and 32

bits, with the exception that 32 bit data is not supported in right justified mode. DIN and LRCLK may

be configured to be sampled on the rising or falling edge of BCLK by adjusting register bits LRP and

BCP.

In left justified, right justified and I²S audio interface modes, the digital audio interface receives data

on the DIN input pin. Stereo audio data is time multiplexed on DIN, with LRCLK indicating whether

the left or right channel is present. LRCLK is also used as a timing reference to indicate the beginning

or end of the data words.

The minimum number of BCLK periods per LRCLK period is two times the selected word length.

LRCLK must be high for a period equal to the minimum number of BCLK periods, and low for a

minimum of the same period. Any mark-to-space ratio on LRCLK is acceptable provided the above

requirements are met.

The WM8742 will automatically detect when data with a LRCLK period of exactly 32 BCLKs is

received, and select 16-bit mode. This overrides any previously programmed word length. The

operating word length will revert to a programmed value only if a LRCLK period other than 32 BCLKs

is detected.

In DSP mode A or DSP mode B, the data is time multiplexed onto DIN. LRCLK is used as a frame

sync signal to identify the MSB of the first word. The minimum number of BCLKs per LRCLK period is

two times the selected word length. Any mark to space ratio is acceptable on LRCLK provided the

rising edge is correctly positioned.

LEFT JUSTIFIED MODE

In left justified mode, the MSB is sampled on the first rising edge of BCLK following a LRCLK

transition. LRCLK is high during the left data word and low during the right data word.

1/fs

LEFT CHANNEL

RIGHT CHANNEL

LRCLK

BCLK

DIN

1

2

3

n

1

2

3

n

n-2 n-1

MSB

LSB

MSB

LSB

Figure 14 Left Justified Mode Timing Diagram

22

Rev 4.4

WM8742

RIGHT JUSTIFIED MODE

In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK transition.

LRCLK is high during the left data word and low during the right data word.

1/fs

LEFT CHANNEL

RIGHT CHANNEL

LRCLK

BCLK

DIN

1

2

3

n

1

2

3

n

n-2 n-1

MSB

LSB

MSB

LSB

Figure 15 Right Justified Mode Timing Diagram

I²S MODE

In I²S mode, the MSB is sampled on the second rising edge of BCLK following a LRCLK transition.

LRCLK is low during the left data word and high during the right data word.

1/fs

LEFT CHANNEL

RIGHT CHANNEL

LRCLK

BCLK

1 BCLK

DIN

1

2

3

n

n-2 n-1

1

2

3

n

n-2 n-1

LSB

MSB

Figure 16 I²S Mode Timing Diagram

Rev 4.4

23

WM8742

DSP MODE A

In DSP mode A, the first bit is sampled on the BCLK rising edge following the one that detects a low to

high transition on LRCLK. No BCLK edges are allowed between the data words. The word order is

DIN left, DIN right.

1 BCLK

1/fs

LRCLK

BCLK

LEFT CHANNEL

RIGHT CHANNEL

NO VALID DATA

DIN

1

2

n

1

2

n

n-1

MSB

LSB

Input

Word Length (IWL)

Figure 17 DSP Mode A Timing Diagram

DSP MODE B

In DSP mode B, the first bit is sampled on the BCLK rising edge, which detects a low to high transition

on LRCLK. No BCLK edges are allowed between the data words. The word order is DIN left, DIN

right.

1/fs

LRCLK

BCLK

LEFT CHANNEL

RIGHT CHANNEL

NO VALID DATA

DIN

1

2

n

1

2

n

n-1

1

n-1

MSB

LSB

Input Word Length (IWL)

Figure 18 DSP Mode B Timing Diagram

24

Rev 4.4

WM8742

PCM MODE SAMPLING RATES

The WM8742 supports master clock rates of 128fs to 768fs, where fs is the audio sampling frequency

(LRCLK), typically 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz or 192kHz.

The WM8742 has a master clock detection circuit that automatically determines the relationship

between the master clock frequency and the sampling rate. The master clock should be synchronised

with LRCLK, although the WM8742 is tolerant of phase differences or jitter on this clock.

SAMPLING

RATE

MASTER CLOCK (MCLK) FREQUENCY (MHZ)

128fs

192fs

256fs

384fs

512fs

768fs

(LRCLK)

32kHz

Unavailable

11.2896

Unavailable

16.9344

8.192

11.2896

12.288

22.5792

24.576

12.288

16.9344

18.432

33.8688

36.864

16.384

22.5792

24.576

33.8688

36.864

44.1kHz

48kHz

88.2kHz

96kHz

Unavailable Unavailable

12.288

18.432

176.4kHz

192kHz

22.5792

33.8688

Unavailable Unavailable Unavailable Unavailable

24.576

36.864

Table 11 Typical Relationships Between Master Clock Frequency and Sampling Rate in normal

PCM mode

8FS MODE

Operation in 8FS mode requires that audio data for left and right channels is input separately on two

pins. DINR (pin 4) is the input for right channel data and DINL (pin 2) is the input for left channel data.

Hardware control of the device is not available.

The data can be input in two formats (left or right justified), selectable by register FMT[1:0], and two

word lengths (20 or 24 bit), selectable by register IWL[1:0]. In both modes the data is clocked into the

WM8742 MSB first.

For left justified data the word start is identified by the falling edge of LRCLK. The data is clocked in

on the next 20/24 BCLK rising edges. This format is compatible with industry-standard DSPs and

decoders such as the PMD100.

1/8fs

Sample 1

Sample 2

LRCLK

BCLK

1

2

3

n

1

2

3

n

n-2 n-1

DINL

DINR

MSB

LSB

MSB

LSB

1

n

1

n

n-2 n-1

MSB

LSB

MSB

LSB

Figure 19 8FS Mode Left Justified Timing Requirements

For right justified mode, the data is justified to the rising edge of LRCLK and the data is clocked in on

the preceding 20/24 BCLK rising edges before the LRCLK rising edge. This format is compatible with

industry standard DSPs and decoders such as the DF1704 or SM5842.

Rev 4.4

25

WM8742

1/8fs

Sample 1

Sample 2

LRCLK

BCLK

DINL

DINR

1

2

3

n

1

2

3

n

n-2 n-1

MSB

LSB

MSB

LSB

1

n

1

n

MSB

LSB

MSB

LSB

Figure 20 8FS Mode Right Justified Timing Requirements

In both modes the polarity of LRCLK can be switched using register bit LRP.

8FS MODE SAMPLING RATES

Since the data rate in 8FS mode is much faster than in standard PCM mode, there are restrictions on

the MCLK rate that can be used. Specifically, only 512fs and 768fs modes are permitted restricting

the sample rate to a maximum of 8x48kHz. The master clock should be synchronised with LRCLK,

although the WM8742 is tolerant of phase differences or jitter on this clock.

Unlike in normal PCM mode, the master clock detection circuit does not operate in 8FS mode. The

rate must be manually programmed using the control interface.

SAMPLING

RATE

LRCLK

FREQUENCY

(kHz)

MASTER CLOCK (MCLK)

FREQUENCY (MHz)

8fs

512fs

768fs

fs

32kHz

44.1kHz

48kHz

256

352.8

384

16.384

22.5792

24.576

33.8688

36.864

Table 12 Typical Relationships Between Master Clock Frequency and Sampling Rate in 8FS

Mode

AUDIO INTERFACE DAISY CHAINING

In daisy chain mode the DOUT pin outputs the audio data received on the DIN pin but delayed by two

times the input word length. When this output is connected to the DIN pin of the next device in the

chain, each WM8742 device will simultaneously sample different channel data in the same LRCLK

period. Daisy chaining is only available in DSP audio interface mode and is limited by a maximum

BCLK frequency of 24.576MHz.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8

Mode Control 2

08h

Daisy Chaining Multiple devices –

multichannel off one PCM feed.

4

DOUT

0

0 = No Output

1 = Output on pin 23.

Table 13 Daisy Chaining Audio Data Output Control

26

Rev 4.4

WM8742

The following diagram illustrates timing for a daisy chain with 2 WM8742 devices.

Figure 21 Audio Interface Daisy Chaining Timing

DSD MODE

The WM8742 supports DSD input bitstreams at 64x the oversampling rate. The data is supplied at a

rate of 64 bits per normal word clock. In DSD, no word clock is provided.

The WM8742 supports two channels of bitstream or DSD audio. Data bitstreams and the 64fs clock

are supplied to pins 1, 22 and 3 respectively. The MODESEL[1:0] register bits control whether the

device operates in DSD direct, DSD plus or PCM modes.

DSD DIRECT

In DSD Direct mode the internal digital filters are bypassed, the input bitstream data is subjected to

the minimal possible processing and is applied directly to the switched capacitor stage of the DAC

system. Using this mode provides the purest possible representation of a DSD stream.

It is normally desirable to use an external analogue post-DAC analogue filter to combine the

differential outputs of the DAC and remove high frequency energy from the output. This is particularly

important in the case of DSD operation due to the presence of high frequency energy which is a result

of the aggressive high order noise shaping used in the creation of the modulated DSD datastream.

DSD PLUS MODE

In DSD Plus mode the DSD data can be filtered in a similar manner to the data in the PCM path. The

DSD Plus filters are selected using register bits DSDFILT[1:0]. DSD Plus mode is not available under

hardware control.

Although DSD Plus mode requires that the bitstream is more heavily processed than DSD Direct, the

advantage is that DSD Plus mode reduces the high frequency energy which is a result of the

aggressive high order noise shaping used in the creation of the modulated DSD datastream. This

means that a less aggressive, lower order, analogue filter can be used at the output. Furthermore the

slew-rate requirements of the op-amps can be relaxed compared to DSD direct mode, due to the

reduction in high frequency energy.

Rev 4.4

27

WM8742

DSD DIGITAL AUDIO INTERFACE

DSD audio data is input to the WM8742 via the DSD digital audio interface. Two interface formats are

supported:



Uni-phase

Bi-phase

To use this interface apply left data on input pin 1 (LRCLK/DSDL) and pin 22 (OSR/DSDR). A DSD

clock is also required, running at 64FS, and should be applied to pin 3 (BCLK/DSD64CLK).

64/fs

DSDCLK64

DSDL

DSDR

L0

L1

L2

L3

R0

R1

R2

R3

Figure 22 Uni-phase DSD Mode Timing Diagram

64/fs

DSDCLK64

DSDL

DSDR

L0

L1

L2

L3

R0

R1

R2

R3

Figure 23 Bi-phase DSD Mode Timing Diagram

28

Rev 4.4

WM8742

SOFTWARE CONTROL MODE

Software control allows access to all features of the WM8742. Selection of control mode is achieved

by configuring the state of MODE/LRSEL (pin 24):

NAME

DESCRIPTION

24

MODE/

LRSEL

0 = Hardware control mode

1 = 3-wire serial control mode

Z = 2-wire serial control mode

Table 14 Control Mode Configuration

DSD AND PCM MODE SWITCHING

The audio interface mode can be switched between DSD and PCM by writing MODESEL[1:0] in R7.

It is recommended that the chip is forced into a MUTE state before dynamically switching modes.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DSD/PCM mode select :

00 = PCM mode

R7

Mode Control 1

07h

[1:0] MODESEL

00

01 = Direct DSD Operation

10 = DSD plus mode

11 = Unused

Table 15 PCM/DSD Software Mode Selection

PCM DIGITAL AUDIO INTERFACE CONTROL REGISTERS

The PCM digital audio input format is configured by register bits FMT [1:0] and IWL[1:0]:

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R5

Format Control

05h

Audio interface input word length

select

1:0

IWL[1:0]

10

00 = 16-bit

01 = 20-bit

10 = 24-bit

11 = 32-bit

Audio interface input format select

00 = Right justified

01 = Left justified

10 = I²S

3:2

FMT[1:0]

10

11 = DSP

Table 16 Interface Format Controls

Note:

1. In all modes, the data is signed 2's complement. The WM8742 digital filters always input 24-bit

data. If the interface is programmed into 32 bits, dither is applied according to Table 37 before

truncation to the internal wordlength.

Rev 4.4

29

WM8742

LRCLK POLARITY

In left justified, right justified or I²S modes, the LRP register bit controls the polarity of LRCLK. If this

bit is set high, the expected polarity of LRCLK will be the opposite of that shown in Figure 14, Figure

15 and Figure 16. If this feature is used as a means of swapping the left and right channels, a 1

sample phase difference will be introduced.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R5

Format Control

05h

4

LRP

0

LRCLK polarity select:

0 = normal LRCLK polarity

1 = inverted LRCLK polarity

Table 17 LRCLK Polarity Control

In DSP modes, the LRP register bit is used to select between DSP mode A and B (see Figure 17 and

Figure 18).

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DSP format select:

R5

Format Control

05h

4

LRP

0

0 = DSP mode A

1 = DSP mode B

Table 18 DSP Format Control

BCLK / DSDCLK64 POLARITY

In PCM mode, LRCLK and DIN are sampled on the rising edge of BCLK by default, and should ideally

change on the falling edge. Data sources which change LRCLK and DIN on the rising edge of BCLK

can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the

inverse of that shown in Figure 14, Figure 15, Figure 16, Figure 17 and Figure 18.

In DSD mode, DSDL and DSDR inputs are sampled a fixed delay after a falling 64fs clock edge.

When BCP is set in DSD mode, DSDL and DSDR are sampled a fixed delay after a rising 64fs clock

edge.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

BCLK / DSD64CLK polarity select:

0 = normal polarity

R5

Format Control

05h

5

BCP

0

1 = inverted polarity

Table 19 BCLK Polarity Control

OVERSAMPLING RATE CONTROL

The user has control of the oversampling ratio of the WM8742, and can set to the device to operate in

low, medium or high rate modes. For correct operation of the digital filtering and other processing on

the WM8742, the user must ensure the correct value of OSR[1:0] is set at all times.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Oversampling Rate Selection

00 = Low rate (32/44.1/48kHz)

01 = Medium rate (96kHz)

10 = High rate (192kHz)

11 = Unused

R7

Mode Control 1

07h

[6:5] OSR[1:0]

00

Table 20 Oversampling Rate Control

30

Rev 4.4

WM8742

MCLK/LRCLK RATIO CONTROL (NORMAL PCM MODE)

The ratio of MCLK/LRCLK can be programmed directly or auto-detected.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

MCLK to LRCLK sampling rate ratio

control (Normal PCM Mode):

R7

Mode Control 1

07h

[4:2]

SR[3:0]

000

000 = auto detect sample rate

001 = 128fs

010 = 192fs

011 = 256fs

100 = 384fs

101 = 512fs

110 = 768fs

111 = reserved

Table 21 MCLK/LRCLK Ratio Control (Normal PCM Mode)

8FS MODE

8FS Mode allows the use of custom digital filters by bypassing the WM8742 internal digital filters.

When MODE8X is set, the PCM data input to the WM8742 is applied only to the digital volume control

and then the analogue section of the DAC system, bypassing the digital filters.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

8FS mode select:

R7

Format Control

07h

7

MODE8X

0

0 = Normal operation

1 = 8FS mode (digital filters

bypassed)

Table 22 8FS Mode Control

MCLK/LRCLK RATIO CONTROL (8FS MODE)

In 8FS mode the choice of clock ratios and sampling rates is limited – see Table 12 for details.

Autodetect of MCLK/LRCLK ratio is not available in 8FS mode and must be set manually by the user

for correct operation.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

MCLK to LRCLK sampling rate ratio

control (8FS Mode):

R7

Mode Control 1

07h

[4:2]

SR[2:0]

000

000 = reserved

001 = 512fs

010 = 768fs

011 to 111 = reserved

Table 23 MCLK/LRCLK Ratio Control (8FS Mode)

ATTENUATION CONTROL

Each DAC channel can be attenuated digitally before being applied to the digital filter. Attenuation is

set to 0dB by default but can be set between 0dB and -127.5dB in 0.125dB steps using the ten

attenuation control bits LAT[4:0], LAT[9:5], RAT[4:0] and RAT[9:5].

All attenuation registers are double latched allowing new values to be pre-latched to both channels

before being updated synchronously. Setting the UPDATE bit on any attenuation write will cause all

pre-latched values to be immediately applied to the DAC channels.

Rev 4.4

31

WM8742

REGISTER

ADDRESS

BITS

LABEL

DEFAULT

DESCRIPTION

R0

LSBs of attenuation data for left channel in 0.125dB steps. See

Table 25 for details.

[4:0]

LAT[4:0]

00 (0dB)

DACLLSB

Attenuation

00h

5

Attenuation data load control for left channel.

0 = Store LAT[4:0] value but don’t update

UPDATE

0

1 = Store LAT[4:0] and update attenuation on registers 0-3

R1

MSBs of attenuation data for left channel in 4dB steps. See Table

25 for details.

[4:0]

5

LAT[9:5]

UPDATE

00 (0dB)

0

DACLMSB

Attenuation

01h

Attenuation data load control for left channel.

0 = Store LAT[9:5] value but don’t update

1 = Store LAT[9:5] and update attenuation on registers 0-3

R2

LSBs of attenuation data for right channel in 0.125dB steps. See

Table 25 for details.

[4:0]

5

RAT[4:0]

UPDATE

00 (0dB)

0

DACRLSB

Attenuation

Attenuation data load control for right channel.

0 = Store RAT[4:0] value but don’t update

02h

1 = Store RAT[4:0] and update attenuation on registers 0-3

R3

MSBs of attenuation data for right channel in 4dB step. See Table

25 for details.

[4:0]

5

RAT[9:5]

UPDATE

00 (0dB)

0

DACRMSB

Attenuation

Attenuation data load control for right channel.

0 = Store RAT[9:5] value but don’t update

03h

1 = Store RAT[9:5] and update attenuation on registers 0-3

Table 24 Attenuation Control

Note:

1. The UPDATE bit is not latched. If UPDATE=0, the attenuation value will be written to the pre-latch but not applied to the

relevant DAC. If UPDATE=1, all pre-latched values and the current value being written will be applied on the next input

sample.

DAC OUTPUT ATTENUATION

Registers LAT[9:0] and RAT[9:0] control the left and right channel attenuation. Table 25 shows how

the attenuation levels are configured by the 10-bit words.

L/RAT[9:0]

ATTENUATION LEVEL

000(hex)

0dB

001(hex)

-0.125dB

:

3FE(hex)

3FF(hex)

-127.75dB

-dB (mute)

Table 25 Attenuation Control Levels

ATTENUATION CONTROL MODE

Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and

right channel DACs from the next audio input sample. No update to the attenuation registers is

required for ATC to take effect. Right channels register settings are preserved regardless of the

status of ATC.

32

Rev 4.4

WM8742

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4

Volume Control

04h

2

ATC

0

Attenuator Control Mode:

0 = Right channels use Right

attenuation

1 = Right Channels use Left

Attenuation

Table 26 Attenuator Control Mode

VOLUME RAMP MODE

There are two ways to change the volume in the WM8742, controlled by VOL_RAMP. When

VOL_RAMP=0, the volume changes in a single step from the current volume setting to the new

volume when an update is applied to the gain control registers. When VOL_RAMP=1, the volume is

automatically ramped from the current volume setting to the new volume setting when an update is

applied to the volume control registers. The speed at which this happens is dependant on the sample

rate as shown in Table 27 below:

SAMPLE RATE (kHz)

RAMP RATE (ms/dB)

32

44.1

48

1.000

0.726

0.667

0.726

0.667

0.726

0.667

88.2

96

176.4

196

Table 27 Volume Ramp Rates

REGISTER ADDRESS

BIT

LABEL

VOL_

DEFAULT

DESCRIPTION

R4

Volume Control

04h

Volume ramp mode control:

0

0 = Apply volume change in a single

step.

RAMP

1 = Ramp between current volume

setting and new volume setting.

Table 28 Volume Ramp Control

ANTI-CLIPPING DIGITAL ATTENUATION MODE

Audio material is regularly recorded up to 0dB level and heavily compressed. This may cause clipping

and occasional distortion when the digital media is applied to a DAC. In order to prevent this in the

WM8742, an anti-clipping mode is provided, which attenuates the digital signal by 2dB as it is

processed through the digital filters.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Anti-clipping mode control:

0 = Off, 0dB attenuation

R4

Volume Control

04h

1

ATT2DB

0

1 = On, 2dB attenuation applied

Table 29 Anti-Clipping Digital Attenuation Control

Rev 4.4

33

WM8742

DSD PLUS GAIN CONTROL

The gain in the DSD Plus data path can be adjusted. The default setting provides a 1.4Vrms

differential output level.

REGISTER ADDRESS

BIT

LABEL

DSD_

GAIN

DEFAULT

DESCRIPTION

R8

Mode Control 2

08h

6

0

DSD Plus gain control:

0 = Low gain, 1.4Vrms differential

output level

1 = High gain, 2.0Vrms differential

output level

Table 30 DSD Plus Gain Control

MUTE MODES

0.000

0.020

0.040

0.060

0.080

0.100

0.120

0.140

Time (s)

Figure 24 Application and Release of Soft Mute

Figure 24 shows the application and release of SOFTMUTE for a full amplitude sinusoid being played

at 48kHz sampling rate. When SOFTMUTE (lower trace) is asserted, the WM8742 output (upper

trace) begins to decay exponentially from the DC level of the last input sample. The output decays

towards V_MIDin 1022x4/fs seconds. When SOFTMUTE is de-asserted, the signal gain will return to its

previous value.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Soft mute select

R4

PCM Control

04h

3

SOFTMUTE

0

0 = Normal operation

1 = Soft mute both channels

Table 31 Soft Mute Control

34

Rev 4.4

WM8742

ZERO FLAG OUTPUT

The WM8742 has one zero flag output pin, ZFLAG (pin 21). The zero flag feature is only valid for

PCM data.

The WM8742 asserts Logic 1 on the ZFLAG pin when a sequence of more than 1024 zeros is input to

the chip. The default value is a logical AND of both left and right channels. Under software control,

the user can also set the zero flag pin to respond to either the left channel OR the right channel.

The zero flag pin can be used to control external muting circuits if required.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Zero flag output:

R4

Volume Control

04h

6:5 ZEROFLR

[1:0]

00

00 = Pin assigned to logical AND of

LEFT and RIGHT channels

01 = Pin assigned to LEFT channel

10 = Pin assigned to RIGHT

channel

11 = ZFLAG disabled

Table 32 Zero Flag Output

ZFLAG FORCE HIGH CONTROL

It is possible to force the ZFLAG pin to Logic 1 by setting ZFLAG_HI=1 in R7. This is useful in

situations where an application processor may require manual control of an external mute circuit.

Setting ZFLAG_HI=0 will allow the ZFLAG pin to function as defined by ZFLAGLR[1:0].

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

ZFLAG Force High Control

0 = Normal operation

1 = Output Logic 1

R6

Mode Control 1

06h

7

ZFLAG_HI

0

Table 33 ZFLAG Force High Control

INFINITE ZERO DETECT

The IZD register configures the operation of the WM8742 analogue mute in conjunction with the zero

flag feature. Table 20 shows the interdependency of the MUTEB pin, the IZD register and the zero

flag.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

IZD control of analogue mute:

0 = Never analogue mute

R4

Volume Control

04h

4

IZD

0

1 = Analogue mute when ZFLAG

set

Table 20 Infinite Zero Detect Control

Rev 4.4

35

WM8742

MUTEB

ZFLAG

ZEROFLR

ZDET

DINL

DINR

DAC

SOFT ANA

L&R

Infinite

DSD Direct

Zero

Detect

IZD

Figure 25 Software Control Mode MUTEB and ZFLAG Configuration

DE-EMPHASIS

Setting the DEEMPH[1:0] register bits enables de-emphasis support in the WM8742 digital filters.

There are three de-emphasis filters, one each for sampling rates of 32kHz, 44.1kHz and 48kHz.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

De-emphasis mode select:

00 = De-emphasis Off

R6

Filter Control

06h

[6:5] DEEMPH

[1:0]

00

01 = De-emphasis 32kHz

10 = De-emphasis 44.1kHz

11 = De-emphasis 48kHz

Table 34 De-emphasis Control

OUTPUT PHASE REVERSAL

The REV register bit controls the phase of the output signal. Setting the REV bit causes the phase of

the output signal to be inverted.

Note: The REV bit can only be used in stereo mode. When in differential mono mode, the REV bit

must remain set as 0.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Analogue output phase control:

0 = Normal

R5

Format Control

05h

6

REV

0

1 = Inverted

Table 35 Output Phase Control

36

Rev 4.4

WM8742

DIFFERENTIAL MONO MODE

DIFF[1:0] sets the required differential output mode; normal stereo, reversed stereo, mono left or

mono right, as shown in Table 36.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

00 = Stereo

R8

Mode Control 2

08h

[3:2] DIFF[1:0]

00

10 = Stereo reverse (left and right

channels swapped)

01 = Mono left – differential outputs

VOUTLP (17) is left channel.

VOUTLN (16) is left channel

inverted.

VOUTRP (12) is left channel

inverted.

VOUTRN (13) is left channel.

11 = Mono right – differential outputs.

VOUTLP (17) is right channel

inverted.

VOUTLN (16) is right channel.

VOUTRP (12) is right channel.

VOUTRN (13) is right channel

inverted.

Table 36 Differential Output Modes

Using these controls a pair of WM8742 devices may be used to build a dual differential stereo

implementation with higher performance and differential output.

DITHER

Dither is applied whenever internal truncation occurs. It is also used when a 32 bit input word is

applied to the DAC prior to truncation to the internal wordlength. Three types of dither can be selected

to allow the sound quality if the device to be optimised.

TDF has a triangular probability density function and causes zero noise modulation i.e. the

quantisation noise is invariant to the changes in the signal level. This mode is recommended and is

selected by default.

RPDF has a rectangular probability density function and may cause noise modulation.

HPDF has a triangular probability density function with a high pass characteristic, which has a lower

noise at low frequencies at the expense of raised noise levels at higher frequencies.

Alternatively the dither can be disabled.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Digital filter dither mode select:

00 = dither off

R8

Mode Control 2

08h

[1:0] DITHER

[1:0]

10

01 = RPDF dither applied in Digital

filter

10 = TPDF dither applied in Digital

filter

11 = HPDF dither applied in Digital

filter

Note: DITHER[1:0] applies only to the

dither mode in the Digital filter.

Table 37 Dither Control

Rev 4.4

37

WM8742

NORMAL PCM MODE DIGITAL FILTER SELECTION

The WM8742 has a number of advanced digital filters that can be selected in all PCM operation

modes (with the exception of 8FS mode).

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Selects FIR1 filter response

000 = Response 1

R6

Filter Control

06h

[2:0]

FIRSEL

000

001 = Response 2

010 = Response 3

011 = Response 4

100 = Response 5

Table 38 PCM Advanced Digital Filter Selection

Five digital filters are available for selection in each of the three OSR modes (low, medium and high

rate) as selected by the OSR bit described in Table 20. It is recommended that the device is muted

before the filter response is changed to prevent noise as the filters are reset from appearing on the

outputs. A summary of the filter characteristics is given in Table 39 below:

OSR

RESPONSE

NOTES

Low

Linear phase half-band filter for backward compatibility

Minimum phase ‘soft-knee’ filter

Minimum phase half-band filter

Linear phase apodising filter

Minimum phase apodising filter

Linear phase ‘soft-knee’ filter

Minimum phase ‘soft-knee’ filter

Linear phase ‘brickwall’ filter

Minimum phase apodising filter

Linear phase apodising filter

Linear phase ‘soft-knee’ filter

Minimum phase ‘soft-knee’ filter

Linear phase ‘brickwall’ filter

Minimum phase apodising filter

Linear phase apodising filter

1

2

3

4

5

1

2

3

4

5

1

2

3

4

5

Medium

High

Table 39 PCM Digital Filter Summary

For full details of the filter characteristics available in normal PCM mode, please see Table 64 to Table

66 and Figure 28 to Figure 57.

8FS MODE DIGITAL FILTER

In 8FS mode, the majority of the internal filters are bypassed. In this mode, the data is filtered using

only the filter characteristic described by Table 67 and shown in Figure 58 and Figure 59.

38

Rev 4.4

WM8742

DSD PLUS FILTER SELECTION

The WM8742 has a number of compensation filters that can be selected in DSD Plus mode.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6

Filter Control

06h

Selects Compensation Filter

response

[4:3] DSDFILT

[1:0]

00

00 = Response 1

01 = Response 2

10 = Response 3

11 = Response 4

Table 40 DSD Plus Digital Filter Selection

It is recommended that the device is muted before the filter response is changed to prevent noise as

the filters are reset from appearing on the outputs.

Full details of these filters are described in Table 68 and Figure 60 to Figure 67.

DSD DIRECT DIGITAL FILTERS

The DSD Direct filters have been designed to provide the minimal of processing to the data with no

decimation, re-quantisation or noise-shaping, in order to preserve the signal integrity as much as

possible. As a result the filters have a wide bandwidth and a very gradual attenuation. It is

recommended that whichever DSD Direct filter is chosen it is augmented by analogue post-DAC

filtering in order to adhere to the Scarlet-Book SACD standard.

There are a total of four DSD Direct filter responses available, controlled by two register bits as

described in Table 41 below:

REGISTER ADDRESS

BIT

LABEL

DSD_NO_

NOTCH

DEFAULT

DESCRIPTION

DSD Direct 8fs Notch Filter

0: Enable 8fs notch filter

1: Disable 8fs notch filter

DSD Direct Filter Gain

0: High gain

R32

Additional Control 1

20h

0

1

DSD_

1

LEVEL

1: Low gain

Table 41 DSD Direct Digital Filter Selection

DSD MUTE CONTROL

In DSD Direct mode, an analogue mute can be applied at the output of the DAC. This is controlled by

register bit AMUTE.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DSD Direct mute control:

0 = mute off

R4

Volume Control

04h

7

AMUTE

0

1 = mute on

Table 42 DSD Analogue Mute Control

Rev 4.4

39

WM8742

POWER SAVING STANDBY CONTROL

Setting the PWDN register bit immediately connects all outputs to V_MIDand resets the digital sections

of the DAC system including the DLL, the audio interface and the DSP. Input data samples are not

preserved, but all control register settings are maintained. When PWDN is cleared the WM8742 will

repeat its power-on initialisation sequence.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power Down Mode Select:

0 = Normal Mode

R5

Format Control

05h

7

PWDN

0

1 = Power Down Mode

Table 43 Powerdown Control

HARDWARE CONTROL MODE

When the MODE pin is held ‘low’ the WM8742 is set to hardware control mode and a limited feature

set can be configured.

NAME

MODE/

LRSEL

DESCRIPTION

24

0 = Hardware control mode

1 = 3-wire serial control mode

Z = 2-wire serial control mode

Table 44 MODE/LRSEL Hardware Control Pin Function

DSD AND PCM MODE SWITCHING

The audio interface mode can be switched between DSD Direct and PCM by controlling the state of

pin DSD. It is recommended that the chip is forced into a MUTE state before dynamically switching

modes.

NAME

SCLK/DSD 0 = PCM Mode

1 = DSD Direct Mode

DESCRIPTION

27

Table 45 SCLK/DSD Hardware Control Pin Function

AUDIO INPUT FORMAT

Under hardware control, it is possible to select between four different modes of operation for the PCM

audio interface.

PIN NUMBER

NAME

28

23

DESCRIPTION

16-bit right justified

24-bit right justified

24-bit left justified

24-bit I²S

CSB/SADDR/I2S

IWO/DOUT

STATUS

0

1

0

1

0

1

Table 46 CSB/SADDR/I2S and IWO/DOUT Hardware Control Pin Function

40

Rev 4.4

WM8742

OVERSAMPLING RATE CONTROL

The user has control of the oversampling ratio of the WM8742, and can set to the device to operate in

low, medium or high rate modes. For optimum operation of the digital filtering and other processing

on the WM8742 in PCM hardware mode, the user must ensure the correct value of OSR is set at all

times. Table 47 shows the correct settings:

NAME

DESCRIPTION

22

Oversampling Rate Selection

0 = Low rate (32/44.1/48kHz)

Z = Medium rate (88.2/96kHz)

1 = High rate (176.4/192kHz)

OSR/DSDR

Table 47 OSR/DSDR Hardware Control Pin Function

MUTE PIN

A soft mute can be applied to the WM8742 in the digital domain in all PCM. A logic low on the

MUTEB pin will cause the attenuation to ramp to infinite attenuation at a rate of 1022x(4/fs). Setting

MUTEB high will return the signal gain to its previous value. Figure 26 shows the soft mute

characteristic.

In DSD Direct mode the MUTEB pin controls the analogue mute in the DAC. This analogue mute is a

‘hard’ mute and is applied and released as soon as the MUTEB pin is toggled.

NAME

MUTEB/

SDOUT

DESCRIPTION

Mute control

25

0 = Mute on (no output)

1 = Mute off (normal operation

Table 48 MUTEB Hardware Control Pin Function

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

Time (s)

Figure 26 Hardware Control Mode Soft Mute Characteristic

Rev 4.4

41

WM8742

ZERO FLAG

In hardware control mode the ZFLAG pin asserts when 1024 consecutive zero samples are applied to

the left and right channels of the WM8742 when in PCM mode. In DSD mode, the ZFLAG has no

function.

In hardware mode there is no access to the infinite zero detect and so there is no automute function.

If this functionality is required, software mode must be used. Figure 27 shows the MUTEB and

ZFLAG configuration.

MUTEB

ZFLAG

ZDET

DINL

DINR

DAC

SOFT ANA

L&R

DSD Direct

Figure 27 Hardware Control Mode MUTEB and ZFLAG Configuration

DE-EMPHASIS CONTROL AND ANTI-CLIPPING MODE

In hardware control mode, de-emphasis is supported with a maximum error of +1.5dB at a sampling

rate of 44.1kHz.

Audio material is regularly recorded up to 0dB level and heavily compressed. This causes clipping

and distortion when the digital media is applied to a DAC. In order to prevent this in the WM8742, an

anti-clipping mode is provided, which attenuates the digital signal by 2dB as it is processed through

the digital filters.

Under hardware control de-emphasis and the anti-clipping mode are only available when using PCM

mode.

NAME

SDIN/

DESCRIPTION

Deemphasis Control

26

DEEMPH

0 = De-emphasis off

1 = De-emphasis on

Z = Digital filter anti-clipping mode

Table 49 DEEMPH Hardware Control Pin Function

42

Rev 4.4

WM8742

DIGITAL FILTER SELECTION

The WM8742 includes a wide range of digital filters. A limited set of these can be selected in

hardware control mode as listed in Table 50. Full details of each digital filter response can be found in

section PCM Digital Filter Selection, from page 38.

NAME

FSEL/

DINR

DESCRIPTION

4

Digital filter selection

(32/44.1/48kHz):

0 = Response 1

1 = Response 5

Z = Response 4

Digital filter selection (88.2/96kHz

and 176.4/192kHz):

0 = Response 1

1 = Response 3

Z = Response 2

Table 50 FSEL/DINR Hardware Control Pin Function

There is no choice of digital filters in DSD Direct mode – only the very minimal filtering described in

Figure 72 and Figure 73 is available.

DIFFERENTIAL MONO MODE

If DIFFHW (pin 6) is held to Logic 1, hardware controlled differential mono mode is selected. This

overrides any other control pin or register bit. Differential mono mode allows the user to build a dual

differential stereo DAC implementation with higher performance and differential output. DIFFHW is

used in conjunction with MODE/LRSEL (pin 24) to define a ‘left’ or ‘right’ DAC as shown in Table 51.

PIN NUMBER

NAME

6

24

DESCRIPTION

DIFFHW

MODE/LRSEL

0

1

0

Z

1

0

Hardware control (stereo)

2-wire Software Control

3-wire software control)

Mono Left – differential outputs

VOUTLP = left channel

VOUTLN = left channel inverted

VOUTRP = left channel inverted

VOUTRN = left channel

Mono right – differential outputs

VOUTLP = right channel inverted

VOUTLN = right channel

1

VOUTRP = right channel

VOUTRN = right channel inverted

Table 51 DIFFHW and MODE/LRSEL Hardware Control Pin Functions

Differential mono mode is available for all PCM hardware controlled modes and DSD Direct hardware

mode.

Rev 4.4

43

WM8742

OVERVIEW OF FUNCTIONS

The WM8742 has many modes of operation, and certain restrictions on what functions are available in

which modes. Table 52 gives an overview of the functions available in hardware and software control

modes across all modes of operation:

SOFTWARE MODE

HARDWARE MODE

FUNCTION

NORMAL

PCM

8FS

DSD

DIRECT

NORMAL

PCM

DSD

DIRECT

MODE

PLUS

Selectable Digital Filters

Deemphasis Support

Adjustable DSP Dither

Differential Mono Mode

Digital Softmute

5

4

3























































Analogue Mute

Zero Detect (ZFLAG)

Automute Function

Anti-Clipping Mode

Digital Attenuation

Powerdown Mode

Audio Interface Daisy Chain



3-wire Software Interface

Daisy Chain





Table 52 Comparison of Functions Available across Operating Modes





= function available

= function not available

44

Rev 4.4

WM8742

REGISTER MAP

Reg

Name

Addr

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

DACLLSB

0

UPDATELL

LAT[4:0]

0

00h

0x000

0x00A

0x000

0x002

0x000

Attenuation

DACLMSB

Attenuation

0

UPDATELM

UPDATERL

UPDATERM

LAT[9:5]

RAT[4:0]

RAT[9:5]

ATC

1

2

01h

02h

03h

04h

05h

06h

07h

08h

09h

20h

DACRLSB

Attenuation

DACRMSB

Attenuation

0

3

SOFT

MUTE

AMUTE

PWDN

ZFLAG_HI

MODE8X

0

ZEROFLR[1:0]

IZD

ATT2DB VOL_RAMP

IWL[1:0]

4

Volume Control

Format Control

Filter Control

REV

BCP

LRP

FMT[1:0]

5

DEEMPH[1:0]

DSDFILT[1:0]

FIRSEL[2:0]

6

OSR[1:0]

SR[2:0]

MODESEL[1:0]

DITHER[1:0]

7

Mode Control 1

Mode Control 2

Software Reset

DSD_

GAIN

SDOUT

DOUT

RESET

0

DIFF[1:0]

8

9

Additional

Control 1

DSD_

DSD_NO

_NOTCH

0

32

LEVEL

Rev 4.4

45

WM8742

REGISTER

ADDRESS

R0

BITS

NAME

DEFAULT

DESCRIPTION

LSBs of attenuation data for left channel in 0.125dB steps. See Table

25 for details.

[4:0]

5

LAT[4:0]

UPDATE

00 (0dB)

0

DACLLSB

Attenuation

00h

Attenuation data load control for left channel.

0 = Store LAT[4:0] value but don’t update

1 = Store LAT[4:0] and update attenuation on registers 0-3

Table 53 R0 DACL LSB Attenuation Control Register

REGISTER

ADDRESS

R1

BITS

NAME

DEFAULT

DESCRIPTION

MSBs of attenuation data for left channel in 4dB steps. See Table 25

for details.

[4:0]

5

LAT[9:5]

UPDATE

00 (0dB)

0

DACLMSB

Attenuation

01h

Attenuation data load control for left channel.

0 = Store LAT[9:5] value but don’t update

1 = Store LAT[9:5] and update attenuation on registers 0-3

Table 54 R1 DACL MSB Attenuation Control Register

REGISTER

ADDRESS

R2

BITS

NAME

DEFAULT

DESCRIPTION

LSBs of attenuation data for right channel in 0.125dB steps. See

Table 25 for details.

[4:0]

5

RAT[4:0]

UPDATE

00 (0dB)

0

DACRLSB

Attenuation

Attenuation data load control for right channel.

0 = Store RAT[4:0] value but don’t update

02h

1 = Store RAT[4:0] and update attenuation on registers 0-3

Table 55 R2 DACR LSB Attenuation Control Register

REGISTER

ADDRESS

R3

BITS

NAME

DEFAULT

DESCRIPTION

MSBs of attenuation data for right channel in 4dB step. See Table 25

for details.

[4:0]

5

RAT[9:5]

UPDATE

00 (0dB)

0

DACRMSB

Attenuation

Attenuation data load control for right channel.

0 = Store RAT[9:5] value but don’t update

03h

1 = Store RAT[9:5] and update attenuation on registers 0-3

Table 56 R3 DACR MSB Attenuation Control Register

46

Rev 4.4

WM8742

REGISTER

ADDRESS

R4

BITS

NAME

DEFAULT

DESCRIPTION

Ramps volume from existing attenuation setting to new setting when

UPDATE applied.

0

VOL_RAMP

0

Volume

Control

0: Step volume change

04h

1: Ramp volume change

Anti-clipping mode control. Attenuates PCM gain path by 2 dB:

0: 0dB gain

1

2

ATT2DB

ATC

0

1: -2dB gain

Attenuator Control Mode:

0 = Right channels use Right attenuation

1 = Right Channels use Left Attenuation

Soft mute select

3

SOFTMUTE

IZD

0

0: Normal Operation

1: Soft mute both channels

Enables infinite zero detect (detects 1024 zeros on input):

0 = Disable infinite zero detect

1 = Enable infinite zero detect

Zero flag output:

4

0

6:5

ZEROFLR

[1:0]

00

00 = Pin assigned to logical AND of LEFT and RIGHT channels

01 = Pin assigned to LEFT channel

10 = Pin assigned to RIGHT channel

11 = ZFLAG disabled

Applies analogue mute in DSD mode

0 = Normal operation

7

AMUTE

0

1 = Analogue mute applied

Table 57 R4 Volume Control Register

REGISTER

ADDRESS

R5

BITS

NAME

DEFAULT

DESCRIPTION

Audio interface input word length.

00 = 16-bit

[1:0]

IWL[1:0]

10

Format

Control

01 = 20-bit

05h

10 = 24-bit

11 = 32-bit

Audio data format select.

00 = right justified mode

01 = left justified mode

10 = I2S mode

[3:2]

FMT[1:0]

10

11 = DSP mode

Polarity select for LRCLK/DSP mode select.

0 = normal LRCLK polarity/DSP mode A

1 = inverted LRCLK polarity/DSP mode B

BCLK / DSD64CLK polarity select:

0 = normal polarity

4

5

6

7

LRP

BCP

0

1 = inverted polarity

REV

Analogue output phase control:

0 = Normal

1 = Inverted

Power Down Mode Select:

0 = Normal Mode

PWDN

1 = Power Down Mode

Table 58 R5 Format Control Register

Rev 4.4

47

WM8742

REGISTER

ADDRESS

R6

BITS

NAME

DEFAULT

DESCRIPTION

Select advanced digital filter response:

000 = Response 1

[2:0]

FIRSEL

000

Filter Control

06h

001 = Response 2

010 = Response 3

011 = Response 4

100 = Response 5

Select DSD compensation filter response:

00 = Response 1

[4:3]

[6:5]

7

DSDFILT

00

0

01 = Response 2

10 = Response 3

11 = Response 4

De-emphasis mode select:

00 = De-emphasis Off

01 = De-emphasis 32kHz

10 = De-emphasis 44.1kHz

11 = De-emphasis 48kHz

ZFLAG Force High Control

0 = Normal operation

1 = Output Logic 1

DEEMPH

[1:0]

ZFLAG_HI

Table 59 R6 Filter Control Register

REGISTER

ADDRESS

R7

BITS

NAME

DEFAULT

DESCRIPTION

DSD/PCM mode select.

00 = PCM mode

[1:0]

MODESEL

[1:0]

00

Mode Control 1

07h

01 = DSD Direct mode

10 = DSD Plus mode

11 = Unused

MCLK to LRCLK sampling rate ratio control:

000 = auto detect sample rate

001 = 128fs

[4:2]

SR[3:0]

000

010 = 192fs

011 = 256fs

100 = 384fs

101 = 512fs

110 = 768fs

Selects low, medium or high sample rate mode for filter selection

(equivalent to OSR pin functionality in Hardware Mode)

[6:5]

OSR[1:0]

MODE8X

00

00 = Low rate (32/44.1/48kHz)

01 = Medium rate (96kHz)

10 = High rate (192kHz)

11 = Unused

8FS mode select:

7

0

0 = Normal operation

1 = 8FS mode (digital filters bypassed)

Table 60 R7 Mode Control Register 1

48

Rev 4.4

WM8742

REGISTER

ADDRESS

R8

BITS

NAME

DEFAULT

DESCRIPTION

ALU dither mode select:

[1:0] DITHER[1:0]

10

00 = dither off

Mode Control 2

08h

01 = RPDF dither applied in ALU

10 = TPDF dither applied in ALU

11 = HPDF dither applied in ALU

Note: DITHER[1:0] applies only to the dither mode in the ALU.

00 = Stereo

[3:2]

DIFF[1:0]

00

10 = Stereo reverse (left and right channels swapped)

01 = Mono left – differential outputs

VOUTLP is left channel.

VOUTLN is left channel inverted.

VOUTRP is left channel inverted.

VOUTRN is left channel.

11 = Mono right – differential outputs.

VOUTLP is right channel inverted.

VOUTLN is right channel.

VOUTRP is right channel.

VOUTRN is right channel inverted.

Daisychaining Mode. Audio data output control:

0 = No audio data daisychaining

1 = Audio data output on pin 23

4

5

6

DOUT

SDOUT

0

Daisychaining Mode. Control data output control:

0 = No control data daisychaining

1 = Control data output on pin 25

DSD Plus gain control:

DSD_GAIN

0 = Low gain, 1.4Vrms differential output level

1 = High gain, 2.0Vrms differential output level

Table 61 R8 Mode Control Register 2

REGISTER

ADDRESS

R9

BITS

NAME

DEFAULT

DESCRIPTION

Software reset. Writing to the register resets the entire chip, including

the register map.

[7:0]

RESET

00000000

Software reset

09h

Table 62 R9 Software Reset Control Register

REGISTER

ADDRESS

R32

BITS

NAME

DEFAULT

DESCRIPTION

DSD Direct 8fs Notch Filter

0: Enable 8fs notch filter

1: Disable 8fs notch filter

0

DSD_NO_

NOTCH

0

Additional

Control 1

20h

DSD Direct Filter Gain

0: High Gain

1

DSD_LEVEL

1

1: Low Gain

Table 63 R32 Additional Control 1

Rev 4.4

49

WM8742

DIGITAL FILTER CHARACTERISTICS

PCM MODE FILTER CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Low Rate (32/44.1/48kHz) PCM Filter Response 1

 0.000057dB

0.454fs

Passband

0.000057

dB

Passband Ripple

Stopband

0.546fs

-111.8

dB

fs

Stopband Attenuation

Attenuation at fs/2

Group Delay

-6.02

43

Low Rate (32/44.1/48kHz) PCM Filter Response 2

 0.000036 dB

0.408fs

Passband

0.000036

dB

Passband Ripple

Stopband

0.522fs

-111.1

dB

fs

Stopband Attenuation

Attenuation at fs/2

Group Delay

Fs/2

-28.07

8

Low Rate (32/44.1/48kHz) PCM Filter Response 3

 0.000058 dB

0.454fs

Passband

0.000058

dB

Passband Ripple

Stopband

0.546fs

-110.3

dB

fs

Stopband Attenuation

Attenuation at fs/2

Group Delay

Fs/2

-6.43

7

Low Rate (32/44.1/48kHz) PCM Filter Response 4

 0.000066 dB

0.417fs

Passband

0.000066

dB

Passband Ripple

Stopband

0.500fs

-110.4

dB

fs

Stopband Attenuation

Attenuation at fs/2

Group Delay

Fs/2

-116.19

47

Low Rate (32/44.1/48kHz) PCM Filter Response 5

 0.000041 dB

0.417fs

Passband

0.000041

dB

Passband Ripple

Stopband

0.500fs

-111.8

dB

fs

Stopband Attenuation

Attenuation at fs/2

Group Delay

Fs/2

-112.45

8

Table 64 Low Rate PCM Filter Characteristics

50

Rev 4.4

WM8742

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Medium Rate (88.2/96kHz) PCM Filter Response 1

 0.000021 dB

0.208fs

Passband

0.000021

dB

Passband Ripple

Stopband

0.500fs

-120.3

dB

fs

Stopband Attenuation

Attenuation at fs/2

Group Delay

Fs/2

-120.41

17

Medium Rate (88.2/96kHz) PCM Filter Response 2

 0.000014 dB

0.208fs

Passband

0.000014

dB

Passband Ripple

Stopband

0.500fs

-120.8

dB

fs

Stopband Attenuation

Attenuation at fs/2

Group Delay

Fs/2

-127.96

9

Medium Rate (88.2/96kHz) PCM Filter Response 3

 0.000048 dB

0.417fs

Passband

0.000048

dB

Passband Ripple

Stopband

0.500fs

-115.5

dB

fs

Stopband Attenuation

Attenuation at fs/2

Group Delay

Fs/2

-116.89

48

Medium Rate (88.2/96kHz) PCM Filter Response 4

 0.000021 dB

0.208fs

Passband

0.000021

dB

Passband Ripple

Stopband

0.458fs

-120.0

dB

fs

Stopband Attenuation

Attenuation at fs/2

Group Delay

Fs/2

-126.82

9

Medium Rate (88.2/96kHz) PCM Filter Response 5

 0.000023 dB

0.208fs

Passband

0.000023

dB

Passband Ripple

Stopband

0.458fs

-122.5

dB

fs

Stopband Attenuation

Attenuation at fs/2

Group Delay

Fs/2

-130.52

8

Table 65 Medium Rate PCM Filter Characteristics

Rev 4.4

51

WM8742

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

High Rate (176.4/192kHz) PCM Filter Response 1

 0.000010 dB

0.104fs

Passband

0.000010

dB

Passband Ripple

Stopband

0.500fs

-120.0

dB

fs

Stopband Attenuation

Attenuation at fs/2

Group Delay

Fs/2

-127.5

10

High Rate (176.4/192kHz) PCM Filter Response 2

 0.000031 dB

0.104fs

Passband

0.000031

dB

Passband Ripple

Stopband

0.500fs

-120.0

dB

fs

Stopband Attenuation

Attenuation at fs/2

Group Delay

Fs/2

-124.93

4

High Rate (176.4/192kHz) PCM Filter Response 3

 0.000873 dB

0.400fs

Passband

0.000873

dB

Passband Ripple

Stopband

0.500fs

-110.1

dB

fs

Stopband Attenuation

Attenuation at fs/2

Group Delay

Fs/2

-112.67

31

High Rate (176.4/192kHz) PCM Filter Response 4

 0.000015 dB

0.104fs

Passband

0.000015

dB

Passband Ripple

Stopband

0.400fs

-120.0

dB

fs

Stopband Attenuation

Attenuation at fs/2

Group Delay

Fs/2

-120.58

6

High Rate (176.4/192kHz) PCM Filter Response 5

 0.000001 dB

0.104fs

Passband

0.000001

dB

Passband Ripple

Stopband

0.400fs

-122.8

dB

fs

Stopband Attenuation

Attenuation at fs/2

Group Delay

Fs/2

-128.58

18

Table 66 High Rate PCM Filter Characteristics

8FS MODE FILTER CHARACTERISTICS

PARAMETER

8FS Mode Filter

Passband

TEST CONDITIONS

 0.000021 dB

-3dB point

MIN

TYP

MAX

UNIT

0.455

fs

dB

kHz

fs

0.000021

Passband Ripple

Filter Cut-off

121.13

5

Group Delay

Table 67 8FS Mode Filter Characteristics

52

Rev 4.4

WM8742

DSD PLUS MODE FILTER CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DSD Plus Filter Response 1

 0.020423 dB

22.48

kHz

dB

Passband

0.020423

Passband Ripple

Stopband

127.69

-38.51

kHz

dB

Stopband Attenuation

Filter Cut-off

-3dB point

58.91

71

kHz

fs

Group Delay

DSD Plus Filter Response 2

 0.011308dB

23.04

kHz

dB

Passband

0.011308

Passband Ripple

Stopband

120.41

-44.52

kHz

dB

Stopband Attenuation

Filter Cut-off

-3dB point

49.83

127

kHz

fs

Group Delay

DSD Plus Filter Response 3

 0.019762 dB

27.35

kHz

dB

Passband

0.019762

Passband Ripple

Stopband

70.14

kHz

dB

-26.28

Stopband Attenuation

Filter Cut-off

-3dB point

49.74

46

kHz

Fs

Group Delay

DSD Plus Filter Response 4

 0.004140 dB

20.24

kHz

dB

Passband

0.004140

Passband Ripple

Stopband

70.03

kHz

dB

-48.05

Stopband Attenuation

Filter Cut-off

-3dB point

49.78

127

kHz

fs

Group Delay

Table 68 DSD Plus Filter Characteristics

Rev 4.4

53

WM8742

PCM MODE FILTER RESPONSE

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.5

1

1.5

2

2.5

3

3.5

4

0

0.1

0.2

0.3

0.4

0.5

Frequency (fs)

Figure 28 Low Rate PCM Filter 1 Frequency Response

Figure 29 Low Rate PCM Filter 1 Ripple

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.1

0.2

0.3

0.4

0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

Frequency (fs)

Figure 30 Low Rate PCM Filter 2 Frequency Response

Figure 31 Low Rate PCM Filter 2 Ripple

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.1

0.2

0.3

0.4

0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

Frequency (fs)

Figure 32 Low Rate PCM Filter 3 Frequency Response

Figure 33 Low Rate PCM Filter 3 Ripple

54

Rev 4.4

WM8742

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.1

0.2

0.3

0.4

0.2

0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

2

Frequency (fs)

Figure 34 Low Rate PCM Filter 4 Frequency Response

Figure 35 Low Rate PCM Filter 4 Ripple

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.1

0.2

0.3

0.5

0

0.5

1

1.5

2

2.5

3

3.5

Frequency (fs)

Figure 36 Low Rate PCM Filter 5 Frequency Response

Figure 37 Low Rate PCM Filter 5 Ripple

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.05

0.1

0.15

0.25

0

0.5

1

1.5

Frequency (fs)

Figure 38 Medium Rate PCM Filter 1 Frequency Response

Figure 39 Medium Rate PCM Filter 1 Ripple

Rev 4.4

55

WM8742

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.05

0.1

0.15

0.2

0.25

0

0.5

1

1.5

2

Frequency (fs)

Figure 40 Medium Rate PCM Filter 2 Frequency Response

Figure 41 Medium Rate PCM Filter 2 Ripple

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.05

0.1

0.15

0.25

0

0.5

1

1.5

Frequency (fs)

Figure 42 Medium Rate PCM Filter 3 Frequency Response

Figure 43 Medium Rate PCM Filter 3 Ripple

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.05

0.1

0.15

0.25

0

0.5

1

1.5

Frequency (fs)

Figure 44 Medium Rate PCM Filter 4 Frequency Response

Figure 45 Medium Rate PCM Filter 4 Ripple

56

Rev 4.4

WM8742

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.05

0.1

0.15

0.2

0.25

0.15

0

0.5

1

1.5

2

1

Frequency (fs)

Figure 46 Medium Rate PCM Filter 5 Frequency Response

Figure 47 Medium Rate PCM Filter 5 Ripple

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.025

0.05

0.075

0.1

0.125

0

0.2

0.4

0.6

0.8

Frequency (fs)

Figure 48 High Rate PCM Filter 1 Frequency Response

Figure 49 High Rate PCM Filter 1 Ripple

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.025

0.05

0.075

0.1

0.125

0

0.2

0.4

0.6

0.8

Frequency (fs)

Figure 50 High Rate PCM Filter 2 Frequency Response

Figure 51 High Rate PCM Filter 2 Ripple

Rev 4.4

57

WM8742

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.025

0.05

0.075

Frequency (fs)

0.1

0.125

0.15

0

0.2

0.4

0.6

0.8

1

Frequency (fs)

Figure 52 High Rate PCM Filter 3 Frequency Response

Figure 53 High Rate PCM Filter 3 Ripple

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.025

0.05

0.075

Frequency (fs)

0.15

0

0.2

0.4

0.6

0.8

Frequency (fs)

Figure 54 High Rate PCM Filter 4 Frequency Response

Figure 55 High Rate PCM Filter 4 Ripple

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.025

0.05

0.075

0.15

0

0.2

0.4

0.6

0.8

Frequency (fs)

Figure 56 High Rate PCM Filter 5 Frequency Response

Figure 57 High Rate PCM Filter 5 Ripple

58

Rev 4.4

WM8742

8FS MODE FILTER RESPONSE

0.1

0.08

0.06

0.04

0.02

0

-50

-100

-150

-200

-0.02

-0.04

-0.06

-0.08

-0.1

0

0.1

0.2

0.3

0.4

0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

Frequency (fs)

Figure 58 8FS Mode Filter Frequency Response

Figure 59 8FS Mode Filter Ripple

DSD PLUS MODE FILTER RESPONSE

15

10

5

0

-20

-40

0

-60

-5

-80

-10

-15

-100

0

5

10

15

20

25

0

50

100

150

200

Frequency (kHz)

Figure 60 DSD Plus Mode Filter 1 Frequency Response

Figure 61 DSD Plus Mode Filter 1 Ripple

15

10

5

0

-20

-40

0

-60

-5

-80

-10

-15

-100

0

5

10

15

20

25

0

50

100

150

200

Frequency (kHz)

Figure 62 DSD Plus Mode Filter 2 Frequency Response

Figure 63 DSD Plus Mode Filter 2 Ripple

Rev 4.4

59

WM8742

15

10

5

0

-20

-40

0

-60

-5

-80

-10

-15

-100

0

5

10

15

20

25

0

50

100

150

200

Frequency (kHz)

Figure 64 DSD Plus Mode Filter 3 Frequency Response

Figure 65 DSD Plus Mode Filter 3 Ripple

15

10

5

0

-20

-40

0

-60

-5

-80

-10

-15

-100

0

5

10

15

20

25

0

50

100

150

200

Frequency (kHz)

Figure 66 DSD Plus Mode Filter 4 Frequency Response

Figure 67 DSD Plus Mode Filter 4 Ripple

DSD DIRECT MODE FILTER RESPONSE

15

10

5

0

-20

-40

0

-60

-5

-80

-10

-15

-100

0

5

10

15

20

25

0

50

100

150

200

250

300

350

400

Frequency (kHz)

Figure 69 DSD Direct Mode Standard Low Gain Filter Ripple

(Normalised)

Figure 68 DSD Direct Mode Standard Low Gain Filter

Frequency Response

60

Rev 4.4

WM8742

25

20

15

10

5

0

-20

-40

0

-5

-60

-10

-15

-20

-25

-80

-100

0

5

10

15

20

25

0

50

100

150

200

250

300

350

400

Frequency (kHz)

Figure 70 DSD Direct Mode Standard High Gain Filter

Frequency Response

Figure 71 DSD Direct Mode Standard High Gain Filter Ripple

(Normalised)

15

10

5

0

-20

-40

0

-60

-5

-80

-10

-15

-100

0

5

10

15

20

25

0

50

100

150

200

250

300

350

Frequency (kHz)

Figure 73 DSD Direct Mode 8fs Notch Low Gain Filter Ripple

(Normalised)

Figure 72 DSD Direct Mode 8fs Notch Low Gain Filter

Frequency Response

20

15

10

5

0

-20

-40

0

-5

-60

-10

-15

-20

-80

-100

0

5

10

15

20

25

0

50

100

150

200

250

300

350

Frequency (kHz)

Figure 74 DSD Direct Mode 8fs Notch High Gain Filter

Frequency Response

Figure 75 DSD Direct Mode 8fs Notch High Gain Filter Ripple

(Normalised)

Rev 4.4

61

WM8742

DE-EMPHASIS FILTER RESPONSE

0.0

-2.0

0.4

0.3

0.2

0.1

-4.0

0.0

-6.0

-0.1

-0.2

-0.3

-0.4

-8.0

-10.0

0

5000

10000

15000

20000

0

5000

10000

15000

20000

Frequency (Hz)

Figure 76 De-emphasis Frequency Response (32kHz)

Figure 77 De-emphasis Error (32kHz)

0.0

-2.0

0.4

0.3

0.2

0.1

-4.0

0.0

-6.0

-0.1

-0.2

-0.3

-0.4

-8.0

-10.0

0

5000

10000

15000

20000

0

5000

10000

Frequency (Hz)

Figure 78 De-emphasis Fequency Response (44.1kHz)

Figure 79 De-emphasis Error (44.1kHz)

0.0

-2.0

0.4

0.3

0.2

0.1

-4.0

0.0

-6.0

-0.1

-0.2

-0.3

-0.4

-8.0

-10.0

0

5000

10000

15000

20000

0

5000

10000

Frequency (Hz)

Figure 80 De-emphasis Frequency Response (48kHz)

Figure 81 De-emphasis Error (48kHz)

62

Rev 4.4

WM8742

APPLICATIONS INFORMATION

Figure 82 External Components

Figure 83 External Filter Components

Rev 4.4

63

WM8742

PACKAGE DIMENSIONS

DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm)

DM007.E

b

e

28

15

E1

E

GAUGE

PLANE



14

1

D

0.25

L

c

A1

L₁

A A2

-C-

0.10 C

SEATING PLANE

Dimensions

(mm)

NOM

-----

Symbols

MIN

-----

MAX

A

A₁

A₂

b

c

D

e

E

E₁

L

2.0

0.25

1.85

0.38

0.25

10.50

0.05

1.65

0.22

0.09

9.90

-----

1.75

0.30

-----

10.20

0.65 BSC

7.80

7.40

5.00

0.55

8.20

5.60

0.95

5.30

0.75

L₁



1.25 REF

0^o

4^o

8^o

JEDEC.95, MO-150

REF:

NOTES:

A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.

B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.

D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

64

Rev 4.4

WM8742

IMPORTANT NOTICE

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find one nearest you, go to www.cirrus.com.

For the purposes of our terms and conditions of sale, "Preliminary" or "Advanced" datasheets are non-final datasheets that include

but are not limited to datasheets marked as “Target”, “Advance”, “Product Preview”, “Preliminary Technical Data” and/or “Pre-

production.” Products provided with any such datasheet are therefore subject to relevant terms and conditions associated with

"Preliminary" or "Advanced" designations. The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic, Inc.;

and other companies in the Cirrus Logic group (collectively either “Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms

and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and

limitation of liability. Software is provided pursuant to applicable license terms. Cirrus Logic reserves the right to make changes to its

products and specifications or to discontinue any product or service. Customers should therefore obtain the latest version of relevant

information from Cirrus Logic to verify that the information is current and complete. Testing and other quality control techniques are

utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily performed. In

order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to

minimize inherent or procedural hazards. Cirrus Logic is not liable for applications assistance or customer product design. The

customer is solely responsible for its product design, including the specific manner in which it uses Cirrus Logic components, and

certain uses or product designs may require an intellectual property license from a third party. Features and operations described

herein are for illustrative purposes only and do not constitute a suggestion or instruction to adopt a particular product design or a

particular mode of operation for a Cirrus Logic component.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL

INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS LOGIC PRODUCTS

ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY,

AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL

APPLICATIONS. INCLUSION OF CIRRUS LOGIC PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT

THE CUSTOMER’S RISK AND CIRRUS LOGIC DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR

IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE,

WITH REGARD TO ANY CIRRUS LOGIC PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR

CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS LOGIC PRODUCTS IN CRITICAL APPLICATIONS,

CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS LOGIC, ITS OFFICERS, DIRECTORS, EMPLOYEES,

DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT

MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

This document is the property of Cirrus Logic, and you may not use this document in connection with any legal analysis concerning

Cirrus Logic products described herein. No license to any technology or intellectual property right of Cirrus Logic or any third party is

granted herein, including but not limited to any patent right, copyright, mask work right, or other intellectual property rights. Any

provision or publication of any third party’s products or services does not constitute Cirrus Logic’s approval, license, warranty or

endorsement thereof. Cirrus Logic gives consent for copies to be made of the information contained herein only for use within your

organization with respect to Cirrus Logic integrated circuits or other products of Cirrus Logic, and only if the reproduction is without

alteration and is accompanied by all associated copyright, proprietary and other notices and conditions (including this notice). This

consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for

creating any work for resale. This document and its information is provided “AS IS” without warranty of any kind (express or implied).

All statutory warranties and conditions are excluded to the fullest extent possible. No responsibility is assumed by Cirrus Logic for

the use of information herein, including use of this information as the basis for manufacture or sale of any items, or for infringement

of patents or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design, and SoundClear are among the

trademarks of Cirrus Logic. Other brand and product names may be trademarks or service marks of their respective owners.

Rev 4.4

65

WM8742

REVISION HISTORY

DATE

REV

DESCRIPTION OF CHANGES

CHANGED BY

Digital supply operation changed from 3.0V to 3.6V to 3.15 to 3.6V

14/02/13

4.3

JMacD

Operating temp changed from -40^oC to +85^oC to 0^oC to +70^oC

14/02/13

17/01/20

4.3

4.4

JMacD

PH

Ordering Information and Absolute Maximum Ratings updated – MSL information

removed

66

Rev 4.4


型号：	WM8742
厂家：	CIRRUS LOGIC
描述：	24-bit 192 kHz DAC
文件：	总66页 (文件大小：2054K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

WM8742 [CIRRUS]

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