CPC7584xA [CLARE]
Line Card Access Switch;
| 型号： | CPC7584xA |
| 厂家： | 
CLARE |
| 描述： | Line Card Access Switch |
| 文件： | 总16页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CPC7584
Line Card Access Switch
Features
Description
• Small 16-pin SOIC or micro-leadframe package
• Micro-leadframe package (MLP) printed circuit board
The CPC7584 is a monolithic solid state switch in a
16-pin SOIC or MLP surface mount package. It
provides the necessary functions to replace two
2-Form-C electro-mechanical relays on traditional
analog and integrated voice and data (IVD) line cards
found in Central Office, Access, and PBX equipment.
The device contains solid state switches for tip and
ring line break, ringing injection/ringing return and
channel test access. The CPC7584 requires only a
+5V supply and offers “break-before-make” or
“make-before-break” switch operation using simple
logic-level input control.
TH
footprint is 70% smaller than 4 generation EMRs
and 60% smaller than SOIC version
• Monolithic IC reliability
• Low matched R
• Eliminates the need for zero cross switching
• Flexible switch timing to transition from ringing mode
to talk mode.
ON
• Clean, bounce free switching
• Tertiary protection consisting of integrated current
limiting, voltage clamping, and thermal shutdown for
SLIC protection
• 5V operation with power consumption < 10 mW
• Intelligent battery monitor
The CPC7584xC logic differs from the CPC7584xA/B
with an enhancement permitting channel monitoring in
the test state. See “Functional Description” on page 9
for more information. The CPC7584xC also has a
higher trigger and hold current for the protection SCR.
Specify CPC7584Bx for SOIC or specify CPC7582Mx
for MLP devices shipped in tubes. Append the part
number with the suffix TR for tape and reel packaging.
• Latched logic level inputs, no external drive circuitry
required
Applications
• Central office (CO)
• Digital Loop Carrier (DLC)
• PBX Systems
Ordering Information
• Digitally Added Main Line (DAML)
• Hybrid Fiber Coax (HFC)
• Fiber in the Loop (FITL)
• Pair Gain System
Part Number Description
CPC7584xA
CPC7584xB
CPC7584xC
With protection SCR
Without protection SCR
With protection SCR and “Monitor” test state
• Channel Banks
Figure 1. CPC7584 Block Diagram
(TCHANTEST
)
TTEST
+5 Vdc
T
VDD
6
1
8
RINGING
CPC7584
SW3
SW5
Tip
X
X
X
TLINE
TBAT
3
4
X
SW1
Secondary
Protection
SLIC
Ring
SXW2
RLINE
RBAT
14
13
9
L
A
T
C
H
INTEST
SW6
SW4
X
SCR
and
Trip
Switch
Control
Logic
VREF
10
INRINGING
Circuit
11
LATCH
TSD
VBAT
12
16
2
15
VBAT
8
7
RRINGING
FGND
DGND
300Ω
(min.)
RINGING
RTEST (RCHANTEST
)
DS-CPC7584 - R0B
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1
CPC7584
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Absolute Maximum Ratings (at 25° C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Electrical Characteristics, TA = -40° C to +85° C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4.1 Power Supply Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4.2 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4.3 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4.4 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4.5 Test Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Digital Input Characteristics - IN
,IN
and LATCH Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TEST RINGING
1.6 Power Consumption Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.7 Thermal Shutdown Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.8 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.9 Truth Table - CPC7584xA/B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.10 Truth Table - CPC7584xC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Switch Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Make-Before-Break Operation (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 Break-Before-Make Operation (Ringing to Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.3 Alternate Break-Before-Make Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Ring Access Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6.2 Current Limiting function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7 Temperature Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.8 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.9 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Printed-Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.1 Moisture Reflow Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2
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R0B
CPC7584
1. Specifications
1.1 Package Pinout
1.2 Pinout
Pin
1
Name
Description
CPC7584
TTEST
FGND
TBAT
T
1
2
3
4
5
6
7
8
16 RTEST
15 VBAT
Connect to Tip lead of test bus
Fault ground
TEST
F
2
GND
T
3
Connect to tip lead of SLIC
Connect to tip lead of the line (drop)
Connect to ringing generator return
+5 V supply
BAT
14
RBAT
T
4
LINE
TLINE
TRINGING
VDD
13 RLINE
T
5
RINGING
V
6
12 RRINGING
DD
Temperature shutdown indicator pin.
Bi-directional I/O with internal pull up to
11
LATCH
V
. Output function indicates status of
TSD
DD
10 INRINGING
9 INTEST
T
7
SD
thermal shutdown circuitry, Input function
can be used to set the “All-Off” mode using
an open-drain type output.
DGND
D
8
9
Digital ground
GND
IN
Logic-level switch control input
Logic-level switch control input
TEST
IN
10
RINGING
Data latch control, active high, transparent
low
11
12
LATCH
Connect to ringing generator current
limiting resistor
R
RINGING
R
13
14
15
Connect to ring lead of the line (drop)
Connect to ring lead of the SLIC
Connect to ring lead of SLIC
LINE
R
BAT
V
BAT
Battery voltage supply. Must be capable of
sourcing the trigger current for proper
operation of the protection SCR.
R
16
TEST
Rev. B
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3
CPC7584
Absolute maximum ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at conditions
beyond those indicated in the operational sections of this
data sheet is not implied.
1.3 Absolute Maximum Ratings (at 25° C)
Parameter
Minimum Maximum
Unit
Operating temperature
Storage temperature
-40
-40
5
+110
+150
95
°C
°C
%
1.4.1 Power Supply Specifications
Operating relative humidity
Pin soldering temperature
(10 seconds max)
Supply
Minimum Typical Maximum Unit
-
+260
°C
V
+4.5
-19
+5.0
-
+5.5
-72
V
V
DD
+5 V power supply
Battery Supply
-0.3
-
7
V
V
V
1
V
-85
BAT
1
V
is used only for internal protection circuitry. If V
will enter and remain in the all-off state until the battery exceeds -15 V.
rises above -10 V, the device
BAT
V
+0.3
BAT
Logic input voltage
-0.3
DD
Logic input to switch output
isolation
-
330
V
Switch isolation (SW1,
SW2, SW3, SW5, SW6)
-
-
330
465
V
V
ESD Rating (Human Body Model)
Switch Isolation (SW4)
1000 V
1.4 Electrical Characteristics, T = -40° C to +85° C
A
Unless otherwise specified:
Minimum and maximum values are production testing
requirements. Typical values are provided for
information purposes only and are not part of the
testing requirements. They are characteristic of the
device and are the result of engineering evaluations.
V
= +5V and V
= -48V
DD
dc
BAT dc
1.4.2 Break Switches, SW1 and SW2
Parameter
Conditions
to T
Symbol
Minimum
Typical
Maximum
Unit
V
V
= T
LINE
SW1
BAT
= R
to R
BAT
SW2
LINE
V
V
= -320V to GND
= +260 V to -60 V
+25°C
+85°C
-40°C
SW
0.1
0.3
0.1
SW
Open Contact Isolation -
Off-state leakage current
V
V
= -330V to GND
= +270 V to -60 V
SW
I
-
1
µA
SW
SW
V
V
= -310 V to GND
= +250 V to -60 V
SW
SW
I
= 10 mA, 40 mA, T = -2 V +25°C
BAT
-
-
-
14.5
20.5
10.5
-
28
-
SW
I
I
= 10 mA, 40 mA, T = -2 V +85°C
BAT
R
On Resistance
SW
SW
ON
Ω
= 10 mA, 40 mA, T = -2 V -40°C
BAT
Per On Resistance test conditions above.
Magnitude R SW1 - R SW2
Switch Resistance
Matching
∆R
-
0.15
0.8
ON
ON
ON
V
V
V
(on) = 10 V
(on) = 10 V
(on) = 10 V
+25°C
+85°C
-40°C
-
80
-
300
160
400
-
-
SW
SW
SW
I
DC Current Limit
mA
LIM
425
4
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Rev. B
CPC7584
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Unit
Break switches on, all other switches off,
apply 1 kV 10/1000 µs pulse to Tip/Ring
interface with appropriate protection in place.
Dynamic Current Limit
(t = <0.5 µs)
I
-
2.5
-
A
SW
V
(T , R ) = 320 V
SW LINE LINE
+25°C
+85°C
-40°C
0.1
0.3
0.1
logic inputs = GND
(T , R ) = 330 V
V
SW LINE LINE
I
Contacts to Input Isolation
-
1
µA
SW
logic inputs = GND
(T , R ) = 310 V,
V
SW LINE LINE
logic inputs = GND
Applied voltage = 100 V p-p square wave at
100 Hz
dv/dt sensitivity
-
-
200
-
V/µs
1.4.3 Ringing Return Switch, SW3
Parameter
Conditions
to T
Symbol
Minimum
Typical
Maximum
Unit
V
= T
LINE
SW3
RINGING
V
V
= -320V to GND
= +260 V to -60 V
+25°C
+85°C
-40°C
SW
0.1
0.3
0.1
SW
Open Contact Isolation -
Off-state leakage current
V
V
= -330 V to GND
= +270 V to -60 V
SW
I
-
-
1
µA
SW
SW
V
V
= -310 V to GND
= +250 V to -60 V
SW
SW
I
(on) = 0 mA, 10 mA
(on) = 0 mA, 10 mA
(on) = 0 mA, 10 mA
+25°C
+85°C
-40°C
60
85
45
-
100
-
SW
I
I
R
On Resistance
Ω
SW
SW
ON
V
V
V
(on) = 10 V
+25°C
+85°C
-40°C
135
85
SW
(on) = 10 V
(on) = 10 V
I
DC Current Limit
-
-
-
-
mA
A
SW
SW
SW
210
Ringing switches on, all other switches off,
apply 1 kV 10/1000 µs pulse to Tip/Ring
interface with appropriate protection in place.
Dynamic current limit
(t = <0.5 µs)
I
2.5
SW
V
(T , T
SW LINE RINGING
) = 320 V
) = 330 V
) = 310 V
+25°C
+85°C
-40°C
0.1
0.3
0.1
logic inputs = GND
(T , T
V
SW LINE RINGING
I
Contacts to Input Isolation
-
-
1
µA
SW
logic inputs = GND
(T , T
V
SW LINE RINGING
logic inputs = GND
Applied voltage = 100 V p-p square wave at
100 Hz
dv/dt sensitivity
-
200
-
V/µs
Rev. B
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5
CPC7584
1.4.4 Ringing Switch, SW4
Parameter
Conditions
to R
Symbol
Minimum
Typical
Maximum
Unit
V
= R
LINE
SW4
RINGING
V
V
= -255 V to +210 V
= +255 V to -210 V
+25°C
+85°C
-40°C
SW
0.05
0.1
SW
Open Contact Isolation -
Off-state leakage current
V
V
= -270 V to +210 V
= +270 V to -210 V
SW
I
-
1
µA
SW
SW
V
V
= -245 V to +210 V
= +245 V to -210 V
SW
0.05
SW
I
(on) = 1 mA
V
On Voltage
-
-
1.5
8.5
3
V
SW
SW
I
(on) = 70 mA, 80 mA
R
On Resistance
12
Ω
SW
ON
Ringing generator current
to ground
I
Ringing switches on.
-
0.1
0.25
mA
RINGING
On steady-state current* Ringing switches on.
-
-
-
-
-
-
-
2
2
-
A
A
Surge current*
Release current
Ringing switches on.
I
Remove ringing mode, SW4 on.
300
µA
SW
V
(R , R
) = 320 V
) = 330 V
) = 310 V
+25°C
+85°C
-40°C
SW LINE RINGING
0.05
0.1
logic inputs = GND
(R , R
V
SW LINE RINGING
I
Contacts to Inout Isolation
-
1
µA
SW
logic inputs = GND
(R , R
V
SW LINE RINGING
0.05
logic inputs = GND
Applied voltage = 100 V p-p square wave at
100 Hz
dv/dt sensitivity
-
-
200
-
V/µs
* Secondary protection and ringing source current limiting must prevent exceeding these parameters.
1.4.5 Test Switches, SW5 and SW6
Parameter
Conditions
to T
Symbol
Minimum
Typical
Maximum
Unit
V
V
= T
TEST
SW5
BAT
= R
to R
BAT
SW6
TEST
V
V
= -320 V to GND
= +260 V to -60 V
+25°C
+85°C
-40°C
0.1
0.3
0.1
SW
SW
Open Contact Isolation -
Off-state leakage current
V
V
= -330 V to GND
=+270 V to -60 V
I
-
1
µA
SW
SW
SW
V
V
= -310 V to GND
= +250 V to -60 V
SW
SW
6
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Rev. B
CPC7584
Parameter
Conditions
Symbol
Minimum
Typical
38
Maximum
Unit
T
T
T
= 10 mA, 40 mA, T = -2 V +25°C
BAT
-
70
-
LINE
LINE
LINE
= 10 mA, 40 mA, T = -2 V +85°C
BAT
R
On Resistance
-
46
Ω
ON
= 10 mA, 40 mA, T = -2 V -40°C
BAT
28
V
V
V
(on) = 10 V
(on) = 10 V
(on) = 10 V
+25°C
+85°C
-40°C
-
80
-
175
110
210
-
-
SW
SW
SW
I
DC Current Limit
mA
A
SW
250
Test switches on , ringing access switches
off, apply 1 kV at 10/1000 µs pulse, with
appropriate secondary protection in place.
Dynamic current limit
(t = <0.5 µs)
I
-
2.5
-
SW
V
(T
, R
SW TEST TEST
) = 320 V
) = 330 V
) = 310 V
+25°C
+85°C
-40°C
0.1
0.3
0.1
logic inputs = GND
(T , R
V
SW TEST TEST
I
Contacts to Input Isolation
-
-
1
µA
SW
logic inputs = GND
(T , R
V
SW TEST TEST
logic inputs = GND
Applied voltage = 100 V p-p square wave at
100 Hz
dv/dt sensitivity
-
200
-
V/µs
1.5 Digital Input Characteristics - IN
,IN
and LATCH Pins
TEST RINGING
Parameter
Input Threshold
Conditions
Symbol
Minimum
Typical
Maximum
Unit
V
Logic low
Logic high
-
3.5
-
-
1.5
-
IL
V
V
-
IH
V
= 5.5 V, V = -75 V, V = 5 V
BAT IH
I
0.1
0.1
1
DD
DD
IH
Input Leakage Current
µA
V
= 5.5 V, V = -75 V, V = 0 V
BAT IL
I
-
1
IL
1.6 Power Consumption Characteristics
Parameter
Conditions
= 5 V, V = -48V,
Symbol
Minimum
Typical
Maximum
Unit
V
DD
BAT
-
1.1
2.0
Talk or All-Off states.
V
V
Current Consumption
I
mA
DD
DD
V
= 5 V, V = -48 V,
BAT
DD
-
-
1.3
0.1
5.5
6.5
2.0
10
10
10
Ringing or Test states.
= 5 V, V = -48 V,
V
DD
BAT
Current Consumption
I
µA
BAT
BAT
Any state
= 5 V, V = -48 V,
V
DD
BAT
Talk or All-Off states.
= 5 V, V = -48 V,
Power Consumption
P
-
mW
V
DD
BAT
Ringing or Test states.
Rev. B
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7
CPC7584
1.7 Thermal Shutdown Characteristics
Parameter
Activation Temperature
Hysteresis
Conditions
Symbol
Minimum
110
Typical
Maximum
150
Unit
°C
T
T
=> Low
=> High
T
125
-
SD
∆T
10
25
°C
SD
1.8 Protection Circuitry Electrical Specifications
Parameter Conditions
Symbol
Minimum
Typical
Maximum
Unit
Parameters Related to the Diodes in the Diode Bridge
Voltage drop at continuous
current (50/60 Hz)
V
Apply dc current limit of break switches
-
-
2.1
5
3
-
F
V
Voltage drop at surge
current
Apply dynamic current limit of break
switches
V
F
Parameters Related to the Protection SCR
Surge current
-
-
-
-
-
*
-
A
+25°C
+85°C
+25°C
+85°C
60
35
100
70
I
Trigger current
Hold current
mA
TRIG
-
I
-
mA
HOLD
60
V
or
TBAT
I
= I
GATE Tr igger
**
V
-4
V
-2
Gate trigger voltage
Reverse leakage current
On-state voltage
-
V
µA
V
BAT
BAT
V
RBAT
V
= -48V
I
-
-
1.0
BAT
VBAT
0.5 A, t = 0.5 ms
2.0 A, t = 0.5 ms
V
or
-3
-5
TBAT
-
-
V
RBAT
*Passes GR1089 and ITU-T K.20 with appropriate protection in place.
** V must be capable of sourcing I for the internal SCR to activate.
BAT
TRIGGER
8
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Rev. B
CPC7584
1.9 Truth Table - CPC7584xA/B
Break
Switches
Ringing
Switches
Test
Switches
1
IN
IN
Test
State
LATCH
TSD
RINGING
Talk
0
1
0
1
X
X
0
0
1
1
On
Off
Off
Off
Off
On
Off
Off
Off
Off
On
Off
Ringing
Test
0
1 or Floating
All Off
Latched
X
X
1
Unchanged Unchanged Unchanged
All off
X
0
Off
Off
Off
1
If TSD = 5V, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism is enabled.
1.10 Truth Table - CPC7584xC
Break
Switches
Ringing
Switches
Test
Switches
1
IN
IN
Test
State
LATCH
TSD
RINGING
Talk
0
1
0
1
X
X
0
0
1
1
On
Off
On
Off
Off
On
Off
Off
Off
Off
On
Off
Ringing
0
Test / Monitor
All Off
1 or Floating
Latched
X
X
1
Unchanged Unchanged Unchanged
Off Off Off
All off
X
0
1
If TSD = 5V, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism is enabled.
Rev. B
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9
CPC7584
2. Functional Description
2.1 Introduction
The CPC7584xA/B has four states:
To protect the CPC7584 from an overvoltage fault
condition, use of a secondary protector is required.
The secondary protector must limit the voltage seen at
the tip and ring terminals to a level below the
maximum breakdown voltage of the switches. To
minimize the stress on the solid-state contacts, use of
a foldback or crowbar type secondary protector is
recommended. With proper selection of the secondary
protector, a line card using the CPC7582BC will meet
all relevant ITU, LSSGR, FCC and UL protection
requirements.
• Talk. Line break switches SW1 and SW2 closed,
ringing switches SW3 and SW4 open, and test
switches SW5 and SW6 open.
• Ringing. Line break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test-in
switches SW5 and SW6 open.
• Test. Line break switches SW1 and SW2 open,
ringing switches SW3 and SW4 open, and test-in
switches SW5 and SW6 closed.
• All off. Line break switches SW1 and SW2 open,
ringing switches SW3 and SW4 open, and loop test
switches SW5 and SW6 open.
The CPC7584 operates from a +5 V supply only. This
gives the device extremely low idle and active power
dissipation and allows use with virtually any range of
battery voltage. A battery voltage is also used by the
CPC7584 as a reference for the integrated protection
circuit. In the event of a loss of battery voltage, the
CPC7584 enters the all-off state.
The CPC7584xC replaces the Test state with the
Test/Monitor state as defined below.
• Test/Monitor. Line break switches SW1 and SW2
closed, ringing switches SW3 and SW4 open, and
test-in switches SW5 and SW6 closed.
2.2 Switch Timing
The CPC7584 provides, when switching from the
ringing state to the idle/talk state, the ability to control
the release timing of the ringing access switches SW3
and SW4 relative to the state of the line break
switches SW1 and SW2 using simple logic-level input.
This is referred to a make-before-break or
break-before-make operation. When the line break
switch contacts (SW1 and SW2) are closed (or made)
before the ringing access switch contacts (SW3 and
SW4) are opened (or broken), this is referred to
make-before-break operation. Break-before-make
operation occurs when the ringing access contacts
(SW3 and SW4) are opened (broken) before the line
break switch contacts (SW1 and SW2) are closed
(made). With the CPC7584, the make-before-break
and break-before-make operations can easily be
selected by applying logic-level inputs to pins 9 and 10
The CPC7584 offers break-before-make and
make-before-break switching with simple logic-level
input control. Solid-state switch construction means no
impulse noise is generated when switching during ring
cadence or ring trip, eliminating the need for external
zero-cross switching circuitry. State-control is via
logic-level input so no additional driver circuitry is
required. The line break switches SW1 and SW2 are
linear switches that have exceptionally low RDS
ON
and excellent matching characteristics. The ringing
access switch SW4 has a breakdown voltage rating of
greater than 480 V. This is sufficiently high, with proper
protection, to prevent breakdown in the presence of a
transient fault condition (i.e., passing the transient on
to the ring generator).
(IN
and IN
) of the device.
RING
TEST-IN
Integrated into the CPC7584 is a diode bridge/SCR
clamping circuit, current limiting, and a thermal
shutdown mechanism to provide protection to the
SLIC device during a fault condition. Positive and
negative surges are reduced by the current limiting
circuitry and steered to ground via diodes and the
integrated SCR. Power-cross transients are also
reduced by the current limiting and thermal shutdown
circuits. Note that only the CPC7584xA and
CPC7584xC parts include the integrated protection
SCR.
The logic sequences for either mode of operation are
given in “Make-Before-Break Operation (Ringing to
Talk Transition)” on page 11 and “Break-Before-Make
Operation (Ringing to Talk Transition)” on page 11.
Logic states and explanations are given in “Truth Table
- CPC7584xA/B” on page 9.
Break-before-make operation can also be achieved
using pin 7 (TSD) as an input. In “Break-Before-Make
Operation (Ringing to Talk Transition)” on page 11
lines 2 and 3, it is possible to induce the switches to
the all-off state by grounding pin 7 (TSD) instead of
10
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Rev. B
CPC7584
apply logic input to the pins. This has the effect of
overriding the logic inputs and forcing the device to the
all-off state. Hold this input state for 25 ms. During this
hold period, toggle the inputs from the ringing state
(10) to the idle/talk state (00). After the 25 ms, release
pin 7 (TSD) to return the switch control to the input
pins 9 and 10 and reset the device to the idle/talk
state.
Setting TSD to +5 V allows switch control using the
logic pins 9 and 10. This setting, however, also
disables the thermal shutdown circuit and is therefore
not recommended. When using logic controls via the
input pins 9 and 10, pin 7 (TSD) should be allowed to
float. As a result, the two recommended states when
using pin 7 (TSD) as a control are 0, which forces the
device to the all-off state, or float, which allows logic
inputs to pins 9 and 10 to remain active. This may
require the use of an open-collector buffer.
2.2.1 Make-Before-Break Operation (Ringing to Talk Transition)
Ringing
Ringing
Break
Return
Test
Switches
IN
IN
T
SD
State
Timing
Switch
(SW4)
RINGING
TEST
Switches Switch
(SW3)
Ringing
1
0
Floating
Floating
Floating
-
Open
Closed
Closed
Closed
Open
Open
Closed
Closed
Open
Open
Open
Open
SW4 waiting for next zero-current crossing
to turn off. Maximum time is one-half of
ringing. In this transition state, current that is
limited to the dc break switch current limit
value will be sourced from the ring node of
the SLIC.
Make-
before-
break
0
0
Talk
0
0
Zero-cross current has occurred
2.2.2 Break-Before-Make Operation (Ringing to Talk Transition)
Ringing
Return
Switches Switch
(SW3)
Ringing
Switch
(SW4)
Break
Test
Switches
IN
IN
T
SD
State
Timing
RINGING
TEST
Ringing
All-off
Talk
1
1
0
0
1
0
Floating
Floating
Floating
-
Open
Closed
Open
Open
Closed
Closed
Open
Open
Open
Hold this state for at least 25 ms. SW4
waiting for zero current to turn off.
Open
SW4 has opened.
Open
Open
Close Break Switches
Closed
2.2.3 Alternate Break-Before-Make Operation
Break-before-make operation can also be achieved
using TSD as an input. In lines 2 and 3 of
logic input pins. However, setting TSD to +5 V also
disables the thermal shutdown mechanism. This is not
recommended. Therefore, to allow switch control via
the logic input pins, allow TSD to float.
“Break-Before-Make Operation (Ringing to Talk
Transition)” on page 11, instead of using the logic
input pins to force the all-off state, force TSD to
ground. This overrides the logic inputs and also forces
the all off state. Hold this state for 25 ms. During this
25 ms all-off state, toggle the inputs from the ringing
state (Ring = 5 V, Test-In = 0 V) to the idle/talk state
(Ring = 0 V, Test-In=0 V). After 25 ms, release TSD to
return switch control to the input pins which will set the
idle talk state.
When using TSD as an input, the two recommended
states are 0 (overrides logic input pins and forces all
off state) and float (allows switch control via logic input
pins and the thermal shutdown mechanism is active).
This may require use of an open-collector buffer.
When using the CPC7584 in this mode, forcing TSD to
ground overrides the input pins and force an all off
state. Setting TSD to +5 V allows switch control via the
Rev. B
www.clare.com
11
CPC7584
2.3 Ring Access Switch Zero-Cross Current Turn Off
After the application of a logic input to turn SW4 off,
the ring access switch is designed to delay the change
in state until the next zero-crossing. Once on, the
switch requires a zero-current cross to turn off, and
therefore should not be used to switch a pure DC
signal. The switch will remain in the on state no matter
what logic input until the next zero crossing. For proper
positive transient condition, the fault current is
conducted through the diode bridge to ground. Voltage
is clamped to the diode drop above ground. During a
negative transient of 2 to 4 V more negative than the
battery, the SCR conducts and faults are shunted to
ground via the SCR and diode bridge.
In order for the SCR to crowbar or foldback, the on
voltage (see “Protection Circuitry Electrical
Specifications” on page 8) of the SCR must be less
negative than the battery reference voltage. If the
battery voltage is less negative the SCR on voltage,
the SCR will not crowbar, however it will conduct fault
currents to ground.
operation, pin 12 (R
) should be connected using
RING
proper impedance to a ring generator or other AC
source. These switching characteristics will reduce
and possibly eliminate overall system impulse noise
normally associated with ringing access switches. The
attributes of ringing access switch SW4 may make it
possible to eliminate the need for a zero-cross
switching scheme. A minimum impedance of 300 Ω in
series with the ring generator is recommended.
For power induction or power-cross fault conditions,
the positive cycle of the transient is clamped to the
diode drop above ground and the fault current directed
to ground. The negative cycle of the transient will
cause the SCR to conduct when the voltage exceeds
the battery reference voltage by two to four volts,
steering the current to ground.
2.4 Power Supplies
Both a +5 V supply and battery voltage are connected
to the CPC7584. CPC7584 switch state control is
powered exclusively by the +5 V supply. As a result,
the CPC7584 exhibits extremely low power dissipation
during both active and idle states.
2.6.2 Current Limiting function
If a lightning strike transient occurs when the device in
the talk/idle state, the current is passed along the line
to the integrated protection circuitry and limited by the
dynamic current limit response of break switches SW1
and SW2. When a 1000V 10/1000 pulse (LSSGR
lightning) is applied to the line though a properly
clamped external protector, the current seen at pins 2
(T ) and pin 15 (R ) will be a pulse with a typical
The battery voltage is not used for switch control but
rather as a reference for the integrated secondary
protection circuitry. The integrated SCR is designed to
trigger when pin 3 (T ) or pin 14 (R ) drops 2 to
BAT
BAT
4 V below the battery. This trigger prevents a fault
induced overvoltage event at the T
or R
nodes.
BAT
BAT
BAT
BAT
magnitude of 2.5 A and a duration of less than 0.5 ms.
If a power-cross fault occurs with the device in the
talk/idle state, the current is passed though break
switches SW1 and SW2 on to the integrated
protection circuit and is limited by the dynamic DC
current limit response of the two break switches. The
DC current limit, specified over temperature, is
between 80 mA and 425 mA, and the circuitry has a
negative temperature coefficient. As a result, if the
device is subjected to extended heating due to power
2.5 Battery Voltage Monitor
The CPC7584 also uses the voltage reference to
monitor battery voltage. If battery voltage is lost, the
CPC7582BC immediately enters the all-off state. It
remains in this state until the battery voltage is
restored. The device also enters the all-off state if the
battery voltage rises above –10 V and remains in the
all-off state until the battery voltage drops below
–15 V. This battery monitor feature draws a small
current from the battery (less than 1 mA typical) and
will add slightly to the device’s overall power
dissipation.
cross fault, the measured current at pin 2 (T ) and
BAT
pin 15 (R ) will decrease as the device temperature
BAT
increases. If the device temperature rises sufficiently,
the temperature shutdown mechanism will activate
and the device will default to the all-off state.
2.6 Protection
2.6.1 Diode Bridge/SCR
2.7 Temperature Shutdown
The CPC7584 uses a combination of current limited
break switches, a diode bridge/SCR clamping circuit,
and a thermal shutdown mechanism to protect the
SLIC device or other associated circuitry from damage
during line transient events such as lightning. During a
The thermal shutdown mechanism will activate when
the device temperature reaches a minimum of 110° C,
placing the device in the all-off state regardless of
logic input. During thermal shutdown mode, pin 7
(TSD) will read 0 V. Normal output of TSD is +V
.
DD
12
www.clare.com
Rev. B
CPC7584
If presented with a short duration transient such as a
lightning event, the thermal shutdown feature will
typically not activate. But in an extended power-cross
transient, the device temperature will rise and the
thermal shutdown will activate forcing the switches to
the all-off state. At this point the current measured at
switches will remain in the position they were in when
the LATCH changed from logic 0 to logic 1 and will not
respond to changes in input as long as the latch is at
logic 1. The TSD input is not tied to the data latch.
Therefore, TSD is not affected by the LATCH input and
the TSD input will override state control via pin 10
pin 3 (T ) and pin 14 (R ) will drop to zero. Once
(IN
) and pin 9 (IN
) and the LATCH.
BAT
BAT
RING
TEST-IN
the device enters thermal shutdown it will remain in
the all-off state until the temperature of the device
drops below the activation level of the thermal
shutdown circuit. This will return the device to the state
prior to thermal shutdown. If the transient has not
passed, current will flow at the value allowed by the
dynamic DC current limiting of the switches and
heating will begin again, reactivating the thermal
shutdown mechanism. This cycle of entering and
exiting the thermal shutdown mode will continue as
long as the fault condition persists. If the magnitude of
the fault condition is great enough, the external
secondary protector could activate and shunt all
current to ground.
The thermal shutdown mechanism of the CPC7584
can be disable by applying +V to pin 7 (TSD).
DD
2.8 External Protection Elements
The CPC7584 requires only one overvoltage
secondary protector on the loop side of the device.
The integrated protection feature described above
negates the need for protection on the line side. The
secondary protector limits voltage transients to levels
that do not exceed the breakdown voltage or
input-output isolation barrier of the CPC7584. A
foldback or crowbar type protector is recommended to
minimize stresses on the device.
Consult Clare’s application note, AN-100, “Designing
Surge and Power Fault Protection Circuits for Solid
State Subscriber Line Interfaces” for equations related
to the specifications of external secondary protectors,
fused resistors and PTCs.
2.9 Data Latch
The CPC7584 has an integrated data latch. The latch
operation is controlled by logic-level input pin 11
(LATCH). The data input of the latch is pin 10 (IN
)
RING
and pin 9 (IN
) of the device while the output of
TEST-IN
the data latch is an internal node used for state
control. When LATCH control pin is at logic 0, the data
latch is transparent and data control signals flow
directly through to state control. A change in input will
be reflected in a change is switch state. When LATCH
control pin is at logic 1, the data latch is active and a
change in input control will not affect switch state. The
Rev. B
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13
CPC7584
3. Manufacturing Information
3.1 Mechanical Dimensions
3.1.1 SOIC
16 Pin SOIC (JEDEC Package)
10.11 MIN / 10.31 MAX
(.398 MIN / .406 MAX)
1.27
(.050)
0.23 MIN / 0.32 MAX
(.0091 MIN / .0125 MAX)
2.44 MIN / 2.64 MAX
(.096 MIN / .104 MAX)
10.11 MIN / 10.51 MAX
(.398 MIN / .414 MAX)
7.40 MIN / 7.60 MAX
(.291 MIN / .299 MAX)
0.51 MIN / 1.01 MAX
(.020 MIN / .040 MAX)
0.36 MIN / 0.46 MAX
(.014 MIN / .018 MAX)
3.1.2 MLP
7
6
INDEX AREA
TOP VIEW
0.2
0.80
0.10)
(
SEATING
PLANE
SIDE VIEW
0.02
(+0.05, -0)
0.33
(+0.07, -0.05)
1
2
EXPOSED PAD
0.55
4.0
0.05)
(
0.55
0.1)
(
16
6.0
0.05)
(
Terminal Tip
0.80
BOTTOM VIEW
Dimensions in mm
14
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Rev. B
CPC7584
3.2 Printed-Circuit Board Layout
3.2.2 MLP
5.75
0.75 on center
3.2.1 SOIC
0.65
PC Board Pattern
(Top View)
0.38
1.270
(.050)
5.35 on center
6.1
Detail A
9.728 .051
(.383 .002)
1.193
(.047)
6.13
Detail A
0.65
.787
(.031)
All dimensions in mm
Not drawn to scale
0.66
0.47
0.38
3.3 Tape and Reel Packaging
3.3.1 SOIC
A0
6.50
3.00
R = .50
2.00
2.30
K1
K0
B0
6.80
2.70
1.30
16.00
7.50
12.00
4.00
2.00
1.50
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS AND CARRY TOLERANCES OF EIA
STANDARD 481-2. 2. THE TAPE COMPLIES WITH ALL "NOTES" FOR CONSTANT DIMENSIONS
LISTED ON PAGE 5 OF EIA-481-2.
A0 =
B0 =
K0 =
K1 =
6.5 mm
10.3 mm
2.3 mm
2.7 mm
3.4 Soldering
3.4.1 Moisture Reflow Sensitivity
Clare has characterized the moisture reflow sensitivity
of LCAS products using IPC/JEDEC standard
J-STD-020A. Moisture uptake from atmospheric
humidity occurs by diffusion. During the solder reflow
process, in which the component is attached to the
PCB, the whole body of the component is exposed to
high process temperatures. The combination of
moisture uptake and high reflow soldering
Rev. B
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15
temperatures may lead to moisture induced
delamination and cracking of the component. To
prevent this, this component must be handled in
accordance with IPC/JEDEC standard J-STD-020A
per the labeled moisture sensitivity level (MSL), level 1
for the SOIC package, and level 2 for the MLP
package.
3.4.2 Reflow Profile
The maximum ramp rates, dwell times, and
temperatures of the assembly reflow profile should not
exceed those specified in IPC/JEDEC standard
J-STD-020A, which were used to determine the
moisture sensitivity level of this component.
3.5 Washing
Clare does not recommend ultrasonic cleaning of
LCAS parts.
For additional information please visit www.clare.com
Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set
forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its
products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a
person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.
Specifications: DS-CPC7584 - R0B
© Copyright 2004, Clare, Inc.
All rights reserved. Printed in USA.
1/23/2004
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