M-88L70-01P [CLARE]
3V DTMF Receiver; 3V DTMF接收器
| 型号： | M-88L70-01P |
| 厂家： | 
CLARE |
| 描述： | 3V DTMF Receiver |
| 文件： | 总8页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M-88L70
3V DTMF Receiver
Description
Features
The M-88L70 monolithic DTMF receiver offers small size,
low power consumption and high performance, with 3 volt
operation. Its architecture consists of a bandsplit filter
section, which separates the high and low group tones,
followed by a digital counting section which verifies the
frequency and duration of the received tones before
passing the corresponding code to the output bus.
• Operates between 2.7 and 3.6 volts
• Low power consumption
• Power-down mode
• Inhibit mode
• Central office quality and performance
• Inexpensive 3.58 MHz time base
• Adjustable acquisition and release times
• Dial tone suppression
• Functionally compatible with Clare’s M-8870
Ordering Information
Applications
Part #
Description
• Telephone switch equipment
• Mobile radio
• Remote control
• Paging systems
• PCMCIA
M-88L70-01P 18-pin plastic DIP
M-88L70-01S 18-pin SOIC
M-88L70-01T 18-pin SOIC, Tape and Reel
• Portable TAD
• Remote data entry
Figure 1 Pin Connections
The M-88L70 is a full DTMF Receiver that integrates
both bandsplit filter and decoder functions into a single
18-pin DIP or SOIC package. Manufactured using
CMOS process technology, the M-88L70 offers low
power consumption (18 mW max), precise data handling
and 3V operation. Its filter section uses switched capaci-
tor technology for both the high and low group filters and
for dial tone rejection. Its decoder uses digital counting
techniques to detect and decode all 16 DTMF tone pairs
into a 4-bit code. External component count is minimized
by provision of an on-chip differential input amplifier,
clock generator, and latched tri-state interface bus.
Minimal external components required include a low-cost
3.579545 MHz color burst crystal, a timing resistor, and a
timing capacitor.
Figure 2 Block Diagram
DS-M88L70-R1
1
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M-88L70
Filter
tion”), it raises the Early Steering flag (ESt). Any subse-
quent loss of signal condition will cause ESt to fall.
The low and high group tones are separated by applying
the dual-tone signal to the inputs of two 9th order
switched capacitor bandpass filters with bandwidths that
correspond to the bands enclosing the low and high
group tones. The filter also incorporates notches at 350
and 440 Hz, providing excellent dial tone rejection. Each
filter output is followed by a single-order switched capac-
itor section that smoothes the signals prior to limiting.
Signal limiting is performed by high-gain comparators
provided with hysteresis to prevent detection of unwant-
ed low-level signals and noise. The comparator outputs
provide full-rail logic swings at the frequencies of the
incoming tones.
Steering Circuit
Before a decoded tone pair is registered, the receiver
checks for a valid signal duration (referred to as “char-
acter-recognition-condition”). This check is performed
by an external RC time constant driven by ESt. A logic
high on ESt causes VC (see Figure 3) to rise as the
capacitor discharges. Provided that signal condition is
maintained (ESt remains high) for the validation period
(tGTP), VC reaches the threshold (VTSt) of the steering
logic to register the tone pair, thus latching its corre-
sponding 4-bit code (see Table 2) into the output latch.
At this point, the GT output is activated and drives VC to
VDD. GT continues to drive high as long as ESt remains
high. Finally, after a short delay to allow the output latch
to settle, the “delayed steering” output flag (StD) goes
high, signaling that a received tone pair has been reg-
istered. The contents of the output latch are made
available on the 4-bit output bus by raising the three-
state control input (OE) to a logic high. The steering cir-
cuit works in reverse to validate the interdigit pause
between signals. Thus, as well as rejecting signals too
short to be considered valid, the receiver will tolerate
signal interruptions (dropouts) too short to be consid-
Decoder
The M-88L70 decoder uses a digital counting technique
to determine the frequencies of the limited tones and to
verify that they correspond to standard DTMF frequen-
cies. A complex averaging algorithm is used to protect
against tone simulation by extraneous signals (such as
voice) while tolerating small frequency variations. The
algorithm ensures an optimum combination of immunity
to talkoff and tolerance to interfering signals (third tones)
and noise. When the detector recognizes the simultane-
ous presence of two valid tones (known as “signal condi-
Table 1 Pin Functions
Pin
1
Name
IN+
IN
Description
Connections to the front-end differential amplifier
Non-inverting input
-Inverting input
2
3
GS
Gain select. Gives access to output of front-end amplifier for connection of feedback resistor.
4
V
Reference voltage output (nominally V /2). May be used to bias the inputs at mid-rail.
REF
DD
5
INH
PD
Inhibits detection of tones representing keys A, B, C, and D. This input is internally pulled down.
6
Power down. Logic high powers down the device and inhibits the oscillator. This input is internally pulled down.
7
OSC1
OSC2
Clock input
3.579545 MHz crystal connected between these pins completes internal oscillator.
Clock output
8
9
V
Negative power supply (normally connected to 0 V).
SS
10
OE
Tri-state output enable (input). Logic high enables the outputs Q1 - Q4. Internal pullup.
11-14 Q1, Q2,
Q3, Q4
Tri-state outputs. When enabled by OE, provides the code corresponding to the last valid tone pair received
(see Table 5.)
15
16
17
StD
Delayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is
updated. Returns to logic low when the voltage on St/GT falls below V
TSt
ESt
Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair
(signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
St/GT
Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to
register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new
tone pair. The GT output acts to reset the external steering time constant, and its state is a function of ESt and the
voltage on St. (See Figure 5).
18
V
Positive power supply
DD
Rev. 1
2
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M-88L70
ered a valid pause. This capability, together with the
ability to select the steering time constants externally,
allows the designer to tailor performance to meet a wide
variety of system requirements.
Figure 3 Basic Steering Circuit
Guard Time Adjustment
Where independent selection of receive and pause are
not required, the simple steering circuit of Figure 3 is
applicable. Component values are chosen according to
the formula:
tREC = tDP + tGTP
tGTP @ 0.67 RC
The value of tDP is a parameter of the device and tREC is
the minimum signal duration to be recognized by the
receiver. A value for C of 0.1 µF is recommended for
most applications, leaving R to be selected by the
designer. For example, a suitable value of R for a tREC of
40 ms would be 300 K ohm. A typical circuit using this
steering configuration is shown in Figure 4. The timing
requirements for most telecommunication applications
are satisfied with this circuit. Different steering arrange-
ments may be used to select independently the guard
times for tone-present (tGTP) and tone-absent (tGTA). This
may be necessary to meet system specifications that
place both accept and reject limits on both tone duration
and interdigit pause.
Table 2 Tone Decoding
Guard time adjustment also allows the designer to tailor
system parameters such as talkoff and noise immunity.
Increasing tREC improves talkoff performance, since it
reduces the probability that tones simulated by speech
will maintain signal condition long enough to be regis-
tered. On the other hand, a relatively short tREC with a
long tDO would be appropriate for extremely noisy envi-
ronments where fast acquisition time and immunity to
dropouts would be required. Design information for
guard time adjustment is shown in Figure 5.
FLOW FHIGH Key OE INH ESt
(ref.)
Q4
Q3
Q2 Q1
ANY ANY ANY
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Z
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Z
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
Z
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Z
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
697 1209
697 1336
697 1477
770 1209
770 1336
770 1477
852 1209
852 1336
852 1477
941 1336
941 1209
941 1477
697 1633
770 1633
852 1633
941 1633
1
2
3
4
5
6
7
8
Input Configuration
9
The input arrangement of the M-88L70 provides a dif-
ferential input operational amplifier as well as a bias
source (VREF) to bias the inputs at mid-rail. Provision is
made for connection of a feedback resistor to the op-
amp output (GS) for gain adjustment.
0
*
#
A
B
C
D
L
In a single-ended configuration, the input pins are con-
nected as shown in Figure 4 with the op-amp connect-
L
L
ed for unity gain and VREF biasing the input at 1/2VDD
.
697 1633
770 1633
852 1633
941 1633
A
B
C
D
H
H
H
D
H
H
H
H
L
L
L
L
Undetected, the output
code will remain the
same as the previous
detected code.
Figure 7 shows the differential configuration, which per-
mits gain adjustment with the feedback resistor R5.
L = logic low, H = logic high, Z = high impedance, X = don’t care
Rev. 1
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3
M-88L70
Absolute Maximum Ratings
Absolute Maximum Ratings are stress ratings. Stresses
in excess of these ratings can cause permanent dam-
age to the device. Functional operation of the device at
these or any other conditions beyond those indicated in
the operational sections of this data sheet is not implied.
Exposure of the device to the absolute maximum ratings
for an extended period may degrade the device and
effect its reliability.
Parameter
Symbol
Value
Power supply voltage
V
6.0 V max
DD
(VDD - V )
SS
Voltage on any pin
V
VSS -0.3 Min,
DD +0.3 Max
dc
V
Current on any pin
IDD
TA
TS
10 mA max
Operating temperature
-40˚C to + 85˚C
-65˚C to + 150˚C
Storage temperature
Note:
Exceeding these ratings may cause permanent damage. Functional operation under these condi-
tions is not implied.
Table 4 DC Characteristics
PARAMETER
SYMBOL
MIN
TYP
3.0
3.0
5.0
9
MAX
3.6
5.0
10
18
1.0
-
UNITS
V
TEST CONDITIONS
Operating supply voltage
Operating supply current
Standby supply current
Power consumption
V
2.7
DD
IDD
IDDS
PO
-
-
mA
µA
mW
V
PD=V
DD
-
Low level input voltage
High level input voltage
Input leakage current
V
-v
2
-
VDD = 3.0 V
IL
V
-
V
VDD = 3.0 V
IH
IIH/IIL
ISO
-
0.1
-
-
µA
µA
µA
µA
MΩ
V
V = VSS or VDD (see Note 2)
IN
Pullup (source) current on OE
Pull down (sink) Curent PD
Pull down (sink) Current INH
Input impedance, signal inputs 1, 2
Steering threshold voltage
Low level output voltage
High level output voltage
Output high (source) current
-12
-
-
OE = 0 V
PD = 3.0 V
INH = 3.0 V
@ 1 kHz
IPD
1.0
1.0
10
1.5
0.1
2.6
45
45
-
IINH
RIN
-
-
V
-
-
TSt
V
-
0.4
-
V
IOL = 1.0 mA
OL
V
2.4
1.0
-
V
IOH = -400 mA
OH
IOH
-
mA
V
V
OUT = 2.5 V @ VDD = 2.7 V
Output voltage V
V
1.5
10
-
No load
REF
REF
Output resistance V
ROR
-
-
kΩ
REF
Notes:
1. All voltages referenced to VSS unless otherwise noted. For typical values, VDD = 3.0 V + 20%/-10%, VSS = 0 V, TA = 25˚C
2. Input pins defined as IN+, IN-, and OE.
Rev. 1
4
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M-88L70
Table 5 Operating Characteristics - Gain Setting Amplifier
PARAMETER
SYMBOL
MIN
-
TYP
100
10
15
60
60
65
1.0
2.2
-
MAX
UNITS
nA
TEST CONDITIONS
Input leakage current
Input resistance
IN
-
V
SS < V < V
IN
DD
RIN
-
-
MΩ
mV
dB
Input offset voltage
V
-
25
OS
Power supply rejection
Common mode rejection
DC open loop voltage gain
Open loop unity gain bandwidth
Output voltage swing
Tolerable capacitive load (GS)
Tolerable resistive load (GS)
Common mode range
PSRR
CMRR
50
40
32
0.3
-
-
1 kHz
-
dB
-3.0V < V < 3.0V
IN
A
-
dB
VOL
fC
-
MHz
V
-
100
-
V
RL 3 100 kΩ to V
SS
O
P-P
CL
RL
-
pF
kΩ
50
-
-
V
1.5
-
V P-P
No load
CM
All voltages referenced to VSS unless otherwise noted. VDD = 3.0 V +20%/-10%, VSS = 0 V, TA = -40˚C to + +85˚C
Table 6 AC Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
dBm
mVRMS
dB
NOTES
Valid input signal levels
-
-
-36
-
-6.4
1,2,3,4,5,8
(each tone of composite signal)
Positive twist accept
12.3
-
370
-
-
-
6
Negative twist accept
-
-
-
6
dB
Frequency deviation accept limit
Frequency deviation reject limit
Third tone tolerance
-
-
-
1.5% ±2 Hz
Nom.
Nom.
dB
2,3,5,8,10
2,3,5
-
±3.5%
-
-
-
-
-
-16
-
2,3,4,5,8,9,13,14
2,3,4,5,6,8,9
2,3,4,5,7,8,9
See Figure 8
Noise tolerance
-
-12
-
dB
Dial tone tolerance
-
-
+22
-
dB
Tone present detection time
Tone absent detection time
Minimum tone duration accept
Maximum tone duration reject
Minimum interdigit pause accept
Maximum interdigit pause reject
Propagation delay (St to Q)
Propagation delay (St to StD)
Output data setup (Q to StD)
Propagation delay (OE to Q), enable
Propagation delay (OE to Q), disable
Crystal clock frequency
tDP
tDA
tREC
tREC
tID
tDO
tPQ
tPStD
tQStD
tPTE
tPTD
fCLK
CLO
5
8
14
ms
0.5
3
8.5
ms
-
40
ms
User adjustable (see Figures 3
and Figure 5)
20
-
-
ms
-
-
-
40
ms
20
-
ms
-
13
-
µs
OE = V
DD
-
8
-
µs
-
3.4
200
500
3.5795
-
-
µs
-
-
-
ns
RL = 10kΩ, CL = 50 pF
-
3.5759
-
ns
3.5831
30
MHz
Clock output (OSC2), capacitive load
pF
All voltages referenced to VSS unless otherwise noted. For typical values VDD = 3.0 V, VSS = 0 V, TA = -40˚C to +85˚C, fCLK = 3.579545 MHz.
1. dBm = decibels above or below a reference power of 1 mW into a 600 Ω load.
2. Digit sequence consists of all 16 DTMF tones.
Notes:
3. Tone duration = 40 ms. Tone pause = 40 ms.
4. Nominal DTMF frequencies are used, measured at GS.
5. Both tones in the composite signal have an equal amplitude.
6. Bandwidth limited (0 to 3 kHz) Gaussian noise.
7. The precise dial tone frequencies are (350 and 440 Hz) ± 2%.
8. For an error rate of better than 1 in 10,000.
9. Referenced to lowest level frequency component in DTMF signal.
10. Minimum signal acceptance level is measured with specified maximum frequency deviation.
11. Input pins defined as IN+, IN-, and OE.
12. External voltage source used to bias VREF.
13. This parameter also applies to a third tone injected onto the power supply.
14. Referenced to Figure 4. Input DTMF tone level at -28 dBm.
Rev. 1
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5
M-88L70
Figure 4 Single-Ended Input Configuration
Figure 5 Guard Time Adjustment
Figure 6 Timing Diagram
Explanation of Symbols
VIN
DTMF composite input signal.
ESt
Early steering output. Indicates detection of
valid tone frequencies.
St/GT
Steering input/guard time output. Drives
external RC timing circuit.
Q1 - Q4
StD
4-bit decoded tone output.
Delayed steering output. Indicates that valid
frequencies have been present/absent for
the required guard time, thus constituting a
valid signal.
OE
Output enable (input). A low level shifts Q1 -
Q4 to its high impedance state.
tREC
tREC
Maximum DTMF signal duration not detected
as valid.
Minimum DTMF signal duration required for
valid recognition.
Explanation of Events
(A) Tone bursts detected, tone duration invalid, outputs not
updated.
tID
Minimum time between valid DTMF signals.
tDO
Maximum allowable dropout during valid DTMF
signal.
(B) Tone #n detected, tone duration valid, tone decoded
and latched in outputs.
tDP
tDA
Time to detect the presence of valid DTMF
signals.
(C) End of tone #n detected, tone absent duration valid,
outputs remain latched until next valid tone.
Time to detect the absence of valid DTMF
signals.
(D) Outputs switched to high impedance state.
(E) Tone #n + 1 detected, tone duration valid, tone decod-
ed and latched in outputs (currently high impedance).
tGTP
tGTA
Guard time, tone present.
Guard time, tone absent.
(F) Acceptable dropout of tone #n + 1, tone absent duration
invalid, outputs remain latched.
(G) End of tone #n + 1 detected, tone absent duration valid,
outputs remain latched until next valid tone.
Rev. 1
6
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M-88L70
Figure 8 Common Crystal Connection
Figure 7 Differential Input Configuration
Figure 9 Package Dimensions
Tolerances
Inches
Metric (mm)
Min
Max
.210
Min
Max
5.33
A
A1
b
.015
.014
.045
.008
.880
.300
.240
.38
36
.022
.070
.014
.920
.325
.280
.
.
.56
1.7
b2
C
1.1
.20
.36
D
E
23.35
7.62
6.10
23.37
8.26
7.11
E1
e
.100 BSC
2.54 BSC
ec
L
0˚
15˚
0˚
15˚
.115
.150
2.92
3.81
Tolerances
Inches
Metric (mm)
Min
Max
Min
2.35
.10
Max
2.65
.30
A
A1
b
.0926
.0040
.013
.1043
.0118
.020
.33
.51
D
E
.4469
.2914
.4625
.2992
11.35
7.4
11.75
7.6
e
.050 BSC
.394
.016
1.27 BSC
H
L
.419
.050
10.00
.40
10.65
1.27
Rev. 1
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7
Worldwide Sales Offices
CLARE LOCATIONS
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ASIA PACIFIC
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Tel: 1-978-524-6700
Fax: 1-978-524-4900
Toll Free: 1-800-27-CLARE
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Tel: 32-11-300868
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Lead Rep
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91160 Champlan
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Tel: 33 1 69 79 93 50
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AMERICAS
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http://www.clare.com
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Clare cannot assume responsibility for use of any circuitry other
than circuitry entirely embodied in this Clare product. No circuit
patent licenses nor indemnity are expressed or implied. Clare
reserves the right to change the specification and circuitry, with-
out notice at any time. The products described in this document
are not intended for use in medical implantation or other direct life
support applications where malfunction may result in direct phys-
ical harm, injury or death to a person.
Canada
Clare Canada Ltd.
3425 Harvester Road, Suite 202
Burlington, Ontario L7N 3N1
Tel: 1-905-333-9066
Fax: 1-905-333-1824
Specification: DS-M88L70-R1
©Copyright 2000, Clare, Inc.
All rights reserved. Printed in USA.
1/29/01
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