FX105A_技术文档

FX105A

Tone Detector

D/105A/5 September 1999

Provisional Issue

1.0

Features

·

Operates in High Noise Conditions

³ 36dB Signal Input Range

High Sensitivity

·

Adjustable Bandwidth

Adjustable Frequency

Wide Voltage Range (2.7V to 5.5V)

Low Power

Single and Multitone System

Applications

1.1

Brief Description

The FX105A is a monolithic CMOS tone operated switch, designed for tone decoding in single and

multitone signalling systems. The FX105A uses decoding techniques which allow a tone to be

recognised in the presence of high noise levels or strong adjacent signals. Detection centre frequency

and bandwidth can each be independently adjusted. The design is immune to high levels of harmonic

and sub-harmonic interference. Excellent noise immunity and constant bandwidth are maintained over

a wide range of input signal levels.

ã 1999 Consumer Microcircuits Limited

Tone Detector

FX105A

CONTENTS

Section

Page

1.0 Features ......................................................................................................1

1.1 Brief Description.........................................................................................1

1.2 Block Diagram ............................................................................................3

1.3 Signal List...................................................................................................4

1.4 External Components.................................................................................5

1.5 General Description....................................................................................6

1.6 Application Notes.......................................................................................7

1.6.1 General ........................................................................................7

1.6.2 Method for Calculating External Component Values................7

1.6.3 Replacement for FX105.............................................................11

1.7 Performance Specification.......................................................................12

1.7.1 Electrical Performance..............................................................12

1.7.2 Packaging..................................................................................14

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FX105A

1.2

Block Diagram

Figure 1 Block Diagram

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FX105A

1.3

Signal List

Package

D4/P3

Signal

Description

Pin No.

Name

Type

1

INPUT AMP IN

I/P

AC couple to this input of the input buffer

amplifier.

2

INPUT AMP OUT

O/P

The input buffer amplifier output.

3

4

5

6

7

8

9

RW

RV

I/P

The input to the Detect/Word filter.

The input to the VCO loop filter.

Word filter capacitor pin A.

I/P

C3A

O/P

C3B

Word filter capacitor pin B.

C2A

VCO Loop filter capacitor pin A.

VCO Loop filter capacitor pin B.

C2B

DETECT OUT

Open drain CMOS output, active on detect.

Note that a load resistor to V_SSis required.

10

11

12

13

14

15

V_SS

R2HI

R2LO

C1B

C1A

R1

Power

I/P

Ground.

Bandwidth control resistor pin A.

Bandwidth control resistor pin B.

VCO capacitor B.

I/P

O/P

I/P

VCO capacitor A.

VCO discharge resistor. When potentiometer

tuning is required, a series resistor is

recommended to prevent possible shorting to

ground.

16

V_DD

Power

Power supply.

Notes: I/P

=

Input

O/P = Output

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1.4

External Components

C_1A

C_1B

C_2A

C_2B

C_3A

C_3B

C₄

See section 1.6

0.27µF ±20%

R_1F

R_1V

R₂

See section 1.6

R_L

20kohm

±20%

R_V

R_W

D₁

See section 1.6

IN914 or similar

C₅

C₆

0.1µF

±20%

Notes:

1. For improved performance C4 may be chosen to provide 30° phase shift at the VCO

loop filter input.

2. For compatibility with the FX105P; capacitors (C1 .... C4) may be connected to V_DD

instead of V_SS

.

3. For improved de-response time, a diode (D₁) may be added.

4. Any value load resistance (R_L) may be used, providing the maximum load current does

not exceed the value given in section 1.7.1

Figure 2 Recommended External Components

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1.5

General Description

The input signal to the FX105A is ac coupled to the buffer amplifier input, which is internally biased at

50% of supply voltage. The signal appears at the output of the buffer amplifier as an ac voltage

superimposed on the dc bias level. The signal is then coupled via R_Vand R_Wto the voltage controlled

oscillator (VCO) and word sampling switches, which cyclically connect C₂and C₃into the circuit to

form four sample-and-hold RC circuit integrators. See Figure 3.

With no input signal level, each capacitor charges to the dc bias level so differential voltages are zero.

When an input signal is applied each capacitor receives an additional charge. This charge is

determined by the integrated average of the signal waveform during the time the capacitor is switched

into the circuit.

Figure 3 shows the operating sequence of the VCO sampling switches and their relationship to a

locked-on in-band signal. C_2Aand C_2Bshould not receive any additional charge since they always

sample the input as it crosses the dc bias level. Should the signal not be locked to the VCO, a

positive or negative charge voltage will appear on C_2Aor C_2B. This voltage, when differentially

amplified, is applied to the VCO as an error correcting signal to enable the VCO to “lock.”

Figure 3 also shows the operating sequence of the “Word” sampling switches and their relationship to

a locked-on in-band signal. As the figure shows, the charge applied to C_3Ashould always be positive,

and the charge applied to C_3Bshould always be negative (with respect to the common bias level).

These capacitor potentials are differentially amplified and applied to a dc comparator, which switches

at a pre-determined threshold voltage V_TH(known as the word filter sensitivity). The comparator

output is a logic signal used to control a counter. This counter switches the FX105A output ON when

the comparator output is maintained in the “Word present” state for a minimum number of consecutive

signal samples. The activated output switch reduces the comparator threshold by 50%, introducing

threshold hysteresis. Output chatter with marginal input signal amplitudes is thereby minimised.

Figure 3 Sampling Clocks of Commutating Filters

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1.6

Application Notes

1.6.1 General

The external components shown in Figure 2 are used to adjust the various performance parameters of

the FX105A. The signal-to-noise performance, response time and signal bandwidth are all interrelated

factors which should be optimised to meet the requirements of the application.

By selecting component values in accordance with the following formulae, optimum circuit

performance is obtained for any given application.

First define the following application parameters:

(a) The input frequency to be detected (f₀). The free running frequency of the VCO is set to 6 times

this frequency by observing the output across C₁or R₁. (The frequency observed at pin 15 (R₁) is

6 x f₀and the frequency observed at pins 13 or 14 (C_1Aor C_1B) is 3 x f₀).

(b) The FX105A Minimu mUsable Bandwidth (MUBW). This is obtained by taking into account the

worst case tolerances D(f₀) of the input frequency and the variations in the FX105A VCO

frequency due to supply voltage DV(_DD) and temperature D(TEMP) variation of the FX105A and its

supporting components.

(c) The maximum permissible FX105A response time.

(d) The minimum input signal amplitude. (This must be larger than the threshold voltage, V_TH).

(e) The maximum input signal amplitude.

Using this information the appropriate component values can be calculated, and the signal-to-noise

performance can be read from a chart. Do not add large safety margins for response time and

minimum signal amplitude: reasonable margins are already included in the formulae. Excessive

margins may result in reduced noise immunity.

1.6.2 Method for Calculating External Component Values

The example on the following pages demonstrates the calculation of component values for any given

application. For the purpose of this example, the values below are used:

(a) f₀= 2800Hz

(b) DTEMP = 100°C, DV_DD= 1V, Df₀= 0.5%

(c)

Maximum allowe dresponse time T_ON= 50msec

(d) Minimum input signal amplitude V_IN_MIN= 200mVrms

(e) Maximum input signal amplitude V_IN_MAX= 400mVrms

1.6.2.1 Calculate R₁C₁(C_1A= C_1B

)

The components R₁, C_1Aand C_1Bset the free running frequency of the VCO and therefore the f₀of

the FX105A. As shown below, the frequency of 2800Hz corresponds to a capacitor value of 220pF

and a resistor value of 385 Wk. This resistance can be achieved with a 330 Wkfixed resistor and a

100kW potentiometer. R₁should lie in the range 100 Wk to 680kW .

R₁C_1A= 1/ [2Kf₀] = 1/ (2 x 2.1 x 2800 )= 85µsec

where K is a constan t= 2.1 ± 5%.

Note that the values of C_1Aand C_1Bneed to include the stray capacitance

attributable to the package style and printed circuit board layout. A typical

value of 6.6pF per pin should be assumed.

If C_1A= C_1B= 233.2pF, then R₁» 364kohm

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1.6.2.2 Calculate Minimum Usable Bandwidth (%)

Minimum Usable Bandwidth (MUBW) is the TOTAL (%) bandwidth required for the following:

(a) Input signal frequency tolerance (Df₀)

(b) FX105A VCO temperature coefficient (T_C= - 100ppm/ºC)

(c)

FX105A VCO supply voltage coefficient (V_C= 2330ppm/V)

Add (a), (b) and (c) and express as TOTAL (%) bandwidth, not as a ± (%) value.

MUBW = Df₀+ |T_c|DTEMP + V_cDV_DD

MUBW = 0.5 + 0.01 x 100 + 0.233 x 1 » 2%

1.6.2.3 Calculate the Recommended Operating Bandwidth

Note again that this is the TOTAL (%) bandwidth:

BW = ½ [10 + MUBW] = ½ (10 + 2) = 6%

1.6.2.4 Select R₂for Operating BW

R₂= 4.8 BW/ [10.35 -BW] = 4.8 x 6/ (10.35 -6) » 6.8kW

The exact bandwidth given by any value of R₂will vary slightly. In applications where an exact

bandwidth is required, R₂should be a variable resistor to permit adjustment.

1.6.2.5 Calculate R_VC_2A(C_2A= C_2B) Use nearest preferred values

R_VC_2A» 100/ [3 f₀BW] » 100/ (3 x 2800 x 6) » 2msec

Therefore

R_V» 200kW for C_2A= C_2B= 10nF

1.6.2.6 Define the Maximum Allowed Response Time

The maximum response time (T_ON) is the sum of the VCO lock time (T_LOCK) and the Word integration

time (T_WORD). The FX105A’s T_ONmust not exceed the maximum time allowed for the application, but

a value lying near the maximum gives the best S/N performance.

(a) Calculate T_LOCK

T_LOCK= 150/ [f₀BW] = 150/ (2800 x 6) » 9msec

Note: T_LOCKmay vary from near zero to the value given, causing corresponding variations in actual

T_ON

(b) Calculate Maximum Allowable T_WORD

T_WORD= T_ON_MAX-T_LOCK= 50 - 9 = 41msec

.

Note: Since the maximum allowed response time (T_ON) is 50msec, a maximum Word integration time

of 41msec is available.

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1.6.2.7 Calculate R_WC_3A(C_3A= C_3B) Use nearest preferred values.

R_WC_3A» T_WORD/ [-3In (1 - V_TH/ V_IN_MIN) ]

where V_THis the word filter

sensitivity, see Section 1.7.1

A signal amplitude of 200mV and a resistor value R_Wof 465kW with a 220nF capacitor for C_3Aand

C_3Bwill yield a T_WORDtime of 41msec. This in turn yields a response time of 9msec + 41msec =

50msec.

1.6.2.8 Calculate the Maximum De-response Time

T

_OFF» -3 R_WC_3AIn (V_TH/ V_IN

)

where V_THis the word filter

sensitivity, see Section 1.7.1

MAX

For improved de-response time, a diode (1N914 or similar) can be placed between pins 5 and 6, as

shown in Figure 2. The formula and figure below show the approximate time the FX105A will take to

turn off after an in-band signal has been removed. The effect of this diode is to greatly reduce the

turn-off time with signal input amplitudes greater than 300mV_rms. Figure 4 is for V_DD= 5V; for lower

V_DDthen K_DTincreases.

T

_OFF» K_DTR_WC_3A

So for a maximum signal amplitude of 400mV, a resistor value R_Wof 465kW with a 220nF capacitor

for C_3Aand C_3Band a diode between pins 5 and 6, a de-response time of » 363msec is obtained.

Figure 4 K_DTFactor for T_OFFvs. Signal Input Amplitude

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1.6.2.9 Calculate Signal to Noise Performance

Worst-case S/N calculations depend on calculation of a value “M” using the formula shown below:

M = R_WC_3A/ [3 R_VC_2A]

substituting our example values,

M = 465 x 0.22 / (3 x 200 x 0.01) = 17.05

By substituting this value for M in Figure 5 the minimum required S/N of an in band tone with respect

to an adjacent interfering tone can be found. This has to be increased if the required tone amplitude is

close to the word filter sensitivity V_TH

.

Figure 5 S/N vs. BW Separation

The following formula expresses the reduction in noise immunity as the input signal approaches the

word filter sensitivity V_TH

.

required S/N = 20 log (V_IN/ [V_IN- V_TH] ) + S/N_{Figure 5}

If this S/N is better than required for the application, R_WC_3Acan be reduced, or the operating

bandwidth can be increased to obtain a faster tone detection time.

If the S/N performance is not adequate, the operating bandwidth can be reduced toward the MUBW,

or R_WC_3Acan be increased to improve S/N performance at the expense of a slower response time.

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1.6.2.10 Calculation of PLL Filter Phase Shift

Capacitor C₄is used to phase shift the input to the VCO commutating filter by 30°, thus shifting the

sampling clocks by the same amount. This enables the "Word" sampling filter to sample and integrate

at the maxima and minima of the input tone.

C₄= tan (30°) / [2p f₀R_V] » 0.092 / [f₀R_V] » 164pF

1.6.3

Replacement for FX105

Figure 6 depicts the circuit changes required to replace a FX105 with a FX105A device. A 5V zener

diode and a resistor can be used to generate a 5V supply voltage from an existing 12V supply. If the

Detect Output needs to pull up beyond the 5V supply, a transistor amplifier following the output can

be used.

Figure 6 Circuit changes for 12V to 5V conversion

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1.7

Performance Specification

1.7.1 Electrical Performance

Absolute Maximum Ratings

Exceeding these maximum ratings can result in damage to the device.

Min.

Max.

Units

Supply (V_DD- V_SS

Voltage on any pin to V_SS

Current into or out of V_DDand V_SSpins

Current into or out of any other pin

Maximum Output Switch Load Current

)

-0.3

-30

-20

7.0

V_DD+ 0.3

+30

+20

+10

V

mA

P3/D4 Package

Min.

Max.

Units

Total Allowable Power Dissipation at Tamb = 25°C

... Derating

Storage Temperature

800

13

+125

+85

mW

mW/°C

°C

-55

-40

Operating Temperature

°C

Operating Limits

Correct operation of the device outside these limits is not implied.

Notes

Min.

Max.

Units

Supply (V_DD- V_SS

Operating Temperature

)

2.7

-40

5.5

+85

V

°C

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Operating Characteristics

For the following conditions unless otherwise specified:

V_DD= 3.0V to 5.0V, Tamb = -40°C to +85°C, Load resistance on decoder output pin = 20kW

Notes

Min.

Typ.

Max.

Units

Static Parameters

I_DD

Amplifier Input Impedance

Digital Output Impedance

Analogue Output Impedance

2

-

0.9

200

500

3.0

mA

kW

W

-

1000

W

Dynamic Parameters

Input Signal

Amplitude

Frequency

2

-

40

-

1.0

20,000

-

10

-

Vrms

Hz

mVrms

%f₀

dB

Response Threshold

Deresponse Threshold

BW Range

Signal to Noise Performance

(f₀/2) Subharmonic Rejection

(5 f₀) Harmonic Rejection

1,2

4

30

10

-

-9

30

20

-

5.6

-6

-

VCO

Frequency

3

240

-

120,000

Hz

Frequency Stability (T_C)

Frequency Stability (V_C)

-

-100

2330

-

ppm/°C

ppm/V

Amplifier

Open Loop Gain

Gain Bandwidth Product

Closed Loop Gain

-

60

1.0

0

-

dB

MHz

dB

Word Commutating Filter

Sensitivity (V_TH

)

2

-

25.0

-

mVrms

Notes:

1. With diode (D₁) fitted.

2. For V_DD= 5V. Multiply by V_DD/5V for other supply values.

3. Observing pins 13, 14 or 15 (D4/P3 package) will cause a frequency shift due to additional

loading. If tuning the centre frequency by observing the VCO, design in a buffer amplifier

between pin 15 and the probe/calibration point and tune with no input signal. Otherwise, tune

by observing the detect output band edges while sweeping the input signal. The frequency at

pin 15 is 6xfo, while at pins 13 and 14 the frequency is 3xfo.

4. Adjust according to equation for R₂in Section 1.6.2.

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1.7.2 Packaging

Figure 7 - SOIC Mechanical Outline: Order as part no. FX105AD4

Figure 8 - DIL Mechanical Outline: Order as part no. FX105AP3

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FX105A

Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from

electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent

licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML

has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification.

Specific testing of all circuit parameters is not necessarily performed.

Oval Park - LANGFORD Telephone: +44 (0)1621 875500

Telefax:

e-mail:

+44 (0)1621 875600

sales@cmlmicro.co.uk

http://www.cmlmicro.co.uk

MALDON - ESSEX

CM9 6WG - ENGLAND

CML Microcircuits

COMMUNICATION SEMICONDUCTORS

CML Product Data

In the process of creating a more global image, the three standard product semiconductor

companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc

(USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst

maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA)

Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Micro-

circuits.

These companies are all 100% owned operating companies of the CML Microsystems Plc

Group and these changes are purely changes of name and do not change any underlying legal

entities and hence will have no effect on any agreements or contacts currently in force.

CML Microcircuits Product Prefix Codes

Until the latter part of 1996, the differentiator between products manufactured and sold from

MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX

respectively. These products use the same silicon etc. and today still carry the same prefixes.

In the latter part of 1996, both companies adopted the common prefix: CMX.

This notification is relevant product information to which it is attached.

Company contact information is as below:

CML Microcircuits

(UK)Ltd

CML Microcircuits

(USA) Inc.

CML Microcircuits

(Singapore)PteLtd

COMMUNICATION SEMICONDUCTORS

Oval Park, Langford, Maldon,

Essex, CM9 6WG, England

Tel: +44 (0)1621 875500

Fax: +44 (0)1621 875600

uk.sales@cmlmicro.com

www.cmlmicro.com

4800 Bethania Station Road,

Winston-Salem, NC 27105, USA

Tel: +1 336 744 5050,

0800 638 5577

Fax: +1 336 744 5054

us.sales@cmlmicro.com

www.cmlmicro.com

No 2 Kallang Pudding Road, 09-05/

06 Mactech Industrial Building,

Singapore 349307

Tel: +65 7450426

Fax: +65 7452917

sg.sales@cmlmicro.com

www.cmlmicro.com

D/CML (D)/1 February 2002


型号：	FX105A
厂家：	CML MICROCIRCUITS
描述：	Tone Detector 音频检测器
文件：	总16页 (文件大小：347K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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