Chip Schottky Barrier Rectifier
Comchip
S M D D i o d e S p e c i a l i s t
CDBD8060-G Thru. CDBD8100-G
Reverse Voltage: 60 to 100 Volts
Forward Current: 8.0 Amp
RoHS Device
TO-263/D2PAK
Features
-Batch process design, excellent power dissipation offers
better reverse leakage current and thermal resistance.
0.413(10.50)
0.394(10.00)
-Low profile surface mounted application in order to
0.059(1.50)
0.031(0.80)
0.185(4.70)
optimize board space.
0.169(4.30)
-Low power loss, high efficiency.
-High current capability, low forward voltage drop.
-High surge capability.
0.055(1.40)
0.047(1.20)
4
0.370(9.40)
0.327(8.30)
-Guardring for overvoltage protection.
-Ultra high-speed switching.
1
2
3
0.024(0.60)
0.014(0.35)
-Silicon epitaxial planar chip, metal silicon junction.
0.114(5.30)
0.098(4.40)
0.063(1.60)
0.055(1.30)
-Lead-free parts meet environmental standards of
MIL-STD-19500 /228
0.205(5.20)
0.189(4.80)
0.106(2.70)
0.091(2.30)
Mechanical data
-Epoxy: U/L 94-V0 rate flame retardant.
Case: TO-263/D2PAK, Transfer Molded.
-Terminals: Solderable per MIL-STD-202,
-
2=4
Dimensions in inches and (millimeters)
method 208.
-Polarity: As marked.
Weunting Position: Any
-
3
-Weight:1.46 gram(approx.).
Maximum Ratings (At Ta=25O
C, unless otherwise noted)
CDBD
CDBD
Symbol
Parameter
Unit
8060-G
8100-G
Maximum Recurrent peak reverse voltage
Maximum RMS voltage
VRRM
VRMS
VDC
IO
60
42
60
100
70
V
V
V
A
Maximum DC blocking voltage
Forward rectified current (See fig. 1)
Maximum forward voltage at IO
100
8.0
VF
0.75
0.85
V
A
Forward surge current, 8.3ms single half sine-wave superimposed on
rated load (JEDEC method)
IFSM
175
Maximum Reverse current at 25°C per leg (Note1)
Maximum Reverse current at 100°C per leg (Note1)
Typical Thermal resistance junction to case Per Leg
Operating temperature range
IR
IR
5.0
50
mA
mA
°C/W
°C
RθJC
TJ
4.0
-55 to +150
-55 to +150
Storage temperature range
TSTG
°C
Notes: 1. Pulse Test: 300µS pulse width, 1% duty cycle.
REV:A
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Comchip Technology CO., LTD.