DV75C [CONNOR-WINFIELD]
IEEE 1588 Applications;
| 型号： | DV75C |
| 厂家： | 
CONNOR-WINFIELD CORPORATION |
| 描述： | IEEE 1588 Applications |
| 文件： | 总4页 (文件大小：494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Available at Digi-Key
www.digikey.com
5x7mm
Precision TCXO
Model DV75C
Description:
Features:
• 3.3 Vdc Operation
The Connor-Winfield’s DV75C is a 5x7mm
Surface Mount Temperature Compensated
Crystal Controlled Oscillator (TCXO) with
LVCMOS output. Through the use of Analog
Temperature Compensation the DV75C is
capable of holding sub 1-ppm stabilities
over the -40 to 85°C temperature range. The
DV75C meets STRATUM 3 requirements.
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630-851-5040
• LVCMOS Output
• Frequency Stability: 0.28 ppm
• Temperature Range: -40 to 85°C
• Low Jitter <1ps RMS
• 5x7mm Surface Mount Package
• Tape and Reel Packaging
• RoHS Compliant / Pb Free
www.conwin.com
US Headquarters:
630-851-4722
Applications:
• IEEE 1588 Applications
European Headquarters:
+353-61-472221
• Synchronous Ethernet slave clocks, ITU-T G.8262 EEC options 1 & 2
• Compliant to Stratum 3, GR-1244-CORE, GR-253-CORE & ITU-T-G.812 Type IV
• Wireless Communications
• Small Cells
• Test and Measurement
Absolute Maximum Ratings
Parameter
Minimum
-55
Nominal
Maximum
85
Units
°C
Vdc
Vdc
Notes
Notes
Storage Temperature
Supply Voltage (Vcc)
Input Voltage
-
-
-
-0.5
-0.5
6.0
Vcc+0.5
Operating Specifications
Parameter
Nominal Frequency (Fo)
Minimum
Nominal
Maximum
Units
MHz
ppm
ppm
ppm
ppm
ppm
ppm
ppm
°C
10.0, 12.8 or 20.0, 25.0 and 40.0
Frequency Calibration @ 25 °C
Frequency Stability vs. Temperature
Holdover Stability (Over 24 Hours)
Frequency vs. Load Stability
Frequency vs. Voltage Stability
Static Temperature Hysteresis
Total Frequency Tolerance:
Operating Temperature Range:
Supply Voltage (Vcc)
-1.0
-
1.0
1
2
3
5ꢀ
-0.28
-0.32
-0.05
-0.05
-
-
-
-
-
-
0.28
0.32
0.05
0.05
0.4
5ꢀ
Absolute, 4
5
-4.6
-40
3.135
-
-
-
4.6
85
3.3
-
3.465
6
Vdc
mA
ps rms
ps rms
5ꢀ
6
Supply Current (Icc)
Period Jitter
Integrated Phase Jitter
-
3
5
1.0
-
0.5
Typical Phase Noise Fo = 10.0 MHz
SSB Phase Noise at 10Hz offset
SSB Phase Noise at 100Hz offset
SSB Phase Noise at 1KHz offset
SSB Phase Noise at 10KHz offset
SSB Phase Noise at 100KHz offset
Start-up Time
-
-
-
-
-
-
-99
-122
-145
-152
-153
-
-
-
-
-
-
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ms
10
LVCMOS Output Characteristics
Parameter
Load
Voltage (High) (Voh)
Minimum
Nominal
Maximum
Units
pF
Vdc
Vdc
ꢀ
Notes
-
15
-
-
50
-
-
7
90ꢀVcc
-
10ꢀVcc
55
(Low)
(Vol)
-
45
-
Duty Cycle at 50ꢀ of Vcc
Rise / Fall Time 10ꢀ to 90ꢀ
8
ns
Notes:
1. Initial calibration @ 25°C. Specifications at time of shipment after 48 hours of operation.
2. Frequency stability vs. change in temperature. [± ±Fmaꢀ ꢁ Fminꢂ)±2ꢃFoꢂ].
3. Inclusive of frequency stability, supply voltage change ±± 1ꢄꢂ, load change, aging, for 24 hours.
4. Frequency change after reciprocal temperature ramped over the operating range. Frequency measured before and after at 25°C.
5. Inclusive of calibration @ 25C, frequency vs. change in temperature, change in supply voltage ±± 5ꢄꢂ, load change ±± 5ꢄꢂ, reflow soldering
process and 20 years aging, referenced to Fo
6. BW = 12 KHz to Fo)2 MHz.
Bulletin
Tx355
1 of 4
Page
Revision
04
Date
7. For best performance it is recommended that the circuit connected to this output should have an equivalent input capacitance of 15pF.
01 April 2015
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630-851-5040
www.conwin.com
Package Characteristics
Hermetically sealed crystal mounted on a ceramic package
Package
Environmental Characteristics
Vibration per Mil Std 883E Method 2007.3 Test Condition A
Vibration:
Shock:
Soldering Process;
Mechanical Shock per Mil Std 883E Method 2002.4 Test Condition B.
RoHS compliant lead free. See soldering profile on page 2.
Ordering Information
DV75C-010.0M, DV75C-012.8M, DV75C-020.0M, DV75C-025.0M, DV75C-040.0M
Phase Noise Information
TIE
DV75C-010.0M: WANDER GENERATION IN A STRATUM 3 PLL AT 0.098 Hz BANDWIDTH
MTIE
TDEV
DV75C-010.0M: MTIE per GR-253-CORE
DV75C-010.0M: TDEV per GR-253-CORE
Bulletin
Tx355
2 of 4
04
Page
Revision
Date
01 April 2015
Specifications subject to change without notification. See Connor-Winfield's website for latest revision. All dimensions in inches.
© Copyright 2015 The Connor-Winfield Corporation Not intended for life support applications.
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630-851-5040
www.conwin.com
Package Layout
Suggested Pad Layout
Pad Connections
1:ꢀꢀꢀꢀꢀꢀN/C
ꢀꢀ2:ꢀꢀꢀꢀꢀꢀGround
ꢀꢀ3:ꢀꢀꢀꢀꢀꢀOutputꢀ(Fo)
.±276 ± .±..6
(7±.mm)
.±.79 Max±
(2±.mm)
0.071
(1.8mm)
4 Places
(Top View)
4
3
ꢀꢀ4:ꢀꢀꢀꢀꢀꢀSupplyꢀVoltageꢀ(Vcc)
.±197
0.047
0.165
DV70C 12.2
± .±..6
(1.2mm)
(4.2mm)
(Top View)
12±8 MHZ
(0±.mm)
4 Places
Keep
Pad 1
Out
Area
*
2
1
0.224
(5.7mm)
1
2
Dimensional Tolerance:
± ±..0 (±127mm)
ꢃ Do not route any traces in the keep out area.
It is recommended the neꢀt layer under the
keep out area is to be ground plane.
.±.34
(.±9.mm)
(4 Places)
(Bottom View)
± ±.2 (±0.8mm)
3
4
.±.00
(1±4.mm)
(4 Places)
Alternate Package Layout
Test Circuit
Output Waveform
0.095
(2.4mm)
0.006
0.276
Vcc
Supply
Voltage
(7.0mm)
3
4
1
0.1 uF
Bypass
0.197
0.006
(5.0mm)
10 nF
Bypass
Output
DV75C 1511
40.0 MHz
15 pF
2
N/C
1V/Div
Design Recommendations
Vcc, should have
0.010”(0.254mm)
Recommended
a large copper
area for reduced
inductance.
50 Ohm trace
<1”by design
Vcc
Solder Profile
clearance
Connect a 0.01uF
bypass capacitor
<0.1”(2.54mm)
from the pad.
inductance
for internal
Temperature
260°C
copper flood.
3
4
Buffer
260°C
220°C
180°C
150°C
120°C
Ground
1
Ground,
should have
2
Ground
Top View
Top View
a large copper
area for reduced
inductance.
0
50 Ohm Trace
Without
Vias
10 s
Up to 120 s
60 to 90 s
Typical
OSC
Output
Buffer
Typical
TOP LAYER
Meets IPC/JEDEC J-STD-020C
GROUND LAYER
BOTTOM LAYER
Attention: To achieve optimal frequency stability, and in some cases to meet the specification stated on this data
sheet, it is required that the circuit connected to this TCXO output must have the equivalent input capacitance that is
specified by the nominal load capacitance. Deviations from the nominal load capacitance will have a graduated effect
on the stability of approꢀimately 20 ppb per pF load difference.
Bulletin
Tx355
3 of 4
04
Page
Revision
Date
01 April 2015
Specifications subject to change without notification. See Connor-Winfield's website for latest revision. All dimensions in inches.
© Copyright 2015 The Connor-Winfield Corporation Not intended for life support applications.
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630-851-5040
www.conwin.com
Tape and Reel Dimensions
PIN 1
.69
(17.5mm)
.31
(7.9mm)
.08
(2.0mm)
.08
(2.0mm)
8.46 DIA
(216mm DIA)
.21
(5.4mm)
9.84 DIA
(250mm DIA)
.157
(4.0mm)
Direction
Of
.08
(2.0mm)
Feed
(Customer)
3.15
(80mm)
.315
(8.0mm)
.06 DIA
(1.5mm DIA)
1.00 DIA
(25mm DIA)
.295 (7.5mm)
.07 (1.75mm)
.83 (16.0mm)
MEETS EIA-481A and EIAJ-1009B
2,000 PCS/REEL
Revision History
Revision
Date
Note
00
01
02
03
04
01/11/12
11/26/12
04/15/13
12/03/13
04/01/15
Data sheet released
Removed tri-state information from features and description.
Added "Applications", Phase noise, TIE, MTIE and TDEV plots.
Removed TR information from Ordering Information.
Add frequencies and update to Phase Noise Plot and Operating Specs
Bulletin
Tx355
4 of 4
Page
Revision
04
Date
01 April 2015
Specifications subject to change without notification. See Connor-Winfield's website for latest revision. All dimensions in inches.
© Copyright 2015 The Connor-Winfield Corporation Not intended for life support applications.
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