MSTM-S3-IT3 [CONNOR-WINFIELD]
Stratum 3 Timing Module;
| 型号： | MSTM-S3-IT3 |
| 厂家： | 
CONNOR-WINFIELD CORPORATION |
| 描述： | Stratum 3 Timing Module |
| 文件： | 总16页 (文件大小：1150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSTM-S3-IT3-19.44M
Stratum 3
Timing Module
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630- 851- 5040
www.conwin.com
Features
Application
• -40° to 85° Temp.
Range
The Connor-Winfield MSTM-S3-IT3
Simplified Control Timing Module acts as a
complete system clock module for Stratum 3
timing applications in accordance with GR-
1244, Issue 2 and GR-253, Issue 3.
Connor Winfield’s Stratum 3 timing modules
helps reduce the cost of your design by
minimizing your development time and
maximizing your control of the system clock
with our simplified design.
• 5V Miniature Timing
Module
• Redundant 8kHz
References
• 40 sec., Filtered,
Hold Over History
• Operational Status
Flags
Bulletin
TM034
Page
1 of 16
Revision
P01
Date
04 DEC 02
Issued By
MBatts
General Description
Functional Block Diagram
The Connor-Winfield Stratum 3 Simplified Control Timing
Module acts as a complete system clock module for general
Stratum 3 timing applications.
Figure 1
CNTL A
CNTL B
Free Run
Ref 1
PLL TVL
Free Run
Holdover
Full external control input allows for selection and monitoring
of any of four possible operating states: 1) Holdover, 2) External
Reference #1, 3) External Reference #2, and 4) Free Run. Table
#1 illustrates the control signal inputs and corresponding opera-
tional states.
In the absence of External Control Inputs (A,B), the MSTM
enters the Free Run mode and signals an External Alarm. The
MSTM will enter other operating modes upon application of a
proper control signal. Mode 1 operation (A=1, B=0) results in an
output signal that is phase locked to the External Reference
Input #1. Mode 2 operation (A=0, B=1) results in an output sig-
nal that is phase locked to External Reference Input #2. Hold-
over mode operation (A=1, B=1) results in an output signal at or
near the frequency as determined by the latest (last) locked-
signal input values and the holdover performance of the MSTM.
Free Run ModeFree Run mode operation (A=0, B=0) is a guar-
anteed output of 4.6 ppm of the nominal frequency.
Mode
Control
Ref 2
Alarm Out
Holdover
Reference
Select
Ex Ref 1
Ex Ref 2
LOL/LOR
Phase
Comparator
SYNC_OUT
Stratum
3
OCXO
DAC
Filters
DAC
Tuning
Voltage
Monitor
FIFO
PLL TVL
Alarm signals are generated at the Alarm Output during Hold-
over and Free Run operation. Alarm Signals are also generated
by loss-of-lock, loss of Reference, and by a Tune-Limit indication
from the PLL. A Tune-Limit alarm signal indicates that the
OCXO tuning voltage is approaching within 10% the limits of its
lock capability and that the External Reference Input may be
erroneous. A high level indicates an alarm condition. Real-time
indication of the operational mode is available at unique operat-
ing mode outputs on pins 1-4.
Control loop 0.1 Hz filters effectively attenuate any reference
jitter, smooth out phase transients, comply with wander transfer
and jitter tolerances.
Function Control Table
Table 1
CNTL
A
CNTL
B
Operational
Mode
Ref 1
Ref 2
Hold Over Free Run
PLL_TVL
Alarm Out
0
0
Free Run (Default Mode)
0
0
0
1
0
1
External
Reference
#1
Normal
Tune Limit
LOR + LOL
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
External
Reference
#2
Normal
Tune Limit
LOR + LOL
0
0
0
1
1
1
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
Hold Over
0
0
1
0
0
1
Absolute Maximum Rating
Table 2
Symbol
VCC
Parameter
Minimum
-0.5
Nominal
Maximum
7.0
Units
Volts
Notes
1.0
Power Supply Voltage
Input Voltage
VI
-0.5
VCC + 0.5
100
Volts
1.0
Ts
Storage Temperature
-55
deg. C
1.0
Data Sheet #: TM034
Page 2 of 16
Rev: P01 Date: 12 / 04 / 02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Recommended Operating Conditions
Table 3
Symbol
Vcc
Parameter
Minimum
Nominal
5.00
Maximum
5.25
VCC
Units
Volts
Volts
Volts
ns
Notes
Power supply voltage
High level input voltage - TTL
Low level input voltage - TTL
Input signal transition - TTL
Input capacitance
4.75
2.0
0
VIH
VIL
0.8
tIN
250
CIN
15
pF
VOH
High level output voltage,
IOH = -4.0mA, VCC = min.
2.4
5.25
Volts
2.0
VOL
Low level output voltage,
IOL = 12.0 mA, VCC = min.
0.4
85
Volts
tTRANS
Clock out transition time
4.0
ns
ns
tPULSE
8kHz input reference pulse
width( positive or negative)
30
TOP
Operating temperature
-40
°C
Specifications
Table 4
Parameter
Specifications
19.44 MHz
Notes
Frequency Range (SYNC_OUT)
Supply Current
250 mA typical, 400 mA during warm-up (Maximum)
Dual 8 kHz references
Timing Reference Inputs
Jitter, Wander and Phase Transient Tolerances
Wander Generation
Wander Transfer
3.0
GR-1244-CORE 4.2-4.4, GR-253-CORE 5.4.4.3.6
GR-1244-CORE 5.3, GR-253-CORE 5.4.4.3.2
GR-1244-CORE 5.4
Jitter Generation
GR-1244-CORE 5.5, GR-253-CORE 5.6.2.3
GR-1244-CORE 5.5, GR-253-CORE 5.6.2.1
GR-1244-CORE 5.6, GR-253-CORE 5.4.4.3.3
4.6 ppm over TOP
Jitter Transfer
Phase Transients
Free Run Accuracy
Hold Over Stability
Inital Offset
0.37 ppm for initial 24 hrs
4.0
5.0
0.05 ppm
Temperature
0.28 ppm
Drift
0.04 ppm
Maximum Hold Over History
Pull-in/ Hold-in Range
Lock Time
40 seconds
4.6 ppm minimum
<100 sec.
PLL_TVL Alarm Limit
Extreme 10% ranges of Pull-in/Hold-in Range
NOTES:
1.0: Stresses beyond those listed under Absolute Maximum Rating may cause damage
to the device. Operation beyond Recommended Conditions is not implied.
4.0: Hold Over stability is the cumulative fractional frequency offset as described by
GR-1244-CORE, 5.2
5.0: Pull-in Range is the maximum frequency deviation from nominal clock rate on the
reference inputs to the timing module that can be overcome to pull into synchronization
with the reference
2.0: Logic is 3.3V CMOS
3.0
GR-1244-CORE 3.2.1
Data Sheet #: TM034
Page 3 of 16
Rev: P01 Date: 12 / 04 / 02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Pin Description
Table 5
Pin #
Connection
Description
1
2
3
4
5
6
HOLD OVER
REF 1
Indicator output. High output when Hold Over mode is selected by control pins.
Indicator output. High output when Ref 1 mode is selected by control pins.
Indicator output. High output when Ref 2 mode is selected by control pins.
Indicator output. High output when Free Run mode is selected by control pins.
Ground
REF 2
FREE RUN
GND
ALARM _OUT
Alarm output. High output if module is in Free Run, or Hold Over, or LOR, or LOL, or
PLL_TVL mode.
7
8
9
CNTL A
CNTL B
PLL_TVL
Mode control input
Mode control input
Tuning Voltage Limit alarm output. High output when Sync_Out is near the extreme
10% ranges of the Pull-in/Hold-in range.
10
11
12
13
14
15
16
17
18
GND
Ground
SYNC_OUT
GND
Primary timing output signal. Signal is sychronized to reference.
Ground
N/C
Do not connect. It may affect the module adversely if a signal is apllied.
GND
Ground
EX_REF_2
GND
External Input Reference #2
Ground
EX_REF_1
VCC
External Input Reference #1
+5V dc supply
Typical Application
Figure 2
BITS
System
Signal
Input Select
Line Card #1
Timing Card #1
#1
Clockout
RCV
Y
CW’s SCG
2500/4500
MUX
CW’s STM/MSTM module
#N
S
Timing Card #2
Line Card #N
#1
Clockout
RCV
Y
MUX
CW’s SCG
2500/4500
CW’s STM/MSTM module
#N
S
System Select
Data Sheet #: TM034
Page 4 of 16
Rev: P01 Date: 12 / 04 / 02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical Module Test Set-up
Figure 3
Vcc
Stratum 1 Reference
1 - Hold Over
2 - Ref 1
5 Vdc - 18
Ext. Ref 1 - 17
Gnd - 16
8 kHz
Stratum 1 Traceable
Signal
3 - Ref 2
4 - Free Run
5 - Gnd
Ext. Ref 2 - 15
Gnd - 14
Oscilloscope
Vcc
Probe
Probe
6 - Alarm Out
7 - Cntl A
N/C - 13
Gnd - 12
Frequency Counter
Sync_Out - 11
Gnd - 10
8 - Cntl B
9 - PLL_TVL
Top View
Typical System Test Set-up
Figure 4
GPS or LORAN
Timing Source
This device supplies system time
information. It can be thought of as
supplying "absolute time" reference
information
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Target System Under Test
External
Standards
Reference
DS1 rate RZ (1.544 MHz), E1 rate RZ or 8 kHz
clock RZ with noise modulation
Arbitrary
Waveform
Generator
Input
Compliance
Documents
Clock or BITS logic level
clock input (TTL, CMOS,
etc.)
MTIE, TDEV, Wander Transfer,
and Wander Generation Plots
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Arbitrary
Waveform
Generator
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e
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r
a
t
i
o
n
T
i
m
e
(
s
e
c
)
External
Reference
Input
Source]
Time-stamped ensemble
based on absolute time
reference (10MHz input)
10
MHz
DS1 rate [1.544 MHz] BITS Bipolar
Phase Error data output
DS-1, OC-3, OC-12 electrical or optical signals
External
Tektronix
SJ300E
10
Reference
HP53310A
Input
MHz
Modulation Analyzer / Time Interval Analyzer
Wander Analyzer data (IEEE-488)
External
Reference
Input
IEEE-488 Controller
Platform for software
HP 53305A Phase Analyzer
HP E1748A Sync
Measurement
Tektronix Wander Analyzer
Data Sheet #: TM034
Page 5 of 16
Rev: P01 Date: 12 / 04 / 02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
MSTM-S3-IT3 Typical Current Draw
Figure 5
0.4
0.38
0.36
0.34
0.32
0.3
0.28
0.26
0.24
0.22
0.2
0
10
20
30
40
50
60
Time (sec)
MSTM-S3-IT3 Typical Phase Noise Plot
Figure 6
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
10.0E+0
100.0E+0
1.0E+3
10.0E+3
100.0E+3
1.0E+6
10.0E+6
Hz
Data Sheet #: TM034
Page 6 of 16
Rev: P01 Date: 12 / 04 / 02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
MSTM-S3-IT3 Typical Phase Gain
Figure 7
10.00
0.00
-10.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
-100.00
-110.00
0.01
0.10
1.00
10.00
100.00
1000.00
10000.00
Reference Modulation Frequency (Hz)
MSTM-S3-IT3 Typical Hold Over Stability over Temperature
Figure 8
250
200
150
100
50
0
0
10
20
30
40
50
60
70
Temperature (C°)
Data Sheet #: TM034
Page 7 of 16
Rev: P01 Date: 12 / 04 / 02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical Wander Generation MTIE
Figure 9
1000
GR1244, Fig 5.2 (A)
GR1244, Fig 5.2 (B)
GR253-5.4.4.3.2, Fig 5.17
Jittered Reference
Pristine Reference
Temperature Stressed Reference
100
10
1
0.1
1
10
100
1000
10000
100000
1000000
Observation Time (sec.)
Typical Wander Generation TDEV
Figure 10
100
GR1244, Fig 5.1
Jittered Reference
Pristine Reference
Temperature Stressed Reference
10
1
0.1
0.01
0.1
1
10
100
1000
10000
Integration Time (sec.)
Data Sheet #: TM034
Page 8 of 16
Rev: P01 Date: 12 / 04 / 02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical Calibrated Wander Transfer TDEV
Figure 11
10000
1000
100
10
TDEV (ns)
GR1244, Fig 5.3
1
0.01
0.1
1
10
100
1000
10000
Integration Time (Sec.)
Typical Reference Switch MTIE
Figure 12
10000
1000
100
10
GR1244, Fig 5-7, Stratum 2/3E
GR1244, Fig 5-7, Stratum 3/4E
MTIE (ns)
1
0.001
0.01
0.1
1
10
100
1000
Observation Time (sec)
Data Sheet #: TM034
Page 9 of 16
Rev: P01 Date: 12 / 04 / 02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical Entry Into Hold Over MTIE
Figure 13
10000
1000
100
10
G R-1244 O bjective, F ig. 5-8
G R-1244 Requirem ent, F ig. 5-8
G R-253, F ig. 5-19, Requirem ent
Typical M TIE
1
0.001
0.01
0.1
1
10
100
1000
O b servatio n T im e (seco n d s)
Typical Return from Hold Over MTIE
Figure 14
10000
1000
100
10
G R-1244 Requirem ent, F ig. 5-7 M TIE (ns )
Ty pic al M TIE
1
0.001
0.01
0.1
O b se rva tio n T im e (se c.)
1
10
100
Data Sheet #: TM034
Page 10 of 16
Rev: P01 Date: 12 / 04 / 02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical 1us Phase Transient TIE
Figure 15
1200
1000
800
600
400
200
0
-200
0
1
2
3
4
5
6
7
8
9
10
Time (sec)
Typical Phase Transient MTIE
Figure 16
10000
1000
100
10
G R-253, F ig . 5-19, Re q u ire m e n t
M T IE (n s)
1
0.01
0.1
1
10
100
1000
O b servatio n T im e (sec)
Data Sheet #: TM034
Page 11 of 16
Rev: P01 Date: 12 / 04 / 02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
MSTM-S3-IT3 Mode Indicator Delay
Figure 17
Change in
Operational Mode
Operational Mode
Indicator
∆
tm
2 msec <∆tm < 4.125 msec
Tuning Voltage Limit Alarm Timing Diagram
Figure 18
TVL Limit High
Frequency
Sync_Out
(Nominal Frequency)
TVL Limit Low
Frequency
TVL Alarm
&
Alarm Out
∆t
0 < ∆t < 2.125 msec
*The DAC is updated only when the output changes level. The maximum
update rate is 8 kHz
Data Sheet #: TM034
Page 12 of 16
Rev: P01 Date: 12 / 04 / 02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Loss of Reference Timing Diagram
Figure 19
External
Reference
Input
Alarm
tAon
tAoff
2 msec < tAon < 6.125 msec
0 msec < t off < 2.125 msec
Solder Clearance
Figure 20
.020" MAX.
.020"
.030"
PIN LAND
ALL SOLDER AND/OR WIRE TAGS
SHALL NOT EXTEND MORE THAN .020"
BELOW PC BOARD BOTTOM SURFACE
Data Sheet #: TM034
Page 13 of 16
Rev: P01 Date: 12 / 04 / 02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
MECHANICAL OUTLINE:
GROUND AND POWER SUPPLY LINES:
The mechanical outline of the MSTM-S3-IT3 is
Power specifications will vary depending primarily
shown in Figure 21. The board space required is 2” x on the temperature range. At wider temperature
2”. The pins are .040” in diameter and are .150” in
length. The unit is spaced off the PCB by .030”
shoulders on the pins. Due to the height of the
device it is recommended to have heat sensitive
devices away where the air flow might not be
blocked.
ranges starting at 0 to 70 deg. C., an ovenized
oscillator, OCXO, will be incorporated. The turn-on
current for an OCXO requires a peak current of about
.4A for about a minute. The steady state current will
the vary from 50-150 mA depending on the
temperature. It is suggested to plan for the peak
current in the power and ground traces pin 18 and
pin 5. The other four ground pins 10, 12, 14, and 16
are intended for signal grounds.
PAD ARRAY AND PAD SPACING:
The pins are arranged in a dual-in-line
configuration as shown in Figure 21. There is .2”
space between the pins in-line and each line is
separated by 1.6”. See Figures 21 & 22 and Table
6.
POWER SUPPLY REGULATION:
Good power supply regulation is recommended for
the MSTM-S3-IT3 The internal oscillators are
regulated to operate from 4.75 - 5.25 volts. Large
jumps within this range may still produce varying
degrees of wander. If the host system is subject to
large voltage jumps due to hot-swapping and the like,
it is suggested that there be some form of external
regulation such as a DC/DC converter.
PAD CONSTRUCTION:
The recommended pad construction is shown in
Figure 23. For the pin diameter of .040” a hole
diameter of .055” is suggested for ease of insertion
and rework. A pad diameter of .150” is also
suggested for support. This leaves a spacing of
.050” between the pads which is sufficient for most
signal lines to pass through.
SOLDERING RECOMMENDATIONS:
Due to the sensitive nature of this part, hand
soldering or wave soldering of the pins is
recommended after reflow processes.
SOLDER MASK:
A solder mask is recommended to cover most the
top pad to avoid excessive solder underneath the
shoulder of the pin to avoid rework damage. See
Table 6 and Figure 23.
WASHING RECOMMENDATIONS:
The MSTM-S3-IT3 is not in a hermetic enclosure.
It is recommended that the leads be hand cleaned
after soldering. Do not completely immerse the
module.
VIA KEEP OUT AREA:
It is recommended that there be no vias or feed
throughs underneath the main body of the module
between the pins. It is suggested that the traces in
this area be kept to a minimum and protected by a
layer of solder mask. See Figure 22.
MODULE BAKEOUT:
Do not bakeout the MSTM-S3-IT3
Data Sheet #: TM034
Page 14 of 16
Rev: P01 Date: 12 / 04 / 02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Package Dimensions
Characteristic Measurements
Figure 21
Table 6
Characteristic Item
Pad to Pad Spacing
Solder pad top O.D.
Solder pad top I.D.
Measurement (inches)
0.200
0.150
0.055
0.150
0.055
0.070
0.155
1.600
Solder pad bottom O.D.
Solder pad bottom I.D.
Solder mask top dia.
Solder mask bottom dia.
Pin row to row spacing
Recommended Footprint Dimensions
Side Assembly View
Figure 22
Figure 23
TOP SIDE
SOLDER RESIST
(OVER PAD)
PCB
SIDE VIEW
BOTTOM SIDE
SOLDER RESIST
(UP TO PAD)
Data Sheet #: TM034
Page 15 of 16
Rev: P01 Date: 12 / 04 / 02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630- 851- 5040
www.conwin.com
Revision
P00
Revision Date
12/07/01
Note
Final Release
P01
12/04/02
Increased upper temp. range to 85° C
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