SCG4505-077.76M [CONNOR-WINFIELD]
Support Circuit, 1-Func,;
| 型号： | SCG4505-077.76M |
| 厂家： | 
CONNOR-WINFIELD CORPORATION |
| 描述： | Support Circuit, 1-Func, ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总16页 (文件大小：761K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SCG4505 V3.0
Synchronous Clock
Generators
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630-851-5040
www.conwin.com
Features
• LVPECL Output Frequencies @ 155.52 MHz
or 77.76 MHz
• CMOS Output Frequency @ 77.76 MHz
• Phase Locked Output Frequency Control
• Intrinsically Low Jitter Crystal Oscillator
• LVPECL Outputs with Disable Function
• Dual Input References
• LOR & LOL combined alarm output
• Force Free Run Function
• Automatic Free Run operation on loss of both
References A & B
Bulletin
SG058
Page
1 of 16
• Input Duty Cycle Tolerant
• 3.3V dc Power Supply
• Small Size: 1 Square Inch
Revision
P00
Date
19 AUG 02
Issued By
MBatts
General Description
Maximum Dimension Package Outline
The SCG4505 is a mixed-signal phase locked loop
generating LVPECL outputs from an intrinsically low
jitter, voltage controlled, crystal oscillator. The LVPECL
outputs may be disabled. The SCG4505 also provides
a CMOS Output @ 77.76 MHz on the REF_OUT pin.
The SCG4505 can lock to one of two external
references, which is selectable using the SELAB input
select pin. The unit has a fast acquisition time of about
1 second and it is tolerant of different reference duty
cycles.
Figure 1
The SCG4505 includes an alarm output that
indicates deviations from normal operation. If a Loss-
of-Reference (LOR) or Loss-of-Lock (LOL) is detected
the alarm with indicate the need for a reference
rearrangement. If both references A and B are absent
the module will enter Free Run operation. The FRstatus
pin will indicate that the module is in Free Run
operation. Frequency stability during Free Run
operation is guaranteed to 20 ppm. Additionally the
Free Run mode may be entered manually.
The package dimensions are 1.00” x 1.025” x 0.45”
on a 6 layer FR4 board with castellated pins. Parts are
assembled using high temperature solder to withstand
63/37 alloys, 180°C surface mount reflow processes.
Block Diagram
Figure 2
FREE RUN STATUS
FORCE
FREE RUN
ALARM
Q
REFA
LOW JITTER
VCXO
8 KHz PHASE
ANALOG
FILTER
DPFD
ALIGNER
REFB
QN
1 / N
SEL AB
77.76 MHz CMOS
on REF_OUT
PIN
ENABLE/
TRI-STATE
Preliminary Data Sheet #: SG058
Page 2 of 16
Rev: P00
Date: 08/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Absolute Maximum Rating
Table 1
Symbol
Parameter
Minimum
-0.5
Nominal
Maximum
+4.0
Units
Volts
Volts
°C
Notes
1.0
Vcc
Power Supply Voltage
Input Voltage
-
-
-
Vi
-0.5
+5.5
1.0
Ts
Storage Temperature
-65.0
+100
1.0
Operating Specifications
Table 2
Symbol
Vcc
Icc
Parameter
Minimum
Nominal
Maximum
Units
Volts
mA
Notes
2.0
Power Supply Voltage
Power Supply Current
Temperature Range
3.135
3.3
3.465
170
230
280
70
-
5.0
To
0
-
°C
fin
Input Frequency
-
8
kHz
MHz
MHz
ppm
ppm
Hz
fout
LVPECL Synchronized Output Frequency
CMOS Output Frequency
Free Run Frequency
Capture/pull-in range
Jitter Filter Bandwidth
-
77.76 or 155.52
-
fref
-
77.76
-
ffr
-20
-25
-
-
-
-
-
20
25
10
-
fcap
fbw
3.0
tjtol
Input Jitter Tolerance
1
µs
(Input Jitter Frequencies ≥ 10 Hz)
taq
Acquisition Time
-
1
-
s
4.0
5.0
trf
Output Rise and Fall Time (20% 80%)
Output Duty Cycle
100
40
225
50
350
60
ps
%
DC
MTIEsr
MTIE at Synchronization Rearrangement
GR-253-CORE.1999 R5-136
6.0, 7.0
Output Jitter Specifications
Table 3
Jitter BW 10 Hz - 1 MHz
SONET Jitter BW 12 kHz - 20 MHz
Frequency (MHz)
pS (RMS)
m UI
pS (RMS)
m UI
LVPECL (Synchronized Output)
77.76
10 Typ.
10 Typ.
0.776 Typ.
1.556 Typ.
1 Max.
1 Max.
0.076 Max.
155.52
0.156 Max.
CMOS (Filtered Reference Output)
77.76
10 Typ.
0.776 Typ.
2 Typ.
0.155 Typ.
NOTES:
1.0 Operation of the device at these or any other condition beyond those listed under Operating Specifications is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
2.0 Requires external regulation and supply decoupling. (22 uF, 330 pF)
3.0 3db loop response.
4.0 From a 20 PPM step in reference frequency at 25°C @ 3.3V
5.0 50-ohm load biased to 1.3 volts.
6.0 Entry into Free Run doesn’t meet requirement for initial 2.33 seconds of self-timing.
7.0 If the selected reference is removed system response to the ALARM must be less than 100ns.
Preliminary Data Sheet #: SG058 Page 3 of 16
Rev: P00
Date: 08/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Input And Output Characteristics
Table 4
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
CMOS Input and Output Characteristics
Vih
High Level Input Voltage
Low Level Input Voltage
I/O to Output Valid
2.0
0.0
-
-
-
-
-
-
-
-
5.5
0.8
10
10
-
V
Vil
V
Tio
Cl
ns
pF
V
Output Capacitance
-
Voh
Vol
Tir
High Level Output Voltage
Low Level Output Voltage
Input Reference Pulse Width
2.4
-
0.4
-
V
12.5
ns
LVPECL Output Characteristics
Voh
High Level PECL Voltage
2.27
2.34
1.51
-
2.52
1.68
10
V
Vol
Low Level PECL Voltage
Output Capacitance
1.49
V
Cl
-
-
pF
ps
Tskew
Differential Output Skew
50
-
Input Selection / Output Response
Table 5
INPUTS
REFA
OUTPUTS
ALARM
NOTE
RESET
ENABLE SELAB
REFB
X
FR
X
X
1
FRstatus
Q
X
0
QN
1
X
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
X
X
X
0
1
0
1
1
0
X
X
1
X
1
0
0
0
0
0
0
1
X
X
X
0
0
1
0
1
0
1
X
1
FR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FR
RA
RB
U
A
A
0
A
A
0
NA
NA
A
A
0
A
0
RB
U
NA
NA
NA
0
A
0
RA
FR
NA
0
NOTES:
A
Active
FR Free Run Mode
NA Not Active
RA Locked to Reference A
RB Locked to Reference B
U
X
Unstable (due to conditions shown, switch to active reference or Free Run)
Don’t care
Preliminary Data Sheet #: SG058
Page 4 of 16
Rev: P00
Date: 08/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Pin Description
Table 6
Pin #
Pin Name
Pin Information
Note
9.0
1
ENABLE/TRI-STATE
VCXO Enable. (Enable = 0, Disable = 1 = CMOS Outputs Tri-stated)
No Connection, Internal Factory Programming Input.
No Connection, Internal Factory Programming Input.
CMOS Reference Frequency Input.
Input Reference Select Pin. (REFA = 0, REFB = 1)
RESET. (RESET = 1)
2
TCK
TDO
REFA
SELAB
RESET
REFB
Vee
8.0
3
8.0
4
5
9.0
9.0
6
7
CMOS Reference Frequency Input.
Ground.
8
9
FRstatus
Vcc
Free Run Status. (FR = 1)
10
11
12
13
14
15
16
17
18
Supply Voltage relative to ground.
REF_OUT
ALARM
FR
Filtered 77.76 MHz CMOS output
Loss of Reference / Lock alarm. (Alarm = 1)
Force Free Run. (Phase Lock = 0, Free Run = 1)
No Connection, Internal Factory Programming Input.
No Connection, Internal Factory Programming Input.
LVPECL Complementary Output.
9.0
8.0
8.0
TDI
TMS
QN
Vee
Ground.
Q
LVPECL Output.
NOTES
8.0 Do not connect pin
9.0 Input pulled to ground
Circuit Board Footprint & Keepout Recommendations
Figure 3
0.8650
[21.97 mm]
0.0650
[1.65 mm]
Keep Out
Area
0.8400
[21.34 mm]
1.0400
[26.42 mm]
0.1000
[2.54 mm]
0.1000
[2.54 mm]
0.0350
[0.89 mm]
1.0700
[27.18 mm]
Preliminary Data Sheet #: SG058 Page 5 of 16
Rev: P00
Date: 08/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Loss of Reference Condition Alarm Timing
Figure 4
Start-up
Region
Alarm Output
(LOR + LOL)
LOR
(Internal Signal)
4
LOL
(Internal Signal)
2
1
1
Phase Detector
(Internal Signal)
3
External Reference
(Selected Input A or B)
Internal Reference
(Internal Signal)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
AlarmTiming Legend
Use for all alarm timing diagrams
Table 7
SCG4505 Alarm Characteristics
< 1 µsec
1 µsec
1
2
3
4
5
> 1 µsec
124 µsec(min) to 374 µsec(max) after LOL
Minimum pulse width = 2 µs
During Start-up, The LOL Alarm will pulse
during the few seconds of operation
Start-up Region
Preliminary Data Sheet #: SG058
Page 6 of 16
Rev: P00
Date: 08/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Loss of Lock Condition Alarm Timing
Figure 5
Alarm Output
(LOR + LOL)
LOR
(Internal Signal)
LOL
(Internal Signal)
5
1
1
1
1
1
Phase Detector
(Internal Signal)
3
3
External Reference
(Selected Input A or B)
Internal Reference
(Internal Signal)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Preliminary Data Sheet #: SG058 Page 7 of 16
Rev: P00
Date: 08/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B when both are good signals
Figure 6
Ref A
Ref B
Alarm
LOL portion of
Alarm is
Blanked
0.5 sec
Sel A/B
New Reference
Qualification time
Switch from A to B when Reference B is lost
Figure 7
Ref A
Ref B
Alarm
~8ns
Sel A/B
Preliminary Data Sheet #: SG058
Page 8 of 16
Rev: P00
Date: 08/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B after Reference A is lost
Figure 8
Ref A
Ref B
Alarm
Blanked
Alarm
126µs
Sel A/B
New Reference
Qualification time
Switch from A to B when A is out of range
Figure 9
Out of
Range
Ref A
Ref B
Alarm
In
Range
Alarm
Blanked
Sel A/B
New Reference
Qualification time
Preliminary Data Sheet #: SG058 Page 9 of 16
Rev: P00
Date: 08/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B when B is out of range
Figure 10
Switch from A to B when B is out of range
In
Range
Ref A
Ref B
Alarm
Out of
Range
Alarm
Blanked
SEL A/B
New Reference
Qualification Time
0.5 sec.
Switch from A to B when B is out of range
Figure 11
Ref A
Ref B
Alarm
Alarm
Blanked
Sel A/B
New Reference
Qualification time
Free Run
Status
Preliminary Data Sheet #: SG058
Page 10 of 16
Rev: P00
Date: 08/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical MTIE Measurement
Figure 12
Typical TDEV Measurement
Figure 13
Preliminary Data Sheet #: SG058 Page 11 of 16
Rev: P00
Date: 08/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Recommended PECLTermination
Figure 14
3.3 VDC
3.3 VDC
3.3 VDC
130
82
Vcc
Q
Vcc
D
50 OHM Transmission Line
50 OHM Transmission Line
SCGxxx
LVPECL
OUTPUT
LVPECL
INPUT
QN
DN
GND
GND
130
82
3.3 VDC
3.3 VDC
Vcc - 2 VDC
3.3 VDC
50
Vcc
Q
Vcc
D
50 OHM Transmission Line
50 OHM Transmission Line
SCGxxx
LVPECL
OUTPUT
LVPECL
INPUT
QN
DN
GND
GND
50
Vcc - 2 VDC
3.3 VDC
3.3 VDC
150
Vcc
Q
Vcc
D
50 OHM Transmission Line
50 OHM Transmission Line
50
SCGxxx
LVPECL
OUTPUT
LVPECL
INPUT
100
50
QN
DN
GND
GND
150
If PECL outputs do not drive a long line (< 0.5”),
a single 150Ω termination resistor to ground may be used for each pin.
Preliminary Data Sheet #: SG058
Page 12 of 16
Rev: P00
Date: 08/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Tape and Reel Packaging
Figure 15
Preliminary Data Sheet #: SG058 Page 13 of 16
Rev: P00
Date: 08/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Solder Profile
Figure 16
250
200
150
100
50
Temp
(C˚)
0
1
2
3
4
5
6
7
8
Time(minutes)
Recommended Reflow Profile
Peak Temp:217C˚
MaxRiseSlope:1.5C˚/Sec
Time Above150C˚:100Sec
Ordering Information
SCG{XXXX}-{FFF.FFF}{M}
XXXX equals a specific model (4505)
FFF.FFF equals the Oscillator Output frequency (077.76, 155.52)
M equals MHZ and is added to all part numbers
Example: To order an SCG4505 with an Oscillator Output of 155.52 MHz,
Order part number SCG4505-155.52M
Preliminary Data Sheet #: SG058
Page 14 of 16
Rev: P00
Date: 08/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Preliminary Data Sheet #: SG058 Page 15 of 16
Rev: P00
Date: 08/19/02
© Copyright 2002 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Revision
Revision Date
Note
P00
08/19/02
Preliminary informational release
相关型号：
SCG4525
PLL Based Clock Driver, 4000/14000/40000 Series, 1 True Output(s), 1 Inverted Output(s), 1 X 1.025 INCH, 0.45 INCH HEIGHT, SMT-18
CONNOR-WINFIE
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