SFX-424G-DFF-F1XX [CONNOR-WINFIELD]
Support Circuit, 1-Func, ROHS COMPLIANT, SURFACE MOUNT PACKAGE-14/13;
| 型号： | SFX-424G-DFF-F1XX |
| 厂家： | 
CONNOR-WINFIELD CORPORATION |
| 描述： | Support Circuit, 1-Func, ROHS COMPLIANT, SURFACE MOUNT PACKAGE-14/13 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总8页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SFX-424G
Synchronous Clock
Generators
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630- 851- 5040
www.conwin.com
Applications
• SONET / SDH / ATM
• DWDM / FDM
• FEC (Forward Error Correction)
Features
• 3.3V High Precision PLL
• Jitter Generation OC-192 Compliant
• Surface Mount
• Accepts up to 4 Inputs from an External MUX
• Inputs Compatible with CMOS/LVDS/LVPECL
• Frequency Translation up to 800 MHz
• Alarm detection for Loss of Lock/ Loss of Reference condition
• ROHS Compliant
Bulletin
SG124
Page
1 of 8
Revision
00
Date
09 DEC 08
Issued By
ENG
General Description
The SFX-424G is a high precision frequency translator that
translates up to four inputs from 8 kHz to 100MHz , to output
frequencies between 8 MHz and 800 MHz. The SFX-424G
supports all major FEC rates such as 15/14, 255/237 etc.
SFX-424G is well suited for use in line cards, service
termination cards and similar functions to provide reliable
reference, phase locked, synchronization for TDM, PDH,
SONET and SDH network equipment. The SFX-424G provides
a jitter filtered, wander following output signal synchronized to
a superior Stratum or peer input reference signal.
The SFX-424G includes a lock detect alarm output.
The PLL control voltage is brought out through a 470 kΩ
resistor and can be used to determine when the pull
range limits are reached. The LVPECL outputs may be
put into the tri-state high impedance condition for
external testing purposes by asserting a high signal to
the Enable/Disable pin.
Parts are assembled using high temperature solder to
withstand surface mount reflow process. This product is
compliant with all required ROHS specifications.
Absolute Maximum Rating
Table 1
Symbol
Parameter
Minimum
-0.3
Nominal
Maximum
4.0
Units Notes
Volts
Vcc
Power Supply Voltage (OptionD)
Input Voltage
-
-
V
I
-0.2
Vcc +0.3V
Volts
Ts
Storage Temperature (OptionF)
Storage Temperature (OptionA)
-55
-40
-
-
125
85
°C
°C
Specifications
Table 2
Symbol
Parameter
Minimum
Nominal
Maximum
Units Notes
fIN
Input Frequencies
8 k
-
100 M
Hz
fOUT
Output Frequencies (LVPECL)
Output Frequencies (LVCMOS)
19.44 M
8 M
-
-
800 M
130 M
Hz
Hz
Vcc
ICC
Supply Voltage (3.3 VDC
Supply Current
)
3.13
-
3.3
60
3.46
-
Volts
mA
LVCMOS INPUT
VIH
VIL
2
-0.3
-
-
VCC
0.8
Volts
Volts
LVPECL INPUT
VIH
VIL
1.49
0.86
-
-
2.72
2.125
Volts
Volts
LVCMOS OUTPUT (Option A)
LVPECL OUTPUT (Option F)
TYP. LVCMOS
VOH
VOL
V
(Temp. Range C = 0°C to 70°C)
(Temp. Range C = 0°C to 70°C)
(Temp. Range F = -40°C to 85°C)
(Temp. Range F = -40°C to 85°C)
Rise/Fall Time @20% to 80%
2.275
-
-
-
-
V
V
V
V
ns
-
1.68
2.275
VOH
TRO/LTF
-
-
1.68
1.5
0.6
SYM
Output Symmetry
45
-
55
1
%
JGEN
Jitter Generation RMS
(12 kHz - 20 MHz)
-
ps
JTRAN
APR
TOP
Jitter Transfer
-
-
-
0.1
dB
1.0
Input Frequency Tracking
±40
ppm
Operating Temperature
F =
C =
-40
0
-
-
85
70
°C
°C
NOTES: 1.0: GR-253-CORE, Sec. 5.6.2.1.2
Data Sheet #: SG124 Page 2 of 8
Rev: 00
Date: 12/09/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Functional Block Diagram
Figure 1
LD
(Pin 10)
470 kΩ
VMON
(Pin 5)
F
OUT
Frequency
Divider
Loop
Filter
(Pin 8)
FIN
(Pin 13)
OSC
0.01 µF
CFOut
(Pin 9)
Frequency
Divider
10 kΩ
SEL0
(Pin 1)
Microprocessor
SEL1
(Pin 2)
10 kΩ
OD
(Pin 6)
Pin Description
Table 3
PIN # SYMBOL
I/O
Level
LVTTL
LVTTL
Supply
Function
1
2
3
4
5
SEL0
SEL1
GND
I
I
Input Frequency Select .* 10kΩPull down resistor
Input Frequency Select .* 10kΩ Pull down resistor
GND
Ground
Missing
VMON
OD
O
I
Analog
VCXO Control VoltageUnder locked conditions VMON should
be > 0.3V and <3.0V. The Input Frequency may be out of
range if the voltage is outside of this voltage range.
6
LVCMOS
Output Disable
Disable = Logic 1
Enable = Logic 0 or No Connect
7
8
9
GND
FOUT
GND
O
Supply
Ground
LVPECL or LVCMOS
LVPECL or GND
Frequency Output
CFOUT
O
Complementary Frequency Output
Note: For the LVCMOS Option, this
connection is tied to GND
10
LD
O
LVCMOS
Lock Detect
Locked = Logic 1
Loss of Signal = Logic 0
11
12
13
GND
GND
FIN
GND
GND
I
Supply
Supply
Ground
Ground
LVPECL or LVCMOS
Input FrequencyNote: Input is AC coupled
for handling either LVCMOS or LVPECL input signals
14
VCC
VCC
Supply
Power Supply Voltage (3.3V ±5%)
Data Sheet #: SG124 Page 3 of 8
Rev: 00
Date: 12/09/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Output Load and Power Supply Filtering Recommendations
Figure 2
*
It is highly recommended
*
*
*
that either a linear regulator
or bypass capacitors be
used. Typical values would
be 10 uF, 0.1 uF, 100 pF.
Only Required for Option F
VCC -2 VDC
LD
(Pin 10)
470 kΩ
VMON
(Pin 5)
50Ω
50Ω
FIN
(Pin 13)
REF 1
REF 2
FOUT
Frequency
Divider
Loop
Filter
OSC
(Pin 8)
REF 3
REF 4
0.01 µF
CFOUT
(Pin 9)
Frequency
Divider
10 kΩ
SEL0
(Pin 1)
Microprocessor
SEL1
(Pin 2)
10 kΩ
OD
(Pin 6)
Package Dimensions
Recommended Footprint Dimensions
Figure 3
Figure 4
1.905
mm
[ inches ]
mm
(in)
[0.075]
3.048
[0.120]
19.81
.780
5.84
.230
20.32
.800
C
L
12.19
.480
13.72
.540
PIINN 11
4.29
.169
R
00..5511
.020
2.54
.100
7.620
2.540
[0.100]
[0.300]
C
L
15.240
[0.600]
Data Sheet #: SG124 Page 4 of 8
Rev: 00
Date: 12/09/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Solder Profile
Figure 5
300
Peak Temp.
250
200
150
100
50
245°-255°C for 15 sec Typ.
221°C
Reflow Zone
30/90 sec
(Min/Max)
Soaking Zone
60-90 sec Typ.
(2 min Max)
Ramp Slope not
to exceed
3°C/sec
0
0
50
100
150
200
250
300
350
Time (sec)
Data Sheet #: SG124 Page 5 of 8
Rev: 00
Date: 12/09/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Standard Frequencies
8 kHz
C
D
E
F
38.8800 MHz
44.7360 MHz
51.84 MHz
X
Y
0
1
2
3
4
5
6
7
8
9
S
S
16 kHz
64 kHz
1.024 MHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
13.0000 MHz
16.3840 MHz
19.4400 MHz
20.4800 MHz
26.0000 MHz
27.0000 MHz
61.44 MHz
H
J
77.76 MHz
82.944 MHz
K
L
112.00 MHz
139.2640 MHz
155.5200 MHz
166.6286 MHz
622.0800 MHz
666.5143 MHz
Input Freq. not listed
Output Freq. not listed
M
N
P
R
T
W
Ordering Information
SFX-424G- X X X - X X X X
Output Frequency (Options L - 9)
See standard frequencies chart above.
* If the desired frequency is not listed,
Please Consult a sales representative
for availabilty of additional frequencies.
Supply Voltage
D = 3.3 VDC
±5%
Output Logic
A = LVCMOS
F = Comp. LVPECL
Input Frequency (Options C - 3)
See standard frequencies chart above.
* If the desired frequency is not listed, Please Consult
a sales representative for availabilty of additional
frequencies.
Temperature Range
C = 0˚C to 70˚C
F = -40˚C to 85˚C
Input Logic
A = LVCMOS
F = LVPECL
Number of Input Frequencies
1: 1 Input Frequency
2: 2 Input Frequencies
3: 3 Input Frequencies
4: 4 Input Frequencies
Data Sheet #: SG124 Page 6 of 8
Rev: 00
Date: 12/09/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Data Sheet #: SG124 Page 7 of 8
Rev: 00
Date: 12/09/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630- 851- 5040
www.conwin.com
Revision Revision Date Note
P00
P01
P02
P03
P04
P05
00
6/30/06
2/6/07
Preliminary Release
Added Solder Profile
3/1/07
Added Mechanical Drawing
Updated Solder Profile
6/7/07
1/22/08
9/19/08
12/09/08
Updated Output Frequency Range
Added Input Frequency Range to Tbl. 2
Change from Preliminary to Release
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