SM3-8RG5_技术文档

SM3-8RG5

8 REFERENCE

STRATUM 3 MODULE

2111 Comprehensive Drive

Aurora, Illinois 60505

Phone: 630-851-4722

Fax: 630-851-5040

www.conwin.com

Application

Features

ꢀ SmallꢀPackageꢀSize:ꢀꢀ ꢀ

2.05”ꢀxꢀ1.25”ꢀxꢀ0.515”ꢀ

ꢀ TheꢀSM3-8RG5ꢀTimingꢀModuleꢀisꢀ

aꢀcompleteꢀsystemꢀclockꢀmoduleꢀforꢀ

Stratumꢀ3ꢀtimingꢀapplicationsꢀandꢀ

conformsꢀtoꢀGR-1244-COREꢀ(Issueꢀ

2),ꢀGR-253-COREꢀ(Issueꢀ3)ꢀandꢀITU-Tꢀ

G.812ꢀ(Optionꢀ3).ꢀApplicationsꢀꢀincludeꢀ

sharedꢀportꢀadapters,ꢀdataꢀdigitalꢀ

crossꢀconnects,ꢀADM’s,ꢀDSLAM’s,ꢀ

multiserviceꢀplatforms,ꢀswitchesꢀandꢀ

routersꢀinꢀTDM,ꢀSDHꢀandꢀSONETꢀ

environments.

ꢀ EightꢀAutoꢀSelectꢀInputꢀ

References,ꢀꢀ

8ꢀkHzꢀ-ꢀ77.76ꢀMHz

ꢀFrequencyꢀQualiﬁcationꢀandꢀLossꢀ

ofꢀReferenceꢀdetectionꢀforꢀeachꢀ

input

ꢀHitlessꢀReferenceꢀSwitching

ꢀMaster/SlaveꢀOperationꢀwithꢀ

PhaseꢀAdjustment

ꢀManual/AutonomousꢀꢀOperation

ꢀBi-DirectionalꢀSPIꢀPortꢀControlꢀ

andꢀStatusꢀReporting

ꢀ TheꢀSM3-8RG5ꢀTimingꢀModuleꢀ

guaranteesꢀfullꢀStratumꢀ3ꢀcomplianceꢀ

withꢀaꢀminimumꢀofꢀeffortꢀandꢀcostꢀ

inꢀtheꢀsmallestꢀcompleteꢀpackageꢀ

available.

ꢀThreeꢀCMOSꢀFrequencyꢀOutputsꢀ

-ꢀOutput1ꢀfromꢀ1.544ꢀ-ꢀ77.76MHz,ꢀ

M/S_Out@8KHz,ꢀBITSꢀ@2.048ꢀ

MHzꢀorꢀ1.544ꢀMHzꢀ

ꢀ3.3Vꢀoperation

ꢀ ThisꢀproductꢀisꢀROHS-5ꢀcompliant.ꢀꢀ

ROHS-5ꢀindicatesꢀthatꢀthisꢀproductꢀisꢀ

ROHSꢀcompliantꢀexceptꢀforꢀleadꢀfromꢀ

thoseꢀmanufacturersꢀwishingꢀtoꢀtakeꢀ

theꢀleadꢀexemption.

ꢀROHS-5ꢀCompliant

Bulletin

TM088

1 of 32

Page

Revision

07

Date

06 Sept 11

IssuedꢀBy

ENG

General Description

ꢀ

TheꢀSM3-8RG5ꢀtimingꢀmoduleꢀprovidesꢀaꢀclockꢀoutputꢀthatꢀmeetsꢀorꢀexceedsꢀStratumꢀ3ꢀspeciﬁcationsꢀgivenꢀinꢀGR-1244-COREꢀ

(Issueꢀ2),ꢀGR-253-COREꢀ(Issueꢀ3)ꢀandꢀITU-TꢀG.812ꢀ(optionꢀ3).ꢀꢀTheꢀSM3-8RG5ꢀfeaturesꢀeightꢀreferenceꢀinputs.ꢀꢀEachꢀinputꢀwillꢀauto-

detectꢀtheꢀfollowingꢀreferenceꢀfrequencies:ꢀ8ꢀkHz,ꢀ1.544ꢀMHz,ꢀ2.048ꢀMHz,ꢀ12.96ꢀMHz,ꢀ19.44ꢀMHz,ꢀ25.92ꢀMHz,ꢀ38.88ꢀMHz,ꢀ51.84ꢀMHzꢀ

andꢀ77.76ꢀMHz.

ꢀ

TheꢀSM3-8RG5ꢀtimingꢀmoduleꢀcanꢀbeꢀconﬁguredꢀduringꢀproductionꢀtoꢀproduceꢀanꢀoutputꢀupꢀtoꢀ77.76MHz.ꢀThisꢀoutputꢀisꢀderivedꢀfromꢀ

anꢀonboardꢀVCXOꢀandꢀmustꢀbeꢀspeciﬁedꢀwhenꢀordering.ꢀꢀTheꢀsecondꢀoutputꢀisꢀaꢀBITSꢀoutputꢀselectableꢀforꢀeitherꢀ1.544ꢀorꢀ2.048ꢀMHz.ꢀꢀ

Theꢀmaster/slaveꢀoutputꢀisꢀ8KHz.ꢀꢀTheꢀuserꢀcommunicatesꢀwithꢀtheꢀSM3-8RG5ꢀmoduleꢀthroughꢀaꢀSPIꢀport.ꢀTheꢀuserꢀcontrolsꢀtheꢀSM3-

8RG5ꢀoperationꢀbyꢀwritingꢀtoꢀtheꢀappropriateꢀregisters.ꢀTheꢀuserꢀcanꢀalsoꢀenableꢀorꢀdisableꢀSPIꢀoperationꢀthroughꢀaꢀSPI_Enableꢀpin.

ꢀ

TheꢀSM3-8RG5ꢀoffersꢀaꢀwideꢀrangeꢀofꢀoptionsꢀforꢀtheꢀsystemꢀdesigner.ꢀꢀTheꢀbandwidthꢀisꢀSPIꢀPort-selectableꢀfromꢀ0.025ꢀHzꢀtoꢀ1.6ꢀ

Hz.ꢀꢀ0.098ꢀHzꢀisꢀtheꢀrecommendedꢀoperationalꢀbandwidthꢀforꢀStratumꢀ3ꢀapplications.ꢀꢀTheꢀ8ꢀkHzꢀoutputꢀhasꢀanꢀadjustableꢀpulseꢀwidth.ꢀꢀ

Theꢀpull-inꢀrangeꢀisꢀalsoꢀadjustableꢀtoꢀestablishꢀtheꢀdesiredꢀreferenceꢀfrequencyꢀrejectionꢀlimits.ꢀꢀAꢀFreeꢀRunꢀfrequencyꢀcalibrationꢀ

valueꢀcanꢀbeꢀwrittenꢀtoꢀtheꢀmoduleꢀtoꢀprovideꢀaꢀhighꢀdegreeꢀofꢀaccuracyꢀinꢀtheꢀfreeꢀrunꢀmode.ꢀꢀTheꢀreferenceꢀfrequencyꢀforꢀanyꢀgivenꢀ

referenceꢀinputꢀisꢀautomaticallyꢀdetected.ꢀꢀAꢀwealthꢀofꢀstatusꢀinformationꢀisꢀavailableꢀthroughꢀtheꢀSPIꢀPortꢀregisters.ꢀꢀTheꢀuserꢀalsoꢀhasꢀ

aꢀchoiceꢀbetweenꢀautonomousꢀorꢀfullꢀmanualꢀcontrolꢀoperation.

ꢀ

Inꢀmanualꢀmode,ꢀtheꢀuserꢀcontrolsꢀtheꢀmoduleꢀoperatingꢀmodesꢀFreeꢀRun,ꢀHoldꢀOverꢀorꢀlockedꢀtoꢀaꢀspeciﬁcꢀreference.ꢀꢀIfꢀtheꢀ

chosenꢀreferenceꢀisꢀunavailableꢀorꢀdisqualiﬁedꢀtheꢀmoduleꢀautomaticallyꢀentersꢀHoldꢀOver.

Inꢀautonomousꢀcontrolꢀmode,ꢀoperationalꢀmodeꢀselectionꢀoccursꢀautomaticallyꢀbasedꢀonꢀreferenceꢀpriorityꢀandꢀqualiﬁcationꢀstatus.ꢀ

ꢀ

Whenꢀtheꢀactiveꢀreferenceꢀbecomesꢀdisqualiﬁed,ꢀtheꢀmoduleꢀwillꢀswitchꢀtoꢀanotherꢀqualiﬁedꢀreference.ꢀIfꢀnoneꢀisꢀavailable,ꢀitꢀwillꢀswitchꢀ

toꢀHoldꢀOver.ꢀInꢀtheꢀrevertiveꢀmodeꢀtheꢀmoduleꢀwillꢀseekꢀtoꢀacquireꢀtheꢀhighestꢀpriorityꢀqualiﬁedꢀreference.ꢀꢀInꢀtheꢀnon-revertiveꢀmodeꢀ

theꢀmoduleꢀwillꢀnotꢀreturnꢀtoꢀtheꢀpreviousꢀreferenceꢀevenꢀafterꢀitꢀisꢀre-qualiﬁedꢀunlessꢀthereꢀareꢀnoꢀotherꢀqualiﬁedꢀreferences.

ꢀ

Switchingꢀbetweenꢀreferencesꢀisꢀhitless.ꢀꢀLikewise,ꢀtheꢀoutputꢀfrequencyꢀslewꢀrateꢀisꢀminimizedꢀduringꢀanyꢀchangeꢀofꢀoperatingꢀ

mode,ꢀincludingꢀentryꢀintoꢀandꢀreturnꢀfromꢀFreeꢀRunꢀorꢀHoldꢀOverꢀtoꢀprotectꢀtrafﬁcꢀfromꢀtransient-inducedꢀbitꢀerrors.

ReferenceꢀStatusꢀinformationꢀandꢀtheꢀoperatingꢀmodeꢀinformationꢀisꢀaccessedꢀthroughꢀstatusꢀregisters.ꢀꢀTheꢀmoduleꢀwillꢀsetꢀtheꢀ

Interruptꢀpinꢀ(SPI_INT)ꢀlowꢀtoꢀindicateꢀaꢀstatusꢀchange.ꢀ

FreeꢀRunꢀoperationꢀguaranteesꢀanꢀoutputꢀwithinꢀ4.6ppmꢀofꢀnominalꢀfrequencyꢀandꢀHoldꢀOverꢀoperationꢀguaranteesꢀtheꢀoutputꢀ

ꢀ

frequencyꢀwillꢀnotꢀchangeꢀbyꢀmoreꢀthanꢀ0.37ppmꢀduringꢀtheꢀﬁrstꢀ24ꢀhours.ꢀꢀFrequencyꢀaccuracyꢀisꢀbasedꢀonꢀaꢀprecisionꢀovenꢀtoꢀ

provideꢀtheꢀstabiltyꢀrequiredꢀforꢀStratumꢀ3ꢀcompliance.ꢀ

ꢀ

TheꢀSM3-8RG5ꢀcanꢀbeꢀprogrammedꢀtoꢀstartupꢀinꢀanyꢀmodeꢀorꢀbandwidth.ꢀꢀTheꢀmoduleꢀmayꢀevenꢀbeꢀprogrammedꢀtoꢀoperateꢀinꢀanꢀ

aꢀfullyꢀautonomousꢀmodeꢀwithꢀnoꢀfurtherꢀconﬁgurationꢀrequired.ꢀ

Theꢀmoduleꢀoperatesꢀonꢀ3.3Vꢀ ꢀ5%ꢀwithꢀaꢀtypicalꢀpowerꢀdrainꢀofꢀlessꢀthanꢀ1.6Wꢀatꢀturnꢀon,ꢀdroppingꢀtoꢀapproximatelyꢀ1Wꢀ@ꢀroomꢀ

temperatureꢀafterꢀwarmingꢀup.ꢀꢀꢀTheꢀmoduleꢀoperatesꢀoverꢀtheꢀ0°ꢀtoꢀ70°ꢀCꢀcommercialꢀtemperatureꢀrange.ꢀꢀ

PhaseꢀbuildoutꢀcanꢀbeꢀenabledꢀorꢀdisabledꢀbyꢀmeansꢀofꢀtheꢀSPIꢀport.

ꢀ

Functional Block Diagram

Figure 1

TRST

TCK

TDO

EEPROM

DAC

OCXO

VCXO

Output 1

M/S_OUT

TDI

BITS_Clk

TMS

Reference Input Monitor

M/S REF

Ref 1 - 8

Reset

8

Control

Mode

Reference

Selection

DPLL

APLL

MASTER SELECT

T1/E1

LOS

Reference Priority,

Revertivity and Mask

Table

LOL

SPI_ENBL

SPI_Clk

Hold_Good

SPI_In

SPI_Out

Bus Interface

SPI_INT

SM3-8RG5 Data Sheet #: TM088 Page 2 of 32

Rev: 07 Date: 09/06/11

Speciﬁcations for Ultra Miniature Stratum 3

Table 1

Parameter

Speciﬁcation

Voltageꢀ

Powerꢀ

OperatingꢀTempꢀRangeꢀ

ReferenceꢀFrequencyꢀ1ꢀ-ꢀ8ꢀ

ꢀ

3.3Vꢀ ꢀ5%

1.6WꢀMaximumꢀduringꢀstartꢀup,ꢀ1.0WꢀTypicalꢀ@ꢀroomꢀtemperature

0°ꢀ-ꢀ70°C

8ꢀkHzꢀ-ꢀ77.76ꢀMHzꢀꢀ(Determinedꢀbyꢀcustomer’sꢀapplication)

CMOSꢀOutputꢀFrequencyꢀ#1ꢀ

M/S_Outꢀ

ꢀ

8ꢀkHzꢀ-ꢀ77.76ꢀMHzꢀꢀ

8ꢀkHzꢀ

BITS_Clkꢀ

ꢀ

1.544/2.048ꢀMHzꢀ(Selectable)

8ꢀkHzꢀ-ꢀ77.76ꢀMHz

10ꢀnsꢀMinꢀ@ꢀ8ꢀkHz,ꢀ5ꢀnsꢀMinꢀ@ꢀ>8ꢀkHz

4.6ꢀppm

Master/SlaveꢀInputꢀReferenceꢀ

InputꢀReferenceꢀPulseꢀWidthꢀ

FreeꢀRunꢀAccuracyꢀ

HoldꢀOverꢀAccuracyꢀ

Dimensionsꢀ

0.37ꢀppm

2.05ꢀxꢀ1.25ꢀxꢀ0.515ꢀinchesꢀ(52.07ꢀxꢀ31.75ꢀxꢀ13.08ꢀmm)ꢀ

Pin Description

Table 2

ꢀ Pinꢀ#ꢀ

I/Oꢀ

Oꢀ

Iꢀ

ꢀ

PinꢀNameꢀ

LOSꢀ

LOLꢀ

M/SꢀREFꢀ

REF1ꢀ

REF2ꢀ

REF3ꢀ

REF4ꢀ

TDIꢀ

TMSꢀ

TRSTꢀ

BITS_CLKꢀ

M/S_OUTꢀ

OUTPUT1ꢀ

PinꢀDescription

AlarmꢀOutputꢀ-ꢀLossꢀofꢀActiveꢀReferenceꢀSignal

AlarmꢀOutputꢀ-ꢀLossꢀofꢀLock

ꢀ

1ꢀ

2ꢀ

3ꢀ

4ꢀ

5ꢀ

6ꢀ

7ꢀ

8ꢀ

9ꢀ

10ꢀ

11ꢀ

12ꢀ

13ꢀ

Master/SlaveꢀReferenceꢀInput

ReferenceꢀInputꢀ1ꢀ–ꢀ8ꢀkHzꢀtoꢀ77.76ꢀMHzꢀautoꢀdetected

ReferenceꢀInputꢀ2ꢀ–ꢀ8ꢀkHzꢀtoꢀ77.76ꢀMHzꢀautoꢀdetected

ReferenceꢀInputꢀ3ꢀ–ꢀ8ꢀkHzꢀtoꢀ77.76ꢀMHzꢀautoꢀdetected

ReferenceꢀInputꢀ4ꢀ–ꢀ8ꢀkHzꢀtoꢀ77.76ꢀMHzꢀautoꢀdetected

JTAGꢀTDIꢀpin

JTAGꢀTMSꢀpin

JTAGꢀTRSTꢀpin

1.544ꢀorꢀ2.048ꢀMHzꢀoutputꢀselectedꢀbyꢀpinꢀ14

Master/Slaveꢀ8ꢀkHzꢀoutput

SynchronousꢀPrimaryꢀOutput

ꢀ

Oꢀ

ꢀ

14ꢀ

ꢀ

VPPꢀ

ꢀ

PositiveꢀProgrammingꢀSupplyꢀPin.ꢀDuringꢀnormalꢀoperation,ꢀitꢀisꢀꢀ

recommendedꢀtoꢀﬂoatꢀthisꢀpin.

ꢀ

15ꢀ

16ꢀ

17ꢀ

18ꢀ

ꢀ

REF5ꢀ

REF6ꢀ

REF8ꢀ

REF7ꢀ

ReferenceꢀInputꢀ5ꢀ–ꢀ8ꢀkHzꢀtoꢀ77.76ꢀMHzꢀautoꢀdetected

ReferenceꢀInputꢀ6ꢀ–ꢀ8ꢀkHzꢀtoꢀ77.76ꢀMHzꢀautoꢀdetected

ReferenceꢀInputꢀ8ꢀ–ꢀ8ꢀkHzꢀtoꢀ77.76ꢀMHzꢀautoꢀdetected

ReferenceꢀInputꢀ7ꢀ–ꢀ8ꢀkHzꢀtoꢀ77.76ꢀMHzꢀautoꢀdetected

ꢀ

19ꢀ

ꢀ

VPNꢀ

ꢀ

NegativeꢀProgrammingꢀSupplyꢀPin.ꢀDuringꢀnormalꢀoperation,ꢀitꢀisꢀꢀ

recommendedꢀtoꢀﬂoatꢀthisꢀpin.

ꢀ

20ꢀ

21ꢀ

22ꢀ

23ꢀ

24ꢀ

25ꢀ

26ꢀ

27ꢀ

28ꢀꢀ

29ꢀ

30ꢀ

31ꢀ

32ꢀ

Iꢀ

Oꢀ

ꢀ

Iꢀ

ꢀ

Iꢀ

Oꢀ

Iꢀ

Tꢀ1/E1ꢀ

HOLD_GOODꢀ

TDOꢀ

BITS_CLKꢀselectꢀinputꢀ–ꢀ1=1.544ꢀMHz,ꢀ0=2.-48ꢀMHz,ꢀ4.7kꢀOhmꢀPull-up

HoldoverꢀGoodꢀOutputꢀFlagꢀ–ꢀ1=HoldoverꢀAvailable

JTAGꢀTDOꢀpin

JTAGꢀTCKꢀpin

ModuleꢀGround

SPIꢀPortꢀClockꢀinput

SPIꢀPortꢀDataꢀinput

3.3ꢀVdcꢀVCCꢀSupplyꢀInput

SPIꢀPortꢀEnableꢀinputꢀ–ꢀActiveꢀLow,ꢀ4.7kꢀOhmꢀPull-up

ModuleꢀResetꢀ–ꢀActiveꢀLow,ꢀ4.7kꢀOhmꢀPull-up

SPIꢀPortꢀDataꢀOutput

SPIꢀPortꢀInterruptꢀOutput

Master/Slaveꢀselectꢀinputꢀ–ꢀ1=Master,ꢀ0=Slave

TCKꢀ

GNDꢀ

SPI_CLKꢀ

SPI_INꢀ

VCCꢀ

SPI_ENBLꢀ

RESETꢀ

SPI_OUTꢀ

SPI_INTꢀ

MASTERꢀSELECTꢀ

SM3-8RG5 Data Sheet #: TM088 Page 3 of 32

Rev: 07 Date: 09/06/11

Pin Diagram

Figure 2

SM3-8RG5

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

LOS

LOL

MASTER SELECT

SPI_INT

SPI_OUT

RESET

SPI_ENBL

Vcc

2

3

M/S REF

REF1

4

5

REF2

6

REF3

7

REF4

SPI_IN

(TOP VIEW)

8

TDI

SPI_CLK

GND

9

TMS

10

11

12

13

14

15

16

TRST

TCK

BITS_CLK

M/S_OUT

OUTPUT1

VPP

TDO

HOLD_GOOD

T1/E1

VPN

REF5

REF7

REF6

REF8

Register Map

Table 3

Addressꢀ

0x00ꢀ

0x01ꢀ

0x02ꢀ

0x03ꢀ

RegꢀNameꢀ

Chip_ID_Lowꢀ

Chip_ID_Highꢀ

Chip_Revisionꢀ

Bandwidth_PBOꢀ

Descriptionꢀ

Type

R

R/W

LowꢀbyteꢀofꢀchipꢀIDꢀ

HighꢀbyteꢀofꢀchipꢀIDꢀ

Chipꢀrevisionꢀnumberꢀ

Bandwidthꢀ&ꢀPhaseꢀBuild-Outꢀoptionꢀ

0x04ꢀ

ꢀ

Ctl_Modeꢀ

ꢀ

ManualꢀorꢀautomaticꢀselectionꢀofꢀOp_Mode,BITSꢀclockꢀoutputꢀfrequencyꢀꢀ R/Wꢀ

indication,ꢀandꢀframe/multi-frameꢀsyncꢀpulseꢀwidthꢀmodeꢀcontrol

0x05ꢀ

0x06ꢀ

0x07ꢀ

0x08ꢀ

0x09ꢀ

0x0aꢀ

0x0bꢀ

0x0cꢀ

Op_Modeꢀ

MasterꢀFreeꢀRun,ꢀLocked,ꢀorꢀHoldꢀOverꢀmode,ꢀorꢀSlaveꢀmodeꢀ

Maximumꢀpull-inꢀrangeꢀinꢀ0.1ꢀppmꢀunitsꢀ

CrossꢀReferenceꢀactivityꢀ

R/W

R

R/W

R

Max_Pullin_Rangeꢀ

M/SꢀInput_Activityꢀ

Ref_Activityꢀ

Ref_Pullin_Stsꢀ

Ref_Qualiﬁedꢀ

Ref_Maskꢀ

Activitiesꢀofꢀ8ꢀreferenceꢀinputsꢀꢀ

Inꢀorꢀoutꢀofꢀpull-inꢀrangeꢀofꢀ8ꢀreferenceꢀinputsꢀ

Qualiﬁcationꢀofꢀ8ꢀreferenceꢀinputsꢀ

Availabilityꢀmaskꢀforꢀ8ꢀreferenceꢀinputsꢀꢀ

Availabilityꢀofꢀ8ꢀreferenceꢀinputsꢀ

Ref_Availableꢀ

SM3-8RG5 Data Sheet #: TM088 Page 4 of 32

Rev: 07 Date: 09/06/11

Register Map Continued

Table 3

0x0dꢀ

0x0eꢀ

ꢀ

Ref_Rev_Delayꢀ

Phase_Offsetꢀ

ꢀ

Calibrationꢀ

Fr_Pulse_Widthꢀ

DPLL_Statusꢀ

Referenceꢀreversionꢀdelayꢀtime,ꢀ0ꢀ-ꢀ255ꢀminutesꢀ

PhaseꢀoffsetꢀbetweenꢀM/SꢀREFꢀ&ꢀM/SꢀOutputꢀ(forꢀtheꢀSlaveꢀinꢀꢀ

M/Sꢀoperation)ꢀinꢀ250psꢀresolutionꢀ

R/W

ꢀ ꢀ

R/W

R

R/W

R

0x0fꢀ

Localꢀoscillatorꢀdigitalꢀcalibrationꢀinꢀ0.05ꢀppmꢀresolutionꢀ

Frameꢀsyncꢀpulseꢀwidthꢀ

0x10ꢀ

0x11ꢀ

0x12ꢀ

0x13ꢀ

0x14ꢀ

0x15ꢀ

0x16ꢀ

0x17ꢀ

0x18ꢀ

0x19ꢀ

0x1aꢀ

0x1bꢀ

0x1cꢀ

0x1dꢀ

0x1eꢀ

0x1fꢀ

0x20ꢀ

0x21ꢀ

0x22ꢀ

0x23ꢀ

0x24ꢀ

0x25ꢀ

0x26ꢀ

0x27ꢀ

0x30ꢀ

0x31ꢀ

0x32ꢀ

0x33ꢀ

0x35ꢀ

0x37ꢀ

0x38ꢀ

0x39ꢀ

DigitalꢀPhaseꢀLockedꢀLoopꢀstatusꢀ

Interruptꢀeventsꢀ

Enableꢀindividualꢀinterruptꢀeventsꢀ

Intr_Eventꢀ

Intr_Enableꢀ

Ref1_Frq_Offsetꢀ

Ref2_Frq_Offsetꢀ

Ref3_Frq_Offsetꢀ

Ref4_Frq_Offsetꢀ

Ref5_Frq_Offsetꢀ

Ref6_Frq_Offsetꢀ

Ref7_Frq_Offsetꢀ

Ref8_Frq_Offsetꢀ

Ref1_Frq_Priorityꢀ

Ref2_Frq_Priorityꢀ

Ref3_Frq_Priorityꢀ

Ref4_Frq_Priorityꢀ

Ref5_Frq_Priorityꢀ

Ref6_Frq_Priorityꢀ

Ref7_Frq_Priorityꢀ

Ref8_Frq_Priorityꢀ

FreeRunꢀPriorityꢀꢀ

History_Policyꢀ

History_CMDꢀ

HoldOver_Timeꢀ

Cfgdataꢀ

Ref1ꢀfrequencyꢀoffsetꢀinꢀ0.2ꢀppmꢀresolutionꢀ

Ref2ꢀfrequencyꢀoffsetꢀinꢀ0.2ꢀppmꢀresolutionꢀ

Ref3ꢀfrequencyꢀoffsetꢀinꢀ0.2ꢀppmꢀresolutionꢀ

Ref4ꢀfrequencyꢀoffsetꢀinꢀ0.2ꢀppmꢀresolutionꢀ

Ref5ꢀfrequencyꢀoffsetꢀinꢀ0.2ꢀppmꢀresolutionꢀ

Ref6ꢀfrequencyꢀoffsetꢀinꢀ0.2ꢀppmꢀresolutionꢀ

Ref7ꢀfrequencyꢀoffsetꢀinꢀ0.2ꢀppmꢀresolutionꢀ

Ref8ꢀfrequencyꢀoffsetꢀinꢀ0.2ꢀppmꢀresolutionꢀ

Ref1ꢀfrequencyꢀandꢀpriorityꢀ

R

R/W

R

R/Wꢀ

R

R/W

Ref2ꢀfrequencyꢀandꢀpriorityꢀ

Ref3ꢀfrequencyꢀandꢀpriorityꢀ

Ref4ꢀfrequencyꢀandꢀpriorityꢀ

Ref5ꢀfrequencyꢀandꢀpriorityꢀ

Ref6ꢀfrequencyꢀandꢀpriorityꢀ

Ref7ꢀfrequencyꢀandꢀpriorityꢀ

Ref8ꢀfrequencyꢀandꢀpriorityꢀ

ControlꢀandꢀPriorityꢀforꢀdesignationꢀofꢀFreeꢀRunꢀasꢀaꢀreferenceꢀ

SetsꢀpolicyꢀforꢀHoldꢀOverꢀhistoryꢀaccumulationꢀ

Save,ꢀrestoreꢀandꢀﬂushꢀcomandsꢀforꢀHoldꢀOverꢀhistoryꢀ

IndicatesꢀtheꢀtimeꢀsinceꢀenteringꢀHoldꢀOverꢀstateꢀ

Conﬁgurationꢀdataꢀwriteꢀregisterꢀ

Cfgctr_Loꢀ

Cfgctr_Hiꢀ

Chksumꢀ

EE_Wrt_Modeꢀ

EE_Cmdꢀ

Conﬁgurationꢀdataꢀwriteꢀcounter,ꢀlowꢀbyteꢀ

Conﬁgurationꢀdataꢀwriteꢀcounter,ꢀhighꢀbyteꢀ

Conﬁgurationꢀdataꢀchecksumꢀpass/failꢀindicatorꢀ

Disables/EnablesꢀwritingꢀtoꢀtheꢀexternalꢀEEPROMꢀ

Read/Writeꢀcommandꢀ&ꢀreadyꢀindicationꢀregisterꢀforꢀext.ꢀEEPROMꢀaccessꢀ R/W

EE_Page_Numꢀ

EE_FIFO_Portꢀ

PageꢀnumberꢀforꢀexternalꢀEEPROMꢀaccessꢀ

Read/WriteꢀdataꢀforꢀexternalꢀEEPROMꢀaccessꢀ

R/W

SM3-8RG5 Data Sheet #: TM088 Page 5 of 32

Rev: 07 Date: 09/06/11

Detailed Description

ꢀ

TheꢀSM3-8RG5ꢀcanꢀacceptꢀupꢀtoꢀ8ꢀexternalꢀreferencesꢀfromꢀ8ꢀkHzꢀtoꢀ77.76ꢀMHzꢀandꢀeachꢀisꢀmonitoredꢀforꢀsignalꢀpresenceꢀandꢀ

frequencyꢀoffset.ꢀAdditionally,ꢀaꢀcross-coupleꢀreferenceꢀinputꢀisꢀprovidedꢀforꢀmaster/slaveꢀoperation.ꢀReferenceꢀselectionꢀmayꢀbeꢀ

manualꢀorꢀautomatic,ꢀaccordingꢀtoꢀpre-programmedꢀpriorities.ꢀAllꢀreferenceꢀswitchesꢀareꢀperformedꢀinꢀaꢀhitlessꢀmanner,ꢀandꢀfrequencyꢀ

rampꢀcontrolsꢀensureꢀsmoothꢀoutputꢀsignalꢀtransitions.ꢀWhenꢀreferencesꢀareꢀswitched,ꢀtheꢀdeviceꢀprovidesꢀanꢀautomaticꢀphaseꢀbuild-

outꢀtoꢀminimizeꢀphaseꢀtransitionsꢀinꢀtheꢀoutputꢀclocks.ꢀ

ꢀ

Threeꢀoutputꢀsignalsꢀareꢀprovided,ꢀtheꢀﬁrstꢀupꢀtoꢀ77.76ꢀMHzꢀ,ꢀtheꢀsecondꢀﬁxedꢀatꢀ8ꢀkHzꢀforꢀuseꢀasꢀaꢀFrameꢀSyncꢀsignalꢀasꢀwellꢀasꢀ

aꢀcross-coupleꢀreferenceꢀforꢀmaster/slaveꢀoperation.ꢀInꢀslaveꢀmode,ꢀtheꢀoutputꢀphaseꢀmayꢀbeꢀadjustedꢀfromꢀ-32ꢀtoꢀ+31.75nSꢀrelativeꢀ

toꢀtheꢀmaster,ꢀtoꢀaccommodateꢀdownstreamꢀsystemꢀneeds,ꢀsuchꢀasꢀdifferentꢀclockꢀdistributionꢀpathꢀlengths.ꢀTheꢀthirdꢀoutputꢀisꢀaꢀBITSꢀ

clock,ꢀselectableꢀasꢀeitherꢀ1.544ꢀMHzꢀorꢀ2.048ꢀMHz.ꢀ

ꢀ

DeviceꢀoperationꢀmayꢀbeꢀinꢀFreeꢀRun,ꢀlocked,ꢀorꢀHoldꢀOverꢀmodes.ꢀInꢀFreeꢀRun,ꢀtheꢀclockꢀfrequenciesꢀareꢀsimplyꢀdeterminedꢀbyꢀ

theꢀaccuracyꢀofꢀtheꢀcalibratedꢀinternalꢀclock.ꢀInꢀlockedꢀmode,ꢀtheꢀSM3-8RG5ꢀphaseꢀlocksꢀtoꢀtheꢀselectedꢀinputꢀreference.ꢀWhileꢀlocked,ꢀ

aꢀfrequencyꢀhistoryꢀisꢀaccumulated.ꢀInꢀHoldꢀOverꢀmode,ꢀtheꢀꢀoutputꢀfrequenciesꢀareꢀgeneratedꢀaccordingꢀtoꢀthisꢀhistory.ꢀ

ꢀ

TheꢀDigitalꢀPhaseꢀLockedꢀLoopꢀprovidesꢀtheꢀcriticalꢀﬁlteringꢀandꢀfrequency/phaseꢀcontrolꢀthatꢀmeetꢀorꢀexceedꢀallꢀrequirementsꢀinꢀ

criticalꢀjitterꢀandꢀaccuracyꢀperformanceꢀparameters.ꢀFilterꢀbandwidthꢀmayꢀbeꢀconﬁguredꢀtoꢀsuitꢀapplicationsꢀrequirements.

ControlꢀfunctionsꢀareꢀprovidedꢀviaꢀstandardꢀSPIꢀbusꢀregisterꢀinterface.ꢀRegisterꢀaccessꢀprovidesꢀvisibilityꢀintoꢀaꢀvarietyꢀofꢀregisteredꢀ

ꢀ

informationꢀasꢀwellꢀasꢀprovidingꢀextensiveꢀprogrammableꢀcontrolꢀcapability.

Operating Modes:The SM3-8RG5 Operates in Either Free Run, Locked, or Hold Over Mode:

Free Runꢀ–ꢀInꢀFreeꢀRunꢀmode,ꢀOutput 1, M/S Output, and BITS_Clk,ꢀtheꢀoutputꢀclocks,ꢀareꢀdeterminedꢀdirectlyꢀfromꢀandꢀ

haveꢀtheꢀaccuracyꢀofꢀtheꢀcalibratedꢀfreeꢀrunningꢀinternalꢀclock.ꢀReferenceꢀinputsꢀcontinueꢀtoꢀbeꢀmonitoredꢀforꢀsignalꢀpresenceꢀandꢀ

frequencyꢀoffset,ꢀbutꢀareꢀnotꢀusedꢀtoꢀsynchronizeꢀtheꢀoutputs.

Lockedꢀ–ꢀTheꢀOutput 1, M/S Output, ꢀandꢀBITS_Clk,ꢀoutputsꢀareꢀphaseꢀlockedꢀandꢀtrackꢀtheꢀselectedꢀinputꢀreference.ꢀUponꢀ

enteringꢀtheꢀLockedꢀmode,ꢀtheꢀdeviceꢀbeginsꢀanꢀacquisitionꢀprocessꢀthatꢀincludesꢀreferenceꢀqualiﬁcationꢀandꢀfrequencyꢀslewꢀrateꢀ

limiting,ꢀifꢀneeded.ꢀOnceꢀsatisfactoryꢀlockꢀisꢀachieved,ꢀtheꢀ“Locked”ꢀbitꢀisꢀsetꢀinꢀtheꢀDPLL_Statusꢀregister,ꢀandꢀaꢀcompilationꢀofꢀtheꢀ

frequencyꢀhistoryꢀofꢀtheꢀselectedꢀreferenceꢀisꢀstarted.ꢀꢀWhenꢀaꢀusableꢀHoldꢀOverꢀhistoryꢀhasꢀbeenꢀestablished,ꢀtheꢀHold_Goodꢀpinꢀisꢀ

set,ꢀandꢀtheꢀ“HoldꢀOverꢀAvailable”ꢀbitꢀisꢀsetꢀinꢀtheꢀDPLL_Statusꢀregister.

ꢀ

PhaseꢀcomparisonꢀandꢀphaseꢀlockꢀloopꢀﬁlteringꢀoperationsꢀinꢀtheꢀSM3-8RG5ꢀareꢀcompletelyꢀdigital.ꢀAsꢀaꢀresult,ꢀdeviceꢀandꢀloopꢀ

behaviorꢀareꢀentirelyꢀpredictable,ꢀrepeatable,ꢀandꢀextremelyꢀaccurate.ꢀCarefullyꢀdesignedꢀandꢀprovenꢀalgorithmsꢀandꢀtechniquesꢀ

ensureꢀcompletelyꢀhit-lessꢀreferenceꢀswitches,ꢀoperationalꢀmodeꢀchanges,ꢀandꢀmaster/slaveꢀswitches.ꢀ

ꢀ

Basicꢀloopꢀbandwidthꢀisꢀprogrammableꢀfromꢀ.025ꢀHzꢀtoꢀ1.6ꢀHz,ꢀgivingꢀtheꢀuserꢀaꢀwideꢀrangeꢀofꢀcontrolꢀoverꢀtheꢀsystemꢀresponse.ꢀ

Whenꢀaꢀnewꢀreferenceꢀisꢀacquired,ꢀmaximumꢀfrequencyꢀslewꢀlimitsꢀensureꢀsmoothꢀfrequencyꢀchanges.ꢀOnceꢀlockꢀisꢀachieved,ꢀ

(<100ꢀsecondsꢀforꢀstratumꢀ3),ꢀtheꢀ“Locked”ꢀbitꢀisꢀset.ꢀIfꢀtheꢀSM3-8RG5ꢀisꢀunableꢀtoꢀmaintainꢀlock,ꢀLossꢀofꢀLockꢀ(LOL)ꢀisꢀasserted.ꢀAllꢀ

transitionsꢀbetweenꢀlocked,ꢀHoldꢀOverꢀandꢀFreeꢀRunꢀmodesꢀareꢀperformedꢀwithꢀminimalꢀphaseꢀeventsꢀandꢀsmoothꢀfrequencyꢀandꢀ

phaseꢀtransitions.ꢀ

ꢀ

Referenceꢀphaseꢀhitsꢀorꢀphaseꢀdifferencesꢀencounteredꢀwhenꢀswitchingꢀreferencesꢀ(orꢀwhenꢀenteringꢀlockedꢀmode)ꢀareꢀnulledꢀoutꢀ

withꢀanꢀautomaticꢀphaseꢀbuild-outꢀfunction,ꢀwithꢀaꢀresidualꢀphaseꢀerrorꢀofꢀlessꢀthanꢀ1ns.ꢀꢀ

Hold Overꢀ–ꢀUponꢀenteringꢀHoldꢀOverꢀmode,ꢀtheꢀOutput 1, M/S Output, and BITS_Clk,ꢀoutputsꢀareꢀdeterminedꢀfromꢀtheꢀHoldꢀ

Overꢀhistoryꢀestablishedꢀforꢀtheꢀlastꢀselectedꢀreference.ꢀOutputꢀfrequencyꢀisꢀdeterminedꢀbyꢀaꢀweightedꢀaverageꢀofꢀtheꢀHoldꢀOverꢀ

history,ꢀandꢀaccuracyꢀisꢀdeterminedꢀbyꢀtheꢀinternalꢀclock.ꢀHoldꢀOverꢀmodeꢀmayꢀbeꢀenteredꢀmanuallyꢀorꢀautomatically.ꢀAutomaticꢀentryꢀ

intoꢀHoldꢀOverꢀmodeꢀoccursꢀwhenꢀoperatingꢀinꢀtheꢀautomaticꢀmode,ꢀtheꢀreferenceꢀisꢀlost,ꢀandꢀnoꢀotherꢀvalidꢀreferenceꢀexists.ꢀTheꢀ

transferꢀintoꢀandꢀoutꢀofꢀHoldꢀOverꢀmodeꢀisꢀdesignedꢀtoꢀbeꢀsmoothꢀandꢀfreeꢀofꢀhits.ꢀTheꢀfrequencyꢀslewꢀisꢀalsoꢀlimitedꢀtoꢀaꢀmaximumꢀofꢀ

2ꢀppm/sec.

ꢀ

Theꢀhistoryꢀaccumulationꢀalgorithmꢀusesꢀaꢀﬁrstꢀorderꢀfrequencyꢀdifferenceꢀﬁlteringꢀalgorithm.ꢀꢀꢀTypicalꢀholdoverꢀaccumulationꢀtakesꢀ

aboutꢀ15ꢀminutes.ꢀWhenꢀaꢀusableꢀholdoverꢀhistoryꢀhasꢀbeenꢀestablished,ꢀtheꢀHold_Good pinꢀisꢀset,ꢀandꢀtheꢀ“HoldoverꢀAvailable”ꢀbitꢀisꢀ

setꢀinꢀtheꢀDPLL_Status register.ꢀTheꢀholdoverꢀhistoryꢀcontinuesꢀtoꢀbeꢀupdatedꢀafterꢀ“HoldoverꢀAvaialble”ꢀisꢀdeclared.

ꢀ

TheꢀalgorithmꢀaccumulatesꢀtheꢀholdoverꢀhistoryꢀonlyꢀwhenꢀitꢀhasꢀlockedꢀtoꢀeitherꢀanꢀexternalꢀreferenceꢀinꢀMasterꢀoperationꢀorꢀtheꢀ

M/S REF clockꢀinꢀSlaveꢀoperation,ꢀstartingꢀ15ꢀminutesꢀafterꢀpowerꢀup.ꢀTrackingꢀwillꢀbeꢀsuspendedꢀautomaticallyꢀwhenꢀswitchingꢀtoꢀaꢀ

newꢀreferenceꢀandꢀinꢀHoldꢀOverꢀorꢀFreeꢀRunꢀmode.ꢀAꢀsetꢀofꢀregistersꢀallowsꢀtheꢀapplicationꢀtoꢀcontrolꢀaꢀholdoverꢀhistoryꢀmaintenanceꢀ

policy,ꢀenablingꢀeitherꢀaꢀre-buildꢀorꢀcontinuanceꢀofꢀtheꢀhistoryꢀwhenꢀaꢀreferenceꢀswitchꢀoccurs.

SM3-8RG5 Data Sheet #: TM088 Page 6 of 32

Rev: 07 Date: 09/06/11

Detailed Description continued

ꢀ

Furthermore,ꢀunderꢀregisterꢀaccessꢀcontrol,ꢀaꢀbackupꢀholdoverꢀhistoryꢀregisterꢀisꢀprovided.ꢀItꢀmayꢀbeꢀloadedꢀfromꢀtheꢀactiveꢀ

holdoverꢀhistoryꢀorꢀrestoredꢀtoꢀtheꢀactiveꢀholdoverꢀhistory.ꢀTheꢀactiveꢀholdoverꢀhistoryꢀmayꢀalsoꢀbeꢀﬂushed.ꢀ

Holdoverꢀmodeꢀmayꢀbeꢀenteredꢀatꢀanyꢀtime.ꢀIfꢀthereꢀisꢀnoꢀholdoverꢀhistoryꢀavailable,ꢀtheꢀpriorꢀoutputꢀfrequencyꢀwillꢀbeꢀmaintained.ꢀ

ꢀ

Whenꢀinꢀholdover,ꢀtheꢀapplicationꢀmayꢀreadꢀ(viaꢀregisterꢀaccess)ꢀtheꢀtimeꢀsinceꢀholdoverꢀwasꢀenterred.

Master/Slave Operation

ꢀ

PairsꢀofꢀSM3-8RG5ꢀdevicesꢀmayꢀbeꢀoperatedꢀinꢀaꢀmaster/slaveꢀconﬁgurationꢀforꢀredundantꢀtimingꢀsourceꢀapplications.ꢀAꢀtypicalꢀ

conﬁgurationꢀisꢀshownꢀbelow.:

Master / Slave Conﬁguration

Figure 3

REFS1-8

SM3-8RG5

STC3500

M/S_OUT / OUTPUT1

1

M/S REF

SM3-8RG5

2

M/S_OUT / OUTPUT1

REFS1-8

ꢀꢀ TheꢀM/SꢀOutputꢀorꢀtheꢀOutputꢀ1ꢀofꢀeachꢀdeviceꢀmayꢀbeꢀcross-connectedꢀtoꢀtheꢀotherꢀdevice’sꢀM/SꢀRefꢀinput.ꢀTheꢀdeviceꢀauto-

detectsꢀtheꢀfrequencyꢀonꢀtheꢀM/SꢀRefꢀinput.ꢀMasterꢀorꢀslaveꢀstateꢀofꢀaꢀdeviceꢀisꢀdeterminedꢀbyꢀtheꢀM/Sꢀpin.ꢀThus,ꢀmaster/slaveꢀstateꢀisꢀ

alwaysꢀmanuallyꢀcontrolledꢀbyꢀtheꢀapplication.ꢀTheꢀmasterꢀsynchronizesꢀtoꢀtheꢀselectedꢀinputꢀreference,ꢀwhileꢀtheꢀslaveꢀsynchronizesꢀ

toꢀtheꢀM/SꢀRefꢀinput.ꢀ(Noteꢀthatꢀ8kHzꢀframeꢀphaseꢀalignmentꢀisꢀmaintainedꢀacrossꢀaꢀmaster/slaveꢀpairꢀofꢀdevicesꢀonlyꢀifꢀM/SꢀOutputꢀisꢀ

usedꢀasꢀtheꢀcrossꢀcoupleꢀsignal.)

ꢀ

Theꢀunitꢀoperatingꢀinꢀslaveꢀmodeꢀlocksꢀonꢀandꢀphase-alignsꢀtoꢀtheꢀcross-referenceꢀclockꢀ(M/SꢀOutputꢀorꢀOutputꢀ1)ꢀfromꢀtheꢀunitꢀ

inꢀmasterꢀmode.ꢀTheꢀphaseꢀskewꢀbetweenꢀtheꢀinputꢀcross-referenceꢀandꢀtheꢀoutputꢀclockꢀforꢀtheꢀslaveꢀunitꢀisꢀtypicallyꢀlessꢀthanꢀ 1nsꢀ

(underꢀ 3nsꢀinꢀdynamicꢀsituations,ꢀincludingꢀreferenceꢀjitterꢀandꢀwander).

ꢀ

PerfectꢀphaseꢀalignmentꢀofꢀtheꢀtwoꢀOutputꢀ1ꢀoutputꢀclocksꢀwouldꢀrequireꢀnoꢀdelayꢀonꢀtheꢀcross-referenceꢀclockꢀconnection.ꢀ

Toꢀaccommodateꢀpathꢀlengthꢀdelays,ꢀtheꢀSM3-8RG5ꢀprovidesꢀaꢀprogrammableꢀphaseꢀskewꢀfeature.ꢀTheꢀslave’sꢀOutputꢀ1ꢀorꢀM/Sꢀ

Outputꢀꢀmayꢀbeꢀphaseꢀshiftedꢀ-32nSꢀtoꢀ+31.75nSꢀrelativeꢀtoꢀM/SꢀInputꢀaccordingꢀtoꢀtheꢀcontentsꢀofꢀtheꢀMS_Phase_Offsetꢀregisterꢀtoꢀ

compensateꢀforꢀtheꢀpathꢀlengthꢀofꢀtheꢀM/SꢀOutputꢀorꢀOutputꢀ1ꢀtoꢀM/SꢀInputꢀconnection.ꢀThisꢀoffsetꢀmayꢀthereforeꢀbeꢀprogrammedꢀtoꢀ

exactlyꢀcompensateꢀforꢀtheꢀactualꢀpathꢀlengthꢀdelayꢀassociatedꢀwithꢀtheꢀparticularꢀapplication’sꢀcross-referenceꢀtraces.ꢀTheꢀoffsetꢀmayꢀ

furtherꢀbeꢀadjustedꢀtoꢀaccommodateꢀanyꢀoutputꢀclockꢀdistributionꢀpathꢀdelayꢀdifferences.ꢀThus,ꢀmaster/slaveꢀswitchesꢀwithꢀtheꢀSM3ꢀ

devicesꢀmayꢀbeꢀaccomplishedꢀwithꢀnear-zeroꢀphaseꢀhits.

ꢀ

Theꢀﬁrstꢀtimeꢀaꢀunitꢀbecomesꢀaꢀslave,ꢀsuchꢀasꢀimmediatelyꢀafterꢀpower-up,ꢀitsꢀoutputꢀclockꢀphaseꢀstartsꢀoutꢀarbitrary,ꢀandꢀwillꢀ

quicklyꢀphase-alignꢀtoꢀtheꢀcross-referenceꢀfromꢀtheꢀmasterꢀunit.ꢀTheꢀphaseꢀskewꢀwillꢀbeꢀeliminatedꢀ(orꢀconvergedꢀtoꢀtheꢀprogrammedꢀ

phaseꢀoffset)ꢀstepꢀbyꢀstep.ꢀTheꢀwholeꢀpull-in-and-lockꢀprocessꢀwillꢀcompleteꢀinꢀaboutꢀ60ꢀseconds.ꢀThereꢀisꢀnoꢀfrequencyꢀslewꢀ

protectionꢀinꢀslaveꢀmode.ꢀInꢀslaveꢀmode,ꢀtheꢀunit’sꢀmissionꢀisꢀtoꢀlockꢀtoꢀandꢀfollowꢀtheꢀmaster.

ꢀ

Onceꢀaꢀpairꢀofꢀunitsꢀhasꢀbeenꢀoperatingꢀinꢀalignedꢀmaster/slaveꢀmode,ꢀandꢀaꢀmaster/slaveꢀswitchꢀoccurs,ꢀtheꢀunitꢀthatꢀbecomesꢀ

masterꢀwillꢀmaintainꢀitsꢀoutputꢀclockꢀphaseꢀandꢀfrequencyꢀwhileꢀaꢀphaseꢀbuild-outꢀ(toꢀtheꢀcurrentꢀoutputꢀclockꢀphase)ꢀisꢀperformedꢀonꢀ

itsꢀselectedꢀreferenceꢀinput.ꢀTherefore,ꢀasꢀmasterꢀmodeꢀoperationꢀcommences,ꢀthereꢀwillꢀbeꢀnoꢀphaseꢀorꢀfrequencyꢀhitsꢀonꢀtheꢀclockꢀ

output.

ꢀ

Likewise,ꢀtheꢀunitꢀthatꢀbecomesꢀtheꢀslaveꢀwillꢀmaintainꢀitsꢀoutputꢀclockꢀfrequencyꢀandꢀphaseꢀforꢀ1ꢀmsecꢀbeforeꢀstartingꢀtoꢀfollowꢀtheꢀ

cross-reference,ꢀprotectingꢀtheꢀdownstreamꢀclockꢀusersꢀduringꢀtheꢀswitch.ꢀAssumingꢀtheꢀphaseꢀoffsetꢀisꢀprogrammedꢀforꢀtheꢀactualꢀ

propagationꢀdelayꢀofꢀthisꢀcross-referenceꢀpath,ꢀthereꢀwillꢀagainꢀbeꢀnoꢀphaseꢀhitsꢀonꢀtheꢀoutputꢀclockꢀofꢀtheꢀunitꢀthatꢀhasꢀtransitionedꢀ

fromꢀmasterꢀtoꢀslave.

SM3-8RG5 Data Sheet #: TM088 Page 7 of 32

Rev: 07 Date: 09/06/11

Detailed Description continued

Serial Communication

ꢀ

TheꢀuserꢀcanꢀcontrolꢀtheꢀoperationꢀofꢀtheꢀSM3-8RG5ꢀmoduleꢀthroughꢀtheꢀSPIꢀport.ꢀꢀTimingꢀdiagramsꢀareꢀshownꢀbelow.ꢀꢀThisꢀ

interfaceꢀisꢀonlyꢀforꢀpoint-to-pointꢀapplications.ꢀ

Serial Interface Timing, Read Access

Figure 4

SPI_Enable

SPI_Clk

t_CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

t_CH

t_CL

t_RWs

t_RWh

A0

A1

A2

A3

A4

A5

A6

0

SPI_In

MSB

LSB

t_DRDY

SPI_Out

D0

D1

D2

D3

D4

D5

D6

D7

LSB

MSB

NOTE:ꢀꢀꢀSPI_OUTꢀisꢀnormallyꢀheldꢀatꢀlogicꢀ0ꢀexceptꢀꢀwhenꢀtri-statedꢀduringꢀanꢀꢀ

ꢀ

ꢀꢀꢀꢀꢀꢀꢀꢀꢀ addressꢀreadꢀcycleꢀonꢀtheꢀSPI_INꢀpinꢀorꢀwhenꢀdataꢀisꢀbeingꢀoutputꢀonꢀtheꢀꢀ

ꢀ

SPI_OUTꢀpin.ꢀ

Serial Interface Timing, Write Access

Figure 5

CS

t_CSMIN

t_CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SCLK

t_CH

t_CL

t_RWs

t_RWh

A1

A0

A2

A3

A4

A5

A6

1

D0

D1

D2

D3

D4

D5

D6

D7

SDI

MSB

LSB

SM3-8RG5 Data Sheet #: TM088 Page 8 of 32

Rev: 07 Date: 09/06/11

Detailed Description continued

Serial Interface Timing

Table 4

Symbolꢀ

t_CSꢀ

Parameterꢀ

Minimumꢀ

Nominalꢀ

Maximumꢀ

Unitsꢀ

ns

Notes

SPI_EnableꢀlowꢀtoꢀSPI_CLKꢀlowꢀ

SPI_CLKꢀhighꢀtimeꢀ

SPI_CLKꢀlowꢀtimeꢀ

Read/Writeꢀsetupꢀtimeꢀ

Read/Writeꢀholdꢀtimeꢀ

Dataꢀreadyꢀ

DataꢀHoldꢀ

ChipꢀSelectꢀtoꢀdataꢀtri-stateꢀ

Minimumꢀdelayꢀbetweenꢀsuccessiveꢀaccessesꢀ 300ꢀ

15ꢀ

25ꢀ

15ꢀ

-ꢀ

25ꢀ

-ꢀ

t_CH

ꢀ

t_CLꢀ

t_RWs

ꢀ

t_RWh

t_DRDY

t_HLD

t_CSTRI

t_CSMIN

ꢀ

15ꢀ

5ꢀ

ꢀ

-ꢀ

ns

Reference Input Quality Monitoring

ꢀ

Eachꢀreferenceꢀinputꢀisꢀmonitoredꢀforꢀsignalꢀpresenceꢀandꢀfrequencyꢀoffset.ꢀSignalꢀpresenceꢀforꢀtheꢀRef1-8ꢀinputsꢀisꢀindicatedꢀinꢀ

theꢀRef_ActivityꢀregisterꢀandꢀsignalꢀpresenceꢀforꢀtheꢀM/S REFꢀisꢀindicatedꢀinꢀbitꢀ0ꢀofꢀtheꢀM/S REF_Activityꢀregister.ꢀTheꢀfrequencyꢀ

offsetꢀbetweenꢀtheꢀRef1-8ꢀinputsꢀandꢀtheꢀcalibratedꢀlocalꢀoscillatorꢀisꢀavailableꢀinꢀtheꢀRef_Frq_Offsetꢀregistersꢀ(8).ꢀRegisterꢀRef_

Pullin_Stsꢀindicates,ꢀforꢀeachꢀofꢀtheꢀRef1-8ꢀinputs,ꢀifꢀtheꢀreferenceꢀisꢀwithinꢀtheꢀmaximumꢀpull-inꢀrange.ꢀTheꢀmaximumꢀpull-inꢀrangeꢀ

isꢀindicatedꢀinꢀregisterꢀMax_Pullin_Range,ꢀandꢀmayꢀbeꢀsetꢀinꢀ0.1ppmꢀincrements.ꢀTypically,ꢀitꢀwouldꢀbeꢀsetꢀaccordingꢀtoꢀtheꢀvaluesꢀ

speciﬁedꢀbyꢀtheꢀstandardsꢀ(GR-1244)ꢀappropriateꢀforꢀtheꢀparticularꢀstratumꢀofꢀoperation.ꢀ

ꢀ

TheꢀRef_Qualiﬁedꢀregisterꢀcontainsꢀtheꢀ“anded”ꢀconditionꢀofꢀtheꢀRef_ActivityꢀandꢀRef_Pullin_StsꢀregistersꢀforꢀeachꢀofꢀtheꢀRef1-8

inputs,ꢀqualiﬁedꢀforꢀ10ꢀseconds.ꢀWhenꢀaꢀreferenceꢀsignalꢀhasꢀbeenꢀpresentꢀforꢀ>ꢀ10ꢀsecondsꢀandꢀisꢀwithinꢀtheꢀpull-inꢀrange,ꢀit’sꢀbitꢀisꢀ

set.ꢀ

ꢀ

TheꢀRef_Availableꢀregisterꢀcontainsꢀtheꢀ“anded”ꢀconditionꢀofꢀtheꢀRef_QualiﬁedꢀregisterꢀandꢀtheꢀRef_Maskꢀregister,ꢀandꢀthereforeꢀ

representsꢀtheꢀavailabilityꢀofꢀaꢀreferenceꢀforꢀselectionꢀwhenꢀautomaticꢀreferenceꢀandꢀoperationalꢀmodeꢀselectionꢀisꢀenabled.

Reference Input Selection, Frequencies, and Mode Selection

ꢀ

Oneꢀofꢀeightꢀreferenceꢀinputꢀsignalsꢀ(Ref 1-8)ꢀareꢀselectedꢀforꢀsynchronizationꢀinꢀMasterꢀmodeꢀ(asꢀbelowꢀinꢀtheꢀOp_Modeꢀregisterꢀ

description.ꢀ0x05).ꢀꢀRef 1-8ꢀmayꢀeachꢀbeꢀ8ꢀkHz,ꢀ1.544ꢀMHz,ꢀ2.048ꢀMHz,ꢀ12.96ꢀMHz,ꢀ19.44ꢀMHz,ꢀ25.92ꢀMHz,ꢀ38.88ꢀMHz,ꢀ51.84ꢀMHzꢀ

orꢀ77.76ꢀMHz.ꢀ

ꢀ

Referenceꢀfrequenciesꢀareꢀauto-detectedꢀandꢀtheꢀdetectedꢀfrequencyꢀcanꢀbeꢀreadꢀfromꢀtheꢀRef_Frq_Priority registersꢀ(Seeꢀ

Register Descriptions and Operationꢀsection).ꢀ

Activeꢀreferenceꢀandꢀoperationalꢀmodeꢀselectionꢀmayꢀbeꢀmanualꢀorꢀautomatic,ꢀasꢀdeterminedꢀbyꢀbitꢀ1ꢀinꢀtheꢀCtl_Modeꢀregister.ꢀInꢀ

manualꢀmode,ꢀregisterꢀwritesꢀtoꢀOp_Modeꢀselectꢀtheꢀreferenceꢀandꢀmode.ꢀꢀTheꢀresetꢀdefaultꢀisꢀmanualꢀmode.ꢀ

TheꢀM/SꢀREFꢀinputꢀforꢀslaveꢀoperationꢀisꢀfrequencyꢀauto-detectedꢀandꢀmayꢀbeꢀ8kHz,ꢀ1.544MHz,ꢀ2.048MHz,ꢀ12.96MHz,ꢀ19.44MHz,ꢀ

ꢀ

25.92MHz,ꢀ38.88MHz,ꢀ51.84MHzꢀorꢀ77.76MHz.ꢀSignalꢀpresenceꢀandꢀfrequencyꢀforꢀtheꢀM/SꢀREFꢀinputꢀisꢀindicatedꢀinꢀbitsꢀ0-3ꢀofꢀtheꢀ

M/S REF_Activityꢀregister.

ꢀ

Inꢀautomaticꢀmode,ꢀtheꢀreferenceꢀisꢀselectedꢀaccordingꢀtoꢀtheꢀprioritiesꢀwrittenꢀtoꢀtheꢀeightꢀRef_Frq_Priorityꢀregisters.ꢀIndividualꢀ

referencesꢀmayꢀbeꢀmaskedꢀforꢀuse/non-useꢀaccordingꢀtoꢀtheꢀRef_Maskꢀregister.ꢀAꢀreferenceꢀmayꢀonlyꢀbeꢀselectedꢀifꢀitꢀisꢀ“available”ꢀ

-ꢀthatꢀis,ꢀitꢀisꢀqualiﬁed,ꢀasꢀindicatedꢀinꢀtheꢀRef_Qualiﬁed register,ꢀandꢀisꢀnotꢀmaskedꢀ(SeeꢀReference Input Quality Monitoring and

Register Descriptions and Operation sections).ꢀꢀ

ꢀ

Furthermore,ꢀBitꢀ3ꢀofꢀeachꢀRef_Frq_Priority registerꢀwillꢀdetermineꢀifꢀthatꢀreferenceꢀisꢀrevertiveꢀorꢀnon-revertive.ꢀWhenꢀaꢀreferenceꢀ

fails,ꢀtheꢀnextꢀhighestꢀpriorityꢀ“available”ꢀ(signalꢀpresent,ꢀnon-masked,ꢀandꢀacceptableꢀfrequencyꢀoffset)ꢀreferenceꢀwillꢀbeꢀselected.ꢀ

Whenꢀaꢀreferenceꢀreturns,ꢀitꢀwillꢀbeꢀswitchedꢀtoꢀonlyꢀifꢀitꢀisꢀofꢀhigherꢀpriorityꢀandꢀtheꢀcurrentꢀactiveꢀreferenceꢀisꢀmarkedꢀ“Revertive”.ꢀꢀ

Additionally,ꢀtheꢀreversionꢀisꢀdelayedꢀaccordingꢀtoꢀtheꢀvalueꢀwrittenꢀtoꢀtheꢀRef_Rev_Delayꢀregisterꢀ(Fromꢀ0ꢀtoꢀ255ꢀminutes).ꢀ

SM3-8RG5 Data Sheet #: TM088 Page 9 of 32

Rev: 07 Date: 09/06/11

Detailed Description continued

The automatic reference selection is shown in the following state diagram:

Automatic Reference Selection

Figure 6

Stay

Locked on Ref m

time for t=

Ref_Rev_Delay

time expired

Ref n returns,

Ref m marked

“revertive”

Ref n returns,

Ref m marked

“non-revertive”

Select &

Lock on

Ref m

Loss of Ref n

Locked

on Ref n

Select new reference:

Next highest priority,

Qualified (within max. pull-in range, signal present > 10 sec.),

Non-masked

The operational mode is according to the following state diagram:

NoꢀavailableꢀreferenceꢀandꢀnoꢀHoldꢀOverꢀhistory

Refꢀlossꢀw/noꢀgoodꢀHoldꢀOverꢀhistoryꢀandꢀnoꢀotherꢀavailableꢀreference

Automatic Operational Mode Selection

Figure 7

Reference Available

(Select highest priority)

Higher priority Ref return with

prior reference marked

“revertive”

Ref Loss w/alternate

reference available

Locked

Ref loss w/no good hold

over history and no other

available reference

Ref Loss w/good hold over history

and no alternate reference available

Ref

Return

Ref

Return

No available

reference and

no hold over

history

Free Run

Hold Over

SM3-8RG5 Data Sheet #: TM088 Page 10 of 32

Rev: 07 Date: 09/06/11

Detailed Description continued

Output Signals and Frequency

ꢀ

Output 1ꢀisꢀtheꢀprimaryꢀchipꢀoutput,ꢀandꢀinꢀlockedꢀmodeꢀisꢀsynchronizedꢀtoꢀtheꢀselectedꢀreference.ꢀOutput 1ꢀmayꢀbeꢀanyꢀofꢀtheꢀ

followingꢀfrequencies:ꢀ12.96ꢀMHz,ꢀ19.44ꢀMHz,ꢀ25.92ꢀMHz,ꢀ38.88ꢀMHz,ꢀ51.84ꢀMHzꢀorꢀ77.76ꢀMHz.

M/S_Out isꢀanꢀ8ꢀkHzꢀoutputꢀavailableꢀasꢀaꢀframeꢀreferenceꢀorꢀsynchronizationꢀsignalꢀforꢀcross-coupledꢀpairsꢀofꢀSM3-8RG5ꢀdevicesꢀ

ꢀ

operatedꢀinꢀmaster/slaveꢀmode.ꢀInꢀmasterꢀmode,ꢀM/S_Outꢀisꢀsynchronizedꢀtoꢀtheꢀselectedꢀreference.ꢀInꢀslaveꢀmode,ꢀM/S_Outꢀisꢀinꢀ

phaseꢀwithꢀtheꢀM/S REF offsetꢀbyꢀtheꢀvalueꢀwrittenꢀtoꢀtheꢀPhase_offset registerꢀ(+31.75ꢀtoꢀ-32nS,ꢀwithꢀ.25nSꢀresolution).ꢀM/S_Outꢀ

mayꢀbeꢀaꢀ50%ꢀdutyꢀcycleꢀsignal,ꢀorꢀvariableꢀhigh-goingꢀpulseꢀwidth,ꢀasꢀdeterminedꢀbyꢀtheꢀCtl_ModeꢀandꢀFr_Pulse_Widthꢀregisters.ꢀ

Inꢀvariableꢀpulseꢀwidthꢀmode,ꢀtheꢀwidthꢀmayꢀbeꢀfromꢀ1ꢀtoꢀ15ꢀmultiplesꢀofꢀtheꢀOutput 1ꢀcycleꢀtime.ꢀSeeꢀRegisterꢀDescriptionsꢀandꢀ

Operationꢀsection.

BITS_ClkꢀisꢀtheꢀBITSꢀclockꢀoutputꢀatꢀeitherꢀ1.544ꢀMHzꢀorꢀ2.048ꢀMHz.ꢀItꢀisꢀselectedꢀbyꢀtheꢀT1/E1ꢀinputꢀandꢀitsꢀstateꢀmayꢀbeꢀreadꢀinꢀbitꢀ

3ꢀofꢀtheꢀCtl_Modeꢀregister.ꢀWhenꢀT1/E1ꢀ=ꢀ1,ꢀtheꢀBITSꢀfrequencyꢀisꢀ1.544ꢀMHz,ꢀandꢀwhenꢀT1/E1ꢀ=ꢀ0,ꢀtheꢀBITSꢀfrequencyꢀisꢀ2.048ꢀMHz.

Interrupts

ꢀ

TheꢀSM3-8RG5ꢀmoduleꢀsupportsꢀeightꢀdifferentꢀinterruptsꢀandꢀappearsꢀinꢀINTR_EVENT (0x12)ꢀregister.ꢀEachꢀinterruptꢀcanꢀbeꢀ

individuallyꢀenabledꢀorꢀdisabledꢀviaꢀtheꢀINTR_ENABLE (0x13)ꢀregister.ꢀEachꢀbitꢀenablesꢀorꢀdisablesꢀtheꢀcorrespondingꢀinterruptꢀfromꢀ

assertingꢀtheꢀSPI_INTꢀpin.ꢀInterruptꢀeventsꢀstillꢀappearꢀinꢀtheꢀINTR_EVENT (0x12)ꢀregisterꢀindependentꢀofꢀtheirꢀenableꢀstate.ꢀAllꢀ

interruptsꢀareꢀclearedꢀonceꢀINTR_EVENT (0x12)ꢀregisterꢀisꢀread.ꢀTheꢀinterruptsꢀare:

ꢀ

•ꢀꢀ

Anyꢀreferenceꢀchangingꢀfromꢀavailableꢀtoꢀnotꢀavailable

Anyꢀreferenceꢀchangingꢀfromꢀnotꢀavailableꢀtoꢀavailable

M/S REFꢀchangingꢀfromꢀactivityꢀtoꢀnoꢀactivity

M/S REFꢀchangingꢀfromꢀnoꢀactivityꢀtoꢀactivity

DPLLꢀModeꢀstatusꢀchange

Referenceꢀswitchꢀinꢀautomaticꢀreferenceꢀselectionꢀmode

LossꢀofꢀSignal

LossꢀofꢀLock

Interrupts and Reference Change in Autonomous Mode

ꢀ

Interruptsꢀcanꢀbeꢀusedꢀtoꢀdetermineꢀtheꢀcauseꢀofꢀaꢀreferenceꢀchangeꢀinꢀautonomousꢀmode.ꢀLetꢀusꢀassumeꢀthatꢀtheꢀmoduleꢀisꢀ

currentlyꢀlockedꢀtoꢀREF1.ꢀTheꢀmoduleꢀswitchesꢀtoꢀREF2ꢀandꢀSPI_INTꢀpinꢀisꢀasserted.ꢀTheꢀuserꢀreadsꢀtheꢀINTR_EVENT (0x12)ꢀ

register.ꢀ

ꢀ

Ifꢀtheꢀmoduleꢀisꢀoperatingꢀinꢀautonomousꢀnon-revertiveꢀmode,ꢀtheꢀcauseꢀcanꢀbeꢀdeterminedꢀfromꢀbitsꢀ4,ꢀ5,ꢀ6ꢀandꢀ7.ꢀBitꢀ5ꢀisꢀsetꢀtoꢀ

indicateꢀActiveꢀreferenceꢀchange.ꢀIfꢀBitꢀ6ꢀisꢀsetꢀthenꢀtheꢀcauseꢀofꢀtheꢀreferenceꢀchangeꢀisꢀLossꢀofꢀActiveꢀReference.ꢀIfꢀBitꢀ7ꢀisꢀsetꢀthenꢀ

theꢀcauseꢀofꢀtheꢀreferenceꢀchangeꢀisꢀaꢀLossꢀofꢀLockꢀalarmꢀonꢀtheꢀactiveꢀreference.

ꢀ

Ifꢀtheꢀmoduleꢀisꢀoperatingꢀinꢀautonomousꢀrevertiveꢀmode,ꢀtheꢀcauseꢀcanꢀbeꢀdeterminedꢀfromꢀbitsꢀ1,ꢀ4,5,ꢀ6ꢀandꢀ7.ꢀBitꢀ5ꢀisꢀsetꢀtoꢀ

indicateꢀActiveꢀreferenceꢀchange.ꢀIfꢀBitꢀ6ꢀisꢀsetꢀthenꢀtheꢀcauseꢀofꢀtheꢀreferenceꢀchangeꢀisꢀLossꢀofꢀActiveꢀReference.ꢀIfꢀBitꢀ7ꢀisꢀsetꢀ

thenꢀtheꢀcauseꢀofꢀtheꢀreferenceꢀchangeꢀisꢀaꢀLossꢀofꢀLockꢀalarmꢀonꢀtheꢀactiveꢀreference.ꢀIfꢀBitꢀ1ꢀisꢀsetꢀthenꢀtheꢀcauseꢀofꢀtheꢀreferenceꢀ

changeꢀisꢀtheꢀavailabilityꢀofꢀaꢀhigherꢀpriorityꢀreference.

ꢀ

Note:ꢀTheꢀDPLLꢀModeꢀStatusꢀChangeꢀbitꢀ(Bitꢀ4)ꢀisꢀalsoꢀsetꢀtoꢀindicateꢀaꢀchangeꢀinꢀDPLL_STATUS (0x11)ꢀregister,ꢀduringꢀanꢀ

interruptꢀcausedꢀbyꢀaꢀreferenceꢀchange.ꢀTheꢀdataꢀin DPLL_STATUS (0x11)ꢀregisterꢀhoweverꢀisꢀnotꢀusefulꢀinꢀdeterminingꢀtheꢀcauseꢀofꢀ

aꢀreferenceꢀchange.ꢀThisꢀisꢀbecauseꢀbitsꢀ0-2ꢀofꢀthisꢀregisterꢀalwaysꢀreﬂectsꢀtheꢀstatusꢀofꢀtheꢀcurrentꢀactiveꢀreferenceꢀandꢀhenceꢀcannotꢀ

beꢀusedꢀtoꢀdetermineꢀtheꢀstatusꢀofꢀtheꢀlastꢀactiveꢀreference.

Interrupts in Manual Mode

ꢀ

Inꢀmanualꢀoperatingꢀmode,ꢀwhenꢀtheꢀactiveꢀreferenceꢀfailsꢀdueꢀtoꢀaꢀLossꢀofꢀSignalꢀorꢀLossꢀofꢀLockꢀalarm,ꢀanꢀinterruptꢀisꢀgenerated.ꢀ

Forꢀexample,ꢀinꢀcaseꢀofꢀaꢀLossꢀofꢀSignal,ꢀbits4ꢀandꢀ6ꢀofꢀINTR_EVENT (0x12) registerꢀwouldꢀbeꢀsetꢀtoꢀindicateꢀLossꢀofꢀSignalꢀandꢀ

DPLLꢀModeꢀStatusꢀChange.ꢀTheꢀuserꢀmayꢀchooseꢀtoꢀreadꢀtheꢀDPLL_STATUS (0x11)ꢀregister,ꢀthoughꢀinꢀmanualꢀmodeꢀbit6ꢀofꢀINTR_

EVENT (0x12)ꢀregisterꢀisꢀaꢀmirrorꢀofꢀbit0ꢀofꢀDPLL_STATUS (0x11)ꢀregister.ꢀThisꢀholdsꢀtrueꢀforꢀaꢀLossꢀofꢀLockꢀalarm,ꢀwhereꢀbit7ꢀofꢀ

INTR_EVENT (0x12) registerꢀisꢀaꢀmirrorꢀofꢀbit1ꢀofꢀDPLL_STATUS (0x11)ꢀregister.

Internal Clock Calibration

ꢀ

Theꢀinternalꢀclockꢀmayꢀbeꢀcalibratedꢀbyꢀwritingꢀaꢀfrequencyꢀoffsetꢀv.s.ꢀnominalꢀfrequencyꢀintoꢀtheꢀCalibrationꢀregister.ꢀThisꢀ

calibrationꢀisꢀusedꢀbyꢀtheꢀsynchronizationꢀsoftwareꢀtoꢀcreateꢀaꢀfrequencyꢀcorrectedꢀfromꢀtheꢀactualꢀinternalꢀclockꢀoutputꢀbyꢀtheꢀvalueꢀ

writtenꢀtoꢀtheꢀCalibrationꢀregister.ꢀSeeꢀregisterꢀdescriptions.

SM3-8RG5 Data Sheet #: TM088 Page 11 of 32

Rev: 07 Date: 09/06/11

Register Descriptions and Operation

Chip_ID_low, 0x00 (R)

Bitꢀ7ꢀ~ꢀBitꢀ0

Bitꢀ4ꢀ

LowꢀbyteꢀofꢀchipꢀID:ꢀ0x11

Chip_ID_High, 0x01 (R)

HighꢀbyteꢀofꢀchipꢀID:ꢀ0x30

Chip_Revision, 0x02 (R)

Chipꢀrevisionꢀnumber:ꢀ0x06

Bandwidth_PBO, 0x03 (R/W)

ꢀ

Bitꢀ7ꢀ~ꢀBitꢀ5ꢀ

ꢀ

ꢀꢀꢀꢀꢀBitꢀ3ꢀ~ꢀBitꢀ0

Reservedꢀ

0:ꢀDefaultꢀ

BandwidthꢀSelectionꢀinꢀHz:

ꢀ

0000:ꢀ0.025ꢀ

0001:ꢀ0.025ꢀ

0010:ꢀ0.025ꢀ

0011:ꢀ0.025ꢀ

0100:ꢀ0.025ꢀ

0101:ꢀ0.025ꢀ

0110:ꢀ0.049ꢀ

ꢀ

0111:ꢀ0.098ꢀ(ResetꢀDefault)ꢀ

1000:ꢀ0.20ꢀ

1001:ꢀ0.39ꢀ

1010:ꢀ0.78ꢀ

1011ꢀ-ꢀ1111:ꢀ1.6

BITS 3 - 0 select the phase lock loop bandwidth in Hertz.

Ctl_Mode, 0x04 (R/W)

ꢀꢀꢀBitꢀ7ꢀ~ꢀBitꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀBitꢀ5ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀBitꢀ4ꢀ

ꢀꢀꢀBitꢀ3ꢀ

ꢀꢀꢀꢀꢀꢀꢀBitꢀ2ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀBitꢀ1ꢀ

ꢀ

Bitꢀ0

Reservedꢀ

Default:ꢀ0ꢀ

M/SꢀOutputꢀ

Pulseꢀwidthꢀ

control:ꢀ

0:ꢀ50%ꢀ

1:ꢀControlledꢀbyꢀ

FR_Pulse_Widthꢀ (readꢀonly)ꢀ

registerꢀ

Default:ꢀ0

BITSꢀClockꢀ

Outputꢀ

Frequency:ꢀ

1:ꢀ1.544ꢀMHzꢀ

0:ꢀ2.048ꢀMHzꢀ

HMꢀRef:ꢀ

Activeꢀ

Reserved

ꢀ

0:ꢀRegisterꢀcontrolꢀ

ofꢀopꢀmode/refꢀ

(Willꢀalwaysꢀꢀ

beꢀ0)ꢀ

Referenceꢀ

Selection:

1:ꢀManualꢀ

0:ꢀAutomaticꢀ

Default:ꢀ1ꢀ

ꢀ

When bit 1 is reset (automatic reference and mode selection), Bits 3 - 0 of the Op_Mode register become read-only.

The power-up default for Bit 1 = 1 for manual reference selection and default for Bit 4 = 0 for 50% duty cycle on M/S

Output.

When the device is in slave mode, it will lock to the M/S REF, independent of the values written to BITS 3 - 0 of the

Op_mode register. The operational mode and reference selection written to Bits 3 - 0 while in slave mode will, however,

take effect when the device is made the master.

When bit 1 of the Ctl_Mode register is reset (automatic reference and mode selection) and the device is in master

mode, BITS 3 - 0 of the Op_Mode register become read-only.

SM3-8RG5 Data Sheet #: TM088 Page 12 of 32

Rev: 07 Date: 09/06/11

Register Descriptions and Operation continued

Op_Mode, 0x05 (R/W)

Bitꢀ7ꢀ~ꢀBitꢀ5ꢀꢀ

Bitꢀ4ꢀ

ꢀ

Bitꢀ3ꢀ~ꢀBitꢀ0

FreeꢀRun,ꢀLocked,ꢀorꢀHoldꢀOver:

Reservedꢀ

ꢀ

MasterꢀorꢀSlaveꢀModeꢀ

ꢀ

1:ꢀMasterꢀ

0000:ꢀFreeꢀRunꢀmodeꢀ

0001:ꢀLockedꢀonꢀRef1ꢀ

0010:ꢀLockedꢀonꢀRef2ꢀ

0011:ꢀLockedꢀonꢀRef3ꢀ

0100:ꢀLockedꢀonꢀRef4ꢀ

0101:ꢀLockedꢀonꢀRef5ꢀ

0110:ꢀLockedꢀonꢀRef6ꢀ

0111:ꢀLockedꢀonꢀRef7ꢀ

1000:ꢀLockedꢀonꢀRef8ꢀ

ꢀ

0:ꢀSlaveꢀꢀ

(ReadꢀOnly)ꢀ

ꢀ

1001ꢀ-ꢀ1111:ꢀHoldꢀOver

Max_Pullin_Range, 0x06 (R/W)

Bitꢀ7ꢀ~ꢀBitꢀ0

Maximumꢀpull-inꢀrangeꢀinꢀ0.1ꢀppmꢀunit

This register should be set according to the values speciﬁed by the standards (GR-1244) appropriate for the particular

stratum of operation. The power-up default value is 10 ppm. (= 4.6ppm aging + 4.6 ppm pullin + margin).

M/S REF_Activity, 0x07 (R)

ꢀ

Bitꢀ7ꢀ~ꢀBitꢀ4ꢀ

ꢀ

Bitꢀ3ꢀ~ꢀBitꢀ0

Reservedꢀ

ꢀ

Crossꢀreferenceꢀactivity

0000:ꢀNoꢀsignal

0001:ꢀ8kHz

0100:ꢀ12.96MHz

0101:ꢀ19.44MHz

0110:ꢀ25.92MHz

0111:ꢀ38.88MHz

1000:ꢀ51.84MHz

1001:ꢀ77.76MHz

1010-1111:ꢀReserved

ꢀ

Indicates signal presence and auto-detected frequency for the M/S REF input.

Ref_Activity, 0x08 (R)

Bitꢀ7ꢀ

Bitꢀ6ꢀ

Bitꢀ5ꢀ

Bitꢀ4ꢀ

Bitꢀ3ꢀ

Bitꢀ2ꢀ

Bitꢀ1ꢀ

Bitꢀ0

ref8ꢀactivityꢀ ref7ꢀactivityꢀ

ref6ꢀactivityꢀ

1:ꢀonꢀ

0:ꢀoffꢀ

ref5ꢀactivityꢀ

1:ꢀonꢀ

0:ꢀoffꢀ

ref4ꢀactivityꢀ

1:ꢀonꢀ

0:ꢀoffꢀ

ref3ꢀactivityꢀ

1:ꢀonꢀ

0:ꢀoffꢀ

ref2ꢀactivityꢀ

1:ꢀonꢀ

0:ꢀoffꢀ

ref1ꢀactivityꢀ

1:ꢀonꢀ

0:ꢀoff

1:ꢀonꢀ

0:ꢀoffꢀ

1:ꢀonꢀ

0:ꢀoffꢀ

Each bit indicates the presence of a signal for that reference.

SM3-8RG5 Data Sheet #: TM088 Page 13 of 32

Rev: 07 Date: 09/06/11

Register Descriptions and Operation continued

Ref_Pullin_Sts, 0x09 (R)

Bitꢀ7ꢀ

Bitꢀ6ꢀ

Bitꢀ5ꢀ

Bitꢀ4ꢀꢀ

ꢀ

Bitꢀ3ꢀ

Bitꢀ2ꢀꢀ

Bitꢀ1ꢀ

Bitꢀ0

ref8ꢀstsꢀ

1:ꢀinꢀrangeꢀ

0:ꢀoutꢀrangeꢀ 0:ꢀoutꢀrangeꢀ

ref7ꢀstsꢀ

1:ꢀinꢀrangeꢀ

ref6ꢀstsꢀ

1:ꢀinꢀrangeꢀ

0:ꢀoutꢀrangeꢀ

ref5ꢀstsꢀ

1:ꢀinꢀrangeꢀ

0:ꢀoutꢀrangeꢀ

ꢀ

ref4ꢀstsꢀ

1:ꢀinꢀrangeꢀ 1:ꢀinꢀrangeꢀ

0:ꢀoutꢀrangeꢀ 0:ꢀoutꢀrangeꢀ

ref3ꢀstsꢀ

ref2ꢀstsꢀ

1:ꢀinꢀrangeꢀ

0:ꢀoutꢀrangeꢀ

ref1ꢀstsꢀ

1:ꢀinꢀrangeꢀ

0:ꢀoutꢀrange

Each bit indicates if the reference is within the frequency range speciﬁed by the value in the Max_Pullin register.

Ref_Qualiﬁed, 0x0a (R)

Bitꢀ7ꢀ

Bitꢀ6ꢀ

Bitꢀ5ꢀ

Bitꢀ4ꢀꢀ

ꢀ

Bitꢀ3ꢀ

Bitꢀ2ꢀꢀ

Bitꢀ1ꢀ

Bitꢀ0

ref8ꢀqual:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ 0:ꢀnotꢀavail.ꢀ

ref7ꢀqual:ꢀ

1:ꢀavail.ꢀ

ref6ꢀqual:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ

ref5ꢀqual:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ

ꢀ

ref4ꢀqual:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ 0:ꢀnotꢀavail.ꢀ

ref3ꢀqual:ꢀ

1:ꢀavail.ꢀ

ref2ꢀqual:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ

ref1ꢀqual:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.

This register contains the “anded” condition of the Ref_Activity and Ref_Pullin_Sts registers for each of the Ref1-8

inputs, qualiﬁed for 10 seconds. When a reference signal has been present for > 10 seconds and is within the pull-in

range, its bit is set.

Ref_Mask, 0x0b (R/W)

Bitꢀ7ꢀ

Bitꢀ6ꢀ

Bitꢀ5ꢀ

Bitꢀ4ꢀꢀ

ꢀ

Bitꢀ3ꢀ

Bitꢀ2ꢀꢀ

Bitꢀ1ꢀ

Bitꢀ0

ref8ꢀmask:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ 0:ꢀnotꢀavail.ꢀ

Default:ꢀ0ꢀ Default:ꢀ0ꢀ

ref7ꢀmask:ꢀ

1:ꢀavail.ꢀ

ref6ꢀmask:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ

Default:ꢀ0ꢀ

ref5ꢀmask:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ

Default:ꢀ0ꢀ

ꢀ

ref4ꢀmask:ꢀ ref3ꢀmask:ꢀ

1:ꢀavail.ꢀ 1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ 0:ꢀnotꢀavail.ꢀ

Default:ꢀ0ꢀ Default:ꢀ0ꢀ

ref2ꢀmask:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ

Default:ꢀ0ꢀ

ref1ꢀmask:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ

Default:ꢀ0

Individual references may be marked as “available” or “not available” for selection in the automatic reference selection

mode

(bit 1 = 0 in the Ctl_Mode register). The reset default value is 0, “not available”. In manual reference selection, either

hardware or register controlled, the reference masks have no effect, but do remain valid and are applied upon a transi-

tion to automatic mode.

Ref_Available, 0x0c (R)

Bitꢀ7ꢀ

Bitꢀ6ꢀ

Bitꢀ5ꢀ

ꢀ

Bitꢀ4ꢀ

ꢀ

ꢀ Bitꢀ3ꢀ

ꢀ Bitꢀ2ꢀ

ꢀ Bitꢀ1ꢀ

Bitꢀ0

ref8ꢀavail:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ 0:ꢀnotꢀavail.ꢀ

ref7ꢀavail:ꢀ

1:ꢀavail.ꢀ

ref6ꢀavail:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ

ꢀ

ref5ꢀavail:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ ꢀ

ꢀ

ref4ꢀavail:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ 0:ꢀnotꢀavail.ꢀ

ref3ꢀavail:ꢀ

1:ꢀavail.ꢀ

ref2ꢀavail:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀavail.ꢀ

ref1ꢀavail:ꢀ

1:ꢀavail.ꢀ

0:ꢀnotꢀ

This register contains the “anded” condition of the Ref_Qualiﬁed and Ref_Mask registers.

Ref_Rev_Delay, 0x0d (R/W)

Bitꢀ7ꢀ~ꢀBitꢀ0

Referenceꢀreversionꢀdelayꢀtime,ꢀ0ꢀ-ꢀ255ꢀminutes.ꢀdefaultꢀ=ꢀ0000ꢀ0101,ꢀ5ꢀminutes

In automatic reference selection mode, when a reference fails and later returns, it must be available for the time speci-

ﬁed in the Ref_Rev_Delay register before it can be switched back to as the active reference (if the new reference was

marked as “revertive”).

SM3-8RG5 Data Sheet #: TM088 Page 14 of 32

Rev: 07 Date: 09/06/11

Register Descriptions and Operation continued

Phase_Offset, 0x0e (R/W)

Bitꢀ7ꢀ~ꢀBitꢀ0

Theꢀ2’sꢀcomplementꢀvalueꢀofꢀphaseꢀoffsetꢀbetweenꢀMasterꢀOutputꢀmoduleꢀandꢀSlaveꢀOutputꢀmodule,ꢀrangesꢀfromꢀ-32ꢀnSꢀtoꢀ+31.75ꢀnSꢀ

ꢀ

PositiveꢀValue:ꢀMasterꢀOutputꢀrisingꢀedgeꢀleadsꢀSlaveꢀOutputꢀꢀ

NegativeꢀValue:ꢀMasterꢀOutputꢀrisingꢀedgeꢀlagsꢀSlaveꢀOutputꢀ

In slave mode, the slave’s outputs may be phase shifted -32nS to +31.75nS in .25nS increments, relative to M/S ac-

cording to the contents of the Phase_Offset register, to compensate for the path length of the M/S to M/S connection.

If a phase offset is used, then the two SM3-8RG5 devices would typically be written to the appropriate phase offset val-

ues for the respective path lengths of each Master to Slave connection, to ensure that the same relative output signal

phases will persist through master/slave switches.

Calibration, 0x0f (R/W)

Bitꢀ7ꢀ~ꢀBitꢀ0

2’sꢀcomplementꢀvalueꢀofꢀlocalꢀoscillatorꢀdigitalꢀcalibrationꢀinꢀ0.05ꢀppmꢀresolution

To digitally calibrate the free running clock synthesized from the internal clock, this register is written with a value cor-

responding to the known frequency offset of the oscillator from the nominal center frequency.

Fr_Pulse_Width, 0x10 (R/W)

ꢀ

Bitꢀ7ꢀ~ꢀBit4ꢀ

ꢀ

Bitꢀ3ꢀ~ꢀBitꢀ0

Reservedꢀ

ꢀ

ꢀ PulseꢀwidthꢀforꢀM/Sꢀꢀclockꢀoutput,ꢀꢀ

1-15ꢀmultiplesꢀofꢀtheꢀSync_Clkꢀclockꢀperiod.ꢀ

BITS 4 and 5 of the Ctl_Mode register determine if the M/S 8 kHz output is 50% duty cycle or pulsed (high going)

outputs. When they are pulsed, the Fr_Pulse_Width register determines the width. Width is the register value multiple of

the Sync_Clk clock period. Valid values are 1 - 15.

Reset default is 0001. Writing to 0000 maps to 0001.

DPLL_Status, 0x11 (R)

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀBitꢀ7ꢀ~Bitꢀ5ꢀꢀ

ꢀꢀBitꢀ4ꢀ

ꢀꢀꢀBitꢀ3ꢀ ꢀ

Bitꢀ2ꢀ ꢀ

Bitꢀ1ꢀ

ꢀ Bitꢀ0

Reservedꢀ

HoldꢀOverꢀ

Buildꢀꢀ

Completeꢀ

1:ꢀCompleteꢀ

0:ꢀIncompleteꢀ

ꢀ

HoldꢀOverꢀ

Availableꢀ

1:ꢀAvail.ꢀ

0:ꢀNotꢀavail.ꢀ

ꢀ

Lockedꢀ

1:ꢀLockedꢀ

0:ꢀNotꢀlockedꢀ

ꢀ ꢀ

LossꢀofꢀLockꢀ

1:ꢀLossꢀofꢀLockꢀ

0:ꢀNoꢀlossꢀofꢀlockꢀ

LossꢀofꢀSignal

1:ꢀNoꢀactivity

ꢀꢀꢀꢀonꢀactive

ꢀꢀꢀꢀreferenceꢀ

0:ꢀActiveꢀref-ꢀ

ꢀꢀꢀꢀerenceꢀsignalꢀ

ꢀꢀꢀꢀpresent

ꢀ

Bit 0 indicates the presence of a signal on the selected reference.

Bit 1 indicates a loss of lock (LOL). Loss of lock will be asserted if lock is not achieved within the speciﬁed time for the

stratum level of operation, or lock is lost after being established previously. LOL will not be asserted for automatic refer-

ence switches.

Bit 2 indicates successful phase lock. It will typically be set in <700 seconds for Stratum 3 with a good reference. It will

indicate “not locked” if lock is lost.

Bit 3 indicates if a Hold Over history is available.

Bit 4 indicates when a new Hold Over history has been sucessfully built and transferred to the active Hold Over his-

tory. See Detailed Description section under Interrupts and Reference Change in Autonomous Mode and Interrupts in

Manual Mode

SM3-8RG5 Data Sheet #: TM088 Page 15 of 32

Rev: 07 Date: 09/06/11

Register Descriptions and Operation continued

Intr_Event, 0x12 (R)

Bitꢀ7ꢀ

Bitꢀ6ꢀ

Bitꢀ5ꢀ

Bitꢀ4ꢀ

Bitꢀ3ꢀ

Bitꢀ2ꢀ

Bitꢀ1ꢀ

Bitꢀ0

Lossꢀofꢀꢀ

Lockꢀ

ꢀ

Lossꢀofꢀ

Signalꢀ

ꢀ ꢀ

Activeꢀrefer-ꢀ

enceꢀchangeꢀ

ꢀ ꢀ

DPLLꢀModeꢀ M/SꢀRefꢀ

M/SꢀRefꢀ

Anyꢀrefer-ꢀ

erenceꢀchangeꢀ erenceꢀchangeꢀ

fromꢀnotꢀ

availableꢀtoꢀ

availableꢀ

Anyꢀrefer-ꢀ

statusꢀ

changeꢀ

ꢀ ꢀ

Changeꢀfromꢀ Changeꢀfromꢀꢀ

noꢀactivityꢀtoꢀ activityꢀtoꢀnoꢀꢀ

activityꢀ

ꢀ ꢀ

fromꢀavailableꢀ

ableꢀtoꢀnotꢀ

available

activityꢀ

ꢀ ꢀ

Interrupt state = 1. When an enabled interrupt occurs, the SPI_INT pin is asserted, active low. All interrupts are cleared

and the SPI_INT pin pulled high when the register is read. Reset default is 0. See Detailed Description section under

Interrupts and Reference Change in Autonomous Mode and Interrupts in Manual Mode

Intr_Enable, 0x13 (R/W)

Bitꢀ7ꢀ

Bitꢀ6ꢀ

Bitꢀ5ꢀ

Bitꢀ4ꢀ

ꢀ

Bitꢀ3ꢀ

ꢀ Bitꢀ2ꢀ

ꢀ Bitꢀ1ꢀ

ꢀ

Bitꢀ0

EnableꢀInter-ꢀEnableꢀInter-ꢀ

ruptꢀeventꢀ7:ꢀ ruptꢀeventꢀ6:ꢀ

EnableꢀInter-ꢀ EnableꢀInter-ꢀ ꢀ EnableꢀInter-ꢀ ꢀ EnableꢀInter-ꢀ ꢀ EnableꢀInter-ꢀ ꢀ EnableꢀInter-ꢀ

ruptꢀeventꢀ5:ꢀ

1:ꢀEnableꢀ

0:ꢀDisableꢀ

Default:ꢀ0ꢀ

ruptꢀeventꢀ4:ꢀ ꢀ ruptꢀeventꢀ3:ꢀ ꢀ ruptꢀeventꢀ2:ꢀ ꢀ ruptꢀeventꢀ1:ꢀ ꢀ ruptꢀeventꢀ0:ꢀ

1:ꢀEnableꢀ

0:ꢀDisableꢀ 0:ꢀDisableꢀ

Default:ꢀ0ꢀ Default:ꢀ0ꢀ

1:ꢀEnableꢀ

0:ꢀDisableꢀ

Default:ꢀ0ꢀ

ꢀ

1:ꢀEnableꢀ

0:ꢀDisableꢀ

Default:ꢀ0ꢀ

ꢀ 1:ꢀEnableꢀ

ꢀ 0:ꢀDisableꢀ

ꢀ Default:ꢀ0ꢀ

ꢀ

1:ꢀEnableꢀ

0:ꢀDisableꢀ

Default:ꢀ0ꢀ

ꢀ

1:ꢀEnableꢀ

0:ꢀDisableꢀ

Default:ꢀ0

Enables or disables the corresponding interrupts from asserting the SPI_INT pin. Interrupt events still appear in the

Intr_Event register independent of their “enable” state. Reset default is interrupts disabled.

Ref(1-8)_Frq_Offset, 0x14 ~ 0x1b (R)

Bitꢀ7ꢀ~ꢀBitꢀ0

2’sꢀcomplementꢀvalueꢀofꢀfrequencyꢀoffsetꢀbetweenꢀreferenceꢀandꢀcalibratedꢀlocalꢀoscillator,ꢀ0.2ppmꢀresolution

These registers indicate the frequency offset, in 0.2ppm resolution, between each reference and the local calibrated

oscillator.

0x14 - 0x1b correspond to Ref1 - Ref8.

Ref(1-8)_Frq_Priority, 0x1c ~ 0x23 (R/W)

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀBitꢀ7ꢀ~ꢀBitꢀ4ꢀ

Bitꢀ3ꢀ

ꢀ

Bitꢀ2ꢀ~ꢀBitꢀ0

Frequencyꢀ

0000:ꢀNoneꢀ

0001:ꢀ8ꢀkHzꢀ

Revertivityꢀ

1:ꢀrevertiveꢀ

0:ꢀnon-revertiveꢀ

Default:ꢀ0,ꢀ

nonꢀrevertiveꢀ

Priority

000:ꢀHighestꢀ

111:ꢀLowestꢀ

Default:ꢀ0ꢀ

0010:ꢀ1.544ꢀMHzꢀ

0011:ꢀ2.048ꢀMHzꢀ

0100:ꢀ12.96ꢀMHzꢀ

0101:ꢀ19.44ꢀMHzꢀ

0110:ꢀ25.92ꢀMHzꢀ

0111:ꢀ38.88ꢀMHzꢀ

1000:ꢀ51.84ꢀMHzꢀ

1001:ꢀ77.76ꢀMHzꢀ

1010-1111:ꢀReserved

BITS 2 - 0 indicate the priority of each reference for use in automatic reference selection mode (bit 1 of the Ctl_Mode

register =0). In manual reference selection mode (bit 1 of the Ctl_Mode register = 1), these BITS are read-only and will

contain either the reset default or values written when last in automatic reference selection mode. For equal priority

values, lower reference numbers have higher priority.

Bit 3 speciﬁes if the reference is revertive or non-revertive in automatic reference selection mode. When a reference

fails, the next highest priority “available” (signal present, non-masked, and acceptable frequency offset) reference will

be selected. When a reference returns, it will be switched to only if it is of higher priority and the current active reference

is marked “Revertive”.

BITS 7 - 4 indicate the auto-detected frequency for each reference. Invalid frequencies may result in erroneous device

operation. If there is no activity on a reference, bits 7-4will be = 0000. Bits 7-4 are read only. 0x1c - 0x23 correspond

to Ref1 - Ref8.

SM3-8RG5 Data Sheet #: TM088 Page 16 of 32

Rev: 07 Date: 09/06/11

Register Descriptions and Operation continued

FreeRun_Priority, 0x24 (R/W)

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀBitꢀ7ꢀ-ꢀBitꢀ5ꢀ

ꢀ ꢀ

Bitꢀ4ꢀ

ꢀ Bitꢀ3ꢀ

ꢀ ꢀ

Bitꢀ2ꢀ-ꢀBitꢀ0

ꢀ

ꢀ ꢀ

Enable/ꢀ

Disableꢀ

1:ꢀEnableꢀ

0:ꢀDisableꢀ

Default:ꢀ0ꢀ

Revertivityꢀ

1:ꢀEnableꢀ

0:ꢀDisableꢀ

Default:ꢀ0ꢀ

non-revertiveꢀ

ꢀ

ꢀꢀ

ꢀ

Priorityꢀ

000:ꢀHighestꢀ

111:ꢀLowestꢀ

Default:ꢀ0ꢀ

ꢀ ꢀ

ꢀ

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀReservedꢀ

ꢀ

ꢀ ꢀ

ꢀ

Free Run may be treated like a reference. When it is enabled, Free Run will be entered when all references of higher

priority are lost or masked. If or when a higher priority reference returns, it is switched to if Free Run is set as “re-

vertive”. When disabled, Free Run will be entered only if manually selected or all references fail without an available

Hold Over history. For equal priority value, Free Run will be treated as lower priority.

History_Policy, 0x25 (R/W)

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Bitꢀ7ꢀ-ꢀBitꢀ1ꢀ

ꢀ

ꢀꢀꢀBitꢀ0

ꢀ

ꢀ ꢀ

ꢀ

ꢀ ReferenceꢀSwitchꢀHoldꢀOver

ꢀ HisoryꢀPolicy

ꢀ

ꢀ ꢀ

ꢀ Reservedꢀ

ꢀ ꢀ

ꢀ

ꢀ 0:ꢀRebuildꢀ

ꢀ 1:ꢀContinue

ꢀ ꢀ

ꢀ

Bit 0 determines if Hold Over is retained or rebuilt when a reference switch occurs. See Application Notes, Holdover

History Accumulation and Management section.

History_Cmd, 0x26 (R/W)

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Bitꢀ7ꢀ-ꢀBitꢀ2ꢀ

ꢀ

Bitꢀ1-0

ꢀ

ꢀ ꢀ

ꢀ HoldꢀOverꢀHistroyꢀCommands

ꢀ 01:ꢀSaveꢀactiveꢀhistoryꢀtoꢀbackupꢀhistory

ꢀ 10:ꢀRestoreꢀactiveꢀhistoryꢀfromꢀbackupꢀ

ꢀ 11:ꢀFlushꢀtheꢀactiveꢀhistoryꢀandꢀaccumulationꢀregisterꢀ

ꢀ 00:ꢀNoꢀcommandꢀ-ꢀuseꢀtoꢀwriteꢀBit4ꢀtoꢀchangeꢀpolicy

ꢀ Reservedꢀ

ꢀ ꢀ

ꢀ

Bits 0-1 are written to save a holdover history to the backup history, restore the active holdover history from the

backup, or ﬂush the active history. The default value of the register is 00. The last command is latched and

may be read by the application. A ﬂush does not affect the backup history. See Application Notes, Holdover

History Accumulation and Management section.

HoldOver_Time, 0x27 (R)

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ

Bitꢀ7ꢀ-ꢀBitꢀ0

IndicatesꢀtheꢀtimeꢀsinceꢀenteringꢀtheꢀHoldꢀOverꢀstate.ꢀfromꢀ0-255,ꢀoneꢀbitꢀperꢀhour.ꢀZeroꢀinꢀnon-HoldꢀOverꢀstateꢀandꢀstopsꢀatꢀ255.

Cfgdata, 0x30 (R/W)

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ

Bitꢀ7ꢀ-ꢀBitꢀ0

Conﬁgurationꢀdataꢀwriteꢀregister.

Conﬁguration data is written to this register. Internal use only.

Cfgctr_Lo, 0x31 (R)

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ

Bitꢀ7ꢀ-ꢀBitꢀ0

Conﬁgurationꢀdataꢀwriteꢀcounterꢀlowꢀbyte.ꢀ

Low order byte of conﬁguration data write counter. Internal use only.

SM3-8RG5 Data Sheet #: TM088 Page 17 of 32

Rev: 07 Date: 09/06/11

Register Descriptions and Operation continued

Cfgctr_Hi, 0x32 (R)

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ

Bitꢀ7ꢀ-ꢀBitꢀ0

Conﬁgurationꢀdataꢀwriteꢀcounterꢀhighꢀbyte.ꢀ

High order byte of conﬁguration data write counter. Internal use only.

Chksum, 0x33 (R/W)

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Bitꢀ7ꢀ-ꢀBitꢀ1ꢀ

ꢀ

ꢀꢀꢀBitꢀ0

ꢀ

ꢀ ꢀ

ꢀ

ꢀ ConﬁgurationꢀDataꢀChecksum

ꢀ pass/failꢀindicator

ꢀ

ꢀ ꢀ

ꢀ Reservedꢀ

ꢀ ꢀ

ꢀ

ꢀ 0:ꢀFailꢀ

ꢀ 1:ꢀPass

ꢀ ꢀ

ꢀ

Checksum veriﬁcation register for conﬁguration data. Internal use only.

EE_Mode, 0x36 (R/W)

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Bitꢀ7ꢀ-ꢀBitꢀ1ꢀ

ꢀ

Bitꢀ0

ꢀ

ꢀ ꢀ

ꢀ

ꢀ EEPROMꢀWriteꢀEnable

ꢀ 0:ꢀDisableꢀ

ꢀ 1:ꢀEnable

ꢀ

ꢀ ꢀ

ꢀ Reservedꢀ

ꢀ ꢀ

ꢀ

EEPROM write enable register.

EE_Cmd, 0x37 (R/W)

ꢀꢀꢀBitꢀ7ꢀꢀ

ꢀ

Bitꢀ6ꢀ-ꢀBitꢀ2ꢀ

ꢀ

Bitꢀ1ꢀ-ꢀBitꢀ0

EEPROMꢀread/writeꢀ

readyꢀbit:ꢀ ꢀ ꢀ

0ꢀ=ꢀNotꢀReadyꢀ ꢀ

1ꢀ=ꢀReadyꢀ ꢀ ꢀ

ꢀ ꢀ

ꢀ

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀEEPROMꢀread/writeꢀcommandꢀbits:

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ00ꢀ=ꢀResetꢀFIFO

ꢀ Reservedꢀ ꢀ ꢀ

ꢀ ꢀ

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ01ꢀ=ꢀWriteꢀCommandꢀ ꢀ ꢀ

ꢀ

ꢀ ꢀ

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ10ꢀ=ꢀReadꢀCommand

EEPROM read/write command register.

EE_Page_Num, 0x38 (R/W)

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ

Bitꢀ7ꢀ-ꢀBitꢀ0

EEPROMꢀread/writeꢀpageꢀnumber,ꢀ0x00ꢀtoꢀ0x9fꢀ(0ꢀ-ꢀ159)

EEPROM read/write page number register. EEPROM consist of 160 pages.

EE_FIFO_Port, 0x39 (R/W)

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ

Bitꢀ7ꢀ-ꢀBitꢀ0

EEPROMꢀread/writeꢀFIFOꢀdata.

EEPROM read/write FIFO port register. EEPROM data is written to/read from this location.

SM3-8RG5 Data Sheet #: TM088 Page 18 of 32

Rev: 07 Date: 09/06/11

Performance Speciﬁcations

Performance Deﬁnitions

Jitter and Wanderꢀ–ꢀJitterꢀandꢀwanderꢀareꢀdeﬁnedꢀrespectivelyꢀasꢀ“theꢀshort-termꢀandꢀlong-termꢀvariationsꢀofꢀtheꢀsigniﬁcantꢀ

instantsꢀofꢀaꢀdigitalꢀsignalꢀfromꢀtheirꢀidealꢀpositionsꢀinꢀtime”.ꢀTheyꢀareꢀthereforeꢀtheꢀphaseꢀorꢀpositionꢀinꢀtimeꢀmodulationsꢀofꢀaꢀdigitalꢀ

signalꢀrelativeꢀtoꢀtheirꢀidealꢀpositions.ꢀTheseꢀphaseꢀmodulationsꢀcanꢀinꢀturnꢀbeꢀcharacterizedꢀinꢀtermsꢀofꢀtheirꢀamplitudeꢀandꢀfrequency.ꢀ

Jitterꢀisꢀdeﬁnedꢀasꢀthoseꢀphaseꢀvariationsꢀatꢀratesꢀaboveꢀ10Hz,ꢀandꢀwanderꢀasꢀthoseꢀvariationsꢀatꢀratesꢀbelowꢀ10Hz.ꢀ

Fractional frequency offset and driftꢀ–ꢀTheꢀfractionalꢀfrequencyꢀoffsetꢀofꢀaꢀclockꢀisꢀtheꢀratioꢀofꢀtheꢀfrequencyꢀerrorꢀ(fromꢀtheꢀ

nominalꢀorꢀdesiredꢀfrequency)ꢀtoꢀtheꢀdesiredꢀfrequency.ꢀItꢀisꢀtypicallyꢀexpressedꢀasꢀ(nꢀpartsꢀinꢀ10^X),ꢀorꢀ(nꢀxꢀ10-^X).ꢀꢀDriftꢀisꢀtheꢀmeasureꢀ

ofꢀaꢀclock’sꢀfrequencyꢀoffsetꢀoverꢀtime.ꢀItꢀisꢀexpressedꢀtheꢀsameꢀwayꢀasꢀoffset.

Time Interval Error (TIE)ꢀ–ꢀTIEꢀisꢀaꢀmeasureꢀofꢀwanderꢀandꢀisꢀdeﬁnedꢀasꢀtheꢀvariationꢀinꢀtheꢀtimeꢀdelayꢀofꢀaꢀgivenꢀsignalꢀrelativeꢀ

toꢀanꢀidealꢀsignalꢀoverꢀaꢀparticularꢀtimeꢀperiod.ꢀItꢀisꢀtypicallyꢀmeasuredꢀinꢀns.ꢀTIEꢀisꢀsetꢀtoꢀzeroꢀatꢀtheꢀstartꢀofꢀaꢀmeasurement,ꢀandꢀthusꢀ

representsꢀtheꢀphaseꢀchangeꢀsinceꢀtheꢀbeginningꢀofꢀtheꢀmeasurement.

Maximum Time Interval Error (MTIE)ꢀ–ꢀMTIEꢀisꢀaꢀmeasurementꢀofꢀwanderꢀthatꢀﬁndsꢀtheꢀpeak-to-peakꢀvariationsꢀinꢀtheꢀtimeꢀdelayꢀ

ofꢀaꢀsignalꢀforꢀaꢀgivenꢀwindowꢀofꢀtime,ꢀcalledꢀtheꢀobservationꢀintervalꢀ(t).ꢀThereforeꢀitꢀisꢀtheꢀlargestꢀpeak-to-peakꢀTIEꢀinꢀanyꢀobservationꢀ

intervalꢀofꢀlengthꢀꢀt withinꢀtheꢀentireꢀmeasurementꢀwindowꢀofꢀTIEꢀdata.ꢀMTIEꢀisꢀthereforeꢀaꢀusefulꢀmeasureꢀofꢀphaseꢀtransients,ꢀ

maximumꢀwanderꢀandꢀfrequencyꢀoffsets.ꢀMTIEꢀincreasesꢀmonotonicallyꢀwithꢀincreasingꢀobservationꢀinterval.

Time Deviation (TDEV)ꢀ–ꢀTDEVꢀisꢀaꢀmeasurementꢀofꢀwanderꢀthatꢀcharacterizesꢀtheꢀspectralꢀcontentꢀofꢀphaseꢀnoise.ꢀTDEV(tꢀisꢀtheꢀ

RMSꢀofꢀﬁlteredꢀTIE,ꢀwhereꢀtheꢀbandpassꢀﬁlterꢀisꢀcenteredꢀonꢀaꢀfrequencyꢀofꢀ0.42/t.

SM3-8RG5 Performance

Input Jitter Toleranceꢀ–ꢀInputꢀjitterꢀtoleranceꢀisꢀtheꢀamountꢀofꢀjitterꢀatꢀitsꢀinputꢀaꢀclockꢀcanꢀtolerateꢀbeforeꢀgeneratingꢀanꢀindicationꢀ

ofꢀimproperꢀoperation.ꢀGR-1244ꢀandꢀITU-813ꢀrequirementsꢀspecifyꢀjitterꢀamplitudeꢀv.s.ꢀjitterꢀfrequencyꢀforꢀjitterꢀtolerance.ꢀTheꢀSM3-

8RG5ꢀdeviceꢀprovidesꢀjitterꢀtoleranceꢀthatꢀmeetsꢀtheꢀspeciﬁedꢀrequirements.

Input Wander Toleranceꢀ–ꢀInputꢀwanderꢀtoleranceꢀisꢀtheꢀamountꢀofꢀwanderꢀatꢀitsꢀinputꢀaꢀclockꢀcanꢀtolerateꢀbeforeꢀgeneratingꢀanꢀ

indicationꢀofꢀimproperꢀoperation.ꢀGR-1244ꢀandꢀITU-813ꢀrequirementsꢀspecifyꢀinputꢀwanderꢀTDEVꢀv.s.ꢀintegrationꢀtimeꢀasꢀshownꢀbelow.ꢀ

IntegrationꢀTime,ꢀ(seconds)ꢀ

ꢀ

TDEVꢀ(ns)

0.05ꢀ≤ꢀꢀτ <ꢀ10ꢀ

10ꢀ<ꢀτꢀ<ꢀ1000ꢀꢀ

ꢀ

100

31.6ꢀxꢀτ

0.5

1000ꢀꢀ≤ꢀꢀτꢀ

ꢀ

N/A

TheꢀSM3-8RG5ꢀdeviceꢀprovidesꢀwanderꢀtoleranceꢀthatꢀmeetsꢀtheseꢀrequirements.

Phase Transient Toleranceꢀ–ꢀGR-1244ꢀspeciﬁesꢀmaximumꢀreferenceꢀinputꢀphaseꢀtransientsꢀthatꢀaꢀclockꢀsystemꢀmustꢀtolerateꢀ

withoutꢀgeneratingꢀanꢀindicationꢀofꢀimproperꢀoperation.ꢀTheꢀphaseꢀtransientꢀtoleranceꢀisꢀspeciﬁedꢀinꢀMTIE(nS)ꢀv.s.ꢀobservationꢀtimeꢀ

fromꢀ.001ꢀtoꢀ100ꢀseconds,ꢀasꢀshownꢀbelow.

ObservationꢀtimeꢀSꢀ(Seconds)ꢀ

ꢀ

MTIEꢀ(ns)

61,000ꢀxꢀS

925ꢀ+ꢀ4600ꢀxꢀS

10,000

0.001326ꢀ≤ꢀSꢀ<ꢀꢀ0.0164ꢀ

ꢀ

0.0164ꢀ<ꢀSꢀ<ꢀ1.97ꢀ

1.97ꢀ≤ꢀSꢀ

ꢀ

ꢀTheꢀSM3-8RG5ꢀwillꢀtolerateꢀallꢀreferenceꢀinputꢀtransientsꢀwithinꢀtheꢀGR-1244ꢀspeciﬁcation.

Free-run Frequency Accuracyꢀ–ꢀTheꢀabilityꢀofꢀaꢀclockꢀtoꢀproduceꢀaꢀfrequencyꢀasꢀcloseꢀasꢀpossibleꢀtoꢀtheꢀnominalꢀfrequencyꢀinꢀ

theꢀabsenceꢀofꢀaꢀreference.ꢀꢀ

Hold Over Frequency Stabilityꢀ–ꢀAꢀmeasureꢀofꢀaꢀclock’sꢀperformanceꢀwhileꢀinꢀHoldꢀOverꢀmodeꢀoverꢀ24ꢀhours,ꢀsubjectedꢀtoꢀtheꢀ

speciﬁedꢀtemperatureꢀvariations.

SM3-8RG5 Data Sheet #: TM088 Page 19 of 32

Rev: 07 Date: 09/06/11

Performance Speciﬁcations continued

Wander Generationꢀ–ꢀWanderꢀgenerationꢀisꢀtheꢀprocessꢀwherebyꢀwanderꢀappearsꢀatꢀtheꢀoutputꢀofꢀaꢀclockꢀinꢀtheꢀabsenceꢀofꢀinputꢀ

wander.ꢀTheꢀSM3-8RG5ꢀwanderꢀgenerationꢀcharacteristics,ꢀMTIEꢀandꢀTDEV,ꢀareꢀshownꢀbelow,ꢀalongꢀwithꢀtheꢀrequirementsꢀmasksꢀ

(bandwidthꢀ=ꢀ0.098ꢀHz):

Wander Generation Characteristics – MTIE

Wander Generation Characteristics – TDEV

SM3-8RG5 Data Sheet #: TM088 Page 20 of 32

Rev: 07 Date: 09/06/11

Performance Speciﬁcations continued

Wander Transferꢀ–ꢀWanderꢀtransferꢀisꢀtheꢀdegreeꢀtoꢀwhichꢀinputꢀwanderꢀisꢀattenuatedꢀ(orꢀampliﬁed)ꢀfromꢀinputꢀtoꢀoutputꢀofꢀaꢀclock.ꢀ

TheꢀGR-1244ꢀrequirementsꢀforꢀwanderꢀtransferꢀlimitsꢀareꢀshownꢀbelow.

Integrationꢀtime,ꢀꢀτ (seconds)ꢀ

ꢀ

Stratumꢀ3ꢀTDEVꢀ(nanoseconds)

ꢀτ <ꢀ0.05ꢀ

ꢀ

N/A

1020ꢀxꢀτ

102

0.05ꢀ≤ꢀꢀτ <ꢀ0.1ꢀ

0.1ꢀꢀ≤ τ <ꢀ1.44ꢀ

1.44ꢀꢀ≤ꢀτꢀ<ꢀ10ꢀ

10ꢀꢀ≤ꢀτꢀ<ꢀ300ꢀꢀ

300ꢀꢀ≤ꢀτꢀꢀ≤ꢀ1000ꢀ

102

0.5

32.2ꢀxꢀꢀτ

0.5

32.2ꢀxꢀꢀτ

1000ꢀ<ꢀτꢀ

ꢀ

N/A

TheꢀSM3-8RG5,ꢀwhenꢀconﬁguredꢀforꢀtheꢀappropriateꢀStratumꢀ3ꢀbandwidthꢀfrequency,ꢀmeetsꢀtheꢀStratumꢀ3ꢀrequirements,

Jitter Generationꢀ–ꢀJitterꢀgenerationꢀisꢀtheꢀprocessꢀwherebyꢀjitterꢀappearsꢀatꢀtheꢀoutputꢀofꢀaꢀclockꢀinꢀtheꢀabsenceꢀofꢀinputꢀjitter.

Theꢀdeviceꢀjitterꢀgenerationꢀperformanceꢀisꢀasꢀshownꢀbelow:

Jitterꢀ ꢀ

ꢀ ꢀ

ꢀ

ꢀ ꢀ

19.44ꢀMHzꢀ

ꢀ 77.76ꢀMHz

Broadbandꢀ ꢀ

(10ꢀHzꢀ-ꢀ2ꢀMHz)ꢀ

SONETꢀBandꢀꢀ

ꢀ

ꢀ ꢀ

8ꢀpsꢀTypicalꢀꢀ

ꢀ 8ꢀpsꢀTypicalꢀ

ꢀ

ꢀ ꢀ

(12ꢀkHzꢀ-2MHz)ꢀ

1ꢀpsꢀTypicalꢀꢀ

ꢀ (12ꢀkHzꢀ-20MHz)

ꢀ <1ꢀpsꢀTypical

ꢀ ꢀ

ꢀ

Jitter Transferꢀ–ꢀJitterꢀtransferꢀisꢀtheꢀdegreeꢀtoꢀwhichꢀinputꢀjitterꢀisꢀattenuatedꢀ(orꢀampliﬁed)ꢀfromꢀinputꢀtoꢀoutputꢀofꢀaꢀclock.ꢀItꢀisꢀaꢀ

functionꢀofꢀtheꢀselectedꢀbandwidth.ꢀTheꢀSM3-8RG5ꢀjitterꢀtransferꢀcharacteristicsꢀareꢀshownꢀbelow:

Phase Transientsꢀ–ꢀAꢀphaseꢀtransientꢀisꢀanꢀunusualꢀstepꢀorꢀchangeꢀinꢀtheꢀphase-timeꢀofꢀaꢀsignalꢀoverꢀaꢀrelativelyꢀshortꢀtimeꢀ

period.ꢀThisꢀmayꢀbeꢀdueꢀtoꢀswitchingꢀbetweenꢀequipment,ꢀreferenceꢀswitching,ꢀdiagnostics,ꢀentryꢀorꢀexitꢀto/fromꢀHoldꢀOver,ꢀorꢀinputꢀ

referenceꢀtransients.ꢀTheꢀSM3-8RG5ꢀperformanceꢀforꢀreferenceꢀswitchesꢀisꢀshownꢀbelow:

Phase Transients – MITE

SM3-8RG5 Data Sheet #: TM088 Page 21 of 32

Rev: 07 Date: 09/06/11

Performance Speciﬁcations continued

Capture range and Lock rangeꢀ–ꢀCaptureꢀrangeꢀandꢀlockꢀrangeꢀareꢀtheꢀmaximumꢀfrequencyꢀerrorsꢀonꢀtheꢀreferenceꢀinputꢀwithinꢀ

whichꢀtheꢀphaseꢀlockedꢀloopꢀisꢀableꢀtoꢀachieveꢀlockꢀandꢀholdꢀlock,ꢀrespectively.ꢀTheꢀSM3-8RG5ꢀStratumꢀ3ꢀperformanceꢀisꢀshownꢀ

below:

Characteristicꢀ

Captureꢀrangeꢀ

ꢀ

SM3-8RG5ꢀ ꢀ

ꢀ25.5ꢀppmꢀmaximumꢀ

ꢀ

Requirement

GR-1244-CORE,ꢀSecꢀ3.4

Holdꢀrangeꢀ

ꢀ

Thisꢀisꢀtheꢀminimumꢀcapability,ꢀandꢀguaranteesꢀtheꢀabilityꢀtoꢀcaptureꢀandꢀlockꢀwithꢀaꢀreferenceꢀthatꢀisꢀoffsetꢀtheꢀmaximumꢀallowedꢀinꢀ

oneꢀdirectionꢀinꢀtheꢀpresenceꢀofꢀaꢀclockꢀthatꢀisꢀoffsetꢀtheꢀmaximumꢀinꢀtheꢀoppositeꢀdirectionꢀ(4.6ꢀppmꢀ+ꢀ4.6ꢀppmꢀ=ꢀ9.2ꢀppm).

Master/Slave Skew and Reference switch settling time–ꢀMaster/SlaveꢀSkewꢀandꢀReferenceꢀswitchꢀsettlingꢀtimeꢀperformanceꢀ

areꢀshownꢀbelow:ꢀ

Characteristicꢀ

SM3-8RG5ꢀ

ꢀ

Requirement

Master/Slaveꢀphaseꢀskewꢀ

<ꢀ2ꢀnSꢀꢀ

ꢀ

N/A

Referenceꢀswitchꢀsettlingꢀtimeꢀ

Stratumꢀ3:ꢀ<ꢀ100ꢀsec.ꢀupꢀtoꢀ20ꢀppmꢀꢀ

frequencyꢀoffsetꢀ

ꢀ

Stratumꢀ3:ꢀ<ꢀ100ꢀsec.ꢀupꢀꢀ

toꢀ+/-ꢀ4.6ꢀppmꢀfrequencyꢀoffset

ꢀ

ꢀꢀꢀ

ꢀ

SM3-8RG5 Initialization:

Power-up:

1.ꢀIfꢀpossible,ꢀalwaysꢀstartꢀupꢀinꢀmasterꢀmode.ꢀꢀAfterꢀtheꢀmoduleꢀisꢀpoweredꢀup,ꢀholdꢀtheꢀresetꢀpinꢀlowꢀforꢀ10ms.ꢀWaitꢀ1200msꢀandꢀreadꢀ

theꢀcontentsꢀofꢀregisterꢀ0x33.ꢀIfꢀitꢀreads1ꢀthenꢀtheꢀmoduleꢀcameꢀupꢀproperly.ꢀIfꢀitꢀreadsꢀ0ꢀthenꢀresetꢀtheꢀmoduleꢀandꢀre-readꢀregisterꢀ

0x33ꢀafterꢀ1200ms.ꢀTheꢀcontentsꢀofꢀ0x33ꢀmustꢀreadꢀ1ꢀbeforeꢀcontinuing.ꢀ

2.ꢀRemainꢀinꢀtheꢀdefaultꢀfree-runꢀmodeꢀforꢀ10ꢀsecondsꢀthenꢀreadꢀtheꢀvalueꢀofꢀbitꢀ1ꢀofꢀregisterꢀ0x11ꢀorꢀpinꢀ2,ꢀtheꢀLOLꢀalarmꢀoutput.ꢀꢀIfꢀ

theꢀLOLꢀalarmꢀisꢀset,ꢀtheꢀresetꢀpinꢀmustꢀbeꢀpulledꢀlowꢀasꢀinꢀ1ꢀabove.ꢀꢀInꢀtheꢀfree-runꢀmodeꢀtheꢀLOLꢀalarmꢀshouldꢀneverꢀbeꢀset.ꢀꢀThisꢀ

indicatesꢀtheꢀmoduleꢀisꢀinꢀanꢀinvalidꢀstate.ꢀꢀIfꢀthereꢀisꢀnoꢀLOLꢀalarmꢀinꢀfree-runꢀtheꢀmoduleꢀisꢀready.

Operation:

Onꢀpowerꢀupꢀorꢀafterꢀaꢀresetꢀallꢀtheꢀregistersꢀareꢀloadedꢀwithꢀtheirꢀdefaultꢀvalues.ꢀTheꢀdefaultꢀvaluesꢀofꢀsomeꢀimportantꢀregistersꢀareꢀ

givenꢀbelowꢀassumingꢀtheꢀmoduleꢀoperatesꢀasꢀaꢀMasterꢀ

Address(Hex)ꢀꢀꢀꢀꢀꢀ

Register Nameꢀ ꢀ

ꢀ

ꢀꢀꢀ

ꢀ

Value(Binary MSB ﬁrst)ꢀ ꢀ

Notes

00000111ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Bandwidthꢀ=ꢀ0.098Hz

0000r010ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ rꢀ-ꢀReadꢀOnly

0x03ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

0x04ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

0x05ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

0x06ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

0x0bꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

0x0dꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

0x0eꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

0x0fꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

0x11ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

0x13ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

0x1c-0x23ꢀꢀꢀꢀꢀꢀꢀꢀꢀ

0x33ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ

Bandwidth_PBOꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Ctl_Modeꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Op_Modeꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Max_Pullin_Rangeꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Ref_Maskꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Ref_Rev_Delayꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Phase_Offsetꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Calibrationꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ

00010000ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ IndicatesꢀFreeꢀRunꢀmode

01100100ꢀꢀ

00000000

00000101

00000000ꢀ

00000000

00000000ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ IndicatesꢀNoꢀActiveꢀReference

00000000ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ IndicatesꢀInterruptsꢀareꢀdisabled

xxxx0000ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

xxxxxxx1ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

DPLL_Statusꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Intr_Enableꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

Ref(1-8)_Frq_Priorityꢀꢀꢀꢀ

ꢀ

ꢀꢀ

Frequenciesꢀareꢀautoꢀdetectedꢀ

Bit0ꢀshouldꢀbeꢀhighꢀtoꢀindicateꢀthatꢀꢀ

dataꢀhasꢀbeenꢀloadedꢀꢀ

Chksumꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ꢀ

ꢀ

ꢀꢀꢀꢀꢀꢀꢀꢀꢀ correctlyꢀfromꢀtheꢀEEPROM.

SM3-8RG5 Data Sheet #: TM088 Page 22 of 32

Rev: 07 Date: 09/06/11

SM3G Initialization continued

I.ꢀꢀTheꢀunitꢀstartsꢀupꢀinꢀFreeꢀRunꢀandꢀoperatesꢀinꢀManualꢀmode.ꢀHereꢀareꢀtheꢀstepsꢀthatꢀneedꢀtoꢀbeꢀtakenꢀtoꢀlockꢀtheꢀunitꢀtoꢀaꢀꢀ ꢀ

referenceꢀinꢀManualꢀmode.

ꢀ

1.ꢀ Applyꢀsignalꢀtoꢀtheꢀreferenceꢀinputs.

2.ꢀꢀ Setꢀtheꢀappropriateꢀpullꢀinꢀrangeꢀbyꢀwritingꢀtoꢀaddressꢀ0x06.

3.ꢀꢀ Aꢀvalueꢀofꢀ0001xxxx,ꢀdependingꢀonꢀwhichꢀ(Refꢀ1-8)ꢀreferenceꢀtoꢀlockꢀto,ꢀshouldꢀbeꢀwrittenꢀtoꢀaddressꢀ0x05.

4.ꢀꢀ EnableꢀReferenceꢀmaskꢀforꢀappropriateꢀreferencesꢀbyꢀwritingꢀaꢀ1ꢀtoꢀtheꢀreferenceꢀbitꢀinꢀaddressꢀ0x0b.

5.ꢀꢀ EnableꢀallꢀInterruptsꢀbyꢀwritingꢀ11111111ꢀtoꢀaddressꢀ0x13.ꢀ

II.ꢀꢀToꢀlockꢀtheꢀunitꢀtoꢀaꢀreferenceꢀinꢀautonomousꢀ(automatic)ꢀmodeꢀafterꢀpowerꢀupꢀorꢀreset,ꢀtheꢀfollowingꢀstepsꢀshouldꢀbeꢀtaken.ꢀ

YouꢀcanꢀalsoꢀswitchꢀfromꢀManualꢀtoꢀAutonomousꢀmodeꢀdirectly.ꢀWhenꢀdoingꢀso,ꢀpleaseꢀensureꢀthatꢀtheꢀappropriateꢀreferencesꢀareꢀ

availableꢀbyꢀcheckingꢀREF_AVAILABLEꢀregisterꢀ(address:ꢀ0x0c).

ꢀ

1.ꢀ Clearꢀbit1ꢀofꢀCTL_MODEꢀregisterꢀ(address:ꢀ0x04).ꢀThisꢀputsꢀtheꢀmoduleꢀinꢀautonomousꢀmode.

2.ꢀ Applyꢀsignalꢀtoꢀtheꢀreferenceꢀinputs

3.ꢀ Setꢀtheꢀappropriateꢀpullꢀinꢀrangeꢀbyꢀwritingꢀtoꢀaddressꢀ0x06

4.ꢀ EnableꢀReferenceꢀmaskꢀforꢀappropriateꢀreferencesꢀbyꢀwritingꢀaꢀ1ꢀtoꢀtheꢀreferenceꢀbitꢀinꢀaddressꢀ0x0b.

5.ꢀ SetꢀpriorityꢀandꢀrevertivityꢀforꢀtheꢀinputꢀreferencesꢀbyꢀwritingꢀtoꢀtheꢀappropriateꢀRef_Frq_Priorityꢀꢀregistersꢀ(bitsꢀ3-0).ꢀ

6.ꢀꢀꢀꢀ EnableꢀallꢀInterruptsꢀbyꢀwritingꢀ11111111ꢀtoꢀaddressꢀ0x13.

7.ꢀꢀꢀ Setꢀtheꢀunitꢀtoꢀoperateꢀinꢀautonomousꢀmodeꢀbyꢀclearingꢀbit1ꢀofꢀaddressꢀ0x04

III.ꢀꢀꢀꢀSlaveꢀModeꢀOperation:ꢀ

ꢀ

1.ꢀ AsꢀaꢀSlave,ꢀtheꢀmoduleꢀoperatesꢀinꢀAutonomousꢀmode.ꢀ

2.ꢀ TheꢀBandwidthꢀisꢀset,ꢀbyꢀdefault,ꢀtoꢀ1.6Hzꢀ(Bandwidth_PBOꢀregisterꢀ(Addressꢀ0x03):ꢀ00001011).ꢀ

3.ꢀ NoteꢀthatꢀBitꢀ4ꢀofꢀtheꢀOP_MODEꢀregisterꢀ(Addressꢀ0x05)ꢀisꢀcleared.ꢀ

4.ꢀ TheꢀvaluesꢀinꢀBitsꢀ3-0ꢀofꢀthisꢀregisterꢀhaveꢀnoꢀeffectꢀonꢀtheꢀoperationꢀofꢀtheꢀSlaveꢀmodule.ꢀ

5.ꢀ ForꢀtheꢀSlaveꢀmoduleꢀtoꢀtrackꢀtheꢀMasterꢀaccurately,ꢀanꢀappropriateꢀPhaseꢀOffsetꢀvalueꢀshouldꢀbeꢀwrittenꢀtoꢀꢀꢀ

ꢀ

PHASE_OFFSETꢀregisterꢀ(Addressꢀ0x0e)ꢀisꢀusedꢀtoꢀcompensateꢀforꢀtheꢀpathꢀdelay.ꢀꢀ

6.ꢀ TheꢀmoduleꢀwillꢀlockꢀtoꢀtheꢀCrossꢀReferenceꢀInputꢀ(XREF)ꢀfromꢀtheꢀmaster.

IVꢀꢀꢀRESETꢀParameters:

ꢀ

1.ꢀ Theꢀresetꢀpinꢀshouldꢀbeꢀheldꢀlowꢀforꢀaꢀminimumꢀofꢀ10ꢀmillisecondsꢀtoꢀensureꢀaꢀcompleteꢀresetꢀoccurs.

2.ꢀꢀꢀ TheꢀSPIꢀinterfaceꢀshouldꢀnotꢀbeꢀaccessedꢀforꢀaꢀminimumꢀofꢀ1200msꢀafterꢀtheꢀresetꢀpinꢀisꢀde-asserted.

Switching Master/Slave designations:

TheꢀfollowingꢀstepsꢀneedꢀtoꢀbeꢀtakenꢀbeforeꢀmakingꢀMasterꢀmoduleꢀaꢀSlaveꢀandꢀviceꢀversa.

ꢀ

1.ꢀꢀ CopyꢀtheꢀvalueꢀinꢀtheꢀPHASE_OFFSETꢀregisterꢀ(Addressꢀ0x0e)ꢀofꢀtheꢀSlaveꢀtoꢀtheꢀMasterꢀmodule’sꢀPHASE_OFFSETꢀꢀ

regsiterꢀ(Addressꢀ0x0e).

2.ꢀꢀ ReadꢀtheꢀcontentsꢀofꢀBitsꢀ3-0ꢀofꢀtheꢀMaster’sꢀOP_MODEꢀregisterꢀ(Addressꢀ0x05)ꢀandꢀcopyꢀitꢀintoꢀBitsꢀ3-0ꢀofꢀtheꢀSlave’sꢀꢀ

OP_MODEꢀregisterꢀ(Addressꢀ0x05).

3.ꢀꢀ ItꢀisꢀrecommendedꢀthatꢀtheꢀcontentsꢀofꢀREF(1-8)_FRQ_PRIORITYꢀregistersꢀ(Addressꢀ0x1c-0x23)ꢀandꢀREF_MASKꢀ

ꢀ

registerꢀ(Addressꢀ0x0b)ꢀfromꢀMasterꢀbeꢀcopiedꢀtoꢀSlaveꢀtoꢀensureꢀseamlessꢀMaster/Slaveꢀswitches.ꢀꢀMaster/Slaveꢀꢀ

switchesꢀshouldꢀbeꢀperformedꢀwithꢀminimalꢀdelayꢀbetweenꢀswitchingꢀtheꢀstatesꢀofꢀeachꢀofꢀtheꢀtwoꢀdevices.

ꢀ

SM3-8RG5 Data Sheet #: TM088 Page 23 of 32

Rev: 07 Date: 09/06/11

Application Notes

ꢀ

Acceptableꢀoutputꢀfrequenciesꢀare:ꢀ12.96ꢀMHz,ꢀ19.44ꢀMHz,ꢀ25.92ꢀMHz,ꢀ38.88ꢀMHz,ꢀ51.84ꢀMHzꢀorꢀ77.76MHz.ꢀTheꢀdeviceꢀwillꢀꢀ

autodetectꢀtheꢀoutputꢀfrequency.

Reference Inputsꢀ–ꢀTheꢀapplicationꢀmayꢀsupplyꢀupꢀtoꢀ8ꢀreferenceꢀinputs,ꢀappliedꢀatꢀinputꢀpinsꢀRef1 - 8.ꢀTheyꢀmayꢀeachꢀbeꢀ8ꢀkHz,ꢀ

1.544ꢀMHz,ꢀ2.048ꢀMHz,ꢀ12.96ꢀMHz,ꢀ19.44ꢀMHz,ꢀ25.92ꢀMHz,ꢀ38.88ꢀMHz,ꢀ51.84ꢀMHzꢀorꢀ77.76ꢀMHz.ꢀTheꢀdeviceꢀauto-detectsꢀtheꢀ

referenceꢀfrequencies,ꢀandꢀtheyꢀmayꢀbeꢀreadꢀfromꢀtheꢀRef(1-8)_Frq_Priorityꢀregistersꢀinꢀregisterꢀcontrolꢀmode,ꢀasꢀdescribedꢀinꢀtheꢀ

controlꢀmodeꢀsectionsꢀthatꢀfollow.

ꢀ

Referenceꢀswitchesꢀareꢀperformedꢀinꢀaꢀhitlessꢀmanner.ꢀꢀHowever,ꢀifꢀtheꢀapplicationꢀexternallyꢀchangesꢀtheꢀfrequencyꢀofꢀaꢀparticularꢀ

reference,ꢀtheꢀdeviceꢀrequiresꢀ20msꢀtoꢀauto-detectꢀtheꢀnewꢀfrequency.ꢀꢀManualꢀswitchesꢀtoꢀaꢀfrequencyꢀchangedꢀreferenceꢀshouldꢀnotꢀ

beꢀmadeꢀduringꢀthisꢀinterval.ꢀꢀAutomaticꢀreferenceꢀselectionꢀmodeꢀaccountsꢀforꢀtheꢀauto-detectionꢀinꢀtheꢀreferenceꢀqualiﬁcation.

ꢀ

Referencesꢀwouldꢀtypicallyꢀ(butꢀneedꢀnotꢀbe)ꢀconnectedꢀinꢀdecreasingꢀorderꢀofꢀusageꢀpriority.ꢀForꢀexampleꢀifꢀredundantꢀBITSꢀclocksꢀ

areꢀavailable,ꢀtheyꢀwouldꢀtypicallyꢀbeꢀassignedꢀtoꢀRef1 andꢀRef2,ꢀwithꢀotherꢀtransmissionꢀderivedꢀsignalsꢀfollowingꢀthereafter.

Master/Slave operationꢀ–ꢀForꢀsomeꢀapplications,ꢀreliabilityꢀrequirementsꢀmayꢀdemandꢀthatꢀtheꢀclockꢀsystemꢀbeꢀduplicated.ꢀTheꢀ

SM3-8RG5ꢀdeviceꢀwillꢀsupportꢀtheꢀmaster/slaveꢀduplicatedꢀconﬁgurationꢀforꢀsuchꢀapplications.ꢀToꢀfacilitateꢀit’sꢀuse,ꢀtheꢀdeviceꢀincludesꢀ

theꢀnecessaryꢀsignalꢀcrossꢀcouplingꢀandꢀcontrolꢀfunctions.ꢀRedundancyꢀforꢀreliabilityꢀimpliesꢀtwoꢀmajorꢀconsiderations:ꢀ1)ꢀMaintainingꢀ

separateꢀfailureꢀgroupsꢀsuchꢀthatꢀaꢀfailureꢀinꢀoneꢀgroupꢀdoesꢀnotꢀaffectꢀit’sꢀmate,ꢀandꢀ2)ꢀPhysicalꢀandꢀlogicalꢀpartitioningꢀforꢀrepair,ꢀ

suchꢀthatꢀaꢀfailedꢀcomponentꢀcanꢀbeꢀreplacedꢀwhileꢀtheꢀmateꢀremainsꢀinꢀservice,ꢀifꢀsoꢀdesired.ꢀSystemꢀdesignꢀneedsꢀtoꢀaccountꢀtoꢀ

meetꢀsystemꢀlevelꢀgoals.

Master / Slave Conﬁguration

Figure 8

SM3-8RG5

REF 1

REF1

1

BITS clock output

Synchronized clock output

8 kHz

BITS_CLK

REF 8

^RES^F8TC3500

OUTPUT1

M/S_OUT

M/S REF

M/S REF M/S_OUT

OUTPUT1

8 kHz

Synchronized clock output

BITS clock output

BITS_CLK

REF1

SM3-8RG5

REF8

2

SM3-8RG5 Data Sheet #: TM088 Page 24 of 32

Rev: 07 Date: 09/06/11

Application Notes continued

Master/Slave Conﬁgurationꢀ–ꢀAꢀpairꢀofꢀdevicesꢀareꢀinterconnectedꢀbyꢀcross-couplingꢀtheirꢀrespectiveꢀM/S Outputs orꢀꢀ

Output1ꢀꢀtoꢀtheꢀotherꢀdevice’sꢀM/S REFꢀinputꢀ(SeeꢀFigureꢀ8).ꢀAdditionally,ꢀtheꢀreferenceꢀinputsꢀforꢀeachꢀdeviceꢀwouldꢀtypicallyꢀbeꢀ

correspondinglyꢀtheꢀsame,ꢀsoꢀthatꢀwhenꢀaꢀMaster/Slaveꢀswitchꢀoccurs,ꢀsynchronizationꢀwouldꢀcontinueꢀwithꢀtheꢀsameꢀreference.ꢀTheꢀ

referencesꢀmayꢀbeꢀdrivenꢀbyꢀtheꢀsameꢀsignalꢀdirectlyꢀorꢀviaꢀseparateꢀdrivers,ꢀasꢀtheꢀredundancyꢀofꢀthatꢀpartꢀofꢀtheꢀsystemꢀrequires.ꢀ

Distributionꢀpathꢀlengthsꢀareꢀnotꢀcriticalꢀhere,ꢀasꢀaꢀphaseꢀbuild-outꢀwillꢀoccurꢀwhenꢀaꢀdeviceꢀswitchesꢀfromꢀslaveꢀtoꢀmaster.

ꢀ

TheꢀpathꢀlengthsꢀofꢀtheꢀtwoꢀM/SꢀOutputꢀtoꢀM/S REFꢀsignalsꢀisꢀofꢀinterest,ꢀhowever.ꢀTheyꢀneedꢀnotꢀbeꢀtheꢀsame.ꢀHowever,ꢀtoꢀ

accommodateꢀpathꢀlengthꢀdelays,ꢀtheꢀSM3-8RG5ꢀprovidesꢀaꢀprogrammableꢀphaseꢀskewꢀfeature,ꢀwhichꢀallowsꢀtheꢀapplicationꢀtoꢀ

offsetꢀtheꢀoutputꢀclockꢀfromꢀtheꢀcross-referenceꢀsignalꢀbyꢀꢀ-32nsꢀtoꢀ+31.75ns.ꢀThisꢀoffsetꢀmayꢀthereforeꢀbeꢀprogrammedꢀtoꢀexactlyꢀ

compensateꢀforꢀtheꢀactualꢀpathꢀlengthꢀdelayꢀassociatedꢀwithꢀtheꢀparticularꢀapplication’sꢀcross-referenceꢀtraces.ꢀTheꢀoffsetꢀmayꢀbeꢀ

furtherꢀadjustedꢀtoꢀaccommodateꢀanyꢀoutputꢀclockꢀdistributionꢀpathꢀdelayꢀdifferences.ꢀPhaseꢀoffsetꢀisꢀprogrammedꢀbyꢀwritingꢀtoꢀtheꢀ

Phase_Offsetꢀregister,ꢀandꢀisꢀtypicallyꢀaꢀone-timeꢀdeviceꢀinitializationꢀfunction.ꢀ(SeeꢀregisterꢀdescriptionꢀandꢀRegisterꢀAccessꢀControlꢀ

sections).ꢀThus,ꢀmaster/slaveꢀswitchesꢀwithꢀtheꢀSM3-8RG5ꢀdevicesꢀmayꢀbeꢀaccomplishedꢀwithꢀnear-zeroꢀphaseꢀhits.

ꢀ

ForꢀapplicationsꢀthatꢀuseꢀHardwareꢀControlꢀonlyꢀ(i.e.ꢀphaseꢀoffsetꢀprogrammingꢀisꢀnotꢀavailable),ꢀitꢀisꢀdesirableꢀtoꢀkeepꢀtheꢀcrossꢀ

coupleꢀpathꢀlengthsꢀatꢀaꢀminimumꢀandꢀrelativelyꢀequalꢀinꢀlength,ꢀasꢀtheꢀpathꢀlengthꢀwillꢀappearꢀasꢀaꢀphaseꢀhitꢀinꢀtheꢀslaveꢀclockꢀoutputꢀ

whenꢀaꢀmaster/slaveꢀswitchꢀoccursꢀinꢀaꢀHardwareꢀControlꢀconﬁguration.

Master/Slave Operation and Controlꢀ–ꢀTheꢀMaster/Slaveꢀstateꢀisꢀalwaysꢀmanuallyꢀcontrolledꢀbyꢀtheꢀapplication.ꢀMasterꢀorꢀslaveꢀ

stateꢀofꢀaꢀdeviceꢀisꢀdeterminedꢀbyꢀtheꢀMASTER SELECT pin.ꢀChoosingꢀtheꢀmaster/slaveꢀstatesꢀisꢀaꢀfunctionꢀofꢀtheꢀapplication,ꢀbasedꢀ

onꢀtheꢀconﬁgurationꢀofꢀtheꢀrestꢀofꢀtheꢀsystemꢀandꢀpotentialꢀdetectedꢀfaultꢀconditions.

ꢀ

WhenꢀoperatingꢀinꢀHardwareꢀControlꢀorꢀRegisterꢀAccessꢀManualꢀControlꢀmode,ꢀitꢀisꢀimportantꢀtoꢀsetꢀtheꢀslaveꢀreferenceꢀselectionꢀ

theꢀsameꢀasꢀtheꢀmasterꢀtoꢀensureꢀuseꢀofꢀtheꢀsameꢀreferenceꢀwhen/ifꢀtheꢀslaveꢀꢀbecomesꢀmaster.ꢀInꢀRegisterꢀAccessꢀManualꢀControlꢀ

mode,ꢀtheꢀRef_Maskꢀregisterꢀshouldꢀalsoꢀbeꢀwrittenꢀtoꢀtheꢀsameꢀvalueꢀforꢀbothꢀdevices.ꢀ

ꢀ

Master/slaveꢀswitchesꢀshouldꢀbeꢀperformedꢀwithꢀminimalꢀdelayꢀbetweenꢀswitchingꢀtheꢀstatesꢀofꢀeachꢀofꢀtheꢀtwoꢀdevices.ꢀThisꢀcanꢀ

beꢀeasilyꢀaccomplished,ꢀforꢀexample,ꢀbyꢀcontrollingꢀtheꢀmaster/slaveꢀstateꢀwithꢀaꢀsingleꢀsignal,ꢀcoupledꢀtoꢀoneꢀofꢀtheꢀdevicesꢀthroughꢀ

anꢀinverter.ꢀꢀ

ꢀ

InꢀtheꢀcaseꢀofꢀRegisterꢀAccessꢀAutomaticꢀControlꢀmode,ꢀwhereꢀreferenceꢀselectionꢀisꢀautomatic,ꢀitꢀisꢀnecessaryꢀtoꢀreadꢀtheꢀ

operationalꢀmodeꢀBITSꢀ3-0)ꢀfromꢀtheꢀmaster’sꢀOp_Modeꢀregisterꢀandꢀwriteꢀitꢀtoꢀtheꢀslave’sꢀOp_Modeꢀregister.ꢀꢀTheꢀmaster’sꢀreferenceꢀ

selectionꢀwillꢀthenꢀbeꢀusedꢀbyꢀtheꢀslaveꢀwhenꢀitꢀbecomesꢀmaster.ꢀInꢀadditionꢀtoꢀhavingꢀtheꢀreferencesꢀpopulatedꢀtheꢀsame,ꢀandꢀinꢀtheꢀ

sameꢀorderꢀforꢀbothꢀdevices,ꢀitꢀisꢀdesireableꢀtoꢀwriteꢀtheꢀreferenceꢀfrequencyꢀandꢀpriorityꢀregistersꢀRef(1-8)_Frq_Priorityꢀandꢀtheꢀ

Ref_Maskꢀregistersꢀtoꢀtheꢀsameꢀvaluesꢀforꢀbothꢀdevicesꢀtoꢀensureꢀseamlessꢀmaster/slaveꢀswitches.

Resetꢀ–ꢀDeviceꢀresetꢀisꢀanꢀinitializationꢀtimeꢀfunction,ꢀwhichꢀresetsꢀinternalꢀlogicꢀandꢀregisterꢀvalues.ꢀAꢀresetꢀisꢀperformedꢀ

automaticallyꢀwhenꢀtheꢀdeviceꢀisꢀpoweredꢀup.ꢀRegistersꢀreturnꢀtoꢀtheirꢀdefaultꢀvalues,ꢀasꢀnotedꢀinꢀtheꢀregisterꢀdescriptions.ꢀDeviceꢀ

modeꢀandꢀfunctionalityꢀfollowingꢀaꢀresetꢀareꢀdeterminedꢀbyꢀtheꢀstateꢀofꢀtheꢀvariousꢀhardwareꢀcontrolꢀpins.

Holdover History Accumulation and Maintenance -- Holdoverꢀhistoryꢀaccumulationꢀandꢀmaintenanceꢀmayꢀbeꢀcontrolledꢀinꢀ

greaterꢀdetailꢀifꢀregisterꢀbusꢀaccessꢀtoꢀtheꢀdeviceꢀisꢀprovided.ꢀHoldoverꢀhistoryꢀaccumulationꢀandꢀcontrolꢀencompassesꢀthreeꢀdeviceꢀ

internalꢀregisters,ꢀthreeꢀbusꢀaccessꢀregistersꢀforꢀcontrolꢀandꢀaccess,ꢀandꢀtwoꢀstatusꢀbitsꢀinꢀtheꢀDPLL_Statusꢀregister.

Hold Over History

Active

Accumulation Register

Hold Over History

Backup

Hold Over History

Onceꢀlockꢀhasꢀbeenꢀachieved,ꢀholdoverꢀhistoryꢀisꢀcompiledꢀinꢀtheꢀaccumulationꢀregister.ꢀItꢀisꢀtransferredꢀtoꢀtheꢀActiveꢀholdoverꢀhistoryꢀ

whenꢀitꢀisꢀreadyꢀ(typicallyꢀinꢀaboutꢀ15ꢀminutes).ꢀTheꢀ“HoldoverꢀAvailable”ꢀbitꢀandꢀoutputꢀpinꢀareꢀsetꢀtoꢀ“1”.ꢀFromꢀthenꢀon,ꢀtheꢀActiveꢀ

holdoverꢀhistoryꢀisꢀcontinuallyꢀupdatedꢀandꢀkeptꢀinꢀsyncꢀwithꢀtheꢀholdoverꢀhistoryꢀaccumulationꢀregister.ꢀ(SeeꢀFigureꢀ11).

SM3-8RG5 Data Sheet #: TM088 Page 25 of 32

Rev: 07 Date: 09/06/11

Application Notes continued

Hold Over History access and Control Registers

Table 5

Register

0x25ꢀ

0x26ꢀ

0x27ꢀ

0x11ꢀ

Register Name

History_Policyꢀ

History_Cmdꢀ

Holdover_Timeꢀ

DPLL_Statusꢀ

Description

SetsꢀpolicyꢀforꢀHoldꢀOverꢀhistoryꢀaccumulation:ꢀ“Rebuild”ꢀorꢀ“Continue”

Save,ꢀrestore,ꢀandꢀﬂushꢀcommandsꢀforꢀHoldꢀOverꢀhistoryꢀ

IndicatesꢀtheꢀtimeꢀsinceꢀenteringꢀtheꢀHoldꢀOverꢀstateꢀ

Bitsꢀ3ꢀandꢀ4:ꢀHoldꢀOverꢀAvailable”ꢀandꢀ“HoldꢀOverꢀBuildꢀComplete”ꢀ

Hold Over History and Status States

Figure 9

Flush

Reference Switch

Acquire Reference

Hold Control = 0

Hold Available = 0

Reference Lock

Reference Switch

Flush

Build History

Hold Control = 0

Hold Available = 0

Flush

History Build Complete

Locked, History

Complete

Hold Control =1

Hold Available = 1

Reference Lock

(with "Continue" set)

Reference Switch

History Build

Complete,

Replace Active

Acquire Reference

Hold Control = 0

Reference Switch

Hold Available = 1

Hold Over History

Reference Lock

(with "Rebuild" set)

Build History

Hold Control = 0

Hold Available = 1

History Restored from backup,

re-start the building procedure.

SM3-8RG5 Data Sheet #: TM088 Page 26 of 32

Rev: 07 Date: 09/06/11

Application Notes continued

Holdover History Accumulation and Maintenance continued –ꢀWheneverꢀholdoverꢀisꢀentered,ꢀitꢀisꢀtheꢀActiveꢀHoldoverꢀHistoryꢀ

thatꢀisꢀusedꢀtoꢀdetermineꢀtheꢀholdoverꢀfrequency.ꢀꢀTheꢀHistory_Cmdꢀregisterꢀallowsꢀtheꢀapplicationꢀtoꢀissueꢀthreeꢀholdoverꢀhistoryꢀ

controlꢀcommands:

ꢀ

1)ꢀSaveꢀtheꢀActiveꢀHoldoverꢀHistoryꢀtoꢀtheꢀBackupꢀHistory.

2)ꢀRestoreꢀaꢀBackupꢀHistoryꢀtoꢀtheꢀActive.

3)ꢀFlushꢀtheꢀactiveꢀHistoryꢀasꢀwellꢀasꢀtheꢀaccumulationꢀregister.ꢀTheꢀBackupꢀhistoryꢀremainsꢀintact.

BothꢀtheꢀActiveꢀandꢀtheꢀBackupꢀholdoverꢀhistoriesꢀareꢀloadedꢀwithꢀtheꢀcalibratedꢀfreerunꢀsynthesizerꢀcontrolꢀdataꢀonꢀreset/power-up.

Theꢀapplicationꢀmightꢀuseꢀtheꢀ“saveꢀtoꢀbackup”ꢀinꢀaꢀsituationꢀwhere,ꢀforꢀexample,ꢀtheꢀprimaryꢀreferenceꢀisꢀknownꢀtoꢀbeꢀofꢀhigherꢀ

ꢀ

qualityꢀthanꢀanyꢀsecondaryꢀreferences,ꢀinꢀwhichꢀcaseꢀitꢀmayꢀbeꢀdesirableꢀtoꢀsaveꢀandꢀthenꢀrestoreꢀtheꢀholdoverꢀhistoryꢀaccumulatedꢀ

onꢀtheꢀprimaryꢀreferenceꢀifꢀtheꢀprimaryꢀreferenceꢀisꢀlostꢀandꢀholdoverꢀisꢀenteredꢀuponꢀlossꢀofꢀaꢀsecondaryꢀreference.ꢀUsersꢀcanꢀrestoreꢀ

theꢀhistoryꢀfromꢀbackupꢀanyꢀtime,ꢀevenꢀwhileꢀoperatingꢀinꢀHoldoverꢀmode.ꢀTheꢀfrequencyꢀtransientꢀwillꢀbeꢀsmoothꢀandꢀcontinuous.ꢀ

Itꢀisꢀtheꢀresponsibilityꢀofꢀapplicationꢀsoftwareꢀtoꢀkeepꢀtrackꢀofꢀtheꢀageꢀandꢀviabilityꢀofꢀtheꢀholdoverꢀbackupꢀhistory.ꢀGivenꢀtimeꢀandꢀ

temperatureꢀeffectsꢀonꢀoscillatorꢀaging,ꢀtheꢀapplicationꢀmayꢀwishꢀtoꢀperiodicallyꢀperformꢀaꢀ“Save”ꢀofꢀtheꢀActiveꢀhistoryꢀtoꢀkeepꢀtheꢀ

backupꢀcurrent.

ꢀ

Whenꢀswitchingꢀtoꢀaꢀnewꢀreference,ꢀtheꢀactiveꢀholdoverꢀhistoryꢀwillꢀremainꢀintactꢀandꢀmarkedꢀasꢀ“HoldoverꢀAvailable”ꢀ(ifꢀitꢀwasꢀ

availableꢀbeforeꢀtheꢀreferenceꢀswitch)ꢀuntilꢀaꢀnewꢀhistoryꢀisꢀaccumulatedꢀonꢀtheꢀnewꢀreferenceꢀ(Typicallyꢀ15ꢀminutesꢀafterꢀlockꢀhasꢀ

beenꢀachieved).ꢀDuringꢀtheꢀnewꢀhistoryꢀaccumulation,ꢀtheꢀ“HoldoverꢀBuildꢀComplete”ꢀbitꢀisꢀreset.ꢀOnceꢀtheꢀnewꢀhistoryꢀaccumulationꢀisꢀ

complete,ꢀitꢀisꢀtransferredꢀtoꢀtheꢀActiveꢀHistoryꢀandꢀtheꢀ“HoldoverꢀBuildꢀComplete”ꢀbitꢀisꢀset.ꢀTheꢀactiveꢀhistoryꢀwillꢀthenꢀcontinueꢀtoꢀbeꢀ

updatedꢀtoꢀtrackꢀtheꢀreference.

ꢀ

TheꢀHistory_Policyꢀregisterꢀallowsꢀtheꢀapplicationꢀtoꢀcontrolꢀhowꢀaꢀnewꢀhistoryꢀisꢀbuilt.ꢀWhenꢀsetꢀtoꢀ“Rebuild”:

1)ꢀHistoryꢀaccumulationꢀbeginsꢀwhenꢀlockꢀisꢀachievedꢀonꢀtheꢀnewꢀreference.

2)ꢀTheꢀholdoverꢀhistoryꢀisꢀrebuiltꢀ(takingꢀaboutꢀ15ꢀminutes).ꢀTheꢀActiveꢀHistoryꢀremainsꢀuntouchedꢀuntilꢀitꢀisꢀreplacedꢀwhenꢀtheꢀbuildꢀꢀ

ꢀꢀꢀꢀisꢀcomplete.

Whenꢀtheꢀpolicyꢀisꢀsetꢀtoꢀ“Continue”:

1)ꢀIfꢀthereꢀisꢀnoꢀ“Available”ꢀActiveꢀHistory,ꢀaꢀnewꢀbuildꢀoccurs,ꢀasꢀunderꢀtheꢀ“Rebuild”ꢀpolicy.

2)ꢀIfꢀthereꢀisꢀanꢀ“Available”ꢀActiveꢀHistory,ꢀitꢀwillꢀcontinue,ꢀtheꢀaccumulationꢀregisterꢀwillꢀbeꢀloadedꢀfromꢀthe

ActiveꢀHistory,ꢀandꢀtheꢀ“Build”ꢀprocessꢀisꢀessentiallyꢀcompletedꢀimmediatelyꢀfollowingꢀlockꢀonꢀtheꢀnewꢀreference.

Theꢀ“Continue”ꢀpolicyꢀmayꢀbeꢀusedꢀbyꢀtheꢀapplicationꢀif,ꢀforꢀexample,ꢀitꢀisꢀknownꢀthatꢀtheꢀreferenceꢀswitchedꢀtoꢀmayꢀbeꢀtracedꢀtoꢀtheꢀ

ꢀ

sameꢀsourceꢀandꢀthereforeꢀlikelyꢀhasꢀnoꢀfrequencyꢀoffsetꢀfromꢀtheꢀpriorꢀreference.ꢀInꢀthatꢀcase,ꢀtheꢀ“Continue”ꢀpolicyꢀavoidsꢀtheꢀdelayꢀ

ofꢀrebuildingꢀtheꢀholdoverꢀhistory.ꢀIfꢀtheꢀswitchꢀisꢀlikelyꢀtoꢀbeꢀbetweenꢀreferencesꢀwithꢀknownꢀorꢀunknownꢀfrequencyꢀoffset,ꢀthenꢀitꢀisꢀ

preferableꢀtoꢀuseꢀtheꢀ“Rebuild”ꢀpolicy.

ꢀ

TheꢀtimeꢀsinceꢀtheꢀholdoverꢀstateꢀwasꢀenteredꢀmayꢀbeꢀreadꢀfromꢀtheꢀHoldover_Timeꢀregister.ꢀValuesꢀareꢀfromꢀ0ꢀtoꢀ255ꢀhours,ꢀ

limitedꢀatꢀ255,ꢀandꢀresetꢀtoꢀ0ꢀwhenꢀnotꢀinꢀtheꢀholdoverꢀstate.

Boundary Scan IEEE1149.1-2001 (Limited Testability Support) - Thisꢀmoduleꢀexposesꢀaꢀboundaryꢀscanꢀchainꢀwhichꢀcontainsꢀ

oneꢀorꢀmoreꢀboundaryꢀscanꢀtestableꢀIEEE1149.1-2001ꢀcomplaintꢀdevices.ꢀꢀTheꢀexposedꢀboundaryꢀscanꢀchainꢀisꢀIEEE1149.1-2001ꢀ

compliant,ꢀandꢀsupportsꢀallꢀdocumentedꢀtestingꢀmodesꢀofꢀdevicesꢀcontainedꢀwithinꢀchain.ꢀꢀIntegrationꢀofꢀthisꢀmoduleꢀintoꢀanꢀexistingꢀ

boundaryꢀscanꢀchainꢀwillꢀrequireꢀtheꢀfollowing.ꢀꢀꢀ

ꢀꢀ

-ꢀSubstitutionꢀofꢀmodulesꢀfootprintꢀwithꢀprovidedꢀtestabilityꢀmodelꢀschematic.ꢀꢀ

-ꢀModiﬁedꢀnetꢀlistꢀwillꢀneedꢀtoꢀbeꢀloadedꢀintoꢀboundaryꢀscanꢀtestꢀvectorꢀgenerationꢀsoftware.ꢀꢀ

ꢀ

TestabilityꢀModelꢀSchematicꢀandꢀBSDLꢀﬁle(s)ꢀcanꢀbeꢀobtainedꢀdirectlyꢀfromꢀfactory.

Control Modes

ꢀ

Theꢀdeviceꢀcanꢀinꢀturnꢀbeꢀoperatedꢀinꢀaꢀmanualꢀcontrolꢀmode,ꢀorꢀautomaticꢀcontrolꢀandꢀreferenceꢀselectionꢀmode.ꢀ

Reset mayꢀbeꢀpulledꢀlowꢀforꢀaꢀminimumꢀofꢀ100nSꢀduringꢀchipꢀstart-upꢀ(orꢀanyꢀotherꢀdesiredꢀtime)ꢀtoꢀinitializeꢀtheꢀfullꢀdeviceꢀstate.ꢀ

However,ꢀpower-upꢀwillꢀalsoꢀperformꢀaꢀreset,ꢀsoꢀinꢀaꢀminimalꢀconﬁguration,ꢀReset mayꢀbeꢀtiedꢀinputꢀhigh.

ꢀ

TheꢀBITSꢀclockꢀoutputꢀfrequencyꢀisꢀselectedꢀbyꢀtheꢀT1/E1ꢀpin.ꢀWhenꢀT1/E1ꢀ=ꢀ1,ꢀtheꢀBITSꢀfrequencyꢀisꢀ1.544ꢀMHz,ꢀandꢀwhenꢀ

T1/E1ꢀ=ꢀ0,ꢀtheꢀBITSꢀfrequencyꢀisꢀ2.048ꢀMHz.

MASTER SELECT-ꢀDeterminesꢀtheꢀmasterꢀorꢀslaveꢀmode.ꢀSetꢀtoꢀ“1”ꢀforꢀaꢀmaster,ꢀandꢀ“0”ꢀforꢀaꢀslave.ꢀꢀMaster/slaveꢀswitchesꢀ

ꢀ

shouldꢀbeꢀperformedꢀwithꢀminimalꢀdelayꢀbetweenꢀswitchingꢀtheꢀstatesꢀofꢀeachꢀofꢀtheꢀtwoꢀdevices.ꢀThisꢀcanꢀbeꢀeasilyꢀaccomplished,ꢀforꢀ

example,ꢀbyꢀcontrollingꢀtheꢀmaster/slaveꢀstateꢀwithꢀaꢀsingleꢀsignal,ꢀcoupledꢀtoꢀoneꢀofꢀtheꢀdevicesꢀthroughꢀanꢀinverter.

ꢀ

Forꢀsimplexꢀoperation,ꢀtheꢀdeviceꢀshouldꢀbeꢀinꢀMasterꢀmodeꢀ-ꢀsetꢀMASTER SELECTꢀtoꢀ“1”.

SM3-8RG5 Data Sheet #: TM088 Page 27 of 32

Rev: 07 Date: 09/06/11

Mechanical Speciﬁcations

Mechanical Dimensions

Figure 10

2.050 [52.07mm]

.075 [1.91mm]

1.250 [31.75mm]

1.100 [27.94mm]

.150 [3.81mm]

.515 [13.08mm]

.018 [.46mm]

.100 [2.54mm]

.070 [1.78mm]

PIN 1

Footprint Dimensions

Figure 11

TOP VIEW

1.300

1.200

HOLE/PAD SIZE (32 PLACES):

1. UNSOCKETED MODULE:

0.028" DIA. PLATED HOLE WITH 0.060" DIA. PAD.

CUSTOMER COMPONENT

KEEP OUT AREA

2. SOCKETED MODULE:

0.038" DIA. PLATED HOLE WITH 0.070" DIA. PAD.

NOTE: For compatibllity with both the unsocketed and

socketed modules, Connor-Winfield recommends using

a 0.038" DIA. plated hole with 0.070" DIA. pad

PIN 1

0.100

0.000

SM3-8RG5 Data Sheet #: TM088 Page 28 of 32

Rev: 07 Date: 09/06/11

Mechanical Speciﬁcations continued

Required External Components

1.ꢀ Placeꢀseriesꢀresistorsꢀ(33ꢀohms)ꢀonꢀallꢀreferenceꢀinputsꢀ(Pinsꢀ4ꢀ-ꢀ7ꢀ&ꢀ15-18).

2.ꢀ Placeꢀseriesꢀresistorsꢀ(33ꢀohms)ꢀonꢀSPI_INꢀandꢀSPI_CLKꢀinputsꢀ(Pinsꢀ25,ꢀ26).

3.ꢀ Placeꢀoneꢀ.01uFꢀandꢀoneꢀ47-100uFꢀcapacitorꢀatꢀtheꢀinputꢀpowerꢀpinꢀ(Pinꢀ27).

4.ꢀ Oneꢀ4.7uFꢀ(25V)ꢀcapacitorꢀisꢀrequiredꢀatꢀtheꢀVPPꢀpinꢀ(Pinꢀ14).

5.ꢀ Oneꢀ4.7uFꢀ(25V)ꢀcapacitorꢀisꢀrequiredꢀatꢀtheꢀVPNꢀpinꢀ(Pinꢀ19).

PCB Layout Recommendations

1.ꢀ Orientꢀmoduleꢀsoꢀairﬂowꢀisꢀparallelꢀalongꢀtheꢀheaderꢀstripsꢀ(pins).

2.ꢀ Placeꢀde-couplingꢀand/orꢀﬁlterꢀcomponentsꢀasꢀcloseꢀtoꢀmoduleꢀpinsꢀasꢀpossible.

3.ꢀ DoꢀnotꢀplaceꢀanyꢀcomponentsꢀdirectlyꢀbeneathꢀtheꢀmoduleꢀonꢀtheꢀtopsideꢀofꢀtheꢀhostꢀPCB.

4.ꢀ Ensureꢀthatꢀonlyꢀcleanꢀandꢀwell-regulatedꢀpowerꢀisꢀsuppliedꢀtoꢀtheꢀmodule.

5.ꢀ Isolateꢀpowerꢀandꢀgroundꢀinputsꢀtoꢀtheꢀmoduleꢀfromꢀnoisyꢀsources.

6.ꢀ Provideꢀpowerꢀandꢀgroundꢀconnectionsꢀthroughꢀaꢀ0.050”ꢀwideꢀtraceꢀ(minimum)ꢀusingꢀ1-oz.ꢀCuꢀorꢀequivalentꢀcopperꢀfeatureꢀꢀ

ꢀ

(i.e.ꢀinternalꢀplane,ꢀcopperꢀareaꢀﬁll,ꢀetc.).

7.ꢀ Keepꢀmoduleꢀsignalsꢀawayꢀfromꢀsensitiveꢀorꢀnoisyꢀanalogꢀandꢀdigitalꢀcircuitry.

8.ꢀ Avoidꢀsplitꢀgroundꢀplanesꢀasꢀhigh-frequencyꢀreturnꢀcurrentsꢀmayꢀbeꢀaffected.

9.ꢀ Allowꢀextraꢀspacingꢀbetweenꢀtracesꢀofꢀhigh-frequencyꢀinputsꢀandꢀoutputs.

10.ꢀ Keepꢀallꢀtracesꢀasꢀshortꢀasꢀpossibleꢀ-ꢀavoidꢀmeanderingꢀtraceꢀpaths.

11.ꢀ AvoidꢀroutingꢀsignalsꢀdirectlyꢀbeneathꢀtheꢀmoduleꢀonꢀtheꢀtopsideꢀofꢀtheꢀhostꢀPCB.

12.ꢀ Ifꢀpossible,ꢀprovideꢀaꢀcopperꢀareaꢀdirectlyꢀbeneathꢀtheꢀmoduleꢀonꢀtheꢀtopsideꢀofꢀtheꢀhostꢀPCB.ꢀꢀConnectꢀthisꢀcopperꢀareaꢀtoꢀground.

13.ꢀ ItꢀisꢀrecommendedꢀthatꢀtheꢀconnectionsꢀofꢀtheꢀJTAG,ꢀVPPꢀandꢀVPNꢀpinsꢀbeꢀroutedꢀtoꢀpads,ꢀpreferablyꢀinꢀaꢀSILꢀpatternꢀasꢀshownꢀꢀ

ꢀ

inꢀFigureꢀ13ꢀbelow.ꢀꢀItꢀisꢀrecommendedꢀtoꢀuseꢀ0.1”ꢀcenterꢀtoꢀcenterꢀspacing.

1

8

Figure 13

Optional Socket Mounting Recommendations

MatingꢀsocketsꢀmayꢀbeꢀusedꢀifꢀpermanentꢀinstallationꢀofꢀtheꢀSM3ꢀmoduleꢀisꢀnotꢀdesired.ꢀꢀTwoꢀpossibleꢀsourcesꢀforꢀtheseꢀsocketsꢀ

include:

ꢀ

1.ꢀ

2.ꢀ

Samtec,ꢀ“LowꢀProﬁleꢀSocketꢀStrips”,ꢀSLꢀSeries,ꢀPNꢀSL-116-G-19.ꢀꢀꢀ(http://www.samtec.com/)

Mill-Max,ꢀ“Single-In-LineꢀSockets”,ꢀ315ꢀSeries,ꢀPNꢀ315-xx-114-41-001.ꢀꢀ(http://www.mill-max.com/)

TheꢀSM3-8RG5ꢀrequiresꢀtwoꢀ16-pinꢀsockets.ꢀꢀTheꢀoptionalꢀdualꢀfootprintꢀconﬁgurationꢀshownꢀinꢀFigureꢀ14ꢀrequiresꢀoneꢀ14-pinꢀandꢀtwoꢀ

16-pinꢀsockets.

SM3-8RG5 Data Sheet #: TM088 Page 29 of 32

Rev: 07 Date: 09/06/11

Mechanical Speciﬁcations continued

Optional SM3/SM3-8RG5 Dual Footprint

AꢀdualꢀfootprintꢀconﬁgurationꢀmayꢀbeꢀusedꢀwhenꢀdesigningꢀaꢀhostꢀcircuitꢀboardꢀcontainingꢀtheꢀConnorꢀWinﬁeldꢀSM3ꢀorꢀSM3-8RG5ꢀ

modules.ꢀꢀTheꢀsmallerꢀSM3ꢀcontainsꢀaꢀsubsetꢀofꢀtheꢀsignalꢀpinsꢀfoundꢀonꢀtheꢀlargerꢀSM3-8RG5ꢀinꢀlocationsꢀwhichꢀallowꢀforꢀaꢀsimpleꢀ

dualꢀfootprintꢀarrangementꢀlikeꢀtheꢀoneꢀshownꢀinꢀFigureꢀ14.

SM3-8RG5

32

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

LOS

LOL

MASTER SELECT

SPI_INT

SPI_OUT

RESET

SM3

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

2

3

M/S REF

REF1

4

5

REF2

SPI_ENBL

Vcc

6

REF3

7

REF4

SPI_IN

SPI_CLK

GND

(TOP VIEW)

8

TDI

9

TMS

10

11

12

13

14

15

16

TRST

TCK

BITS_CLK

M/S_OUT

OUTPUT1

VPP

TDO

HOLD_GOOD

T1/E1

VPN

REF5

REF7

REF6

REF8

0.850"

1.100"

Figure 14

TheꢀmodulesꢀshownꢀinꢀFigureꢀ1ꢀareꢀarrangedꢀinꢀaꢀleft-justiﬁedꢀfashion.ꢀꢀNoticeꢀthatꢀrightꢀjustiﬁedꢀorꢀcenterꢀjustiﬁedꢀ(withꢀanꢀadditionalꢀ

columnꢀofꢀSM3ꢀpins)ꢀarrangementsꢀareꢀalsoꢀpossible,ꢀdependingꢀonꢀtheꢀdesigner’sꢀpreference.

Placementꢀofꢀexternalꢀcomponentsꢀ

ꢀ

1.ꢀ Placeꢀseriesꢀresistorsꢀ(33ꢀohms)ꢀonꢀallꢀreferenceꢀinputꢀ(SM3ꢀPinsꢀ4ꢀ-ꢀ7,ꢀSM3-8RG5ꢀPinsꢀ4-7ꢀ&ꢀ15-18).

2.ꢀ Placeꢀseriesꢀresistorsꢀ(33ꢀohms)ꢀonꢀSPI_INꢀandꢀSPI_CLKꢀinputsꢀ(SM3ꢀPinsꢀ21,22,ꢀSM3-8RG5ꢀPinsꢀ25ꢀ&ꢀ26).

3.ꢀ Placeꢀoneꢀ.01uFꢀandꢀoneꢀ47-100uFꢀcapacitorꢀatꢀtheꢀinputꢀpowerꢀpinꢀ(SM3ꢀPinꢀ23,ꢀSM3-8RG5ꢀPinꢀ27).

4.ꢀ Oneꢀ4.7uFꢀ(25V)ꢀcapacitorꢀisꢀrequiredꢀatꢀtheꢀVPPꢀpinꢀ(SM3ꢀ&ꢀSM3-8RG5ꢀPinꢀ14).

5.ꢀ Oneꢀ4.7uFꢀ(25V)ꢀcapacitorꢀisꢀrequiredꢀatꢀtheꢀVPNꢀpinꢀ(SM3ꢀPinꢀ15,ꢀSM3-8RG5ꢀPinꢀ19).

BeꢀsureꢀtoꢀconsultꢀConnorꢀWinﬁeld’sꢀrespectiveꢀdatasheetsꢀforꢀadditionalꢀmechanical,ꢀelectrical,ꢀfootprintꢀandꢀkeep-outꢀinformation.

SM3-8RG5 Data Sheet #: TM088 Page 30 of 32

Rev: 07 Date: 09/06/11

Ordering Information

SM3-8RG5-XXX.XXM

ReplaceꢀXXX.XXꢀwithꢀoneꢀofꢀtheꢀfollowingꢀavailableꢀfrequencies,

012.96MHz,ꢀ019.44MHz,ꢀ025.92MHz,ꢀ038.88MHz,ꢀ051.84MHzꢀorꢀ077.76MHz.

PleaseꢀcontactꢀConnor-Winﬁeldꢀforꢀotherꢀfrequenciesꢀthatꢀmayꢀbeꢀavailable.

SimilarꢀProductsꢀfromꢀConnor-Winﬁeld

ꢀ

SM3G5-XXX.XXMꢀ-ꢀStratumꢀ3ꢀmoduleꢀwithꢀ4ꢀinputꢀreferences.

SM3G5-IT-XXX.XXMꢀ-ꢀIndustrialꢀtemperatureꢀratedꢀStratumꢀ3ꢀmoduleꢀwithꢀ4ꢀinputꢀreferences.

SM3EG5-XXX.XXMꢀ-ꢀStratumꢀ3Eꢀmoduleꢀwithꢀ8ꢀinputꢀreferences.ꢀꢀ

SM3-8RG5 Data Sheet #: TM088 Page 31 of 32

Rev: 07 Date: 09/06/11

2111 Comprehensive Drive

Aurora, Illinois 60505

Phone: 630-851-4722

Fax: 630-851-5040

www.conwin.com

Revisionꢀ

00ꢀ

01ꢀ

02ꢀ

03ꢀ

04ꢀ

05ꢀ

06ꢀ

07ꢀ

RevisionꢀDateꢀ

10/18/06ꢀ

6/14/07ꢀ

Note

FinalꢀReleaseꢀDataꢀSheet

Pg.27,ꢀClariﬁedꢀBoundaryꢀScan

AddꢀInitializationꢀinfo,ꢀPg.ꢀ22-23

AddedꢀInputꢀPulseꢀWidthꢀSpecꢀtoꢀTableꢀ1

RegistrationꢀDescriptionꢀUpdate

PinꢀDescriptionꢀUpdates

10/15/07ꢀ

11/06/08ꢀ

02/11/10ꢀ

07/12/10ꢀ

01/26/11ꢀ

09/06/11ꢀ

SerialꢀTimingꢀBusꢀupdatesꢀtoꢀgraphics

ChipꢀRevisionꢀRegisterꢀupdated


型号：	SM3-8RG5
厂家：	CONNOR-WINFIELD CORPORATION
描述：	8 REFERENCE STRATUM 3 MODULE
文件：	总32页 (文件大小：616K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SM3-8RG5 [CONNOR-WINFIELD]

相关型号：

SM3-IT-019.44M

SM3-IT-019.44MHZ

SM3-IT-025.92M

SM3-IT-025.92MHZ

SM3-IT-038.88M

SM3-IT-051.84M

SM3-IT-051.84MHZ

SM3-IT-077.76M

SM3-IT-077.76MHZ

SM3-ITG

SM3-ITG-012.96M

SM3-ITG-025.92M