STL-S3E_技术文档

Stratum 3E Timing Module

STL-S3E

2111 Comprehensive Drive

Aurora, Illinois 60505

Phone: 630-851-4722

Fax: 630-851-5040

www.conwin.com

Features

• 6 Input

References

• Hitless Switch

Over

• CMOS output up

to 77.76 MHz

• 8 kHz Output

• 12 ppb Composite

Hold Over Mode

• Fast Acquisition

Mode

Application

The Connor-Winfield Stratum 3E Simplified

Control Timing Module acts as a complete

system clock module for Stratum 3E timing

applications in accordance with GR-1244-

CORE, Issue 2, GR-253-CORE, Issue 3,

and ITU-T G.812, Option ΙΙΙ.

Connor-Winfield’s Stratum 3E Timing

module helps reduce the cost of your

design by minimizing your development

time and maximizing your control of the

system clock with our simplified design.

• Manual/

Autonomous

Operation

• Master/Slave

Configuration

• Revertive/Non-

revertive Modes

Bulletin

TM048

Page

1 of 24

Revision

P00

Date

13 MAY 04

Issued By

MBATTS

General

Pin Diagram

Figure 1

Connor-Winfield's STL timing module provides Stratum

3E synchronization for a complete system clock solution in a

single module in accordance with GR-1244-CORE Issue 2, GR-

253-CORE Issue 3, and ITU-T G.812 Option III. The STL

provides a reliable network element clock reference to line cards

used in TDM, PDH, SONET, and SDH application environments.

Typical applications include digital connects, DSLAMs, ADMs,

multiservice platforms, switches and routers.

The STL meets 12 ppb Hold Over requirements over 0°

- 70°C temperature range. The 3.3V power requirement will

draw a maximum of 1.7 A during an initial start-up period and

then drop to a typical current of 0.6 A during normal operating

conditions. It accepts six input references and can supply up to

3 CMOS outputs (see Tables 1-4 for specific information).

Top View

Pin 1

Hold Over

V

Pin 34

CC

Ref. 3 Indicator

Ref. 1 Indicator

Ref. 4 Indicator

Ref. 2 Indicator

Ref. 5 Indicator

Free Run Indicator

Ref. 6 Indicator

GND

Ext. Ref. 5

Ext. Ref. 1

Ext. Ref. 3

GND

Ext. Ref. 6

Ext. Ref. 2

Ext. Ref. 4

GND

Reset

Alarm

Output 3

CNTRL 1

CNTRL 3

CNTRL 2

SPI Enable

Lock

Slave Input

Output 2

SPI_IN

GND

SPI_CLK

Output 1

SPI_OUT

GND

Pin 17

Pin 18

Functional Block Diagram

Figure 2

Reference 1

Reset

Reference 2

Reference 3

Reference 4

Reference 5

Reference 6

SPI_ENBL

SPI_CLK

SPI_IN

SPI_OUT

CNTRL 1

External Ref #1

÷N

a

CNTRL 2

CNTRL 3

DSP

Alarm

Lock

LOR

Detect

External Ref #2

External Ref #3

External Ref #4

External Ref #5

External Ref #6

÷N

b

Hold Over

Free Run

c

÷N

DDS

d

e

X

÷N

÷M

÷N

f

÷W

OCXO

X

Slave Input

÷N

g

Loop

Filter

Output 1

VCXO

÷N

X

÷R

Output 2

Output 3

÷P

Table 1

Symbol

V_CC

Absolute Maximum Rating

Parameter

Minimum

Nominal

Maximum

Units

Volts

Notes

Power Supply Voltage

Input Voltage

-0.5

4.0

1.0

V_I

-0.5

5.5

T_s

Storage Temperature

-40

85

deg. C

Preliminary Data Sheet #: TM048

Page 2 of 24

Rev: P00 Date: 05/13/04

Table 2

Symbol

V_cc

Recommended Operating Conditions

Parameter

Minimum

3.135

2.0

Nominal

Maximum

3.465

5.25

Units

Volts

ns

Notes

2.0

Power Supply Voltage

High level input voltage - CMOS

Low level input voltage - CMOS

V_IH

V_IL

0

0.8

t_PULSE

Minimum pulse width, positve/negative

for external references

30

t_TR

Input signal transistion time

250

100

ns

t_RST

Time for module to re-configure after a reset

(manual or POR)

1.5

sec.

t_HLD

Time to hold reset pin high

0.3

ms

Table 3

Symbol

V_OH

DC Characteristics

Parameter

Minimum

Nominal

Maximum

3.6

Units

Volts

Notes

3.0

High level output voltage,

I_OH= -4.0mA, V_CC= min.

2.4

3.3

V_OL

Low level output voltage,

I_OL= 8.0mA, V_CC= max.

0.4

Volts

Table 4

Specifications

Parameter

Specifications

Notes

7.0

Frequency Range - Output 1

Output 2

8 kHz - 77.76 MHz

7.0

Output 3

7.0

Supply Current

0.6 A typical @ 25°C, 1.7 A during warm-up (Maximum)

Timing Reference Inputs

Slave Input

8 kHz - 77.76 MHz

7.0

8 kHz

Jitter, Wander and Phase Transient Tolerances

Wander Generation

Wander Transfer

GR-1244-CORE 4.2-4.4, GR-253-CORE 5.4.4.3.6

GR-1244-CORE 5.3, GR-253-CORE 5.4.4.3.2

GR-1244-CORE 5.4

Jitter Generation

Jitter Transfer

GR-1244-CORE 5.5, GR-253-CORE 5.6.2.3

GR-1244-CORE 5.5, GR-253-CORE 5.6.2.1

GR-1244-CORE 5.6, GR-253-CORE 5.4.4.3.3

4.6 ppm over temperature range

0.012 ppm

Phase Transients

Output 1,2 & 3 Free Run Accuracy

Hold Over Stability

Inital Offset

4.0

6.0

0.001 ppm

Temperature

0.010 ppm

Drift

0.001 ppm

Maximum Hold Over History

Minimum Time for Hold Over

Lock Time

1049 seconds

701 seconds after a reference rearrangement

700 sec.

6.0

5.0

Lock Accuracy

0.001 ppm

Environmental Characteristics

Shock

100G’s, 6mS, halfsine per MIL-STD-202F, Method 2138, Test Condition C

Vibration

0.06" D.A. or 10G peak 10 to 500 Hz, per MIL-STD-202F, Method 204D, Test Condition A

NOTES:

4.0: Hold Over stability is the cumulative fractional frequency offset as described by

GR-1244-CORE, 5.2

1.0: Stresses beyond those listed under Absolute Maximum Rating may cause damage

to the device. Operation beyond Recommended Conditons is not implied.

5.0: After 700 seconds at stable temperature ( 5° F)

6.0: When configured for STRATUM 3E compatible filter.

7.0: Frequency must be specified at the time of the order

2.0: Inputs are 3.3V CMOS,5V tolerant

3.0: Logic is 3.3V CMOS

Preliminary Data Sheet #: TM048

Page 3 of 24

Rev: P00

Date: 05/13/04

Pin Description

Table 5

Pin #

1

Connection

Hold Over

Reference 3

Reference 1

Reference 4

Reference 2

Reference 5

Free Run

Description

Indicator = 1 when module is in Hold Over

Indicator = 1 when module is locking to or is locked to external reference 3

Indicator = 1 when module is locking to or is locked to external reference 1

Indicator = 1 when module is locking to or is locked to external reference 4

Indicator = 1 when module is locking to or is locked to external reference 2

Indicator = 1 when module is locking to or is locked to external reference 5

Indicator = 1 when module is in Free Run

Indicator = 1 when module is locking to or is locked to external reference 6

Ground

2

3

4

5

6

7

8

Reference 6

GND

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

Reset

Reset Pin (↓)*

Alarm

Indicator = 1 when module is in an alarm condition

8 kHz output derived from system clock

Mode control input for manual operation. (↓)

Enable for SPI communication port. (↑)

Indicator = 0 when module is locked to selected reference.

Ground

Output 3

CNTRL 1

CNTRL 3

CNTRL 2

SPI Enable

Lock

GND

SPI_OUT

Serial data output for SPI communication

System clock output

Output 1

SPI_SCLK

GND

Input clock for SPI communication. (↓)

Ground

SPI_IN

Serial data input for SPI communication

8 kHz output derived from system clock

Input for synchronizing a module in slave configuration.

Ground

Output 2

Slave Input

GND

External Reference 4

External Reference 2

External Reference 6

GND

External reference input #4

External reference input #2

External reference input #6

Ground

External Reference 3

External Reference 1

External Reference 5

V_CC

External reference input #3

External reference input #1

External reference input #5

+3.3V_ccpower supply required

(↑) = Internal pull-up

(↓) = Internal pull-down

Internal pull-up/pull-down resistors range from 50 kΩ to 100 kΩ

(↓)* = 10 kΩ pull-down resistor

Preliminary Data Sheet #: TM048

Page 4 of 24

Rev: P00 Date: 05/13/04

Functional Truth Table

Table 6

Reference#

Alarm

Lock

Hold Over

Free Run

Condition

1

0

1

0

1

0

1

0

Locking to selected reference but the phase error is > 20µs

Tracking selected reference and the phase error is ≤ 20µs

Auto Mode - There are no valid references so module has

entered Hold Over.

0

1

0

1

Manual Mode - Module is in Hold Over mode.

Auto Mode - There are no valid references and there is no

valid Hold Over history so module has entered

Free Run.

0

1

0

1

0

1

0

Manual Mode - Module is in Free Run mode.

Slave Mode - Module is locked to master module and phase

error is ≤ 20µs

0

1

0

Slave Mode - Module is locked to master module and phase

error is > 20µs

Slave Mode - Module is unable to track master module due to

Loss of Reference condition or the frequency

is out of range.

Control Inputs

Table 7

CNTRL3/CF3

CNTRL2/CF2

CNTRL1/CF1

Mode of Operation

Free Run

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Locked to Ref #1

Locked to Ref #2

Hold Over

Locked to Ref #3

Locked to Ref #4

Locked to Ref #5

Locked to Ref #6

Module Restabilization Times

Table 8 - For a given off-time, the time required to meet daily aging, short term stability and TDEV requirements:

OffTime

Restabilization Time

< 2 Hours

< 1 Hour

< 6 Hours

< 24 Hours

1 to 16 Days

> 16 Days

< 12 Hours

< 48 Hours

48 Hours + ¼ off time

< 6 Days

Preliminary Data Sheet #: TM048

Page 5 of 24

Rev: P00

Date: 05/13/04

Operation Overview

The STL offers both manual and autonomous modes of operation, and the option of revertive or non-revertive reference

switching during autonomous mode. In manual mode, the user has control of the module using pins CNTRL 3:1 to determine

whether the module should lock to a specific reference, enter Free Run or enter Hold Over. In autonomous mode, the module

determines the proper operating behavior depending on the state of the external references, which are frequency qualified by the

module. For further details of autonomous operation, see the state diagrams in Figure 4. The STL also offers master and slave

modes and incorporates reference qualification on all 6 external references and the slave input.

When the module is locked to a valid reference, the appropriate external indicator will be asserted for that reference. When

internal phase error is less than 20µs, the Lock signal will be asserted. The STL takes up to 700 seconds to obtain complete phase

lock to a qualified reference. To assure that the STL will always lock to any valid frequency offset within 700 seconds, the module

goes into a Fast Acquisition mode immediately after switching to a new reference. If the module experiences a Lock alarm after it

has phase-locked to the selected reference, the module will re-enter the Fast Acquisition stage of filtering if the reference has not

been disqualified. Once locked, the filtering will return to the 0.002 Hz filter (or the user selected BW if the defaults have been

overwritten). This Fast Acquisition mode has a faster filter that allows the module to lock onto a new frequency quicker than the

0.002 Hz filter for normal, locked operation. The filtering during Fast Acquisition mode will not allow frequency movement faster than

2.9 ppm per second. Fast Acquisition mode is further described as fast start mode in GR-1244-CORE, Issue 3, section 3.6. The

current PLL status can be accessed via SPI port in register 0Eh.

A manual reset pin called Reset is provided on pin 10 of the STL device. This will reset the DSP, FPGA, and DDS causing a

disruption in all programmable devices and is the same type of reset, though not software controlled, described in Table 16. The

STL device will treat this reset as if it were following a power-up; all registers are reset to their default values. Resetting the unit by

cycling the power requires more time for restablization of the internal ovenized oscillator and is not recommended.

Hold Over mode provides a stable frequency that is guaranteed to be within 0.012 ppm over the entire temperature range for

the first 24 hours after entry into Hold Over. The module establishes a new Hold Over history within 701 seconds after a reference

is selected and continues to do a running average every 8 seconds for the next 1049 seconds. Long-term Hold Over values are

based on a 1049 second moving window average. Hold Over values are not updated when the reference is disqualified or during

Fast Acquisition mode. Hold Over values are buffered for at least 32 seconds to allow enough time to respond to the alarms and

frequency qualification status.

Free Run is a mode of operation in which the module is not locked to a reference and its output frequency is solely dependent on

the initial frequency setting of the internal oscillator. The output frequency in Free Run is guaranteed to be 4.6ppm of the nominal

frequency.

Reference qualification continually monitors all 6 input references, as well as the Slave input. The references are monitored for

both frequency accuracy and presence. Although loss of presence is detected almost immediately due to being continually

monitored, a delay of up to 7 seconds may occur before an out-of-band frequency is detected. This delay is caused by the fact that

reference qualification is done one reference at a time, in a round robin fashion. Each reference takes just over one second to

qualify, and so cycle time is the cause of the delay.

The STL module provides three output frequencies. Output 1 is the primary synchronized output. It is phase locked to the input

reference during normal operation and is set to a fixed frequency when operating in Hold Over or Free Run. Output 2 and Output 3

are derived from Output 1.

The STL module provides a variety of alarm and status information to alert the user to multiple conditions that may affect the

overall performance of their system. Some of this information is brought out to external pins, while other information is accessible

through the SPI port on internal memory-mapped registers. Status information from reference qualification, including frequency

offsets, is contained in these registers; information regarding phase build out and valid Hold Over is also stored here. Additionally,

the current mode of operation and SPI status are available. Certain features of the STL are programmable by the user. For complete

details on memory-mapped registers, please see SPI Timing and Operation section. For SPI timing, see Figures 8-9.

In master mode, the module will experience an alarm condition (Alarm=1) when the module is in Hold Over or Free Run. In

manual mode, an alarm condition will occur if the user selects Hold Over, Free Run or a reference that is disqualified. If the

reference is disqualified after the module starts to track it, the module will enter holdover if a valid holdover history is available, or

the unit will enter Free Run. In autonomous mode, the module will experience an alarm condition when there are no available

references. This may be caused by all references being disqualified by LOR or an off-frequency condition or all references may be

set to unavailable in the priority table. In these cases, the module will enter holdover if there is a valid holdover history available, or

the module will enter Free Run. In slave mode, the module will experience an alarm condition if the module is not able to lock to the

master because the master frequency has exceeded the pull-in range of the slave, or due to an LOR of the master.

The Lock indicator will be de-asserted (Lock=1) when the internal phase error is detected at 20 us or greater from the final,

locked value. This alarm can occur when the unit is initially locking to a new reference, or it can occur after lock if the module loses

lock. This alarm will be also de-asserted (Lock=1) during holdover and freerun modes.

Preliminary Data Sheet #: TM048

Page 6 of 24

Rev: P00 Date: 05/13/04

Phase build out operation can be internally enabled or disabled through the internal memory-mapped registers. It is initially

enabled. Internal circuitry monitors the input reference for greater than 3.4µs of change over any 0.1 second interval. When this

occurs, internal buffers are reset so that the phase change is ignored, allowing the phase shift between input and output. Any phase

shift smaller than 3.4µs over 0.1 seconds will be followed to re-establish the original input/output phase relationship, unless the rate

of change causes the reference to be disqualified. Refer to Reference Qualification section (pg. 9 ) for more details on

disqualification.

The STL meets the requirements for wander generation and wander transfer as required by GR-1244, sections 5.3 and 5.4. It

also complies with phase transient requirements during Reference Rearrangement, Entry into Hold Over, and 1µs transient. Input

jitter is attenuated at about 20 dB/decade to minimize the jitter noise passed on to other network elements or clocks. Figure 15

illustrates the STL's typical roll off of attenuated jitter.

Autonomous Mode

During autonomous mode, the unit makes the decision about which reference to track based on priority and qualification status.

The goal of the module is to lock onto the highest priority qualified reference. If the revertive option is selected, the module will

switch out of the current reference, even when that reference is still qualified, as soon as a higher priority qualified reference

becomes available. The module will also switch into the highest priority qualified reference when the current reference is

disqualified. If the non-revertive option is selected, the module will only switch into another reference when the current reference is

disqualified.

If the current reference is disqualified, and there are no other qualified references to switch to, the module will enter the last valid

Hold Over value. As soon as a reference is qualified, the module will begin to track it. If no Hold Over value has been calculated,

then the unit will revert into Free Run until a reference is available. If multiple references are set to the same priority in the priority

table, the module will select the lowest reference number as the highest priority. For example, if Reference 5 and Reference 3 are

both set to priority 1, the module will consider Reference 3 to be of a higher priority than Reference 5 (assuming both are qualified

references).

Autonomous Mode State Diagram

Figure 3

Fast Acquisition

e

V

a

m

r

e

l

n

o

c

i

a

d

b

h

*

e

t

r

e

l

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l

e

V

a

d

b

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l

a

b

f

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t

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a

s

a

l

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h

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i

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a

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a

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a

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r

b

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V

l

e

Lock

All

r

d

e

isqu

f

er

are

H

enc

a

lified

s

old

a

e

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e

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ai

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f

are

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lab

le

erencel

a

n

e

f

r

e

r

d

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no

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u

disqua

e

is

Free Run

Hold Over

y

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v

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s

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H

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*Note: During autonomous, revertive operation,

if a valid reference of a higher priority is

available, the module will switch from a

reference that is still qualified.

Preliminary Data Sheet #: TM048

Page 7 of 24

Rev: P00

Date: 05/13/04

Manual Mode

During manual operation, the mode of operation is determined by the user through either the external control pins CNTRL3:1 or

internal configuration bits CF3:1 (see Table 7). The default configuration is to have external control, but this can be changed to

internal control by setting the INT bit the memory-mapped registers via the SPI port. During manual operation, the user can select

Free Run, Hold Over, or locked operation. Any of the six input references can be selected for the unit to track.

If the module is locked to a reference and that reference becomes disqualified, the module will automatically go into Hold Over.

If the module has been phase-locked to the current reference for at least 50 seconds and is in the final stage of the filter (as

indicated in register 0Eh), the Hold Over value will be derived from the data from the current reference. If the module has been

phase-locked to the current reference for less than 50 seconds, then the last valid Hold Over value will be used. If the control bits/

pins remain in the same selection that caused the unit to go into Hold Over, the unit will remain in Hold Over until the reference is re-

qualified. At that time, after a minimum 10s soak time, the unit will attempt to relock to the same reference.

If the external user control pins select a new reference that the module has not qualified, the module will switch into the last valid

Hold Over value. If the module has not yet established a valid Hold Over, the module will return to the pre-programmed Free Run

value. As soon as the module qualifies the selected reference, it will begin the locking process.

At no time during manual mode will the unit attempt to lock to a reference that is not selected by the external pins/internal bits.

The only mode that the unit will enter automatically is into Hold Over or Free Run, and that is due to a disqualification of the

selected reference.

Manual Mode State Diagram

Figure 4

Fast Acquisition

Lock

Free Run

Hold Over

or

ts

Preliminary Data Sheet #: TM048

Page 8 of 24

Rev: P00 Date: 05/13/04

Master/Slave Operation

During master operation, the master pays no attention to the Slave Input reference other than monitoring it for qualification

purposes. If the slave unit is removed, there is no behavioral change in the master.

During slave operation, the slave module locks to the Slave Input reference from the master, and continually qualifies it. If the

slave module determines that the master input has gone out of range, the slave continues to lock to the master until it reaches the

end of its pull-in/hold-in range, which is approximately 125 ppm. If the slave determines that the Slave Input frequency from the

master has been removed, the slave will use its internal priority table (which should be configured the same as the master module)

and configuration registers to begin locking to the highest priority qualified reference (or to the selected input reference if the master

unit was in manual mode). As soon as the Slave Input from the master returns, (after a 10 sec. minimum soak time) the slave will

begin locking to it.

When the module is in slave mode, the external indicator pins (Reference 1-Reference 6, Free Run, Hold Over) will remain

low, regardless of the mode. If the module is locked to or is attempting to lock to the master, the alarm indicator will be low. The

LOCK alarm works normally as long as the module is tracking the master. If the master is lost (due to LOR or out of tracking range),

and the module enters another mode, the alarm and LOCK indicators will both remain high (=1). The internal PLL status register

(0Eh) must be read to determine the current mode of operation of the module.

The goal of the slave is to maintain a zero-phase error with the Slave Input from the master. In order to accomplish this, the BW

during slave mode is increased so that the slave can respond very quickly to any change in the master's frequency to minimize the

phase difference between master and slave.

Master/Slave State Diagram

Figure 5

Master Mode

Slave mode is selected

Master mode is selected

Slave Mode

Preliminary Data Sheet #: TM048

Page 9 of 24

Rev: P00

Date: 05/13/04

Reference Qualification

Reference qualification requires that a reference be both present and within the required frequency limits for a minimum of 10

seconds. Any time a reference is disqualified due to a loss of signal or frequency offset, the 10 second window will start over. The

active reference can also be disqualified if there is a phase-time movement on the input that is greater than the allowable movement

for jitter tolerance and frequency hold-in range. If active reference is disqualified due to a faster than allowed phase-time change

(phase hit), the module will immediately go into Hold Over (or Free Run if Hold Over is not valid) for a minimum of 2ms, after which

the module will act as though the reference was disqualified due to a LOR or off-frequency condition.

Figure 6

Reference Frequency Qualification Test

Reference

may or may

not be

Reference

may or may

Reference

is not

qualified

Reference

is not

qualified

not be

qualified

(3ppm minimum)

Reference is qualified

Nominal

Frequency

Rejection

Limit

Frequency

Qualification

Limit

Qualification

Limit

Rejection

Limit

SPI Timing and Operation

The SPI port is set up for 8 bit communication. All address bytes are 8 bits in length, reads return 8 bits and writes require 8 bits.

The MSB of each address byte is the read/write bit. The lower 7 bits are the lowest 7 bits of the specified address. For example, a

read from address 01h would require the byte 1000 0001b to be sent to the module, MSB first.

Table 9

A7

A6

A5

A4

A3

A2

A1

A0

R/W

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit0

Format for Address Byte

R/W: Read=1/Write=0

Bit 6 - Bit 0: Address Information

Send A7 First

Table 10

D7

D6

D5

D4

D3

D2

D1

D0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Format for Data Byte

Bit 7 - Bit 0: Data Information

Receive/Send D7 First

Preliminary Data Sheet #: TM048

Page 10 of 24

Rev: P00 Date: 05/13/04

SPI Timing Diagrams

Figure 7

Write Cycle

t_clk

t_pw

t_pause-w

SPI_SCLK

t_s

t_h

SPI_IN

A7 A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

SPI_OUT

SPI Enable

t_ec

t_ce

Figure 8

Read Cycle

t_pause-r

t_clk

t_pw

SPI_SCLK

SPI_IN

A7 A6 A5 A4 A3 A2 A1 A0

SPI_OUT

D7 D6 D5 D4 D3 D2 D1 D0

SPI Enable

Parameter Description

Min

Max

t_CLK

t_S

SPI CLK rising edge to SPI CLK rising edge

Setup time, Valid data to SPI CLK rising edge

Hold time, Valid data following SPI CLK rising edge

Minimum time between address and data byte, Write only

Minimum time between address and data byte, Read only

Setup time, SPI Enable to first SPI CLK rising edge

Hold time, SPI Enable following last SPI CLK rising edge

Pulse width, SPI CLK

100 ns

10 ns

t_h

1 ns

t_pause-w

t_pause-r

t_ec

1 s

1 ms

(t_CLK/2)

(t_CLK/2) - 10 ns

t_ce

t_pw

Preliminary Data Sheet #: TM048

Page 11 of 24

Rev: P00

Date: 05/13/04

SPI Memory Mapped Registers

The internal memory-mapped registers are accessible through the SPI port on the STL module. Some registers are read-only,

while others are are accessible for a read or a write operation. The registers contain status information, alarm information,

configuration tables, and ID registers. To access the registers, please see the read and write timing diagrams in Figures 7-8.

Table 11 - Register Map

Addrs

Description

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

Priority Selection Table

Reserved

Reference Measurement

Slave Reference Measurement

Reserved

Qualification Status for References and Slave Input

Phase-Locked Loop Status

Reserved

Reference Qualification Limits

Configuration

Reserved

Bandwidth Selection

SPI Status

Identification

Reserved

Table 12 - Priority SelectionTable

Read/Write

Addrs

00h

Bit7

P23

P43

P63

Bit6

P22

P42

P62

Bit5

P21

P41

P61

Bit4

P20

P40

P60

Bit3

P13

P33

P53

Bit2

P12

P32

P52

Bit1

P11

P31

P51

Bit0

P10

P30

P50

Description

Priority register for References 1 and 2

Priority register for References 3 and 4

Priority register for References 5 and 6

01h

02h

P13,P12,P11,P10 - Priority for Reference 1(Default - 0110)

P23,P22,P21,P20 - Priority for Reference 2(Default - 0101)

P33,P32,P31,P30 - Priority for Reference 3(Default - 0100)

P43,P42,P41,P40 - Priority for Reference 4(Default - 0011)

P53,P52,P51,P50 - Priority for Reference 5(Default - 0010)

P63,P62,P61,P60 - Priority for Reference 6(Default - 0001)

The Priority Selection Table registers contain default information on the priority of the references, but these registers can be

overwritten by the user. The lowest priority is 0000 and the highest priority is 0110. If a reference is given priority 0000, then that

reference will be evaluated for frequency and presence, but will be considered an unavailable reference.

Preliminary Data Sheet #: TM048

Page 12 of 24

Rev: P00 Date: 05/13/04

If multiple references are assigned the same priority, and the module is in autonomous, revertive mode, the module will select the

lowest number as the highest priority.

All priorities with a binary number greater than 0110 will be treated as though their priority was 0110. No 4-bit binary

combinations will be considered invalid.

Table 13 - Reference Measurement and Qualification Status

Read only

Addrs

04h

05h

06h

07h

08h

09h

0Ah

0Ch

0Dh

Bit7

F17

F27

F37

F47

F57

F67

FS7

R41

X

Bit6

F16

F26

F36

F46

F56

F66

FS6

R40

X

Bit5

F15

F25

F35

F45

F55

F65

FS5

R31

RS1

Bit4

F14

F24

F34

F44

F54

F64

FS4

R30

RS0

Bit3

F13

F23

F33

F43

F53

F63

FS3

R21

R61

Bit2

F12

F22

F32

F42

F52

F62

FS2

R20

R60

Bit1

F11

F21

F31

F41

F51

F61

FS1

R11

R51

Bit0

F10

F20

F30

F40

F50

F60

FS0

R10

R50

Description

Reference 1 Frequency offset from Free Run

Reference 2 Frequency offset from Free Run

Reference 3 Frequency offset from Free Run

Reference 4 Frequency offset from Free Run

Reference 5 Frequency offset from Free Run

Reference 6 Frequency offset from Free Run

Slave Input frequency offset from Free Run

Status indicators for References 1-4

Status indicators for References 5-6

Fx7,Fx6,Fx5,Fx4,Fx3,Fx2,Fx1,Fx0 - Frequency offset of Reference x (Default - 1111 1111)

R#1,R#0 - Describes status of Reference #, see Table 20 (Default - 00)

X - Reserved for future use (Default - 0)

The Reference Measurement and Qualification Status registers hold the information regarding the specified reference’s

frequency offset from nominal (accurate to within 1.5 ppm of actual frequency) and status information regarding presence and

qualification status. The Frequency Offset registers have a resolution of 0.5 ppm, and are in 2s complement form. A maximum

frequency offset of +63.5 ppm or -64 ppm can be shown in these registers. If a reference is determined to have a frequency offset

past these limits, the register will only show the maximum. The Status Indicator registers show qualification status of each reference.

Table 14 - Phase-Locked Loop Status

Read only

Addrs

0Eh

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Description

HA

R2

R1

R0

S3

S2

S1

S0

Reference used in PLL and PLL Status

HA = 1 when Holdover history is available (Default - 0)

R2,R1,R0 - Describes reference in use, see Table 21 (Default - 000)

S3,S2,S1,S0 - Describes state of PLL, see Table 22 (Default - 1001)

Bit HA=1 when holdover history for the current reference is available. It will remain high when switched directly from the current

reference into holdover mode. Changing references, switching into free run, or setting the HOR bit in register 13h will clear the HA

bit. However, the valid holdover history will remain in the module’s memory until it is either overwritten by history from a new

reference, or until it is cleared by HOR.

When the module detects a 3.4 µ second phase-time change in 0.1s, it is unable to determine whether this is an actual

phase hit or a 34 ppm (or higher) frequency step. If phase build out is triggered due to a 34 ppm (or higher) frequency step, the

module will go into continuous phase build out. As the phase of the new frequency varies with the phase of the internal reference

from 0 degrees to 359 degrees and then back to 0, the phase build out bit in the pll status register (0Eh) will blink. The frequency of

this blinking will depend on the actual size of the frequency step

To prevent the module from going into a continuous phase build out state, do not attempt a 34 ppm (or greater) frequency

step unless phase build out is disabled.

Preliminary Data Sheet #: TM048

Page 13 of 24

Rev: P00

Date: 05/13/04

Table 15 - Reference Qualification Limits

Read/Write

Addrs

10h

Bit7

RJ7

FQ7

Bit6

RJ6

FQ6

Bit5

RJ5

FQ5

Bit4

RJ4

FQ4

Bit3

RJ3

FQ3

Bit2

RJ2

FQ2

Bit1

RJ1

FQ1

Bit0

RJ0

FQ0

Description

Frequency rejection limit

Frequency qualification limit

11h

RJ7,RJ6,RJ5,RJ4,RJ3,RJ2,RJ1,RJ0 - Limit beyond which references always rejected (Default - 0001 1111 (+/-15.5 ppm))

FQ7,FQ6,FQ5,FQ4,FQ3,FQ2,FQ1,FQ0 - Limit below which references always qualified (Default - 0001 1001 (+/-12.5 ppm))

The Reference Qualification Limits registers hold the information used to determine the always reject and always qualify regions

for the references. For proper module operation, the minimum space between these numbers should be 3 ppm. The LSB of each of

these registers is 0.5 ppm, and the MSB is 64 ppm, so the max number is 127.5 ppm. The format is 2s complement, positive

numbers. Note that the qualification and rejection ranges are symmetrical so that +15.5 ppm in register 10h gives a frequency

rejection limit at + or - 15.5 ppm. See Figure 6 for further details.

Table 16 - Configuration

Read/Write

Addrs

12h

Bit7

INT

X

Bit6

X

Bit5

X

Bit4

SLV

FRV

Bit3

X

Bit2

CF3

Bit1

CF2

REV

Bit0

CF1

AUT

Description

Mode configuration register

Feature configuration register

13h

X

DPB

RST

HOR

INT - When set to 1, INT selects internal user configuration data over the external CNFG pins. (Default - 0)

SLV - When set to 1, the module is in slave mode. (Default - 0)

CF3,CF2,CF1 - Internal configuration pins, see Table 7 (Default - 000)

DPB - When set to 1, Phase Build Out is disabled. (Default - 0)

FRV - When set to 1, will choose priority of reference based on frequency offset rather than priority table. (Default - 0)

RST - Will internally reset the module when set to 1. (Default - 0)

HOR - Will reset Hold Over history when set to 1. Holdover history defaults to Free Run value when reset. (Default - 0)

REV - Selects revertive reference switching when set to 1. Revertive switching only occurs while in autonomous mode.

(Default - 0)

AUT - Select pin for autonomous mode. When set to 1, enables autonomous selection of modes. (Default - 0)

X - Reserved for future use. (Default - 0)

The Configuration registers are read/write registers that hold all of the configuration options for the device. If INT is set high, the

external pins CNTRL3:1 are ignored, and full user control is maintained through these two registers. Bits CF3:1 mimic pins

CNTRL3:1 operation, and SLV bit in the mode configuration register controls whether the unit acts as a master or slave module. For

complete master/slave operation, see Figure 5. The feature configuration register turns on and off optional features of the device

such as phase build out, revertive switching, and autonomous operation. Bits are also provided to judge priority of references

(applicable during autonomous mode only) based on their frequency offset (see registers 04h-09h) or on the priority table (see

registers 00h-02h). The module also allows a reset of Hold Over history (HOR), as well as a complete module reset (RST).

The RST bit is used to initiate a complete software reset. The proper procedure to reset the device is to write a 1 to RST and

then wait for the device to re-boot. This will reset the DSP, as well as the FPGA and DDS. Due to the complete reset, the output

frequencies will be temporarily disrupted while the programmable chips reinitialize and then the Free Run value will be reestablished.

All previous histories will be cleared. The registers will initialize as though following a power-up. Please note that there will be an

increase in current as the device reinitializes, but the current increase will stay below the stated datasheet maximum.

For optimal performance during master/slave operation, the slave unit should be configured the same as the master unit. This

will allow proper selection of input reference for the slave module in the event the signal from the master module is lost.

Preliminary Data Sheet #: TM048

Page 14 of 24

Rev: P00 Date: 05/13/04

Table 17 - Bandwidth Selection

Read/Write

Addrs

16h

Bit7

FB3

SF3

Bit6

FB2

SF2

Bit5

FB1

SF1

Bit4

FB0

SF0

Bit3

X

Bit2

X

Bit1

X

Bit0

X

Description

Primary PLL Bandwidth selection

Slave mode Bandwidth selection

17h

X

FB3,FB2,FB1,FB0 - Selected bandwidth. See Table 23 (Default - 0001)

SF3,SF2,SF1,SF0 - Slave bandwidth. (Default - 0101, 20 Hz)

X - Reserved for future use. (Default - 0)

The bandwidth may be changed at any time during operation, even when the device is locked. However, the module may

experience a phase hit as the filters change bandwidth and so it is recommended to only change bandwidth upon initialization, or

when in Free Run or Hold Over modes.

If the bandwidth is changed to an undefined selection, no change in operation will occur. The initial bandwidth will remain in

effect until a valid new bandwidth is selected.

Slave mode bandwidth selection will take effect only when the unit is configured to be in slave mode. If the slave input reference

is lost (LOR), and the unit uses its configuration data to determine which reference to lock to, this bandwidth remains the same. The

purpose of the slave mode of operation is to lock to the master; if the master is lost, then the next best reference is used.

Table 18 - SPI Status

Read only

Addrs

18h

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Description

ER7

ER6

ER5

ER4

ER3

ER2

ER1

ER0

Error status

ER7,ER6,ER5,ER4,ER3,ER2,ER1 - SPI Error Status. See Table 24 (Default - 0000 0000)

The SPI Status register holds the state of the last SPI communication. An overrun error occurs when too many bytes of

information have been sent too quickly and the module was not able to process the address information before the clock started for

the data byte. Both reads and writes are invalid if this error follows their communication sequence. If an address error shows up in

this register, then the address that was sent to the module was invalid. No read or write will occur in this case. If an invalid address

is sent to the module, the module will still expect to see the SPI Enable line active and the SPI CLK line pulsed 8 times before the

next read/write cycle. All communication cycles are expected to be 2 bytes wide, whether there is an error or not. If an invalid data

error is displayed in the SPI Status register, it means that either a write was attempted on a read-only address, or an invalid data

word was written to an address. In either case, no data will be written into memory.

Table 19 - Identification

Read only

Addrs

19h

Bit7

CI7

SI7

HI7

Bit6

CI6

SI6

HI6

Bit5

CI5

SI5

HI5

Bit4

CI4

SI4

HI4

Bit3

CI3

SI3

HI3

Bit2

CI2

SI2

HI2

Bit1

CI1

SI1

HI1

Bit0

CI0

SI0

HI0

Description

Customer Identification

1Ah

Software Model/Version Identification

Hardware Model/Version Identification

1Bh

CI7, CI6, CI5, CI4, CI3, CI2, CI1, CI0

SI7, SI6, SI5, SI4, SI3, SI2, SI1, SI0

HI7, HI6, HI5, HI4, HI3, HI2, HI1, HI0

Customer Identification

Software Model/Version Identification

Hardware Model/Version Identification

Preliminary Data Sheet #: TM048

Page 15 of 24

Rev: P00

Date: 05/13/04

Table 20 - Reference Status Table

R#1

0

R#0

0

Description

Reference is not present.

0

1

Reference is present but frequency is disqualified.

Reference is qualified but is ignored.

Reference is present and frequency is qualified.

1

0

1

Table 21 - Active Reference Table

R2

0

R1

0

R0

0

Description

No reference. Module is in Free Run or Hold Over

Tracking reference 1

0

1

0

1

0

Tracking reference 2

0

1

Tracking reference 3

1

0

Tracking reference 4

1

0

1

Tracking reference 5

1

0

Tracking reference 6

1

Module is locked to Slave input.

(Valid only in Slave mode)

Table 22 - Primary PLL State

S3

0

S2

0

S1

0

S0

0

Description

Loss of Lock

Acquisition Filter

Future Use

Final Filter

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Phase Build-Out

Hold Over

1

0

1

0

1

Free Run

Table 23 - Bandwidth Selecton

FB3

0

FB2

0

FB1

0

FB0

1

Description

0.002 Hz BW (S3E compatible)

0.045 Hz BW (S3 compatible)

0

1

Table 24 - SPI Status

ER7

ER6

ER5

ER4

ER3

ER2

ER1

ER0

SPI Status

0

1

0

1

0

1

0

SPI

SPI overrun error

SPI address error

SPI invalid data

Preliminary Data Sheet #: TM048

Page 16 of 24

Rev: P00 Date: 05/13/04

Wander Generation TDEV

Figure 9

100

GR-1244-CORE, Fig. 5-4, GR-253-CORE, Fig 5-8,

Wander Generation TDEV

Stratum 3E Wander Generation TDEV

Stratum 3 Wander Generation TDEV

10

1

0.1

0.01

0.1

1

10

100

1000

10000

Integration Time (sec)

Wander Generation MTIE

Figure 10

1000

GR-1244-CORE, Fig 5-5, Wander Generation-MTIE

GR-253-CORE, Fig 5-17, MTIE for SONET clock

S3E Wander Generation MTIE

S3 Wander Generation MTIE

100

10

1

0.1

1

10

100

1000

10000

See Table 17 and Table 23 for Bandwidth selections

Observation Time (sec)

Preliminary Data Sheet #: TM048

Page 17 of 24

Rev: P00

Date: 05/13/04

Wander Transfer TDEV

Figure 11

10000

GR-1244-CORE, Fig 5-6, Stratum 3E Wander Transfer

GR-1244-CORE, Fig 5-6, Stratum 3 Wander Transfer

Stratum 3E Calibrated Wander Transfer TDEV

Stratum 3 Calibrated Wander Transfer TDEV

1000

100

10

1

0.1

0.01

0.1

1

10

100

1000

Integration Time (sec)

MTIE During Reference Rearrangement

Figure 12

100000

GR-1244-CORE, Fig. 5-7, Stratum 3/4E, Phase Transient during rearrangement

GR-253-CORE, Fig 5-19, MTIE for Phase Transients from SONET Clocks, Objective

and GR-1244-CORE, Fig. 5-7,Stratum 2/3E, Phase Transient during Rearrangment

Stratum 3E Reference Switch MTIE

10000

1000

100

10

Stratum 3 Reference Switch MTIE

1

0.001

0.01

0.1

1

10

100

1000

Observation Time (sec)

Preliminary Data Sheet #: TM048

Page 18 of 24

Rev: P00 Date: 05/13/04

Entry into Hold Over MTIE

Figure 13

1000

GR-1244-CORE, Fig 5-8, Phase Transient

S3E Entry into Hold Over MTIE

S3 Entry into Hold Over MTIE

100

10

1

0.01

0.1

1

10

100

1000

Observation Time (sec)

1µs Phase Transient MTIE

Figure 14

10000

GR-1244-CORE, Fig 5-9, MTIE mask for I/O Phase Transient

GR-253-CORE, Fig 5-19, MTIE for Phase Transients from SONET Clocks, Requirement

S3E 1us MTIE

S3 1us MTIE

1000

100

10

1

0.001

0.01

0.1

1

10

100

1000

10000

Observation Time (sec)

Preliminary Data Sheet #: TM048

Page 19 of 24

Rev: P00

Date: 05/13/04

Jitter Attenuation

Figure 15_10.000

0.000

-10.000

-20.000

-30.000

-40.000

-50.000

-60.000

Stratum3E

Stratum3

Slave

-70.000

0.001

0.01

0.1

1

10

100

INPUT Jitter frequency (Hz)

Hold Over Stability over Temperature

Figure 16

10

8

6

4

2

0

-2

70

60

50

40

30

20

10

0

Temperature (°C)

Preliminary Data Sheet #: TM048

Page 20 of 24

Rev: P00 Date: 05/13/04

Typical Current Consumption Over Temperature

Figure 17

0.800

0.700

0.600

0.500

0.400

0.300

0.200

0.100

0.000

0.00

10.00

20.00

30.00

40.00

50.00

60.00

70.00

Temperature (°C)

Typical Phase Build Out MTIE

Figure 18

100.0E-9

10.0E-9

1.0E-9

100.0E-12

1.0E-3

10.0E-3

100.0E-3

1.0E+0

10.0E+0

100.0E+0

Observation Window (Tau)

Preliminary Data Sheet #: TM048

Page 21 of 24

Rev: P00

Date: 05/13/04

Mode and Alarm Timing Diagram

Figure 19

State Change on Control Input Pins

(CNTRL1-3)

Operational Mode Indicators

(Ref1-Ref6, Hold Over or Free Run)

Alarm Indicator

(See Operation Overview for

details on Alarm Operation)

2 ms < ∆t < 4 ms

LOCK Timing Diagram

Figure 20

Internal 8kHz

(Derived from Sync_Out)

External 8kHz

(Derived from Active Reference)

Internal Phase

Error Signal

≤

>

20 µs

t

delay

≥ 2ms

Lock Indicator

0ms ≤ t

delay

≤ 2ms

Preliminary Data Sheet #: TM048

Page 22 of 24

Rev: P00 Date: 05/13/04

Footprint and Keepout Dimensions

Figure 21

Package Dimensions

Figure22

0.110 [2.79 mm]

1.820 [46.23 mm]

SQUARE

1.600 [40.64 mm]

MAX.

0.160 0.008 [4.06 mm]

Pin #1

0.730 [18.54 mm]

MAX.

0.100 [2.54 mm]

0.110 [2.79 mm]

0.020 [0.51 mm]

Preliminary Data Sheet #: TM048

Page 23 of 24

Rev: P00

Date: 05/13/04

2111 Comprehensive Drive

Aurora, Illinois 60505

Phone: 630-851-4722

Fax: 630- 851-5040

www.conwin.com

Revision #

Revision Date

Notes

P00

05/13/04

Preliminary informational release


型号：	STL-S3E
厂家：	CONNOR-WINFIELD CORPORATION
描述：	Stratum 3E Timing Module 3E级定时模块
文件：	总24页 (文件大小：975K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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